2 * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Berkeley Software Design Inc's name may not be used to endorse or
13 * promote products derived from this software without specific prior
16 * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * from BSDI: locore.s,v 1.36.2.15 1999/08/23 22:34:41 cp Exp
31 * Copyright (c) 2002 Jake Burkholder.
32 * Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
33 * All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD$");
60 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <sys/kernel.h>
66 #include <sys/mutex.h>
69 #include <sys/sched.h>
73 #include <vm/vm_param.h>
75 #include <vm/vm_kern.h>
76 #include <vm/vm_extern.h>
77 #include <vm/vm_map.h>
79 #include <dev/ofw/openfirm.h>
81 #include <machine/asi.h>
82 #include <machine/atomic.h>
83 #include <machine/bus.h>
84 #include <machine/cpu.h>
85 #include <machine/md_var.h>
86 #include <machine/metadata.h>
87 #include <machine/ofw_machdep.h>
88 #include <machine/pcb.h>
89 #include <machine/smp.h>
90 #include <machine/tick.h>
91 #include <machine/tlb.h>
92 #include <machine/tte.h>
93 #include <machine/ver.h>
95 #define SUNW_STARTCPU "SUNW,start-cpu"
96 #define SUNW_STOPSELF "SUNW,stop-self"
98 static ih_func_t cpu_ipi_ast;
99 static ih_func_t cpu_ipi_preempt;
100 static ih_func_t cpu_ipi_stop;
103 * Argument area used to pass data to non-boot processors as they start up.
104 * This must be statically initialized with a known invalid CPU module ID,
105 * since the other processors will use it before the boot CPU enters the
108 struct cpu_start_args cpu_start_args = { 0, -1, -1, 0, 0, 0 };
109 struct ipi_cache_args ipi_cache_args;
110 struct ipi_tlb_args ipi_tlb_args;
111 struct pcb stoppcbs[MAXCPU];
115 cpu_ipi_selected_t *cpu_ipi_selected;
117 static vm_offset_t mp_tramp;
118 static u_int cpuid_to_mid[MAXCPU];
120 static volatile u_int shutdown_cpus;
122 static void ap_count(phandle_t node, u_int mid, u_int cpu_impl);
123 static void ap_start(phandle_t node, u_int mid, u_int cpu_impl);
124 static void cpu_mp_unleash(void *v);
125 static void foreach_ap(phandle_t node, void (*func)(phandle_t node,
126 u_int mid, u_int cpu_impl));
127 static void spitfire_ipi_send(u_int mid, u_long d0, u_long d1, u_long d2);
128 static void sun4u_startcpu(phandle_t cpu, void *func, u_long arg);
130 static cpu_ipi_selected_t cheetah_ipi_selected;
131 static cpu_ipi_selected_t spitfire_ipi_selected;
133 SYSINIT(cpu_mp_unleash, SI_SUB_SMP, SI_ORDER_FIRST, cpu_mp_unleash, NULL);
135 CTASSERT(MAXCPU <= IDR_CHEETAH_MAX_BN_PAIRS);
136 CTASSERT(MAXCPU <= sizeof(u_int) * NBBY);
137 CTASSERT(MAXCPU <= sizeof(int) * NBBY);
140 mp_init(u_int cpu_impl)
145 mp_tramp = (vm_offset_t)OF_claim(NULL, PAGE_SIZE, PAGE_SIZE);
146 if (mp_tramp == (vm_offset_t)-1)
147 panic("%s", __func__);
148 bcopy(mp_tramp_code, (void *)mp_tramp, mp_tramp_code_len);
149 *(vm_offset_t *)(mp_tramp + mp_tramp_tlb_slots) = kernel_tlb_slots;
150 *(vm_offset_t *)(mp_tramp + mp_tramp_func) = (vm_offset_t)mp_startup;
151 tp = (struct tte *)(mp_tramp + mp_tramp_code_len);
152 for (i = 0; i < kernel_tlb_slots; i++) {
153 tp[i].tte_vpn = TV_VPN(kernel_tlbs[i].te_va, TS_4M);
154 tp[i].tte_data = TD_V | TD_4M | TD_PA(kernel_tlbs[i].te_pa) |
155 TD_L | TD_CP | TD_CV | TD_P | TD_W;
157 for (i = 0; i < PAGE_SIZE; i += sizeof(vm_offset_t))
161 * On UP systems cpu_ipi_selected() can be called while
162 * cpu_mp_start() wasn't so initialize these here.
164 if (cpu_impl == CPU_IMPL_ULTRASPARCIIIi ||
165 cpu_impl == CPU_IMPL_ULTRASPARCIIIip)
167 if (cpu_impl == CPU_IMPL_SPARC64V ||
168 cpu_impl >= CPU_IMPL_ULTRASPARCIII)
169 cpu_ipi_selected = cheetah_ipi_selected;
171 cpu_ipi_selected = spitfire_ipi_selected;
175 foreach_ap(phandle_t node, void (*func)(phandle_t node, u_int mid,
178 char type[sizeof("cpu")];
183 /* There's no need to traverse the whole OFW tree twice. */
184 if (mp_maxid > 0 && mp_ncpus >= mp_maxid + 1)
187 for (; node != 0; node = OF_peer(node)) {
188 child = OF_child(node);
190 foreach_ap(child, func);
192 if (OF_getprop(node, "device_type", type,
195 if (strcmp(type, "cpu") != 0)
197 if (OF_getprop(node, "implementation#", &cpu_impl,
198 sizeof(cpu_impl)) <= 0)
199 panic("%s: couldn't determine CPU "
200 "implementation", __func__);
201 if (OF_getprop(node, cpu_cpuid_prop(cpu_impl), &cpuid,
203 panic("%s: couldn't determine CPU module ID",
205 if (cpuid == PCPU_GET(mid))
207 (*func)(node, cpuid, cpu_impl);
213 * Probe for other CPUs.
219 all_cpus = 1 << curcpu;
223 foreach_ap(OF_child(OF_peer(0)), ap_count);
227 ap_count(phandle_t node __unused, u_int mid __unused, u_int cpu_impl __unused)
237 return (mp_maxid > 0);
244 return (smp_topo_none());
248 sun4u_startcpu(phandle_t cpu, void *func, u_long arg)
258 (cell_t)SUNW_STARTCPU,
263 args.func = (cell_t)func;
264 args.arg = (cell_t)arg;
269 * Fire up any non-boot processors.
275 mtx_init(&ipi_mtx, "ipi", NULL, MTX_SPIN);
277 intr_setup(PIL_AST, cpu_ipi_ast, -1, NULL, NULL);
278 intr_setup(PIL_RENDEZVOUS, (ih_func_t *)smp_rendezvous_action,
280 intr_setup(PIL_STOP, cpu_ipi_stop, -1, NULL, NULL);
281 intr_setup(PIL_PREEMPT, cpu_ipi_preempt, -1, NULL, NULL);
283 cpuid_to_mid[curcpu] = PCPU_GET(mid);
285 foreach_ap(OF_child(OF_peer(0)), ap_start);
286 KASSERT(!isjbus || mp_ncpus <= IDR_JALAPENO_MAX_BN_PAIRS,
287 ("%s: can only IPI a maximum of %d JBus-CPUs",
288 __func__, IDR_JALAPENO_MAX_BN_PAIRS));
289 PCPU_SET(other_cpus, all_cpus & ~(1 << curcpu));
294 ap_start(phandle_t node, u_int mid, u_int cpu_impl)
296 volatile struct cpu_start_args *csa;
303 if (mp_ncpus > MAXCPU)
306 if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) <= 0)
307 panic("%s: couldn't determine CPU frequency", __func__);
308 if (clock != PCPU_GET(clock))
309 hardclock_use_stick = 1;
311 csa = &cpu_start_args;
313 sun4u_startcpu(node, (void *)mp_tramp, 0);
315 while (csa->csa_state != CPU_TICKSYNC)
318 csa->csa_tick = rd(tick);
319 if (cpu_impl == CPU_IMPL_SPARC64V ||
320 cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
321 while (csa->csa_state != CPU_STICKSYNC)
324 csa->csa_stick = rdstick();
326 while (csa->csa_state != CPU_INIT)
328 csa->csa_tick = csa->csa_stick = 0;
332 cpuid_to_mid[cpuid] = mid;
333 cpu_identify(csa->csa_ver, clock, cpuid);
335 va = kmem_alloc(kernel_map, PCPU_PAGES * PAGE_SIZE);
336 pc = (struct pcpu *)(va + (PCPU_PAGES * PAGE_SIZE)) - 1;
337 pcpu_init(pc, cpuid, sizeof(*pc));
338 dpcpu_init((void *)kmem_alloc(kernel_map, DPCPU_SIZE), cpuid);
340 pc->pc_clock = clock;
341 pc->pc_impl = cpu_impl;
347 all_cpus |= 1 << cpuid;
352 cpu_mp_announce(void)
358 cpu_mp_unleash(void *v)
360 volatile struct cpu_start_args *csa;
369 ctx_min = TLB_CTX_USER_MIN;
370 ctx_inc = (TLB_CTX_USER_MAX - 1) / mp_ncpus;
371 csa = &cpu_start_args;
372 csa->csa_count = mp_ncpus;
373 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) {
374 pc->pc_tlb_ctx = ctx_min;
375 pc->pc_tlb_ctx_min = ctx_min;
376 pc->pc_tlb_ctx_max = ctx_min + ctx_inc;
379 if (pc->pc_cpuid == curcpu)
381 KASSERT(pc->pc_idlethread != NULL,
382 ("%s: idlethread", __func__));
383 pc->pc_curthread = pc->pc_idlethread;
384 pc->pc_curpcb = pc->pc_curthread->td_pcb;
385 for (i = 0; i < PCPU_PAGES; i++) {
386 va = pc->pc_addr + i * PAGE_SIZE;
387 pa = pmap_kextract(va);
389 panic("%s: pmap_kextract", __func__);
390 csa->csa_ttes[i].tte_vpn = TV_VPN(va, TS_8K);
391 csa->csa_ttes[i].tte_data = TD_V | TD_8K | TD_PA(pa) |
392 TD_L | TD_CP | TD_CV | TD_P | TD_W;
395 csa->csa_pcpu = pc->pc_addr;
396 csa->csa_mid = pc->pc_mid;
398 while (csa->csa_state != CPU_BOOTSTRAP)
409 cpu_mp_bootstrap(struct pcpu *pc)
411 volatile struct cpu_start_args *csa;
413 csa = &cpu_start_args;
415 /* Do CPU-specific initialization. */
416 if (pc->pc_impl == CPU_IMPL_SPARC64V ||
417 pc->pc_impl >= CPU_IMPL_ULTRASPARCIII)
418 cheetah_init(pc->pc_impl);
420 * Enable the caches. Note that his may include applying workarounds.
422 cache_enable(pc->pc_impl);
424 /* Lock the kernel TSB in the TLB. */
428 * Flush all non-locked TLB entries possibly left over by the
431 tlb_flush_nonlocked();
433 /* Initialize global registers. */
436 /* Enable interrupts. */
437 wrpr(pil, 0, PIL_TICK);
438 wrpr(pstate, 0, PSTATE_KERNEL);
440 /* Start the (S)TICK interrupts. */
444 KASSERT(curthread != NULL, ("%s: curthread", __func__));
445 PCPU_SET(other_cpus, all_cpus & ~(1 << curcpu));
446 printf("SMP: AP CPU #%d Launched!\n", curcpu);
450 csa->csa_state = CPU_BOOTSTRAP;
451 while (csa->csa_count != 0)
454 /* Ok, now enter the scheduler. */
459 cpu_mp_shutdown(void)
464 shutdown_cpus = PCPU_GET(other_cpus);
465 if (stopped_cpus != PCPU_GET(other_cpus)) /* XXX */
466 stop_cpus(stopped_cpus ^ PCPU_GET(other_cpus));
468 while (shutdown_cpus != 0) {
470 printf("timeout shutting down CPUs.\n");
478 cpu_ipi_ast(struct trapframe *tf)
484 cpu_ipi_stop(struct trapframe *tf)
487 CTR2(KTR_SMP, "%s: stopped %d", __func__, curcpu);
488 savectx(&stoppcbs[curcpu]);
489 atomic_set_acq_int(&stopped_cpus, PCPU_GET(cpumask));
490 while ((started_cpus & PCPU_GET(cpumask)) == 0) {
491 if ((shutdown_cpus & PCPU_GET(cpumask)) != 0) {
492 atomic_clear_int(&shutdown_cpus, PCPU_GET(cpumask));
493 (void)intr_disable();
498 atomic_clear_rel_int(&started_cpus, PCPU_GET(cpumask));
499 atomic_clear_rel_int(&stopped_cpus, PCPU_GET(cpumask));
500 CTR2(KTR_SMP, "%s: restarted %d", __func__, curcpu);
504 cpu_ipi_preempt(struct trapframe *tf)
507 sched_preempt(curthread);
511 spitfire_ipi_selected(u_int cpus, u_long d0, u_long d1, u_long d2)
515 KASSERT((cpus & (1 << curcpu)) == 0,
516 ("%s: CPU can't IPI itself", __func__));
520 spitfire_ipi_send(cpuid_to_mid[cpu], d0, d1, d2);
525 spitfire_ipi_send(u_int mid, u_long d0, u_long d1, u_long d2)
531 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) & IDR_BUSY) == 0,
532 ("%s: outstanding dispatch", __func__));
533 for (i = 0; i < IPI_RETRIES; i++) {
535 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
536 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
537 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
539 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
542 * Workaround for SpitFire erratum #54; do a dummy read
543 * from a SDB internal register before the MEMBAR #Sync
544 * for the write to ASI_SDB_INTR_W (requiring another
545 * MEMBAR #Sync in order to make sure the write has
546 * occurred before the load).
549 (void)ldxa(AA_SDB_CNTL_HIGH, ASI_SDB_CONTROL_R);
551 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
555 if ((ids & (IDR_BUSY | IDR_NACK)) == 0)
558 * Leave interrupts enabled for a bit before retrying
559 * in order to avoid deadlocks if the other CPU is also
560 * trying to send an IPI.
564 if (kdb_active != 0 || panicstr != NULL)
565 printf("%s: couldn't send IPI to module 0x%u\n",
568 panic("%s: couldn't send IPI to module 0x%u",
573 cheetah_ipi_selected(u_int cpus, u_long d0, u_long d1, u_long d2)
581 KASSERT((cpus & (1 << curcpu)) == 0,
582 ("%s: CPU can't IPI itself", __func__));
583 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
584 IDR_CHEETAH_ALL_BUSY) == 0,
585 ("%s: outstanding dispatch", __func__));
589 for (i = 0; i < IPI_RETRIES * mp_ncpus; i++) {
591 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
592 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
593 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
596 for (cpu = 0; cpu < mp_ncpus; cpu++) {
597 if ((cpus & (1 << cpu)) != 0) {
599 (cpuid_to_mid[cpu] << IDC_ITID_SHIFT) |
600 (isjbus ? 0 : bnp << IDC_BN_SHIFT),
606 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
607 IDR_CHEETAH_ALL_BUSY) != 0)
610 if ((ids & (IDR_CHEETAH_ALL_BUSY | IDR_CHEETAH_ALL_NACK)) == 0)
613 for (cpu = 0; cpu < mp_ncpus; cpu++) {
614 if ((cpus & (1 << cpu)) != 0) {
615 if ((ids & (IDR_NACK << (isjbus ?
616 (2 * cpuid_to_mid[cpu]) :
623 * On at least Fire V880 we may receive IDR_NACKs for
624 * CPUs we actually haven't tried to send an IPI to,
625 * but which apparently can be safely ignored.
630 * Leave interrupts enabled for a bit before retrying
631 * in order to avoid deadlocks if the other CPUs are
632 * also trying to send IPIs.
636 if (kdb_active != 0 || panicstr != NULL)
637 printf("%s: couldn't send IPI (cpus=0x%u ids=0x%lu)\n",
638 __func__, cpus, ids);
640 panic("%s: couldn't send IPI (cpus=0x%u ids=0x%lu)",
641 __func__, cpus, ids);