2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department and William Jolitz of UUNET Technologies Inc.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by the University of
24 * California, Berkeley and its contributors.
25 * 4. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
48 * Manages physical address maps.
50 * In addition to hardware address maps, this module is called upon to
51 * provide software-use-only maps which may or may not be stored in the
52 * same form as hardware maps. These pseudo-maps are used to store
53 * intermediate results from copy operations to and from address spaces.
55 * Since the information managed by this module is also stored by the
56 * logical address mapping module, this module may throw away valid virtual
57 * to physical mappings at almost any time. However, invalidations of
58 * mappings must be done as requested.
60 * In order to cope with hardware architectures which make virtual to
61 * physical map invalidates expensive, this module may delay invalidate
62 * reduced protection operations until such time as they are actually
63 * necessary. This module is given full information as to which processors
64 * are currently using which maps, and to when physical maps must be made
68 #include "opt_kstack_pages.h"
69 #include "opt_msgbuf.h"
72 #include <sys/param.h>
73 #include <sys/kernel.h>
76 #include <sys/msgbuf.h>
77 #include <sys/mutex.h>
80 #include <sys/sysctl.h>
81 #include <sys/systm.h>
82 #include <sys/vmmeter.h>
84 #include <dev/ofw/openfirm.h>
87 #include <vm/vm_param.h>
88 #include <vm/vm_kern.h>
89 #include <vm/vm_page.h>
90 #include <vm/vm_map.h>
91 #include <vm/vm_object.h>
92 #include <vm/vm_extern.h>
93 #include <vm/vm_pageout.h>
94 #include <vm/vm_pager.h>
96 #include <machine/cache.h>
97 #include <machine/frame.h>
98 #include <machine/instr.h>
99 #include <machine/md_var.h>
100 #include <machine/metadata.h>
101 #include <machine/ofw_mem.h>
102 #include <machine/smp.h>
103 #include <machine/tlb.h>
104 #include <machine/tte.h>
105 #include <machine/tsb.h>
106 #include <machine/ver.h>
110 #ifndef PMAP_SHPGPERPROC
111 #define PMAP_SHPGPERPROC 200
115 #include "opt_sched.h"
117 #error "sparc64 only works with SCHED_4BSD which uses a global scheduler lock."
119 extern struct mtx sched_lock;
122 * Virtual address of message buffer
124 struct msgbuf *msgbufp;
127 * Map of physical memory reagions
129 vm_paddr_t phys_avail[128];
130 static struct ofw_mem_region mra[128];
131 struct ofw_mem_region sparc64_memreg[128];
133 static struct ofw_map translations[128];
134 static int translations_size;
136 static vm_offset_t pmap_idle_map;
137 static vm_offset_t pmap_temp_map_1;
138 static vm_offset_t pmap_temp_map_2;
141 * First and last available kernel virtual addresses
143 vm_offset_t virtual_avail;
144 vm_offset_t virtual_end;
145 vm_offset_t kernel_vm_end;
147 vm_offset_t vm_max_kernel_address;
152 struct pmap kernel_pmap_store;
155 * Allocate physical memory for use in pmap_bootstrap.
157 static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size);
160 * Map the given physical page at the specified virtual address in the
161 * target pmap with the protection requested. If specified the page
162 * will be wired down.
164 * The page queues and pmap must be locked.
166 static void pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m,
167 vm_prot_t prot, boolean_t wired);
169 extern int tl1_immu_miss_patch_1[];
170 extern int tl1_immu_miss_patch_2[];
171 extern int tl1_dmmu_miss_patch_1[];
172 extern int tl1_dmmu_miss_patch_2[];
173 extern int tl1_dmmu_prot_patch_1[];
174 extern int tl1_dmmu_prot_patch_2[];
177 * If user pmap is processed with pmap_remove and with pmap_remove and the
178 * resident count drops to 0, there are no more pages to remove, so we
181 #define PMAP_REMOVE_DONE(pm) \
182 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0)
185 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove()
186 * and pmap_protect() instead of trying each virtual address.
188 #define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE)
190 SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "");
192 PMAP_STATS_VAR(pmap_nenter);
193 PMAP_STATS_VAR(pmap_nenter_update);
194 PMAP_STATS_VAR(pmap_nenter_replace);
195 PMAP_STATS_VAR(pmap_nenter_new);
196 PMAP_STATS_VAR(pmap_nkenter);
197 PMAP_STATS_VAR(pmap_nkenter_oc);
198 PMAP_STATS_VAR(pmap_nkenter_stupid);
199 PMAP_STATS_VAR(pmap_nkremove);
200 PMAP_STATS_VAR(pmap_nqenter);
201 PMAP_STATS_VAR(pmap_nqremove);
202 PMAP_STATS_VAR(pmap_ncache_enter);
203 PMAP_STATS_VAR(pmap_ncache_enter_c);
204 PMAP_STATS_VAR(pmap_ncache_enter_oc);
205 PMAP_STATS_VAR(pmap_ncache_enter_cc);
206 PMAP_STATS_VAR(pmap_ncache_enter_coc);
207 PMAP_STATS_VAR(pmap_ncache_enter_nc);
208 PMAP_STATS_VAR(pmap_ncache_enter_cnc);
209 PMAP_STATS_VAR(pmap_ncache_remove);
210 PMAP_STATS_VAR(pmap_ncache_remove_c);
211 PMAP_STATS_VAR(pmap_ncache_remove_oc);
212 PMAP_STATS_VAR(pmap_ncache_remove_cc);
213 PMAP_STATS_VAR(pmap_ncache_remove_coc);
214 PMAP_STATS_VAR(pmap_ncache_remove_nc);
215 PMAP_STATS_VAR(pmap_nzero_page);
216 PMAP_STATS_VAR(pmap_nzero_page_c);
217 PMAP_STATS_VAR(pmap_nzero_page_oc);
218 PMAP_STATS_VAR(pmap_nzero_page_nc);
219 PMAP_STATS_VAR(pmap_nzero_page_area);
220 PMAP_STATS_VAR(pmap_nzero_page_area_c);
221 PMAP_STATS_VAR(pmap_nzero_page_area_oc);
222 PMAP_STATS_VAR(pmap_nzero_page_area_nc);
223 PMAP_STATS_VAR(pmap_nzero_page_idle);
224 PMAP_STATS_VAR(pmap_nzero_page_idle_c);
225 PMAP_STATS_VAR(pmap_nzero_page_idle_oc);
226 PMAP_STATS_VAR(pmap_nzero_page_idle_nc);
227 PMAP_STATS_VAR(pmap_ncopy_page);
228 PMAP_STATS_VAR(pmap_ncopy_page_c);
229 PMAP_STATS_VAR(pmap_ncopy_page_oc);
230 PMAP_STATS_VAR(pmap_ncopy_page_nc);
231 PMAP_STATS_VAR(pmap_ncopy_page_dc);
232 PMAP_STATS_VAR(pmap_ncopy_page_doc);
233 PMAP_STATS_VAR(pmap_ncopy_page_sc);
234 PMAP_STATS_VAR(pmap_ncopy_page_soc);
236 PMAP_STATS_VAR(pmap_nnew_thread);
237 PMAP_STATS_VAR(pmap_nnew_thread_oc);
239 static inline u_long dtlb_get_data(u_int slot);
242 * Quick sort callout for comparing memory regions
244 static int mr_cmp(const void *a, const void *b);
245 static int om_cmp(const void *a, const void *b);
248 mr_cmp(const void *a, const void *b)
250 const struct ofw_mem_region *mra;
251 const struct ofw_mem_region *mrb;
255 if (mra->mr_start < mrb->mr_start)
257 else if (mra->mr_start > mrb->mr_start)
264 om_cmp(const void *a, const void *b)
266 const struct ofw_map *oma;
267 const struct ofw_map *omb;
271 if (oma->om_start < omb->om_start)
273 else if (oma->om_start > omb->om_start)
280 dtlb_get_data(u_int slot)
284 * We read ASI_DTLB_DATA_ACCESS_REG twice in order to work
285 * around errata of USIII and beyond.
287 (void)ldxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG);
288 return (ldxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG));
292 * Bootstrap the system enough to run with virtual memory.
295 pmap_bootstrap(u_int cpu_impl)
307 u_int dtlb_slots_avail;
313 * Find out what physical memory is available from the PROM and
314 * initialize the phys_avail array. This must be done before
315 * pmap_bootstrap_alloc is called.
317 if ((pmem = OF_finddevice("/memory")) == -1)
318 panic("pmap_bootstrap: finddevice /memory");
319 if ((sz = OF_getproplen(pmem, "available")) == -1)
320 panic("pmap_bootstrap: getproplen /memory/available");
321 if (sizeof(phys_avail) < sz)
322 panic("pmap_bootstrap: phys_avail too small");
323 if (sizeof(mra) < sz)
324 panic("pmap_bootstrap: mra too small");
326 if (OF_getprop(pmem, "available", mra, sz) == -1)
327 panic("pmap_bootstrap: getprop /memory/available");
329 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory");
330 qsort(mra, sz, sizeof (*mra), mr_cmp);
332 getenv_quad("hw.physmem", &physmem);
333 physmem = btoc(physmem);
334 for (i = 0, j = 0; i < sz; i++, j += 2) {
335 CTR2(KTR_PMAP, "start=%#lx size=%#lx", mra[i].mr_start,
337 if (physmem != 0 && btoc(physsz + mra[i].mr_size) >= physmem) {
338 if (btoc(physsz) < physmem) {
339 phys_avail[j] = mra[i].mr_start;
340 phys_avail[j + 1] = mra[i].mr_start +
341 (ctob(physmem) - physsz);
342 physsz = ctob(physmem);
346 phys_avail[j] = mra[i].mr_start;
347 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size;
348 physsz += mra[i].mr_size;
350 physmem = btoc(physsz);
353 * Calculate the size of kernel virtual memory, and the size and mask
354 * for the kernel TSB based on the phsyical memory size but limited
355 * by the amount of dTLB slots available for locked entries (given
356 * that for spitfire-class CPUs all of the dt64 slots can hold locked
357 * entries but there is no large dTLB for unlocked ones, we don't use
358 * more than half of it for locked entries).
360 dtlb_slots_avail = 0;
361 for (i = 0; i < dtlb_slots; i++) {
362 data = dtlb_get_data(i);
363 if ((data & (TD_V | TD_L)) != (TD_V | TD_L))
367 dtlb_slots_avail -= PCPU_PAGES;
369 if (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
370 cpu_impl < CPU_IMPL_ULTRASPARCIII)
371 dtlb_slots_avail /= 2;
372 virtsz = roundup(physsz, PAGE_SIZE_4M << (PAGE_SHIFT - TTE_SHIFT));
374 (dtlb_slots_avail * PAGE_SIZE_4M) << (PAGE_SHIFT - TTE_SHIFT));
375 vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz;
376 tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT);
377 tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1;
380 * Allocate the kernel TSB and lock it in the TLB.
382 pa = pmap_bootstrap_alloc(tsb_kernel_size);
383 if (pa & PAGE_MASK_4M)
384 panic("pmap_bootstrap: tsb unaligned\n");
385 tsb_kernel_phys = pa;
386 tsb_kernel = (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size);
388 bzero(tsb_kernel, tsb_kernel_size);
391 * Allocate and map the dynamic per-CPU area for the BSP.
393 pa = pmap_bootstrap_alloc(DPCPU_SIZE);
394 dpcpu0 = (void *)TLB_PHYS_TO_DIRECT(pa);
397 * Allocate and map the message buffer.
399 pa = pmap_bootstrap_alloc(MSGBUF_SIZE);
400 msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(pa);
403 * Patch the virtual address and the tsb mask into the trap table.
406 #define SETHI(rd, imm22) \
407 (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \
408 EIF_IMM((imm22) >> 10, 22))
409 #define OR_R_I_R(rd, imm13, rs1) \
410 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \
411 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
413 #define PATCH(addr) do { \
414 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
415 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, IF_F3_RS1(addr[1])) || \
416 addr[2] != SETHI(IF_F2_RD(addr[2]), 0x0)) \
417 panic("pmap_boostrap: patched instructions have changed"); \
418 addr[0] |= EIF_IMM((tsb_kernel_mask) >> 10, 22); \
419 addr[1] |= EIF_IMM(tsb_kernel_mask, 10); \
420 addr[2] |= EIF_IMM(((vm_offset_t)tsb_kernel) >> 10, 22); \
426 PATCH(tl1_immu_miss_patch_1);
427 PATCH(tl1_immu_miss_patch_2);
428 PATCH(tl1_dmmu_miss_patch_1);
429 PATCH(tl1_dmmu_miss_patch_2);
430 PATCH(tl1_dmmu_prot_patch_1);
431 PATCH(tl1_dmmu_prot_patch_2);
434 * Enter fake 8k pages for the 4MB kernel pages, so that
435 * pmap_kextract() will work for them.
437 for (i = 0; i < kernel_tlb_slots; i++) {
438 pa = kernel_tlbs[i].te_pa;
439 va = kernel_tlbs[i].te_va;
440 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) {
441 tp = tsb_kvtotte(va + off);
442 tp->tte_vpn = TV_VPN(va + off, TS_8K);
443 tp->tte_data = TD_V | TD_8K | TD_PA(pa + off) |
444 TD_REF | TD_SW | TD_CP | TD_CV | TD_P | TD_W;
449 * Set the start and end of KVA. The kernel is loaded starting
450 * at the first available 4MB super page, so we advance to the
451 * end of the last one used for it.
453 virtual_avail = KERNBASE + kernel_tlb_slots * PAGE_SIZE_4M;
454 virtual_end = vm_max_kernel_address;
455 kernel_vm_end = vm_max_kernel_address;
458 * Allocate kva space for temporary mappings.
460 pmap_idle_map = virtual_avail;
461 virtual_avail += PAGE_SIZE * DCACHE_COLORS;
462 pmap_temp_map_1 = virtual_avail;
463 virtual_avail += PAGE_SIZE * DCACHE_COLORS;
464 pmap_temp_map_2 = virtual_avail;
465 virtual_avail += PAGE_SIZE * DCACHE_COLORS;
468 * Allocate a kernel stack with guard page for thread0 and map it
469 * into the kernel TSB. We must ensure that the virtual address is
470 * coloured properly, since we're allocating from phys_avail so the
471 * memory won't have an associated vm_page_t.
473 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE);
475 virtual_avail += roundup(KSTACK_GUARD_PAGES, DCACHE_COLORS) *
477 kstack0 = virtual_avail;
478 virtual_avail += roundup(KSTACK_PAGES, DCACHE_COLORS) * PAGE_SIZE;
479 KASSERT(DCACHE_COLOR(kstack0) == DCACHE_COLOR(kstack0_phys),
480 ("pmap_bootstrap: kstack0 miscoloured"));
481 for (i = 0; i < KSTACK_PAGES; i++) {
482 pa = kstack0_phys + i * PAGE_SIZE;
483 va = kstack0 + i * PAGE_SIZE;
484 tp = tsb_kvtotte(va);
485 tp->tte_vpn = TV_VPN(va, TS_8K);
486 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW |
487 TD_CP | TD_CV | TD_P | TD_W;
491 * Calculate the last available physical address.
493 for (i = 0; phys_avail[i + 2] != 0; i += 2)
495 Maxmem = sparc64_btop(phys_avail[i + 1]);
498 * Add the PROM mappings to the kernel TSB.
500 if ((vmem = OF_finddevice("/virtual-memory")) == -1)
501 panic("pmap_bootstrap: finddevice /virtual-memory");
502 if ((sz = OF_getproplen(vmem, "translations")) == -1)
503 panic("pmap_bootstrap: getproplen translations");
504 if (sizeof(translations) < sz)
505 panic("pmap_bootstrap: translations too small");
506 bzero(translations, sz);
507 if (OF_getprop(vmem, "translations", translations, sz) == -1)
508 panic("pmap_bootstrap: getprop /virtual-memory/translations");
509 sz /= sizeof(*translations);
510 translations_size = sz;
511 CTR0(KTR_PMAP, "pmap_bootstrap: translations");
512 qsort(translations, sz, sizeof (*translations), om_cmp);
513 for (i = 0; i < sz; i++) {
515 "translation: start=%#lx size=%#lx tte=%#lx",
516 translations[i].om_start, translations[i].om_size,
517 translations[i].om_tte);
518 if ((translations[i].om_tte & TD_V) == 0)
520 if (translations[i].om_start < VM_MIN_PROM_ADDRESS ||
521 translations[i].om_start > VM_MAX_PROM_ADDRESS)
523 for (off = 0; off < translations[i].om_size;
525 va = translations[i].om_start + off;
526 tp = tsb_kvtotte(va);
527 tp->tte_vpn = TV_VPN(va, TS_8K);
529 ((translations[i].om_tte &
530 ~((TD_SOFT2_MASK << TD_SOFT2_SHIFT) |
531 (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
532 cpu_impl < CPU_IMPL_ULTRASPARCIII ?
533 (TD_DIAG_SF_MASK << TD_DIAG_SF_SHIFT) :
534 (TD_RSVD_CH_MASK << TD_RSVD_CH_SHIFT)) |
535 (TD_SOFT_MASK << TD_SOFT_SHIFT))) | TD_EXEC) +
541 * Get the available physical memory ranges from /memory/reg. These
542 * are only used for kernel dumps, but it may not be wise to do PROM
543 * calls in that situation.
545 if ((sz = OF_getproplen(pmem, "reg")) == -1)
546 panic("pmap_bootstrap: getproplen /memory/reg");
547 if (sizeof(sparc64_memreg) < sz)
548 panic("pmap_bootstrap: sparc64_memreg too small");
549 if (OF_getprop(pmem, "reg", sparc64_memreg, sz) == -1)
550 panic("pmap_bootstrap: getprop /memory/reg");
551 sparc64_nmemreg = sz / sizeof(*sparc64_memreg);
554 * Initialize the kernel pmap (which is statically allocated).
555 * NOTE: PMAP_LOCK_INIT() is needed as part of the initialization
556 * but sparc64 start up is not ready to initialize mutexes yet.
557 * It is called in machdep.c.
560 for (i = 0; i < MAXCPU; i++)
561 pm->pm_context[i] = TLB_CTX_KERNEL;
565 * Flush all non-locked TLB entries possibly left over by the
568 tlb_flush_nonlocked();
583 * Map the 4MB TSB pages.
585 for (i = 0; i < tsb_kernel_size; i += PAGE_SIZE_4M) {
586 va = (vm_offset_t)tsb_kernel + i;
587 pa = tsb_kernel_phys + i;
588 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV |
590 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) |
591 TLB_TAR_CTX(TLB_CTX_KERNEL));
592 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data);
596 * Set the secondary context to be the kernel context (needed for
597 * FP block operations in the kernel).
599 stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) &
600 TLB_CXR_PGSZ_MASK) | TLB_CTX_KERNEL);
607 * Allocate a physical page of memory directly from the phys_avail map.
608 * Can only be called from pmap_bootstrap before avail start and end are
612 pmap_bootstrap_alloc(vm_size_t size)
617 size = roundup(size, PAGE_SIZE * DCACHE_COLORS);
618 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
619 if (phys_avail[i + 1] - phys_avail[i] < size)
622 phys_avail[i] += size;
625 panic("pmap_bootstrap_alloc");
629 * Initialize a vm_page's machine-dependent fields.
632 pmap_page_init(vm_page_t m)
635 TAILQ_INIT(&m->md.tte_list);
636 m->md.color = DCACHE_COLOR(VM_PAGE_TO_PHYS(m));
642 * Initialize the pmap module.
652 for (i = 0; i < translations_size; i++) {
653 addr = translations[i].om_start;
654 size = translations[i].om_size;
655 if ((translations[i].om_tte & TD_V) == 0)
657 if (addr < VM_MIN_PROM_ADDRESS || addr > VM_MAX_PROM_ADDRESS)
659 result = vm_map_find(kernel_map, NULL, 0, &addr, size,
660 VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, MAP_NOFAULT);
661 if (result != KERN_SUCCESS || addr != translations[i].om_start)
662 panic("pmap_init: vm_map_find");
667 * Extract the physical page address associated with the given
668 * map/virtual_address pair.
671 pmap_extract(pmap_t pm, vm_offset_t va)
676 if (pm == kernel_pmap)
677 return (pmap_kextract(va));
679 tp = tsb_tte_lookup(pm, va);
683 pa = TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp));
689 * Atomically extract and hold the physical page with the given
690 * pmap and virtual address pair if that mapping permits the given
694 pmap_extract_and_hold(pmap_t pm, vm_offset_t va, vm_prot_t prot)
700 vm_page_lock_queues();
701 if (pm == kernel_pmap) {
702 if (va >= VM_MIN_DIRECT_ADDRESS) {
704 m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va));
707 tp = tsb_kvtotte(va);
708 if ((tp->tte_data & TD_V) == 0)
713 tp = tsb_tte_lookup(pm, va);
715 if (tp != NULL && ((tp->tte_data & TD_SW) ||
716 (prot & VM_PROT_WRITE) == 0)) {
717 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
720 vm_page_unlock_queues();
721 if (pm != kernel_pmap)
727 * Extract the physical page address associated with the given kernel virtual
731 pmap_kextract(vm_offset_t va)
735 if (va >= VM_MIN_DIRECT_ADDRESS)
736 return (TLB_DIRECT_TO_PHYS(va));
737 tp = tsb_kvtotte(va);
738 if ((tp->tte_data & TD_V) == 0)
740 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp)));
744 pmap_cache_enter(vm_page_t m, vm_offset_t va)
749 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
750 KASSERT((m->flags & PG_FICTITIOUS) == 0,
751 ("pmap_cache_enter: fake page"));
752 PMAP_STATS_INC(pmap_ncache_enter);
755 * Find the color for this virtual address and note the added mapping.
757 color = DCACHE_COLOR(va);
758 m->md.colors[color]++;
761 * If all existing mappings have the same color, the mapping is
764 if (m->md.color == color) {
765 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] == 0,
766 ("pmap_cache_enter: cacheable, mappings of other color"));
767 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
768 PMAP_STATS_INC(pmap_ncache_enter_c);
770 PMAP_STATS_INC(pmap_ncache_enter_oc);
775 * If there are no mappings of the other color, and the page still has
776 * the wrong color, this must be a new mapping. Change the color to
777 * match the new mapping, which is cacheable. We must flush the page
778 * from the cache now.
780 if (m->md.colors[DCACHE_OTHER_COLOR(color)] == 0) {
781 KASSERT(m->md.colors[color] == 1,
782 ("pmap_cache_enter: changing color, not new mapping"));
783 dcache_page_inval(VM_PAGE_TO_PHYS(m));
785 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
786 PMAP_STATS_INC(pmap_ncache_enter_cc);
788 PMAP_STATS_INC(pmap_ncache_enter_coc);
793 * If the mapping is already non-cacheable, just return.
795 if (m->md.color == -1) {
796 PMAP_STATS_INC(pmap_ncache_enter_nc);
800 PMAP_STATS_INC(pmap_ncache_enter_cnc);
803 * Mark all mappings as uncacheable, flush any lines with the other
804 * color out of the dcache, and set the color to none (-1).
806 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
807 atomic_clear_long(&tp->tte_data, TD_CV);
808 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
810 dcache_page_inval(VM_PAGE_TO_PHYS(m));
816 pmap_cache_remove(vm_page_t m, vm_offset_t va)
821 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
822 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va,
823 m->md.colors[DCACHE_COLOR(va)]);
824 KASSERT((m->flags & PG_FICTITIOUS) == 0,
825 ("pmap_cache_remove: fake page"));
826 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0,
827 ("pmap_cache_remove: no mappings %d <= 0",
828 m->md.colors[DCACHE_COLOR(va)]));
829 PMAP_STATS_INC(pmap_ncache_remove);
832 * Find the color for this virtual address and note the removal of
835 color = DCACHE_COLOR(va);
836 m->md.colors[color]--;
839 * If the page is cacheable, just return and keep the same color, even
840 * if there are no longer any mappings.
842 if (m->md.color != -1) {
843 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
844 PMAP_STATS_INC(pmap_ncache_remove_c);
846 PMAP_STATS_INC(pmap_ncache_remove_oc);
850 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] != 0,
851 ("pmap_cache_remove: uncacheable, no mappings of other color"));
854 * If the page is not cacheable (color is -1), and the number of
855 * mappings for this color is not zero, just return. There are
856 * mappings of the other color still, so remain non-cacheable.
858 if (m->md.colors[color] != 0) {
859 PMAP_STATS_INC(pmap_ncache_remove_nc);
864 * The number of mappings for this color is now zero. Recache the
865 * other colored mappings, and change the page color to the other
866 * color. There should be no lines in the data cache for this page,
867 * so flushing should not be needed.
869 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
870 atomic_set_long(&tp->tte_data, TD_CV);
871 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
873 m->md.color = DCACHE_OTHER_COLOR(color);
875 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
876 PMAP_STATS_INC(pmap_ncache_remove_cc);
878 PMAP_STATS_INC(pmap_ncache_remove_coc);
882 * Map a wired page into kernel virtual address space.
885 pmap_kenter(vm_offset_t va, vm_page_t m)
892 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
893 PMAP_STATS_INC(pmap_nkenter);
894 tp = tsb_kvtotte(va);
895 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
896 va, VM_PAGE_TO_PHYS(m), tp, tp->tte_data);
897 if (DCACHE_COLOR(VM_PAGE_TO_PHYS(m)) != DCACHE_COLOR(va)) {
899 "pmap_kenter: off colour va=%#lx pa=%#lx o=%p ot=%d pi=%#lx",
900 va, VM_PAGE_TO_PHYS(m), m->object,
901 m->object ? m->object->type : -1,
903 PMAP_STATS_INC(pmap_nkenter_oc);
905 if ((tp->tte_data & TD_V) != 0) {
906 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
907 ova = TTE_GET_VA(tp);
908 if (m == om && va == ova) {
909 PMAP_STATS_INC(pmap_nkenter_stupid);
912 TAILQ_REMOVE(&om->md.tte_list, tp, tte_link);
913 pmap_cache_remove(om, ova);
915 tlb_page_demap(kernel_pmap, ova);
917 data = TD_V | TD_8K | VM_PAGE_TO_PHYS(m) | TD_REF | TD_SW | TD_CP |
919 if (pmap_cache_enter(m, va) != 0)
921 tp->tte_vpn = TV_VPN(va, TS_8K);
923 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
927 * Map a wired page into kernel virtual address space. This additionally
928 * takes a flag argument wich is or'ed to the TTE data. This is used by
929 * sparc64_bus_mem_map().
930 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility
931 * to flush entries that might still be in the cache, if applicable.
934 pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags)
938 tp = tsb_kvtotte(va);
939 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx",
940 va, pa, tp, tp->tte_data);
941 tp->tte_vpn = TV_VPN(va, TS_8K);
942 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags;
946 * Remove a wired page from kernel virtual address space.
949 pmap_kremove(vm_offset_t va)
954 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
955 PMAP_STATS_INC(pmap_nkremove);
956 tp = tsb_kvtotte(va);
957 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
959 if ((tp->tte_data & TD_V) == 0)
961 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
962 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
963 pmap_cache_remove(m, va);
968 * Inverse of pmap_kenter_flags, used by bus_space_unmap().
971 pmap_kremove_flags(vm_offset_t va)
975 tp = tsb_kvtotte(va);
976 CTR3(KTR_PMAP, "pmap_kremove_flags: va=%#lx tp=%p data=%#lx", va, tp,
982 * Map a range of physical addresses into kernel virtual address space.
984 * The value passed in *virt is a suggested virtual address for the mapping.
985 * Architectures which can support a direct-mapped physical to virtual region
986 * can return the appropriate address within that region, leaving '*virt'
990 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
993 return (TLB_PHYS_TO_DIRECT(start));
997 * Map a list of wired pages into kernel virtual address space. This is
998 * intended for temporary mappings which do not need page modification or
999 * references recorded. Existing mappings in the region are overwritten.
1002 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count)
1007 PMAP_STATS_INC(pmap_nqenter);
1009 if (!(locked = mtx_owned(&vm_page_queue_mtx)))
1010 vm_page_lock_queues();
1011 while (count-- > 0) {
1012 pmap_kenter(va, *m);
1017 vm_page_unlock_queues();
1018 tlb_range_demap(kernel_pmap, sva, va);
1022 * Remove page mappings from kernel virtual address space. Intended for
1023 * temporary mappings entered by pmap_qenter.
1026 pmap_qremove(vm_offset_t sva, int count)
1031 PMAP_STATS_INC(pmap_nqremove);
1033 if (!(locked = mtx_owned(&vm_page_queue_mtx)))
1034 vm_page_lock_queues();
1035 while (count-- > 0) {
1040 vm_page_unlock_queues();
1041 tlb_range_demap(kernel_pmap, sva, va);
1045 * Initialize the pmap associated with process 0.
1048 pmap_pinit0(pmap_t pm)
1053 for (i = 0; i < MAXCPU; i++)
1054 pm->pm_context[i] = 0;
1057 pm->pm_tsb_obj = NULL;
1058 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1062 * Initialize a preallocated and zeroed pmap structure, such as one in a
1063 * vmspace structure.
1066 pmap_pinit(pmap_t pm)
1068 vm_page_t ma[TSB_PAGES];
1075 * Allocate KVA space for the TSB.
1077 if (pm->pm_tsb == NULL) {
1078 pm->pm_tsb = (struct tte *)kmem_alloc_nofault(kernel_map,
1080 if (pm->pm_tsb == NULL) {
1081 PMAP_LOCK_DESTROY(pm);
1087 * Allocate an object for it.
1089 if (pm->pm_tsb_obj == NULL)
1090 pm->pm_tsb_obj = vm_object_allocate(OBJT_DEFAULT, TSB_PAGES);
1092 VM_OBJECT_LOCK(pm->pm_tsb_obj);
1093 for (i = 0; i < TSB_PAGES; i++) {
1094 m = vm_page_grab(pm->pm_tsb_obj, i, VM_ALLOC_NOBUSY |
1095 VM_ALLOC_RETRY | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1096 m->valid = VM_PAGE_BITS_ALL;
1100 VM_OBJECT_UNLOCK(pm->pm_tsb_obj);
1101 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES);
1103 for (i = 0; i < MAXCPU; i++)
1104 pm->pm_context[i] = -1;
1106 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1111 * Release any resources held by the given physical map.
1112 * Called when a pmap initialized by pmap_pinit is being released.
1113 * Should only be called if the map contains no valid mappings.
1116 pmap_release(pmap_t pm)
1122 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p",
1123 pm->pm_context[curcpu], pm->pm_tsb);
1124 KASSERT(pmap_resident_count(pm) == 0,
1125 ("pmap_release: resident pages %ld != 0",
1126 pmap_resident_count(pm)));
1129 * After the pmap was freed, it might be reallocated to a new process.
1130 * When switching, this might lead us to wrongly assume that we need
1131 * not switch contexts because old and new pmap pointer are equal.
1132 * Therefore, make sure that this pmap is not referenced by any PCPU
1133 * pointer any more. This could happen in two cases:
1134 * - A process that referenced the pmap is currently exiting on a CPU.
1135 * However, it is guaranteed to not switch in any more after setting
1136 * its state to PRS_ZOMBIE.
1137 * - A process that referenced this pmap ran on a CPU, but we switched
1138 * to a kernel thread, leaving the pmap pointer unchanged.
1140 mtx_lock_spin(&sched_lock);
1141 SLIST_FOREACH(pc, &cpuhead, pc_allcpu)
1142 if (pc->pc_pmap == pm)
1144 mtx_unlock_spin(&sched_lock);
1146 obj = pm->pm_tsb_obj;
1147 VM_OBJECT_LOCK(obj);
1148 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1"));
1149 while (!TAILQ_EMPTY(&obj->memq)) {
1150 m = TAILQ_FIRST(&obj->memq);
1151 vm_page_lock_queues();
1152 if (vm_page_sleep_if_busy(m, FALSE, "pmaprl"))
1154 KASSERT(m->hold_count == 0,
1155 ("pmap_release: freeing held tsb page"));
1158 atomic_subtract_int(&cnt.v_wire_count, 1);
1159 vm_page_free_zero(m);
1160 vm_page_unlock_queues();
1162 VM_OBJECT_UNLOCK(obj);
1163 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES);
1164 PMAP_LOCK_DESTROY(pm);
1168 * Grow the number of kernel page table entries. Unneeded.
1171 pmap_growkernel(vm_offset_t addr)
1174 panic("pmap_growkernel: can't grow kernel");
1178 pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1184 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1185 data = atomic_readandclear_long(&tp->tte_data);
1186 if ((data & TD_FAKE) == 0) {
1187 m = PHYS_TO_VM_PAGE(TD_PA(data));
1188 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1189 if ((data & TD_WIRED) != 0)
1190 pm->pm_stats.wired_count--;
1191 if ((data & TD_PV) != 0) {
1192 if ((data & TD_W) != 0)
1194 if ((data & TD_REF) != 0)
1195 vm_page_flag_set(m, PG_REFERENCED);
1196 if (TAILQ_EMPTY(&m->md.tte_list))
1197 vm_page_flag_clear(m, PG_WRITEABLE);
1198 pm->pm_stats.resident_count--;
1200 pmap_cache_remove(m, va);
1203 if (PMAP_REMOVE_DONE(pm))
1209 * Remove the given range of addresses from the specified map.
1212 pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end)
1217 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx",
1218 pm->pm_context[curcpu], start, end);
1219 if (PMAP_REMOVE_DONE(pm))
1221 vm_page_lock_queues();
1223 if (end - start > PMAP_TSB_THRESH) {
1224 tsb_foreach(pm, NULL, start, end, pmap_remove_tte);
1225 tlb_context_demap(pm);
1227 for (va = start; va < end; va += PAGE_SIZE)
1228 if ((tp = tsb_tte_lookup(pm, va)) != NULL &&
1229 !pmap_remove_tte(pm, NULL, tp, va))
1231 tlb_range_demap(pm, start, end - 1);
1234 vm_page_unlock_queues();
1238 pmap_remove_all(vm_page_t m)
1245 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1246 for (tp = TAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) {
1247 tpn = TAILQ_NEXT(tp, tte_link);
1248 if ((tp->tte_data & TD_PV) == 0)
1250 pm = TTE_GET_PMAP(tp);
1251 va = TTE_GET_VA(tp);
1253 if ((tp->tte_data & TD_WIRED) != 0)
1254 pm->pm_stats.wired_count--;
1255 if ((tp->tte_data & TD_REF) != 0)
1256 vm_page_flag_set(m, PG_REFERENCED);
1257 if ((tp->tte_data & TD_W) != 0)
1259 tp->tte_data &= ~TD_V;
1260 tlb_page_demap(pm, va);
1261 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1262 pm->pm_stats.resident_count--;
1263 pmap_cache_remove(m, va);
1267 vm_page_flag_clear(m, PG_WRITEABLE);
1271 pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1277 data = atomic_clear_long(&tp->tte_data, TD_REF | TD_SW | TD_W);
1278 if ((data & TD_PV) != 0) {
1279 m = PHYS_TO_VM_PAGE(TD_PA(data));
1280 if ((data & TD_REF) != 0)
1281 vm_page_flag_set(m, PG_REFERENCED);
1282 if ((data & TD_W) != 0)
1289 * Set the physical protection on the specified range of this map as requested.
1292 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1297 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx",
1298 pm->pm_context[curcpu], sva, eva, prot);
1300 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1301 pmap_remove(pm, sva, eva);
1305 if (prot & VM_PROT_WRITE)
1308 vm_page_lock_queues();
1310 if (eva - sva > PMAP_TSB_THRESH) {
1311 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte);
1312 tlb_context_demap(pm);
1314 for (va = sva; va < eva; va += PAGE_SIZE)
1315 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1316 pmap_protect_tte(pm, NULL, tp, va);
1317 tlb_range_demap(pm, sva, eva - 1);
1320 vm_page_unlock_queues();
1324 * Map the given physical page at the specified virtual address in the
1325 * target pmap with the protection requested. If specified the page
1326 * will be wired down.
1329 pmap_enter(pmap_t pm, vm_offset_t va, vm_prot_t access, vm_page_t m,
1330 vm_prot_t prot, boolean_t wired)
1333 vm_page_lock_queues();
1335 pmap_enter_locked(pm, va, m, prot, wired);
1336 vm_page_unlock_queues();
1341 * Map the given physical page at the specified virtual address in the
1342 * target pmap with the protection requested. If specified the page
1343 * will be wired down.
1345 * The page queues and pmap must be locked.
1348 pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1356 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1357 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1358 PMAP_STATS_INC(pmap_nenter);
1359 pa = VM_PAGE_TO_PHYS(m);
1362 * If this is a fake page from the device_pager, but it covers actual
1363 * physical memory, convert to the real backing page.
1365 if ((m->flags & PG_FICTITIOUS) != 0) {
1366 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1367 if (pa >= phys_avail[i] && pa <= phys_avail[i + 1]) {
1368 m = PHYS_TO_VM_PAGE(pa);
1375 "pmap_enter_locked: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d",
1376 pm->pm_context[curcpu], m, va, pa, prot, wired);
1379 * If there is an existing mapping, and the physical address has not
1380 * changed, must be protection or wiring change.
1382 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) {
1383 CTR0(KTR_PMAP, "pmap_enter_locked: update");
1384 PMAP_STATS_INC(pmap_nenter_update);
1387 * Wiring change, just update stats.
1390 if ((tp->tte_data & TD_WIRED) == 0) {
1391 tp->tte_data |= TD_WIRED;
1392 pm->pm_stats.wired_count++;
1395 if ((tp->tte_data & TD_WIRED) != 0) {
1396 tp->tte_data &= ~TD_WIRED;
1397 pm->pm_stats.wired_count--;
1402 * Save the old bits and clear the ones we're interested in.
1404 data = tp->tte_data;
1405 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W);
1408 * If we're turning off write permissions, sense modify status.
1410 if ((prot & VM_PROT_WRITE) != 0) {
1411 tp->tte_data |= TD_SW;
1413 tp->tte_data |= TD_W;
1414 vm_page_flag_set(m, PG_WRITEABLE);
1415 } else if ((data & TD_W) != 0)
1419 * If we're turning on execute permissions, flush the icache.
1421 if ((prot & VM_PROT_EXECUTE) != 0) {
1422 if ((data & TD_EXEC) == 0)
1423 icache_page_inval(pa);
1424 tp->tte_data |= TD_EXEC;
1428 * Delete the old mapping.
1430 tlb_page_demap(pm, TTE_GET_VA(tp));
1433 * If there is an existing mapping, but its for a different
1434 * phsyical address, delete the old mapping.
1437 CTR0(KTR_PMAP, "pmap_enter_locked: replace");
1438 PMAP_STATS_INC(pmap_nenter_replace);
1439 pmap_remove_tte(pm, NULL, tp, va);
1440 tlb_page_demap(pm, va);
1442 CTR0(KTR_PMAP, "pmap_enter_locked: new");
1443 PMAP_STATS_INC(pmap_nenter_new);
1447 * Now set up the data and install the new mapping.
1449 data = TD_V | TD_8K | TD_PA(pa);
1450 if (pm == kernel_pmap)
1452 if ((prot & VM_PROT_WRITE) != 0) {
1454 vm_page_flag_set(m, PG_WRITEABLE);
1456 if (prot & VM_PROT_EXECUTE) {
1458 icache_page_inval(pa);
1462 * If its wired update stats. We also don't need reference or
1463 * modify tracking for wired mappings, so set the bits now.
1466 pm->pm_stats.wired_count++;
1467 data |= TD_REF | TD_WIRED;
1468 if ((prot & VM_PROT_WRITE) != 0)
1472 tsb_tte_enter(pm, m, va, TS_8K, data);
1477 * Maps a sequence of resident pages belonging to the same object.
1478 * The sequence begins with the given page m_start. This page is
1479 * mapped at the given virtual address start. Each subsequent page is
1480 * mapped at a virtual address that is offset from start by the same
1481 * amount as the page is offset from m_start within the object. The
1482 * last page in the sequence is the page with the largest offset from
1483 * m_start that can be mapped at a virtual address less than the given
1484 * virtual address end. Not every virtual page between start and end
1485 * is mapped; only those for which a resident page exists with the
1486 * corresponding offset from m_start are mapped.
1489 pmap_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end,
1490 vm_page_t m_start, vm_prot_t prot)
1493 vm_pindex_t diff, psize;
1495 psize = atop(end - start);
1498 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1499 pmap_enter_locked(pm, start + ptoa(diff), m, prot &
1500 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1501 m = TAILQ_NEXT(m, listq);
1507 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot)
1511 pmap_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1517 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object,
1518 vm_pindex_t pindex, vm_size_t size)
1521 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
1522 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
1523 ("pmap_object_init_pt: non-device object"));
1527 * Change the wiring attribute for a map/virtual-address pair.
1528 * The mapping must already exist in the pmap.
1531 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired)
1537 if ((tp = tsb_tte_lookup(pm, va)) != NULL) {
1539 data = atomic_set_long(&tp->tte_data, TD_WIRED);
1540 if ((data & TD_WIRED) == 0)
1541 pm->pm_stats.wired_count++;
1543 data = atomic_clear_long(&tp->tte_data, TD_WIRED);
1544 if ((data & TD_WIRED) != 0)
1545 pm->pm_stats.wired_count--;
1552 pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp,
1558 if ((tp->tte_data & TD_FAKE) != 0)
1560 if (tsb_tte_lookup(dst_pmap, va) == NULL) {
1561 data = tp->tte_data &
1562 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W);
1563 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1564 tsb_tte_enter(dst_pmap, m, va, TS_8K, data);
1570 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
1571 vm_size_t len, vm_offset_t src_addr)
1576 if (dst_addr != src_addr)
1578 vm_page_lock_queues();
1579 if (dst_pmap < src_pmap) {
1580 PMAP_LOCK(dst_pmap);
1581 PMAP_LOCK(src_pmap);
1583 PMAP_LOCK(src_pmap);
1584 PMAP_LOCK(dst_pmap);
1586 if (len > PMAP_TSB_THRESH) {
1587 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len,
1589 tlb_context_demap(dst_pmap);
1591 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE)
1592 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL)
1593 pmap_copy_tte(src_pmap, dst_pmap, tp, va);
1594 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1);
1596 vm_page_unlock_queues();
1597 PMAP_UNLOCK(src_pmap);
1598 PMAP_UNLOCK(dst_pmap);
1602 pmap_zero_page(vm_page_t m)
1608 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1609 ("pmap_zero_page: fake page"));
1610 PMAP_STATS_INC(pmap_nzero_page);
1611 pa = VM_PAGE_TO_PHYS(m);
1612 if (m->md.color == -1) {
1613 PMAP_STATS_INC(pmap_nzero_page_nc);
1614 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1615 } else if (m->md.color == DCACHE_COLOR(pa)) {
1616 PMAP_STATS_INC(pmap_nzero_page_c);
1617 va = TLB_PHYS_TO_DIRECT(pa);
1618 cpu_block_zero((void *)va, PAGE_SIZE);
1620 PMAP_STATS_INC(pmap_nzero_page_oc);
1621 PMAP_LOCK(kernel_pmap);
1622 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1623 tp = tsb_kvtotte(va);
1624 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1625 tp->tte_vpn = TV_VPN(va, TS_8K);
1626 cpu_block_zero((void *)va, PAGE_SIZE);
1627 tlb_page_demap(kernel_pmap, va);
1628 PMAP_UNLOCK(kernel_pmap);
1633 pmap_zero_page_area(vm_page_t m, int off, int size)
1639 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1640 ("pmap_zero_page_area: fake page"));
1641 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size"));
1642 PMAP_STATS_INC(pmap_nzero_page_area);
1643 pa = VM_PAGE_TO_PHYS(m);
1644 if (m->md.color == -1) {
1645 PMAP_STATS_INC(pmap_nzero_page_area_nc);
1646 aszero(ASI_PHYS_USE_EC, pa + off, size);
1647 } else if (m->md.color == DCACHE_COLOR(pa)) {
1648 PMAP_STATS_INC(pmap_nzero_page_area_c);
1649 va = TLB_PHYS_TO_DIRECT(pa);
1650 bzero((void *)(va + off), size);
1652 PMAP_STATS_INC(pmap_nzero_page_area_oc);
1653 PMAP_LOCK(kernel_pmap);
1654 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1655 tp = tsb_kvtotte(va);
1656 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1657 tp->tte_vpn = TV_VPN(va, TS_8K);
1658 bzero((void *)(va + off), size);
1659 tlb_page_demap(kernel_pmap, va);
1660 PMAP_UNLOCK(kernel_pmap);
1665 pmap_zero_page_idle(vm_page_t m)
1671 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1672 ("pmap_zero_page_idle: fake page"));
1673 PMAP_STATS_INC(pmap_nzero_page_idle);
1674 pa = VM_PAGE_TO_PHYS(m);
1675 if (m->md.color == -1) {
1676 PMAP_STATS_INC(pmap_nzero_page_idle_nc);
1677 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1678 } else if (m->md.color == DCACHE_COLOR(pa)) {
1679 PMAP_STATS_INC(pmap_nzero_page_idle_c);
1680 va = TLB_PHYS_TO_DIRECT(pa);
1681 cpu_block_zero((void *)va, PAGE_SIZE);
1683 PMAP_STATS_INC(pmap_nzero_page_idle_oc);
1684 va = pmap_idle_map + (m->md.color * PAGE_SIZE);
1685 tp = tsb_kvtotte(va);
1686 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1687 tp->tte_vpn = TV_VPN(va, TS_8K);
1688 cpu_block_zero((void *)va, PAGE_SIZE);
1689 tlb_page_demap(kernel_pmap, va);
1694 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
1702 KASSERT((mdst->flags & PG_FICTITIOUS) == 0,
1703 ("pmap_copy_page: fake dst page"));
1704 KASSERT((msrc->flags & PG_FICTITIOUS) == 0,
1705 ("pmap_copy_page: fake src page"));
1706 PMAP_STATS_INC(pmap_ncopy_page);
1707 pdst = VM_PAGE_TO_PHYS(mdst);
1708 psrc = VM_PAGE_TO_PHYS(msrc);
1709 if (msrc->md.color == -1 && mdst->md.color == -1) {
1710 PMAP_STATS_INC(pmap_ncopy_page_nc);
1711 ascopy(ASI_PHYS_USE_EC, psrc, pdst, PAGE_SIZE);
1712 } else if (msrc->md.color == DCACHE_COLOR(psrc) &&
1713 mdst->md.color == DCACHE_COLOR(pdst)) {
1714 PMAP_STATS_INC(pmap_ncopy_page_c);
1715 vdst = TLB_PHYS_TO_DIRECT(pdst);
1716 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1717 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1718 } else if (msrc->md.color == -1) {
1719 if (mdst->md.color == DCACHE_COLOR(pdst)) {
1720 PMAP_STATS_INC(pmap_ncopy_page_dc);
1721 vdst = TLB_PHYS_TO_DIRECT(pdst);
1722 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1725 PMAP_STATS_INC(pmap_ncopy_page_doc);
1726 PMAP_LOCK(kernel_pmap);
1727 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1728 tp = tsb_kvtotte(vdst);
1730 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1731 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1732 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1734 tlb_page_demap(kernel_pmap, vdst);
1735 PMAP_UNLOCK(kernel_pmap);
1737 } else if (mdst->md.color == -1) {
1738 if (msrc->md.color == DCACHE_COLOR(psrc)) {
1739 PMAP_STATS_INC(pmap_ncopy_page_sc);
1740 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1741 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1744 PMAP_STATS_INC(pmap_ncopy_page_soc);
1745 PMAP_LOCK(kernel_pmap);
1746 vsrc = pmap_temp_map_1 + (msrc->md.color * PAGE_SIZE);
1747 tp = tsb_kvtotte(vsrc);
1749 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1750 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1751 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1753 tlb_page_demap(kernel_pmap, vsrc);
1754 PMAP_UNLOCK(kernel_pmap);
1757 PMAP_STATS_INC(pmap_ncopy_page_oc);
1758 PMAP_LOCK(kernel_pmap);
1759 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1760 tp = tsb_kvtotte(vdst);
1762 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1763 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1764 vsrc = pmap_temp_map_2 + (msrc->md.color * PAGE_SIZE);
1765 tp = tsb_kvtotte(vsrc);
1767 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1768 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1769 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1770 tlb_page_demap(kernel_pmap, vdst);
1771 tlb_page_demap(kernel_pmap, vsrc);
1772 PMAP_UNLOCK(kernel_pmap);
1777 * Returns true if the pmap's pv is one of the first
1778 * 16 pvs linked to from this page. This count may
1779 * be changed upwards or downwards in the future; it
1780 * is only necessary that true be returned for a small
1781 * subset of pmaps for proper page aging.
1784 pmap_page_exists_quick(pmap_t pm, vm_page_t m)
1789 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1790 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1793 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1794 if ((tp->tte_data & TD_PV) == 0)
1796 if (TTE_GET_PMAP(tp) == pm)
1805 * Return the number of managed mappings to the given physical page
1809 pmap_page_wired_mappings(vm_page_t m)
1815 if ((m->flags & PG_FICTITIOUS) != 0)
1817 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1818 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
1819 if ((tp->tte_data & (TD_PV | TD_WIRED)) == (TD_PV | TD_WIRED))
1825 * Remove all pages from specified address space, this aids process exit
1826 * speeds. This is much faster than pmap_remove n the case of running down
1827 * an entire address space. Only works for the current pmap.
1830 pmap_remove_pages(pmap_t pm)
1836 * Returns TRUE if the given page has a managed mapping.
1839 pmap_page_is_mapped(vm_page_t m)
1843 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1845 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1846 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
1847 if ((tp->tte_data & TD_PV) != 0)
1853 * Return a count of reference bits for a page, clearing those bits.
1854 * It is not necessary for every reference bit to be cleared, but it
1855 * is necessary that 0 only be returned when there are truly no
1856 * reference bits set.
1858 * XXX: The exact number of bits to check and clear is a matter that
1859 * should be tested and standardized at some point in the future for
1860 * optimal aging of shared pages.
1863 pmap_ts_referenced(vm_page_t m)
1871 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1872 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1875 if ((tp = TAILQ_FIRST(&m->md.tte_list)) != NULL) {
1878 tpn = TAILQ_NEXT(tp, tte_link);
1879 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1880 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
1881 if ((tp->tte_data & TD_PV) == 0)
1883 data = atomic_clear_long(&tp->tte_data, TD_REF);
1884 if ((data & TD_REF) != 0 && ++count > 4)
1886 } while ((tp = tpn) != NULL && tp != tpf);
1892 pmap_is_modified(vm_page_t m)
1896 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1897 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1899 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1900 if ((tp->tte_data & TD_PV) == 0)
1902 if ((tp->tte_data & TD_W) != 0)
1909 * pmap_is_prefaultable:
1911 * Return whether or not the specified virtual address is elgible
1915 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1922 pmap_clear_modify(vm_page_t m)
1927 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1928 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1930 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1931 if ((tp->tte_data & TD_PV) == 0)
1933 data = atomic_clear_long(&tp->tte_data, TD_W);
1934 if ((data & TD_W) != 0)
1935 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1940 pmap_clear_reference(vm_page_t m)
1945 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1946 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1948 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1949 if ((tp->tte_data & TD_PV) == 0)
1951 data = atomic_clear_long(&tp->tte_data, TD_REF);
1952 if ((data & TD_REF) != 0)
1953 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1958 pmap_remove_write(vm_page_t m)
1963 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1964 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1965 (m->flags & PG_WRITEABLE) == 0)
1967 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1968 if ((tp->tte_data & TD_PV) == 0)
1970 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
1971 if ((data & TD_W) != 0) {
1973 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1976 vm_page_flag_clear(m, PG_WRITEABLE);
1980 pmap_mincore(pmap_t pm, vm_offset_t addr)
1988 * Activate a user pmap. The pmap must be activated before its address space
1989 * can be accessed in any way.
1992 pmap_activate(struct thread *td)
1998 vm = td->td_proc->p_vmspace;
1999 pm = vmspace_pmap(vm);
2001 mtx_lock_spin(&sched_lock);
2003 context = PCPU_GET(tlb_ctx);
2004 if (context == PCPU_GET(tlb_ctx_max)) {
2006 context = PCPU_GET(tlb_ctx_min);
2008 PCPU_SET(tlb_ctx, context + 1);
2010 pm->pm_context[curcpu] = context;
2011 pm->pm_active |= PCPU_GET(cpumask);
2014 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb);
2015 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb);
2016 stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) &
2017 TLB_CXR_PGSZ_MASK) | context);
2020 mtx_unlock_spin(&sched_lock);
2024 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
2030 * Increase the starting virtual address of the given mapping if a
2031 * different alignment might result in more superpage mappings.
2034 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
2035 vm_offset_t *addr, vm_size_t size)