2 * Copyright (c) 2006 Kip Macy <kmacy@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
31 #include <machine/asm.h>
32 #include <machine/asi.h>
33 #include <machine/asmacros.h>
34 #include <machine/hypervisorvar.h>
35 #include <machine/pstate.h>
39 * Section 9 API Versioning
44 * request and check for a version of the hypervisor apis
45 * which may be compatible
47 * arg0 api_group (%o0)
48 * arg1 major_number (%o1)
49 * arg2 req_minor_number (%o2)
52 * ret1 act_minor_number (%o1)
55 ENTRY(api_set_version)
56 mov API_SET_VERSION, %o5
63 * retrieve the major and minor number of the most recently
64 * successfully negotiated API
66 * arg0 api_group (%o0)
69 * ret1 major_number (%o1)
70 * ret2 major_number (%o2)
73 ENTRY(api_get_version)
76 mov API_GET_VERSION, %o5
84 * Section 10 Domain Services
89 * stop all CPUs in the virtual machine domain and place them
90 * in the stopped state
92 * arg0 exit_code (%o0)
103 * copy the most current machine description into buffer
104 * upon success or EINVAL the service returns the actual
105 * size of the machine description
124 * execute a software initiated reset of a virtual machine domain
135 * report the guests soft state to the hypervisor
137 * arg0 soft_state (%o0)
138 * arg1 soft_state_desc_ptr (%o1)
143 ENTRY(hv_mach_set_soft_state)
144 mov MACH_SET_SOFT_STATE, %o5
148 END(hv_mach_set_soft_state)
151 * retrieve the current value of the guest's software state
153 * arg0 soft_desc_ptr (%o0)
156 * arg1 soft_state (%o1)
159 ENTRY(hv_mach_get_soft_state)
161 mov MACH_SET_SOFT_STATE, %o5
165 END(hv_mach_get_soft_state)
168 * set a watchdog timer, 0 disables, upon success
169 * time_remaining contains the time previously remaining
174 * ret1 time_remaining (%o1)
177 ENTRY(hv_mach_watchdog)
179 mov MACH_WATCHDOG, %o5
186 END(hv_mach_watchdog)
189 * Section 11 CPU Services
194 * start CPU with id cpuid with pc in %pc and real trap base address
200 * arg3 target_arg0 (%o3)
213 * stop CPU with id cpuid
228 * set the real trap base address of the local cpu to rtba
229 * upon success the previous_rtba contains the address of the
235 * ret1 previous_rtba(%o1)
238 ENTRY(hv_cpu_set_rtba)
240 mov CPU_SET_RTBA, %o5
248 * return the current real trap base address
254 ENTRY(hv_cpu_get_rtba)
255 mov CPU_GET_RTBA, %o5
262 * suspend execution on current cpu
275 * configure queue of size nentries to be placed at base raddr
278 * arg1 base raddr (%o1)
279 * arg2 nentries (%o2)
292 * return configuration of queue queue
297 * ret1 base raddr (%o1)
298 * ret2 nentries (%o2)
305 * send cpu mondo interrupt to cpulist
308 * arg1 cpu list ra (%o1)
309 * arg2 mondo data ra(%o2)
314 ENTRY(hv_cpu_mondo_send)
315 ldx [PCPU(MONDO_DATA_RA)], %o2
316 mov CPU_MONDO_SEND, %o5
320 END(hv_cpu_mondo_send)
323 * return the hypervisor id for the current cpu
339 * retrieve the current state of cpu cpuid
357 * Section 12 MMU Services
362 * set the tsb(s) for the current cpu for context 0
370 ENTRY(hv_mmu_tsb_ctx0)
371 mov MMU_TSB_CTX0, %o5
378 * set the tsb(s) for the current cpu for non-zero contexts
386 ENTRY(hv_mmu_tsb_ctxnon0)
387 mov MMU_TSB_CTXNON0, %o5
391 END(hv_mmu_tsb_ctxnon0)
394 * demap any page mapping of virtual address vaddr in context ctx
396 * arg0 reserved (%o0)
397 * arg1 reserved (%o1)
405 ENTRY(hv_mmu_demap_page)
406 mov MMU_DEMAP_PAGE, %o5
410 END(hv_mmu_demap_page)
413 * demap all non-permanent virtual address mappings in context ctx
415 * arg0 reserved (%o0)
416 * arg1 reserved (%o1)
423 ENTRY(hv_mmu_demap_ctx)
424 mov MMU_DEMAP_CTX, %o5
428 END(hv_mmu_demap_ctx)
431 * demap all non-permanent virtual address mappings for the current
434 * arg0 reserved (%o0)
435 * arg1 reserved (%o1)
441 ENTRY(hv_mmu_demap_all)
442 mov MMU_DEMAP_ALL, %o5
446 END(hv_mmu_demap_all)
449 * create a non-permanent mapping for the calling virtual cpu
459 ENTRY(hv_mmu_map_addr)
460 mov MMU_MAP_ADDR, %o5
467 * create a permanent mapping for the calling virtual cpu
470 * arg1 reserved (%o1)
477 ENTRY(hv_mmu_map_perm_addr)
478 mov MMU_MAP_PERM_ADDR, %o5
482 END(hv_mmu_map_perm_addr)
485 * demap virtual address vaddr in context ctx on current virtual cpu
494 ENTRY(hv_mmu_unmap_addr)
495 mov MMU_UNMAP_ADDR, %o5
499 END(hv_mmu_unmap_addr)
502 * demap any permanent mapping at virtual address vaddr on current virtual cpu
505 * arg1 reserved (%o1)
511 ENTRY(hv_mmu_unmap_perm_addr)
514 mov MMU_UNMAP_PERM_ADDR, %o5
518 END(hv_mmu_unmap_perm_addr)
521 * configure the MMU fault status area for the current virtual cpu
526 * ret1 prev_raddr (%o1)
529 ENTRY(hv_mmu_fault_area_conf)
531 mov MMU_FAULT_AREA_CONF, %o5
535 END(hv_mmu_fault_area_conf)
538 * enable or disable virtual address translation for the current virtual cpu
540 * arg0 enable_flag (%o0)
541 * arg1 return_target (%o1)
554 * return the TSB configuration as previously defined by mmu_tsb_ctx0
557 * arg1 buffer_ra (%o1)
563 ENTRY(hv_mmu_tsb_ctx0_info)
565 mov MMU_TSB_CTX0_INFO, %o5
569 END(hv_mmu_tsb_ctx0_info)
572 * return the TSB configuration as previously defined by mmu_tsb_ctxnon0
575 * arg1 buffer_ra (%o1)
581 ENTRY(hv_mmu_tsb_ctxnon0_info)
583 mov MMU_TSB_CTXNON0_INFO, %o5
587 END(hv_mmu_tsb_ctxnon0_info)
590 * return the MMU fault status area defined for the current virtual cpu
596 ENTRY(hv_mmu_fault_area_info)
598 mov MMU_FAULT_AREA_INFO, %o5
603 END(hv_mmu_fault_area_info)
606 * Section 13 Cache and Memory Services
611 * zero from raddr to raddr+length-1
617 * ret1 length scrubbed (%o1)
629 * for the memory address range from raddr to raddr+length-1
630 * for the next access within that range from main system memory
636 * ret1 length synced (%o1)
648 * Section 14 Device Interrupt Services
653 * converts a device specific interrupt number given by
654 * devhandle and devino to a system specific ino (sysino)
656 * arg0 devhandle (%o0)
663 ENTRY(hv_intr_devino_to_sysino)
664 mov INTR_DEVINO2SYSINO, %o5
668 END(hv_intr_devino_to_sysino)
671 * return intr enabled state
676 * ret1 intr_enabled (%o1)
679 ENTRY(hv_intr_getenabled)
681 mov INTR_GETENABLED, %o5
685 END(hv_intr_getenabled)
688 * set intr enabled state
691 * arg1 intr_enabled (%o1)
696 ENTRY(hv_intr_setenabled)
697 mov INTR_SETENABLED, %o5
701 END(hv_intr_setenabled)
704 * return current state of the interrupt given
710 * ret1 intr_state (%o1)
713 ENTRY(hv_intr_getstate)
715 mov INTR_GETSTATE, %o5
719 END(hv_intr_getstate)
722 * set the current state of the interrupt given
726 * arg1 intr_state (%o1)
731 ENTRY(hv_intr_setstate)
732 mov INTR_SETSTATE, %o5
736 END(hv_intr_setstate)
739 * return the cpuid that is the current target of the
740 * interrupt given by the sysino
748 ENTRY(hv_intr_gettarget)
750 mov INTR_GETTARGET, %o5
754 END(hv_intr_gettarget)
757 * set the target to cpuid that for the
758 * interrupt given by the sysino
766 ENTRY(hv_intr_settarget)
767 mov INTR_SETTARGET, %o5
771 END(hv_intr_settarget)
774 * get the cookie value that will be delivered
775 * in word 0 of a dev_mondo packet to a guest
777 * arg0 devhandle (%o0)
781 * ret1 cookie_value (%o1)
784 ENTRY(hv_vintr_getcookie)
785 mov VINTR_GETCOOKIE, %o5
789 END(hv_vintr_getcookie)
792 * set the cookie value that will be delivered
793 * in word 0 of a dev_mondo packet to a guest
795 * arg0 devhandle (%o0)
797 * ret2 cookie_value (%o2)
802 ENTRY(hv_vintr_setcookie)
803 mov VINTR_SETCOOKIE, %o5
807 END(hv_vintr_setcookie)
810 * get the enabled status of the interrupt
813 * arg0 devhandle (%o0)
817 * ret1 intr_enabled (%o1)
820 ENTRY(hv_vintr_getenabled)
821 mov VINTR_GETENABLED, %o5
825 END(hv_vintr_getenabled)
828 * set the enabled status of the interrupt
831 * arg0 devhandle (%o0)
833 * arg2 intr_enabled (%o2)
838 ENTRY(hv_vintr_setenabled)
839 mov VINTR_SETENABLED, %o5
843 END(hv_vintr_setenabled)
846 * get the current state of the interrupt
849 * arg0 devhandle (%o0)
853 * ret1 intr_state (%o1)
856 ENTRY(hv_vintr_getstate)
857 mov VINTR_GETSTATE, %o5
861 END(hv_vintr_getstate)
864 * set the current state of the interrupt
867 * arg0 devhandle (%o0)
869 * arg2 intr_state (%o2)
874 ENTRY(hv_vintr_setstate)
875 mov VINTR_SETSTATE, %o5
879 END(hv_vintr_setstate)
882 * get the cpuid that is the current target
883 * of the interrupt defined by devino
885 * arg0 devhandle (%o0)
892 ENTRY(hv_vintr_gettarget)
893 mov VINTR_GETTARGET, %o5
897 END(hv_vintr_gettarget)
900 * set the cpuid that is the current target
901 * of the interrupt defined by devino
903 * arg0 devhandle (%o0)
910 ENTRY(hv_vintr_settarget)
911 mov VINTR_SETTARGET, %o5
915 END(hv_vintr_settarget)
919 * Section 15 Time of Day Services
924 * get the current time of day
927 * ret1 time-of-day (%o1)
939 * set the current time-of-day
953 * Section 16 Console Services
958 * return a character from the console device
961 * ret1 character (%o1)
964 ENTRY(hv_cons_getchar)
966 mov CONS_GETCHAR, %o5
987 * send a character to the console device
993 ENTRY(hv_cons_putchar)
994 mov CONS_PUTCHAR, %o5
1001 * write characters in raddr to console
1006 * ret1 char written (%o1)
1009 ENTRY(hv_cons_write)
1013 brnz,a %o0, 1f ! failure, just return error
1021 * read up to size characters from console in to raddr
1026 * ret1 char written (%o1)
1033 brnz,a %o0, 1f ! failure, just return error
1051 * Section 17 Core Dump Services
1056 * declare a domain dump buffer to the hypervisor
1061 * ret1 required size of the dump buffer (%o1)
1064 ENTRY(hv_dump_buf_update)
1065 mov DUMP_BUF_UPDATE, %o5
1069 END(hv_dump_buf_update)
1072 * return the currently configured dump buffer description
1075 * ret1 ra of the current dump buffer (%o1)
1076 * ret2 size of the current dump buffer (%o2)
1079 ENTRY(hv_dump_buf_info)
1082 mov DUMP_BUF_INFO, %o5
1087 END(hv_dump_buf_info)
1090 * Section 18 Trap Trace Services
1095 * arg0 RA base of buffer (%o0)
1096 * arg1 buf size in no. of entries (%o1)
1099 * ret1 minimum size in no. of entries on failure,
1100 * actual size in no. of entries on success (%o1)
1103 ENTRY(hv_ttrace_buf_conf)
1104 mov TTRACE_BUF_CONF, %o5
1108 END(hv_ttrace_buf_conf)
1111 * return the size and location of a previously declare
1115 * ret1 RA base of buffer (%o1)
1116 * ret2 size in no. of entries (%o2)
1119 ENTRY(hv_ttrace_buf_info)
1122 mov TTRACE_BUF_INFO, %o5
1127 END(hv_ttrace_buf_info)
1130 * enable / disable trap tracing
1132 * arg0 enable / disable (%o0)
1135 * ret1 previous enable state (%o1)
1138 ENTRY(hv_ttrace_enable)
1140 mov TTRACE_ENABLE, %o5
1144 END(hv_ttrace_enable)
1148 * arg0 enable/ freeze (%o0)
1151 * ret1 previous freeze state (%o1)
1154 ENTRY(hv_ttrace_freeze)
1156 mov TTRACE_FREEZE, %o5
1160 END(hv_ttrace_freeze)
1163 * add an entry to the trap trace buffer
1165 * arg0 tag (16-bits) (%o0)
1166 * arg1 data word 0 (%o1)
1167 * arg2 data word 1 (%o2)
1168 * arg3 data word 2 (%o3)
1169 * arg4 data word 3 (%o4)
1174 ENTRY(hv_ttrace_addentry)
1178 END(hv_ttrace_addentry)
1181 * Section 19 Logical Domain Channel Services
1186 * configure ldc tx queue
1189 * arg1 base_raddr (%o1)
1190 * arg2 nentries (%o2)
1195 ENTRY(hv_ldc_tx_qconf)
1196 mov LDC_TX_QCONF, %o5
1200 END(hv_ldc_tx_qconf)
1203 * return configuration info for ldc tx queue
1208 * ret1 base_raddr (%o1)
1209 * ret2 nentries (%o2)
1212 ENTRY(hv_ldc_tx_qinfo)
1215 mov LDC_TX_QINFO, %o5
1223 END(hv_ldc_tx_qinfo)
1226 * get the state of the ldc tx queue
1231 * ret1 head_offset (%o1)
1232 * ret2 tail_offset (%o2)
1233 * ret3 channel_state (%o3)
1236 ENTRY(hv_ldc_tx_get_state)
1238 mov LDC_TX_GET_STATE, %o5
1247 END(hv_ldc_tx_get_state)
1250 * update the tail pointer of the ldc tx queue
1253 * arg1 tail_offset (%o1)
1258 ENTRY(hv_ldc_tx_set_qtail)
1259 mov LDC_TX_SET_QTAIL, %o5
1263 END(hv_ldc_tx_set_qtail)
1266 * configure ldc rx queue
1269 * arg1 base_raddr (%o1)
1270 * arg2 nentries (%o2)
1275 ENTRY(hv_ldc_rx_qconf)
1276 mov LDC_RX_QCONF, %o5
1280 END(hv_ldc_rx_qconf)
1283 * return configuration info for ldc rx queue
1288 * ret1 base_raddr (%o1)
1289 * ret2 nentries (%o2)
1292 ENTRY(hv_ldc_rx_qinfo)
1295 mov LDC_RX_QINFO, %o5
1303 END(hv_ldc_rx_qinfo)
1306 * get the state of the ldc rx queue
1311 * ret1 head_offset (%o1)
1312 * ret2 tail_offset (%o2)
1313 * ret3 channel_state (%o3)
1316 ENTRY(hv_ldc_rx_get_state)
1318 mov LDC_RX_GET_STATE, %o5
1327 END(hv_ldc_rx_get_state)
1330 * update the head pointer of the ldc rx queue
1333 * arg1 head_offset (%o1)
1338 ENTRY(hv_ldc_rx_set_qhead)
1339 mov LDC_RX_SET_QHEAD, %o5
1343 END(hv_ldc_rx_set_qhead)
1346 * declare an export map table
1348 * arg0 channel (%o0)
1349 * arg1 base_ra (%o1)
1350 * arg2 nentries (%o2)
1355 ENTRY(hv_ldc_set_map_table)
1356 mov LDC_SET_MAPTABLE, %o5
1360 END(hv_ldc_set_map_table)
1363 * retrieve the current map table configuration associated
1364 * with the given domain channel
1366 * arg0 channel (%o0)
1369 * ret1 base_ra (%o1)
1370 * ret2 nentries (%o2)
1373 ENTRY(hv_ldc_get_map_table)
1376 mov LDC_GET_MAPTABLE, %o5
1381 END(hv_ldc_get_map_table)
1384 * copy data into or out of a local memory region form or to
1385 * the logical domain at the other end of the specified domain
1388 * arg0 channel (%o0)
1395 * ret1 ret_length (%o1)
1402 * attempt to map into the local guest's real address space the
1403 * page identified by the shared memory cookie
1405 * arg0 channel (%o0)
1424 * attempt unmap from the local guest's real address space the imported
1425 * page mapped at the real address raddr
1440 * forcibly unmap from a remote guest's real address space a page
1441 * previously exported by the local guest
1443 * arg0 channel (%o0)
1445 * arg2 revoke_cookie (%o2)
1450 ENTRY(hv_ldc_revoke)
1458 * Section 20 PCI I/O Services
1463 * create iommu mappings in the device defined by devhandle
1465 * arg0 devhandle (%o0)
1468 * arg3 io_attributes (%o3)
1469 * arg4 io_page_list_p (%o4)
1472 * ret1 nttes_mapped (%o1)
1475 ENTRY(hv_pci_iommu_map)
1476 save %sp, -CCFSZ, %sp
1482 mov PCI_IOMMU_MAP, %o5
1490 END(hv_pci_iommu_map)
1493 * demap and flush iommu mappings in the device defined by devhandle
1495 * arg0 devhandle (%o0)
1500 * ret1 nttes_demapped (%o1)
1503 ENTRY(hv_pci_iommu_demap)
1504 mov PCI_IOMMU_DEMAP, %o5
1510 END(hv_pci_iommu_demap)
1513 * read and return the mapping in the device defined by devhandle
1515 * arg0 devhandle (%o0)
1519 * ret1 io_attributes (%o1)
1523 ENTRY(hv_pci_iommu_getmap)
1526 mov PCI_IOMMU_GETMAP, %o5
1534 END(hv_pci_iommu_getmap)
1537 * create a "special" mapping in the device given by devhandle
1539 * arg0 devhandle (%o0)
1541 * arg2 io_attributes (%o2)
1544 * ret1 io_addr (%o1)
1547 ENTRY(hv_pci_iommu_getbypass)
1548 mov PCI_IOMMU_GETBYPASS, %o5
1555 END(hv_pci_iommu_getbypass)
1558 * read PCI configuration space for adapter specified by devhandle
1560 * arg0 devhandle (%o0)
1561 * arg1 pci_device (%o1)
1562 * arg2 pci_config_offset(%o2)
1566 * ret1 error_flag (%o1)
1570 ENTRY(hv_pci_config_get)
1571 mov PCI_CONFIG_GET, %o5
1579 END(hv_pci_config_get)
1582 * write PCI config space for the PCI adapter
1583 * specified by devhandle
1585 * arg0 devhandle (%o0)
1586 * arg1 pci_device (%o1)
1587 * arg2 pci_config_offset(%o2)
1592 * ret1 error_flag (%o1)
1595 ENTRY(hv_pci_config_put)
1596 mov PCI_CONFIG_PUT, %o5
1600 END(hv_pci_config_put)
1603 * read the io-address given by devhandle, raddr, and size
1605 * arg0 devhandle (%o0)
1610 * ret1 error_flag (%o1)
1626 * attempt to write data to the io-address
1627 * specified by devhandle, raddr, and size
1629 * arg0 devhandle (%o0)
1633 * arg4 pci_device (%o4)
1636 * ret1 error_flag (%o1)
1640 save %sp, -CCFSZ, %sp
1657 * attempt to write data to the io-address
1658 * specified by devhandle, raddr, and size
1660 * arg0 devhandle (%o0)
1663 * arg3 io_sync_direction(%o3)
1666 * ret1 nsynced (%o1)
1669 ENTRY(hv_pci_dma_sync)
1670 mov PCI_DMA_SYNC, %o5
1677 END(hv_pci_dma_sync)
1680 * Section 21 MSI Services
1684 ENTRY(hv_pci_msiq_conf)
1685 END(hv_pci_msiq_conf)
1687 ENTRY(hv_pci_msiq_info)
1688 END(hv_pci_msiq_info)
1690 ENTRY(hv_pci_msiq_getvalid)
1691 END(hv_pci_msiq_getvalid)
1693 ENTRY(hv_pci_msiq_setvalid)
1694 END(hv_pci_msiq_setvalid)
1696 ENTRY(hv_pci_msiq_getstate)
1697 END(hv_pci_msiq_getstate)
1699 ENTRY(hv_pci_msiq_setstate)
1700 END(hv_pci_msiq_setstate)
1702 ENTRY(hv_pci_msiq_gethead)
1703 END(hv_pci_msiq_gethead)
1705 ENTRY(hv_pci_msiq_sethead)
1706 END(hv_pci_msiq_sethead)
1708 ENTRY(hv_pci_msiq_gettail)
1709 END(hv_pci_msiq_gettail)
1711 ENTRY(hv_pci_msi_getvalid)
1712 END(hv_pci_msi_getvalid)
1714 ENTRY(hv_pci_msi_setvalid)
1715 END(hv_pci_msi_setvalid)
1717 ENTRY(hv_pci_msi_getmsiq)
1718 END(hv_pci_msi_getmsiq)
1720 ENTRY(hv_pci_msi_setmsiq)
1721 END(hv_pci_msi_setmsiq)
1723 ENTRY(hv_pci_msi_getstate)
1724 END(hv_pci_msi_getstate)
1726 ENTRY(hv_pci_msi_setstate)
1727 END(hv_pci_msi_setstate)
1729 ENTRY(hv_pci_msg_getmsiq)
1730 END(hv_pci_msg_getmsiq)
1732 ENTRY(hv_pci_msg_setmsiq)
1733 END(hv_pci_msg_setmsiq)
1735 ENTRY(hv_pci_msg_getvalid)
1736 END(hv_pci_msg_getvalid)
1738 ENTRY(hv_pci_msg_setvalid)
1739 END(hv_pci_msg_setvalid)
1742 * Section 22 UltraSPARC T1 Performance Counters
1748 * read the value of the DRAM/JBus performance register as selected by
1749 * the perfreg argument
1751 * arg0 perfreg (%o0)
1757 ENTRY(hv_niagara_get_perfreg)
1759 mov NIAGARA_GET_PERFREG, %o5
1763 END(hv_niagara_get_perfreg)
1766 * set the value of the DRAM/JBus performance register as selected by
1767 * the perfreg argument
1769 * arg0 perfreg (%o0)
1775 ENTRY(hv_niagara_set_perfreg)
1776 mov NIAGARA_SET_PERFREG, %o5
1780 END(hv_niagara_set_perfreg)
1783 * Section 23 UltraSPARC T1 MMU Statistics Counters
1788 * enable MMU statistics collection and supply the buffer to deposit the
1789 * results for the current virtual cpu
1794 * ret1 prev_raddr (%o1)
1797 ENTRY(hv_niagara_mmustat_conf)
1799 mov NIAGARA_MMUSTAT_CONF, %o5
1803 END(hv_niagara_mmustat_conf)
1806 * query the status and the real address for the currently configured buffer
1812 ENTRY(hv_niagara_mmustat_info)
1814 mov NIAGARA_MMUSTAT_INFO, %o5
1818 END(hv_niagara_mmustat_info)
1821 * Simulator Services
1825 ENTRY(hv_magic_trap_on)
1829 END(hv_magic_trap_on)
1831 ENTRY(hv_magic_trap_off)
1835 END(hv_magic_trap_off)