contrib/llvm/lib/CodeGen/ScheduleDAGEmit.cpp

   1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This implements the Emit routines for the ScheduleDAG class, which creates
  11 // MachineInstrs according to the computed schedule.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "pre-RA-sched"
  16 #include "llvm/CodeGen/ScheduleDAG.h"
  17 #include "llvm/CodeGen/MachineConstantPool.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/Target/TargetData.h"
  22 #include "llvm/Target/TargetMachine.h"
  23 #include "llvm/Target/TargetInstrInfo.h"
  24 #include "llvm/Target/TargetLowering.h"
  25 #include "llvm/ADT/Statistic.h"
  26 #include "llvm/Support/CommandLine.h"
  27 #include "llvm/Support/Debug.h"
  28 #include "llvm/Support/MathExtras.h"
  29 using namespace llvm;
  30
  31 void ScheduleDAG::EmitNoop() {
  32   TII->insertNoop(*BB, InsertPos);
  33 }
  34
  35 void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
  36                                   DenseMap<SUnit*, unsigned> &VRBaseMap) {
  37   for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
  38        I != E; ++I) {
  39     if (I->isCtrl()) continue;  // ignore chain preds
  40     if (I->getSUnit()->CopyDstRC) {
  41       // Copy to physical register.
  42       DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
  43       assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
  44       // Find the destination physical register.
  45       unsigned Reg = 0;
  46       for (SUnit::const_succ_iterator II = SU->Succs.begin(),
  47              EE = SU->Succs.end(); II != EE; ++II) {
  48         if (II->isCtrl()) continue;  // ignore chain preds
  49         if (II->getReg()) {
  50           Reg = II->getReg();
  51           break;
  52         }
  53       }
  54       BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
  55         .addReg(VRI->second);
  56     } else {
  57       // Copy from physical register.
  58       assert(I->getReg() && "Unknown physical register!");
  59       unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
  60       bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
  61       (void)isNew; // Silence compiler warning.
  62       assert(isNew && "Node emitted out of order - early");
  63       BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
  64         .addReg(I->getReg());
  65     }
  66     break;
  67   }
  68 }