1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetFrameLowering.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/LLVMContext.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize {
50 const TargetMachine &TM;
51 const TargetLowering &TLI;
54 // Libcall insertion helpers.
56 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
57 /// legalized. We use this to ensure that calls are properly serialized
58 /// against each other, including inserted libcalls.
59 SDValue LastCALLSEQ_END;
61 /// IsLegalizingCall - This member is used *only* for purposes of providing
62 /// helpful assertions that a libcall isn't created while another call is
63 /// being legalized (which could lead to non-serialized call sequences).
64 bool IsLegalizingCall;
66 /// LegalizedNodes - For nodes that are of legal width, and that have more
67 /// than one use, this map indicates what regularized operand to use. This
68 /// allows us to avoid legalizing the same thing more than once.
69 DenseMap<SDValue, SDValue> LegalizedNodes;
71 void AddLegalizedOperand(SDValue From, SDValue To) {
72 LegalizedNodes.insert(std::make_pair(From, To));
73 // If someone requests legalization of the new node, return itself.
75 LegalizedNodes.insert(std::make_pair(To, To));
77 // Transfer SDDbgValues.
78 DAG.TransferDbgValues(From, To);
82 explicit SelectionDAGLegalize(SelectionDAG &DAG);
87 /// LegalizeOp - Return a legal replacement for the given operation, with
88 /// all legal operands.
89 SDValue LegalizeOp(SDValue O);
91 SDValue OptimizeFloatStore(StoreSDNode *ST);
93 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
94 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
95 /// is necessary to spill the vector being inserted into to memory, perform
96 /// the insert there, and then read the result back.
97 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
98 SDValue Idx, DebugLoc dl);
99 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
100 SDValue Idx, DebugLoc dl);
102 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
103 /// performs the same shuffe in terms of order or result bytes, but on a type
104 /// whose vector element type is narrower than the original shuffle type.
105 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
106 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
107 SDValue N1, SDValue N2,
108 SmallVectorImpl<int> &Mask) const;
110 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
111 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
113 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
116 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
117 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
118 unsigned NumOps, bool isSigned, DebugLoc dl);
120 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
121 SDNode *Node, bool isSigned);
122 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
123 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
124 RTLIB::Libcall Call_PPCF128);
125 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
126 RTLIB::Libcall Call_I8,
127 RTLIB::Libcall Call_I16,
128 RTLIB::Libcall Call_I32,
129 RTLIB::Libcall Call_I64,
130 RTLIB::Libcall Call_I128);
131 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
133 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
134 SDValue ExpandBUILD_VECTOR(SDNode *Node);
135 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
136 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
137 SmallVectorImpl<SDValue> &Results);
138 SDValue ExpandFCOPYSIGN(SDNode *Node);
139 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
141 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
143 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
146 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
147 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
149 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
150 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
151 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
153 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
155 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
156 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
160 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
161 /// performs the same shuffe in terms of order or result bytes, but on a type
162 /// whose vector element type is narrower than the original shuffle type.
163 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
165 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
166 SDValue N1, SDValue N2,
167 SmallVectorImpl<int> &Mask) const {
168 unsigned NumMaskElts = VT.getVectorNumElements();
169 unsigned NumDestElts = NVT.getVectorNumElements();
170 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
172 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
174 if (NumEltsGrowth == 1)
175 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
177 SmallVector<int, 8> NewMask;
178 for (unsigned i = 0; i != NumMaskElts; ++i) {
180 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
182 NewMask.push_back(-1);
184 NewMask.push_back(Idx * NumEltsGrowth + j);
187 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
188 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
189 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
192 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
193 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
197 void SelectionDAGLegalize::LegalizeDAG() {
198 LastCALLSEQ_END = DAG.getEntryNode();
199 IsLegalizingCall = false;
201 // The legalize process is inherently a bottom-up recursive process (users
202 // legalize their uses before themselves). Given infinite stack space, we
203 // could just start legalizing on the root and traverse the whole graph. In
204 // practice however, this causes us to run out of stack space on large basic
205 // blocks. To avoid this problem, compute an ordering of the nodes where each
206 // node is only legalized after all of its operands are legalized.
207 DAG.AssignTopologicalOrder();
208 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
209 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
210 LegalizeOp(SDValue(I, 0));
212 // Finally, it's possible the root changed. Get the new root.
213 SDValue OldRoot = DAG.getRoot();
214 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
215 DAG.setRoot(LegalizedNodes[OldRoot]);
217 LegalizedNodes.clear();
219 // Remove dead nodes now.
220 DAG.RemoveDeadNodes();
224 /// FindCallEndFromCallStart - Given a chained node that is part of a call
225 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
226 static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
227 // Nested CALLSEQ_START/END constructs aren't yet legal,
228 // but we can DTRT and handle them correctly here.
229 if (Node->getOpcode() == ISD::CALLSEQ_START)
231 else if (Node->getOpcode() == ISD::CALLSEQ_END) {
236 if (Node->use_empty())
237 return 0; // No CallSeqEnd
239 // The chain is usually at the end.
240 SDValue TheChain(Node, Node->getNumValues()-1);
241 if (TheChain.getValueType() != MVT::Other) {
242 // Sometimes it's at the beginning.
243 TheChain = SDValue(Node, 0);
244 if (TheChain.getValueType() != MVT::Other) {
245 // Otherwise, hunt for it.
246 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
247 if (Node->getValueType(i) == MVT::Other) {
248 TheChain = SDValue(Node, i);
252 // Otherwise, we walked into a node without a chain.
253 if (TheChain.getValueType() != MVT::Other)
258 for (SDNode::use_iterator UI = Node->use_begin(),
259 E = Node->use_end(); UI != E; ++UI) {
261 // Make sure to only follow users of our token chain.
263 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
264 if (User->getOperand(i) == TheChain)
265 if (SDNode *Result = FindCallEndFromCallStart(User, depth))
271 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
272 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
273 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
275 assert(Node && "Didn't find callseq_start for a call??");
276 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
277 Node = Node->getOperand(0).getNode();
278 assert(Node->getOperand(0).getValueType() == MVT::Other &&
279 "Node doesn't have a token chain argument!");
280 switch (Node->getOpcode()) {
283 case ISD::CALLSEQ_START:
288 case ISD::CALLSEQ_END:
296 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
297 /// see if any uses can reach Dest. If no dest operands can get to dest,
298 /// legalize them, legalize ourself, and return false, otherwise, return true.
300 /// Keep track of the nodes we fine that actually do lead to Dest in
301 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
303 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
304 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
305 if (N == Dest) return true; // N certainly leads to Dest :)
307 // If we've already processed this node and it does lead to Dest, there is no
308 // need to reprocess it.
309 if (NodesLeadingTo.count(N)) return true;
311 // If the first result of this node has been already legalized, then it cannot
313 if (LegalizedNodes.count(SDValue(N, 0))) return false;
315 // Okay, this node has not already been legalized. Check and legalize all
316 // operands. If none lead to Dest, then we can legalize this node.
317 bool OperandsLeadToDest = false;
318 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
319 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
320 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
323 if (OperandsLeadToDest) {
324 NodesLeadingTo.insert(N);
328 // Okay, this node looks safe, legalize it and return false.
329 LegalizeOp(SDValue(N, 0));
333 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
334 /// a load from the constant pool.
335 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
336 SelectionDAG &DAG, const TargetLowering &TLI) {
338 DebugLoc dl = CFP->getDebugLoc();
340 // If a FP immediate is precise when represented as a float and if the
341 // target can do an extending load from float to double, we put it into
342 // the constant pool as a float, even if it's is statically typed as a
343 // double. This shrinks FP constants and canonicalizes them for targets where
344 // an FP extending load is the same cost as a normal load (such as on the x87
345 // fp stack or PPC FP unit).
346 EVT VT = CFP->getValueType(0);
347 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
349 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
350 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
351 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
356 while (SVT != MVT::f32) {
357 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
358 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
359 // Only do this if the target has a native EXTLOAD instruction from
361 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
362 TLI.ShouldShrinkFPConstant(OrigVT)) {
363 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
364 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
370 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
371 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
373 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
375 CPIdx, MachinePointerInfo::getConstantPool(),
376 VT, false, false, Alignment);
377 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
378 MachinePointerInfo::getConstantPool(), false, false,
382 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
384 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
385 const TargetLowering &TLI) {
386 SDValue Chain = ST->getChain();
387 SDValue Ptr = ST->getBasePtr();
388 SDValue Val = ST->getValue();
389 EVT VT = Val.getValueType();
390 int Alignment = ST->getAlignment();
391 DebugLoc dl = ST->getDebugLoc();
392 if (ST->getMemoryVT().isFloatingPoint() ||
393 ST->getMemoryVT().isVector()) {
394 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
395 if (TLI.isTypeLegal(intVT)) {
396 // Expand to a bitconvert of the value to the integer type of the
397 // same size, then a (misaligned) int store.
398 // FIXME: Does not handle truncating floating point stores!
399 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
400 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
401 ST->isVolatile(), ST->isNonTemporal(), Alignment);
403 // Do a (aligned) store to a stack slot, then copy from the stack slot
404 // to the final destination using (unaligned) integer loads and stores.
405 EVT StoredVT = ST->getMemoryVT();
407 TLI.getRegisterType(*DAG.getContext(),
408 EVT::getIntegerVT(*DAG.getContext(),
409 StoredVT.getSizeInBits()));
410 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
411 unsigned RegBytes = RegVT.getSizeInBits() / 8;
412 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
414 // Make sure the stack slot is also aligned for the register type.
415 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
417 // Perform the original store, only redirected to the stack slot.
418 SDValue Store = DAG.getTruncStore(Chain, dl,
419 Val, StackPtr, MachinePointerInfo(),
420 StoredVT, false, false, 0);
421 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
422 SmallVector<SDValue, 8> Stores;
425 // Do all but one copies using the full register width.
426 for (unsigned i = 1; i < NumRegs; i++) {
427 // Load one integer register's worth from the stack slot.
428 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
429 MachinePointerInfo(),
431 // Store it to the final location. Remember the store.
432 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
433 ST->getPointerInfo().getWithOffset(Offset),
434 ST->isVolatile(), ST->isNonTemporal(),
435 MinAlign(ST->getAlignment(), Offset)));
436 // Increment the pointers.
438 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
440 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
443 // The last store may be partial. Do a truncating store. On big-endian
444 // machines this requires an extending load from the stack slot to ensure
445 // that the bits are in the right place.
446 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
447 8 * (StoredBytes - Offset));
449 // Load from the stack slot.
450 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
451 MachinePointerInfo(),
452 MemVT, false, false, 0);
454 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
456 .getWithOffset(Offset),
457 MemVT, ST->isVolatile(),
459 MinAlign(ST->getAlignment(), Offset)));
460 // The order of the stores doesn't matter - say it with a TokenFactor.
461 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
464 assert(ST->getMemoryVT().isInteger() &&
465 !ST->getMemoryVT().isVector() &&
466 "Unaligned store of unknown type.");
467 // Get the half-size VT
468 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
469 int NumBits = NewStoredVT.getSizeInBits();
470 int IncrementSize = NumBits / 8;
472 // Divide the stored value in two parts.
473 SDValue ShiftAmount = DAG.getConstant(NumBits,
474 TLI.getShiftAmountTy(Val.getValueType()));
476 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
478 // Store the two parts
479 SDValue Store1, Store2;
480 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
481 ST->getPointerInfo(), NewStoredVT,
482 ST->isVolatile(), ST->isNonTemporal(), Alignment);
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
484 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
485 Alignment = MinAlign(Alignment, IncrementSize);
486 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
487 ST->getPointerInfo().getWithOffset(IncrementSize),
488 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
491 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
494 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
496 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
497 const TargetLowering &TLI) {
498 SDValue Chain = LD->getChain();
499 SDValue Ptr = LD->getBasePtr();
500 EVT VT = LD->getValueType(0);
501 EVT LoadedVT = LD->getMemoryVT();
502 DebugLoc dl = LD->getDebugLoc();
503 if (VT.isFloatingPoint() || VT.isVector()) {
504 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
505 if (TLI.isTypeLegal(intVT)) {
506 // Expand to a (misaligned) integer load of the same size,
507 // then bitconvert to floating point or vector.
508 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
510 LD->isNonTemporal(), LD->getAlignment());
511 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
512 if (VT.isFloatingPoint() && LoadedVT != VT)
513 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
515 SDValue Ops[] = { Result, Chain };
516 return DAG.getMergeValues(Ops, 2, dl);
519 // Copy the value to a (aligned) stack slot using (unaligned) integer
520 // loads and stores, then do a (aligned) load from the stack slot.
521 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
522 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
523 unsigned RegBytes = RegVT.getSizeInBits() / 8;
524 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
526 // Make sure the stack slot is also aligned for the register type.
527 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
529 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
530 SmallVector<SDValue, 8> Stores;
531 SDValue StackPtr = StackBase;
534 // Do all but one copies using the full register width.
535 for (unsigned i = 1; i < NumRegs; i++) {
536 // Load one integer register's worth from the original location.
537 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
538 LD->getPointerInfo().getWithOffset(Offset),
539 LD->isVolatile(), LD->isNonTemporal(),
540 MinAlign(LD->getAlignment(), Offset));
541 // Follow the load with a store to the stack slot. Remember the store.
542 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
543 MachinePointerInfo(), false, false, 0));
544 // Increment the pointers.
546 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
547 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
551 // The last copy may be partial. Do an extending load.
552 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
553 8 * (LoadedBytes - Offset));
554 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
555 LD->getPointerInfo().getWithOffset(Offset),
556 MemVT, LD->isVolatile(),
558 MinAlign(LD->getAlignment(), Offset));
559 // Follow the load with a store to the stack slot. Remember the store.
560 // On big-endian machines this requires a truncating store to ensure
561 // that the bits end up in the right place.
562 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
563 MachinePointerInfo(), MemVT,
566 // The order of the stores doesn't matter - say it with a TokenFactor.
567 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
570 // Finally, perform the original load only redirected to the stack slot.
571 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
572 MachinePointerInfo(), LoadedVT, false, false, 0);
574 // Callers expect a MERGE_VALUES node.
575 SDValue Ops[] = { Load, TF };
576 return DAG.getMergeValues(Ops, 2, dl);
578 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
579 "Unaligned load of unsupported type.");
581 // Compute the new VT that is half the size of the old one. This is an
583 unsigned NumBits = LoadedVT.getSizeInBits();
585 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
588 unsigned Alignment = LD->getAlignment();
589 unsigned IncrementSize = NumBits / 8;
590 ISD::LoadExtType HiExtType = LD->getExtensionType();
592 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
593 if (HiExtType == ISD::NON_EXTLOAD)
594 HiExtType = ISD::ZEXTLOAD;
596 // Load the value in two parts
598 if (TLI.isLittleEndian()) {
599 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
600 NewLoadedVT, LD->isVolatile(),
601 LD->isNonTemporal(), Alignment);
602 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
603 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
604 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
605 LD->getPointerInfo().getWithOffset(IncrementSize),
606 NewLoadedVT, LD->isVolatile(),
607 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
609 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
610 NewLoadedVT, LD->isVolatile(),
611 LD->isNonTemporal(), Alignment);
612 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
613 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
614 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
615 LD->getPointerInfo().getWithOffset(IncrementSize),
616 NewLoadedVT, LD->isVolatile(),
617 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
620 // aggregate the two parts
621 SDValue ShiftAmount = DAG.getConstant(NumBits,
622 TLI.getShiftAmountTy(Hi.getValueType()));
623 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
624 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
626 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
629 SDValue Ops[] = { Result, TF };
630 return DAG.getMergeValues(Ops, 2, dl);
633 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
634 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
635 /// is necessary to spill the vector being inserted into to memory, perform
636 /// the insert there, and then read the result back.
637 SDValue SelectionDAGLegalize::
638 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
644 // If the target doesn't support this, we have to spill the input vector
645 // to a temporary stack slot, update the element, then reload it. This is
646 // badness. We could also load the value into a vector register (either
647 // with a "move to register" or "extload into register" instruction, then
648 // permute it into place, if the idx is a constant and if the idx is
649 // supported by the target.
650 EVT VT = Tmp1.getValueType();
651 EVT EltVT = VT.getVectorElementType();
652 EVT IdxVT = Tmp3.getValueType();
653 EVT PtrVT = TLI.getPointerTy();
654 SDValue StackPtr = DAG.CreateStackTemporary(VT);
656 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
659 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
660 MachinePointerInfo::getFixedStack(SPFI),
663 // Truncate or zero extend offset to target pointer type.
664 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
665 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
666 // Add the offset to the index.
667 unsigned EltSize = EltVT.getSizeInBits()/8;
668 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
669 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
670 // Store the scalar value.
671 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
673 // Load the updated vector.
674 return DAG.getLoad(VT, dl, Ch, StackPtr,
675 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
679 SDValue SelectionDAGLegalize::
680 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
681 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
682 // SCALAR_TO_VECTOR requires that the type of the value being inserted
683 // match the element type of the vector being created, except for
684 // integers in which case the inserted value can be over width.
685 EVT EltVT = Vec.getValueType().getVectorElementType();
686 if (Val.getValueType() == EltVT ||
687 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
688 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
689 Vec.getValueType(), Val);
691 unsigned NumElts = Vec.getValueType().getVectorNumElements();
692 // We generate a shuffle of InVec and ScVec, so the shuffle mask
693 // should be 0,1,2,3,4,5... with the appropriate element replaced with
695 SmallVector<int, 8> ShufOps;
696 for (unsigned i = 0; i != NumElts; ++i)
697 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
699 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
703 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
706 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
707 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
708 // FIXME: We shouldn't do this for TargetConstantFP's.
709 // FIXME: move this to the DAG Combiner! Note that we can't regress due
710 // to phase ordering between legalized code and the dag combiner. This
711 // probably means that we need to integrate dag combiner and legalizer
713 // We generally can't do this one for long doubles.
714 SDValue Tmp1 = ST->getChain();
715 SDValue Tmp2 = ST->getBasePtr();
717 unsigned Alignment = ST->getAlignment();
718 bool isVolatile = ST->isVolatile();
719 bool isNonTemporal = ST->isNonTemporal();
720 DebugLoc dl = ST->getDebugLoc();
721 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
722 if (CFP->getValueType(0) == MVT::f32 &&
723 TLI.isTypeLegal(MVT::i32)) {
724 Tmp3 = DAG.getConstant(CFP->getValueAPF().
725 bitcastToAPInt().zextOrTrunc(32),
727 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
728 isVolatile, isNonTemporal, Alignment);
731 if (CFP->getValueType(0) == MVT::f64) {
732 // If this target supports 64-bit registers, do a single 64-bit store.
733 if (TLI.isTypeLegal(MVT::i64)) {
734 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
735 zextOrTrunc(64), MVT::i64);
736 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
737 isVolatile, isNonTemporal, Alignment);
740 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
741 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
742 // stores. If the target supports neither 32- nor 64-bits, this
743 // xform is certainly not worth it.
744 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
745 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
746 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
747 if (TLI.isBigEndian()) std::swap(Lo, Hi);
749 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
750 isNonTemporal, Alignment);
751 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
752 DAG.getIntPtrConstant(4));
753 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
754 ST->getPointerInfo().getWithOffset(4),
755 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
757 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
761 return SDValue(0, 0);
764 /// LegalizeOp - Return a legal replacement for the given operation, with
765 /// all legal operands.
766 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
767 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
770 SDNode *Node = Op.getNode();
771 DebugLoc dl = Node->getDebugLoc();
773 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
774 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
775 TargetLowering::TypeLegal &&
776 "Unexpected illegal type!");
778 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
779 assert((TLI.getTypeAction(*DAG.getContext(),
780 Node->getOperand(i).getValueType()) ==
781 TargetLowering::TypeLegal ||
782 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
783 "Unexpected illegal type!");
785 // Note that LegalizeOp may be reentered even from single-use nodes, which
786 // means that we always must cache transformed nodes.
787 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
788 if (I != LegalizedNodes.end()) return I->second;
790 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
792 bool isCustom = false;
794 // Figure out the correct action; the way to query this varies by opcode
795 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
796 bool SimpleFinishLegalizing = true;
797 switch (Node->getOpcode()) {
798 case ISD::INTRINSIC_W_CHAIN:
799 case ISD::INTRINSIC_WO_CHAIN:
800 case ISD::INTRINSIC_VOID:
803 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
805 case ISD::SINT_TO_FP:
806 case ISD::UINT_TO_FP:
807 case ISD::EXTRACT_VECTOR_ELT:
808 Action = TLI.getOperationAction(Node->getOpcode(),
809 Node->getOperand(0).getValueType());
811 case ISD::FP_ROUND_INREG:
812 case ISD::SIGN_EXTEND_INREG: {
813 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
814 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
817 case ISD::ATOMIC_STORE: {
818 Action = TLI.getOperationAction(Node->getOpcode(),
819 Node->getOperand(2).getValueType());
825 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
826 Node->getOpcode() == ISD::SETCC ? 2 : 1;
827 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
828 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
829 ISD::CondCode CCCode =
830 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
831 Action = TLI.getCondCodeAction(CCCode, OpVT);
832 if (Action == TargetLowering::Legal) {
833 if (Node->getOpcode() == ISD::SELECT_CC)
834 Action = TLI.getOperationAction(Node->getOpcode(),
835 Node->getValueType(0));
837 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
843 // FIXME: Model these properly. LOAD and STORE are complicated, and
844 // STORE expects the unlegalized operand in some cases.
845 SimpleFinishLegalizing = false;
847 case ISD::CALLSEQ_START:
848 case ISD::CALLSEQ_END:
849 // FIXME: This shouldn't be necessary. These nodes have special properties
850 // dealing with the recursive nature of legalization. Removing this
851 // special case should be done as part of making LegalizeDAG non-recursive.
852 SimpleFinishLegalizing = false;
854 case ISD::EXTRACT_ELEMENT:
855 case ISD::FLT_ROUNDS_:
863 case ISD::MERGE_VALUES:
865 case ISD::FRAME_TO_ARGS_OFFSET:
866 case ISD::EH_SJLJ_SETJMP:
867 case ISD::EH_SJLJ_LONGJMP:
868 case ISD::EH_SJLJ_DISPATCHSETUP:
869 // These operations lie about being legal: when they claim to be legal,
870 // they should actually be expanded.
871 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
872 if (Action == TargetLowering::Legal)
873 Action = TargetLowering::Expand;
875 case ISD::INIT_TRAMPOLINE:
876 case ISD::ADJUST_TRAMPOLINE:
878 case ISD::RETURNADDR:
879 // These operations lie about being legal: when they claim to be legal,
880 // they should actually be custom-lowered.
881 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
882 if (Action == TargetLowering::Legal)
883 Action = TargetLowering::Custom;
885 case ISD::BUILD_VECTOR:
886 // A weird case: legalization for BUILD_VECTOR never legalizes the
888 // FIXME: This really sucks... changing it isn't semantically incorrect,
889 // but it massively pessimizes the code for floating-point BUILD_VECTORs
890 // because ConstantFP operands get legalized into constant pool loads
891 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
892 // though, because BUILD_VECTORS usually get lowered into other nodes
893 // which get legalized properly.
894 SimpleFinishLegalizing = false;
897 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
898 Action = TargetLowering::Legal;
900 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
905 if (SimpleFinishLegalizing) {
906 SmallVector<SDValue, 8> Ops, ResultVals;
907 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
908 Ops.push_back(LegalizeOp(Node->getOperand(i)));
909 switch (Node->getOpcode()) {
916 // Branches tweak the chain to include LastCALLSEQ_END
917 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
919 Ops[0] = LegalizeOp(Ops[0]);
920 LastCALLSEQ_END = DAG.getEntryNode();
927 // Legalizing shifts/rotates requires adjusting the shift amount
928 // to the appropriate width.
929 if (!Ops[1].getValueType().isVector())
930 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
936 // Legalizing shifts/rotates requires adjusting the shift amount
937 // to the appropriate width.
938 if (!Ops[2].getValueType().isVector())
939 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
944 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
947 case TargetLowering::Legal:
948 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
949 ResultVals.push_back(Result.getValue(i));
951 case TargetLowering::Custom:
952 // FIXME: The handling for custom lowering with multiple results is
954 Tmp1 = TLI.LowerOperation(Result, DAG);
955 if (Tmp1.getNode()) {
956 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
958 ResultVals.push_back(Tmp1);
960 ResultVals.push_back(Tmp1.getValue(i));
966 case TargetLowering::Expand:
967 ExpandNode(Result.getNode(), ResultVals);
969 case TargetLowering::Promote:
970 PromoteNode(Result.getNode(), ResultVals);
973 if (!ResultVals.empty()) {
974 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
975 if (ResultVals[i] != SDValue(Node, i))
976 ResultVals[i] = LegalizeOp(ResultVals[i]);
977 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
979 return ResultVals[Op.getResNo()];
983 switch (Node->getOpcode()) {
990 assert(0 && "Do not know how to legalize this operator!");
995 // Scalarize vector SRA/SRL/SHL.
996 EVT VT = Node->getValueType(0);
997 assert(VT.isVector() && "Unable to legalize non-vector shift");
998 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
999 unsigned NumElem = VT.getVectorNumElements();
1001 SmallVector<SDValue, 8> Scalars;
1002 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
1003 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1005 Node->getOperand(0), DAG.getIntPtrConstant(Idx));
1006 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1008 Node->getOperand(1), DAG.getIntPtrConstant(Idx));
1009 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
1010 VT.getScalarType(), Ex, Sh));
1012 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
1013 &Scalars[0], Scalars.size());
1017 case ISD::BUILD_VECTOR:
1018 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1019 default: assert(0 && "This action is not supported yet!");
1020 case TargetLowering::Custom:
1021 Tmp3 = TLI.LowerOperation(Result, DAG);
1022 if (Tmp3.getNode()) {
1027 case TargetLowering::Expand:
1028 Result = ExpandBUILD_VECTOR(Result.getNode());
1032 case ISD::CALLSEQ_START: {
1033 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1035 // Recursively Legalize all of the inputs of the call end that do not lead
1036 // to this call start. This ensures that any libcalls that need be inserted
1037 // are inserted *before* the CALLSEQ_START.
1038 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1039 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1040 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1044 // Now that we have legalized all of the inputs (which may have inserted
1045 // libcalls), create the new CALLSEQ_START node.
1046 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1048 // Merge in the last call to ensure that this call starts after the last
1050 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1051 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1052 Tmp1, LastCALLSEQ_END);
1053 Tmp1 = LegalizeOp(Tmp1);
1056 // Do not try to legalize the target-specific arguments (#1+).
1057 if (Tmp1 != Node->getOperand(0)) {
1058 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1060 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1061 Ops.size()), Result.getResNo());
1064 // Remember that the CALLSEQ_START is legalized.
1065 AddLegalizedOperand(Op.getValue(0), Result);
1066 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1067 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1069 // Now that the callseq_start and all of the non-call nodes above this call
1070 // sequence have been legalized, legalize the call itself. During this
1071 // process, no libcalls can/will be inserted, guaranteeing that no calls
1073 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1074 // Note that we are selecting this call!
1075 LastCALLSEQ_END = SDValue(CallEnd, 0);
1076 IsLegalizingCall = true;
1078 // Legalize the call, starting from the CALLSEQ_END.
1079 LegalizeOp(LastCALLSEQ_END);
1080 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1083 case ISD::CALLSEQ_END:
1084 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1085 // will cause this node to be legalized as well as handling libcalls right.
1086 if (LastCALLSEQ_END.getNode() != Node) {
1087 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1088 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1089 assert(I != LegalizedNodes.end() &&
1090 "Legalizing the call start should have legalized this node!");
1094 // Otherwise, the call start has been legalized and everything is going
1095 // according to plan. Just legalize ourselves normally here.
1096 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1097 // Do not try to legalize the target-specific arguments (#1+), except for
1098 // an optional flag input.
1099 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
1100 if (Tmp1 != Node->getOperand(0)) {
1101 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1103 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1104 &Ops[0], Ops.size()),
1108 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1109 if (Tmp1 != Node->getOperand(0) ||
1110 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1111 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1114 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1115 &Ops[0], Ops.size()),
1119 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1120 // This finishes up call legalization.
1121 IsLegalizingCall = false;
1123 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1124 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1125 if (Node->getNumValues() == 2)
1126 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1127 return Result.getValue(Op.getResNo());
1129 LoadSDNode *LD = cast<LoadSDNode>(Node);
1130 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1131 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1133 ISD::LoadExtType ExtType = LD->getExtensionType();
1134 if (ExtType == ISD::NON_EXTLOAD) {
1135 EVT VT = Node->getValueType(0);
1136 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1137 Tmp1, Tmp2, LD->getOffset()),
1139 Tmp3 = Result.getValue(0);
1140 Tmp4 = Result.getValue(1);
1142 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1143 default: assert(0 && "This action is not supported yet!");
1144 case TargetLowering::Legal:
1145 // If this is an unaligned load and the target doesn't support it,
1147 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1148 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1149 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1150 if (LD->getAlignment() < ABIAlignment){
1151 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1153 Tmp3 = Result.getOperand(0);
1154 Tmp4 = Result.getOperand(1);
1155 Tmp3 = LegalizeOp(Tmp3);
1156 Tmp4 = LegalizeOp(Tmp4);
1160 case TargetLowering::Custom:
1161 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1162 if (Tmp1.getNode()) {
1163 Tmp3 = LegalizeOp(Tmp1);
1164 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1167 case TargetLowering::Promote: {
1168 // Only promote a load of vector type to another.
1169 assert(VT.isVector() && "Cannot promote this load!");
1170 // Change base type to a different vector type.
1171 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1173 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1174 LD->isVolatile(), LD->isNonTemporal(),
1175 LD->getAlignment());
1176 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1177 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1181 // Since loads produce two values, make sure to remember that we
1182 // legalized both of them.
1183 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1184 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1185 return Op.getResNo() ? Tmp4 : Tmp3;
1188 EVT SrcVT = LD->getMemoryVT();
1189 unsigned SrcWidth = SrcVT.getSizeInBits();
1190 unsigned Alignment = LD->getAlignment();
1191 bool isVolatile = LD->isVolatile();
1192 bool isNonTemporal = LD->isNonTemporal();
1194 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1195 // Some targets pretend to have an i1 loading operation, and actually
1196 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1197 // bits are guaranteed to be zero; it helps the optimizers understand
1198 // that these bits are zero. It is also useful for EXTLOAD, since it
1199 // tells the optimizers that those bits are undefined. It would be
1200 // nice to have an effective generic way of getting these benefits...
1201 // Until such a way is found, don't insist on promoting i1 here.
1202 (SrcVT != MVT::i1 ||
1203 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1204 // Promote to a byte-sized load if not loading an integral number of
1205 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1206 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1207 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1210 // The extra bits are guaranteed to be zero, since we stored them that
1211 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1213 ISD::LoadExtType NewExtType =
1214 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1216 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1217 Tmp1, Tmp2, LD->getPointerInfo(),
1218 NVT, isVolatile, isNonTemporal, Alignment);
1220 Ch = Result.getValue(1); // The chain.
1222 if (ExtType == ISD::SEXTLOAD)
1223 // Having the top bits zero doesn't help when sign extending.
1224 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1225 Result.getValueType(),
1226 Result, DAG.getValueType(SrcVT));
1227 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1228 // All the top bits are guaranteed to be zero - inform the optimizers.
1229 Result = DAG.getNode(ISD::AssertZext, dl,
1230 Result.getValueType(), Result,
1231 DAG.getValueType(SrcVT));
1233 Tmp1 = LegalizeOp(Result);
1234 Tmp2 = LegalizeOp(Ch);
1235 } else if (SrcWidth & (SrcWidth - 1)) {
1236 // If not loading a power-of-2 number of bits, expand as two loads.
1237 assert(!SrcVT.isVector() && "Unsupported extload!");
1238 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1239 assert(RoundWidth < SrcWidth);
1240 unsigned ExtraWidth = SrcWidth - RoundWidth;
1241 assert(ExtraWidth < RoundWidth);
1242 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1243 "Load size not an integral number of bytes!");
1244 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1245 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1247 unsigned IncrementSize;
1249 if (TLI.isLittleEndian()) {
1250 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1251 // Load the bottom RoundWidth bits.
1252 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1254 LD->getPointerInfo(), RoundVT, isVolatile,
1255 isNonTemporal, Alignment);
1257 // Load the remaining ExtraWidth bits.
1258 IncrementSize = RoundWidth / 8;
1259 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1260 DAG.getIntPtrConstant(IncrementSize));
1261 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1262 LD->getPointerInfo().getWithOffset(IncrementSize),
1263 ExtraVT, isVolatile, isNonTemporal,
1264 MinAlign(Alignment, IncrementSize));
1266 // Build a factor node to remember that this load is independent of
1268 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1271 // Move the top bits to the right place.
1272 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1273 DAG.getConstant(RoundWidth,
1274 TLI.getShiftAmountTy(Hi.getValueType())));
1276 // Join the hi and lo parts.
1277 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1279 // Big endian - avoid unaligned loads.
1280 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1281 // Load the top RoundWidth bits.
1282 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1283 LD->getPointerInfo(), RoundVT, isVolatile,
1284 isNonTemporal, Alignment);
1286 // Load the remaining ExtraWidth bits.
1287 IncrementSize = RoundWidth / 8;
1288 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1289 DAG.getIntPtrConstant(IncrementSize));
1290 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1291 dl, Node->getValueType(0), Tmp1, Tmp2,
1292 LD->getPointerInfo().getWithOffset(IncrementSize),
1293 ExtraVT, isVolatile, isNonTemporal,
1294 MinAlign(Alignment, IncrementSize));
1296 // Build a factor node to remember that this load is independent of
1298 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1301 // Move the top bits to the right place.
1302 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1303 DAG.getConstant(ExtraWidth,
1304 TLI.getShiftAmountTy(Hi.getValueType())));
1306 // Join the hi and lo parts.
1307 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1310 Tmp1 = LegalizeOp(Result);
1311 Tmp2 = LegalizeOp(Ch);
1313 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1314 default: assert(0 && "This action is not supported yet!");
1315 case TargetLowering::Custom:
1318 case TargetLowering::Legal:
1319 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1320 Tmp1, Tmp2, LD->getOffset()),
1322 Tmp1 = Result.getValue(0);
1323 Tmp2 = Result.getValue(1);
1326 Tmp3 = TLI.LowerOperation(Result, DAG);
1327 if (Tmp3.getNode()) {
1328 Tmp1 = LegalizeOp(Tmp3);
1329 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1332 // If this is an unaligned load and the target doesn't support it,
1334 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1336 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1337 unsigned ABIAlignment =
1338 TLI.getTargetData()->getABITypeAlignment(Ty);
1339 if (LD->getAlignment() < ABIAlignment){
1340 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1342 Tmp1 = Result.getOperand(0);
1343 Tmp2 = Result.getOperand(1);
1344 Tmp1 = LegalizeOp(Tmp1);
1345 Tmp2 = LegalizeOp(Tmp2);
1350 case TargetLowering::Expand:
1351 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1352 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1353 LD->getPointerInfo(),
1354 LD->isVolatile(), LD->isNonTemporal(),
1355 LD->getAlignment());
1359 ExtendOp = (SrcVT.isFloatingPoint() ?
1360 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1362 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1363 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1364 default: llvm_unreachable("Unexpected extend load type!");
1366 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1367 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1368 Tmp2 = LegalizeOp(Load.getValue(1));
1372 // If this is a promoted vector load, and the vector element types are
1373 // legal, then scalarize it.
1374 if (ExtType == ISD::EXTLOAD && SrcVT.isVector() &&
1375 TLI.isTypeLegal(Node->getValueType(0).getScalarType())) {
1376 SmallVector<SDValue, 8> LoadVals;
1377 SmallVector<SDValue, 8> LoadChains;
1378 unsigned NumElem = SrcVT.getVectorNumElements();
1379 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
1381 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1382 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1383 DAG.getIntPtrConstant(Stride));
1384 SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
1385 Node->getValueType(0).getScalarType(),
1386 Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
1387 SrcVT.getScalarType(),
1388 LD->isVolatile(), LD->isNonTemporal(),
1389 LD->getAlignment());
1391 LoadVals.push_back(ScalarLoad.getValue(0));
1392 LoadChains.push_back(ScalarLoad.getValue(1));
1394 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1395 &LoadChains[0], LoadChains.size());
1396 SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
1397 Node->getValueType(0), &LoadVals[0], LoadVals.size());
1399 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1400 Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
1404 // If this is a promoted vector load, and the vector element types are
1405 // illegal, create the promoted vector from bitcasted segments.
1406 if (ExtType == ISD::EXTLOAD && SrcVT.isVector()) {
1407 EVT MemElemTy = Node->getValueType(0).getScalarType();
1408 EVT SrcSclrTy = SrcVT.getScalarType();
1409 unsigned SizeRatio =
1410 (MemElemTy.getSizeInBits() / SrcSclrTy.getSizeInBits());
1412 SmallVector<SDValue, 8> LoadVals;
1413 SmallVector<SDValue, 8> LoadChains;
1414 unsigned NumElem = SrcVT.getVectorNumElements();
1415 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
1417 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1418 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1419 DAG.getIntPtrConstant(Stride));
1420 SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
1421 SrcVT.getScalarType(),
1422 Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
1423 SrcVT.getScalarType(),
1424 LD->isVolatile(), LD->isNonTemporal(),
1425 LD->getAlignment());
1426 if (TLI.isBigEndian()) {
1427 // MSB (which is garbage, comes first)
1428 LoadVals.push_back(ScalarLoad.getValue(0));
1429 for (unsigned i = 0; i<SizeRatio-1; ++i)
1430 LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
1432 // LSB (which is data, comes first)
1433 for (unsigned i = 0; i<SizeRatio-1; ++i)
1434 LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
1435 LoadVals.push_back(ScalarLoad.getValue(0));
1437 LoadChains.push_back(ScalarLoad.getValue(1));
1440 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1441 &LoadChains[0], LoadChains.size());
1442 EVT TempWideVector = EVT::getVectorVT(*DAG.getContext(),
1443 SrcVT.getScalarType(), NumElem*SizeRatio);
1444 SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
1445 TempWideVector, &LoadVals[0], LoadVals.size());
1447 // Cast to the correct type
1448 ValRes = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), ValRes);
1450 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1451 Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
1456 // FIXME: This does not work for vectors on most targets. Sign- and
1457 // zero-extend operations are currently folded into extending loads,
1458 // whether they are legal or not, and then we end up here without any
1459 // support for legalizing them.
1460 assert(ExtType != ISD::EXTLOAD &&
1461 "EXTLOAD should always be supported!");
1462 // Turn the unsupported load into an EXTLOAD followed by an explicit
1463 // zero/sign extend inreg.
1464 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1465 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1466 LD->isVolatile(), LD->isNonTemporal(),
1467 LD->getAlignment());
1469 if (ExtType == ISD::SEXTLOAD)
1470 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1471 Result.getValueType(),
1472 Result, DAG.getValueType(SrcVT));
1474 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1475 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1476 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1481 // Since loads produce two values, make sure to remember that we legalized
1483 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1484 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1485 return Op.getResNo() ? Tmp2 : Tmp1;
1488 StoreSDNode *ST = cast<StoreSDNode>(Node);
1489 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1490 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1491 unsigned Alignment = ST->getAlignment();
1492 bool isVolatile = ST->isVolatile();
1493 bool isNonTemporal = ST->isNonTemporal();
1495 if (!ST->isTruncatingStore()) {
1496 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1497 Result = SDValue(OptStore, 0);
1502 Tmp3 = LegalizeOp(ST->getValue());
1503 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1508 EVT VT = Tmp3.getValueType();
1509 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1510 default: assert(0 && "This action is not supported yet!");
1511 case TargetLowering::Legal:
1512 // If this is an unaligned store and the target doesn't support it,
1514 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1515 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1516 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1517 if (ST->getAlignment() < ABIAlignment)
1518 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1522 case TargetLowering::Custom:
1523 Tmp1 = TLI.LowerOperation(Result, DAG);
1524 if (Tmp1.getNode()) Result = Tmp1;
1526 case TargetLowering::Promote:
1527 assert(VT.isVector() && "Unknown legal promote case!");
1528 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1529 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1530 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1531 ST->getPointerInfo(), isVolatile,
1532 isNonTemporal, Alignment);
1538 Tmp3 = LegalizeOp(ST->getValue());
1540 EVT StVT = ST->getMemoryVT();
1541 unsigned StWidth = StVT.getSizeInBits();
1543 if (StWidth != StVT.getStoreSizeInBits()) {
1544 // Promote to a byte-sized store with upper bits zero if not
1545 // storing an integral number of bytes. For example, promote
1546 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1547 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1548 StVT.getStoreSizeInBits());
1549 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1550 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1551 NVT, isVolatile, isNonTemporal, Alignment);
1552 } else if (StWidth & (StWidth - 1)) {
1553 // If not storing a power-of-2 number of bits, expand as two stores.
1554 assert(!StVT.isVector() && "Unsupported truncstore!");
1555 unsigned RoundWidth = 1 << Log2_32(StWidth);
1556 assert(RoundWidth < StWidth);
1557 unsigned ExtraWidth = StWidth - RoundWidth;
1558 assert(ExtraWidth < RoundWidth);
1559 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1560 "Store size not an integral number of bytes!");
1561 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1562 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1564 unsigned IncrementSize;
1566 if (TLI.isLittleEndian()) {
1567 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1568 // Store the bottom RoundWidth bits.
1569 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1571 isVolatile, isNonTemporal, Alignment);
1573 // Store the remaining ExtraWidth bits.
1574 IncrementSize = RoundWidth / 8;
1575 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1576 DAG.getIntPtrConstant(IncrementSize));
1577 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1578 DAG.getConstant(RoundWidth,
1579 TLI.getShiftAmountTy(Tmp3.getValueType())));
1580 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1581 ST->getPointerInfo().getWithOffset(IncrementSize),
1582 ExtraVT, isVolatile, isNonTemporal,
1583 MinAlign(Alignment, IncrementSize));
1585 // Big endian - avoid unaligned stores.
1586 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1587 // Store the top RoundWidth bits.
1588 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1589 DAG.getConstant(ExtraWidth,
1590 TLI.getShiftAmountTy(Tmp3.getValueType())));
1591 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1592 RoundVT, isVolatile, isNonTemporal, Alignment);
1594 // Store the remaining ExtraWidth bits.
1595 IncrementSize = RoundWidth / 8;
1596 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1597 DAG.getIntPtrConstant(IncrementSize));
1598 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1599 ST->getPointerInfo().getWithOffset(IncrementSize),
1600 ExtraVT, isVolatile, isNonTemporal,
1601 MinAlign(Alignment, IncrementSize));
1604 // The order of the stores doesn't matter.
1605 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1607 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1608 Tmp2 != ST->getBasePtr())
1609 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1614 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1615 default: assert(0 && "This action is not supported yet!");
1616 case TargetLowering::Legal:
1617 // If this is an unaligned store and the target doesn't support it,
1619 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1620 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1621 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1622 if (ST->getAlignment() < ABIAlignment)
1623 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1627 case TargetLowering::Custom:
1628 Result = TLI.LowerOperation(Result, DAG);
1630 case TargetLowering::Expand:
1632 EVT WideScalarVT = Tmp3.getValueType().getScalarType();
1633 EVT NarrowScalarVT = StVT.getScalarType();
1635 if (StVT.isVector()) {
1636 unsigned NumElem = StVT.getVectorNumElements();
1637 // The type of the data we want to save
1638 EVT RegVT = Tmp3.getValueType();
1639 EVT RegSclVT = RegVT.getScalarType();
1640 // The type of data as saved in memory.
1641 EVT MemSclVT = StVT.getScalarType();
1643 bool RegScalarLegal = TLI.isTypeLegal(RegSclVT);
1644 bool MemScalarLegal = TLI.isTypeLegal(MemSclVT);
1646 // We need to expand this store. If the register element type
1647 // is legal then we can scalarize the vector and use
1648 // truncating stores.
1649 if (RegScalarLegal) {
1650 // Cast floats into integers
1651 unsigned ScalarSize = MemSclVT.getSizeInBits();
1652 EVT EltVT = EVT::getIntegerVT(*DAG.getContext(), ScalarSize);
1654 // Round odd types to the next pow of two.
1655 if (!isPowerOf2_32(ScalarSize))
1656 ScalarSize = NextPowerOf2(ScalarSize);
1658 // Store Stride in bytes
1659 unsigned Stride = ScalarSize/8;
1660 // Extract each of the elements from the original vector
1661 // and save them into memory individually.
1662 SmallVector<SDValue, 8> Stores;
1663 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
1664 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1665 RegSclVT, Tmp3, DAG.getIntPtrConstant(Idx));
1667 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1668 DAG.getIntPtrConstant(Stride));
1670 // This scalar TruncStore may be illegal, but we lehalize it
1672 SDValue Store = DAG.getTruncStore(Tmp1, dl, Ex, Tmp2,
1673 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
1674 isVolatile, isNonTemporal, Alignment);
1676 Stores.push_back(Store);
1679 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1680 &Stores[0], Stores.size());
1684 // The scalar register type is illegal.
1685 // For example saving <2 x i64> -> <2 x i32> on a x86.
1686 // In here we bitcast the value into a vector of smaller parts and
1687 // save it using smaller scalars.
1688 if (!RegScalarLegal && MemScalarLegal) {
1689 // Store Stride in bytes
1690 unsigned Stride = MemSclVT.getSizeInBits()/8;
1692 unsigned SizeRatio =
1693 (RegSclVT.getSizeInBits() / MemSclVT.getSizeInBits());
1695 EVT CastValueVT = EVT::getVectorVT(*DAG.getContext(),
1697 SizeRatio * NumElem);
1699 // Cast the wide elem vector to wider vec with smaller elem type.
1700 // Example <2 x i64> -> <4 x i32>
1701 Tmp3 = DAG.getNode(ISD::BITCAST, dl, CastValueVT, Tmp3);
1703 SmallVector<SDValue, 8> Stores;
1704 for (unsigned Idx=0; Idx < NumElem * SizeRatio; Idx++) {
1705 // Extract the Ith element.
1706 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1707 NarrowScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
1709 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1710 DAG.getIntPtrConstant(Stride));
1712 // Store if, this element is:
1713 // - First element on big endian, or
1714 // - Last element on little endian
1715 if (( TLI.isBigEndian() && (Idx % SizeRatio == 0)) ||
1716 ((!TLI.isBigEndian() && (Idx % SizeRatio == SizeRatio-1)))) {
1717 SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
1718 ST->getPointerInfo().getWithOffset(Idx*Stride),
1719 isVolatile, isNonTemporal, Alignment);
1720 Stores.push_back(Store);
1723 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1724 &Stores[0], Stores.size());
1728 assert(false && "Unable to legalize the vector trunc store!");
1732 // TRUNCSTORE:i16 i32 -> STORE i16
1733 assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
1734 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1735 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1736 isVolatile, isNonTemporal, Alignment);
1744 assert(Result.getValueType() == Op.getValueType() &&
1745 "Bad legalization!");
1747 // Make sure that the generated code is itself legal.
1749 Result = LegalizeOp(Result);
1751 // Note that LegalizeOp may be reentered even from single-use nodes, which
1752 // means that we always must cache transformed nodes.
1753 AddLegalizedOperand(Op, Result);
1757 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1758 SDValue Vec = Op.getOperand(0);
1759 SDValue Idx = Op.getOperand(1);
1760 DebugLoc dl = Op.getDebugLoc();
1761 // Store the value to a temporary stack slot, then LOAD the returned part.
1762 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1763 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1764 MachinePointerInfo(), false, false, 0);
1766 // Add the offset to the index.
1768 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1769 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1770 DAG.getConstant(EltSize, Idx.getValueType()));
1772 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1773 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1775 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1777 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1779 if (Op.getValueType().isVector())
1780 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1782 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1783 MachinePointerInfo(),
1784 Vec.getValueType().getVectorElementType(),
1788 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1789 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1791 SDValue Vec = Op.getOperand(0);
1792 SDValue Part = Op.getOperand(1);
1793 SDValue Idx = Op.getOperand(2);
1794 DebugLoc dl = Op.getDebugLoc();
1796 // Store the value to a temporary stack slot, then LOAD the returned part.
1798 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1799 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1800 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1802 // First store the whole vector.
1803 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1806 // Then store the inserted part.
1808 // Add the offset to the index.
1810 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1812 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1813 DAG.getConstant(EltSize, Idx.getValueType()));
1815 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1816 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1818 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1820 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1823 // Store the subvector.
1824 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1825 MachinePointerInfo(), false, false, 0);
1827 // Finally, load the updated vector.
1828 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1832 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1833 // We can't handle this case efficiently. Allocate a sufficiently
1834 // aligned object on the stack, store each element into it, then load
1835 // the result as a vector.
1836 // Create the stack frame object.
1837 EVT VT = Node->getValueType(0);
1838 EVT EltVT = VT.getVectorElementType();
1839 DebugLoc dl = Node->getDebugLoc();
1840 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1841 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1842 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1844 // Emit a store of each element to the stack slot.
1845 SmallVector<SDValue, 8> Stores;
1846 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1847 // Store (in the right endianness) the elements to memory.
1848 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1849 // Ignore undef elements.
1850 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1852 unsigned Offset = TypeByteSize*i;
1854 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1855 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1857 // If the destination vector element type is narrower than the source
1858 // element type, only store the bits necessary.
1859 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1860 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1861 Node->getOperand(i), Idx,
1862 PtrInfo.getWithOffset(Offset),
1863 EltVT, false, false, 0));
1865 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1866 Node->getOperand(i), Idx,
1867 PtrInfo.getWithOffset(Offset),
1872 if (!Stores.empty()) // Not all undef elements?
1873 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1874 &Stores[0], Stores.size());
1876 StoreChain = DAG.getEntryNode();
1878 // Result is a load from the stack slot.
1879 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1882 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1883 DebugLoc dl = Node->getDebugLoc();
1884 SDValue Tmp1 = Node->getOperand(0);
1885 SDValue Tmp2 = Node->getOperand(1);
1887 // Get the sign bit of the RHS. First obtain a value that has the same
1888 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1890 EVT FloatVT = Tmp2.getValueType();
1891 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1892 if (TLI.isTypeLegal(IVT)) {
1893 // Convert to an integer with the same sign bit.
1894 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1896 // Store the float to memory, then load the sign part out as an integer.
1897 MVT LoadTy = TLI.getPointerTy();
1898 // First create a temporary that is aligned for both the load and store.
1899 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1900 // Then store the float to it.
1902 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1904 if (TLI.isBigEndian()) {
1905 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1906 // Load out a legal integer with the same sign bit as the float.
1907 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1909 } else { // Little endian
1910 SDValue LoadPtr = StackPtr;
1911 // The float may be wider than the integer we are going to load. Advance
1912 // the pointer so that the loaded integer will contain the sign bit.
1913 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1914 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1915 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1916 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1917 // Load a legal integer containing the sign bit.
1918 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1920 // Move the sign bit to the top bit of the loaded integer.
1921 unsigned BitShift = LoadTy.getSizeInBits() -
1922 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1923 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1925 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1926 DAG.getConstant(BitShift,
1927 TLI.getShiftAmountTy(SignBit.getValueType())));
1930 // Now get the sign bit proper, by seeing whether the value is negative.
1931 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1932 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1934 // Get the absolute value of the result.
1935 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1936 // Select between the nabs and abs value based on the sign bit of
1938 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1939 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1943 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1944 SmallVectorImpl<SDValue> &Results) {
1945 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1946 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1947 " not tell us which reg is the stack pointer!");
1948 DebugLoc dl = Node->getDebugLoc();
1949 EVT VT = Node->getValueType(0);
1950 SDValue Tmp1 = SDValue(Node, 0);
1951 SDValue Tmp2 = SDValue(Node, 1);
1952 SDValue Tmp3 = Node->getOperand(2);
1953 SDValue Chain = Tmp1.getOperand(0);
1955 // Chain the dynamic stack allocation so that it doesn't modify the stack
1956 // pointer when other instructions are using the stack.
1957 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1959 SDValue Size = Tmp2.getOperand(1);
1960 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1961 Chain = SP.getValue(1);
1962 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1963 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1964 if (Align > StackAlign)
1965 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1966 DAG.getConstant(-(uint64_t)Align, VT));
1967 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1968 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1970 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1971 DAG.getIntPtrConstant(0, true), SDValue());
1973 Results.push_back(Tmp1);
1974 Results.push_back(Tmp2);
1977 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1978 /// condition code CC on the current target. This routine expands SETCC with
1979 /// illegal condition code into AND / OR of multiple SETCC values.
1980 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1981 SDValue &LHS, SDValue &RHS,
1984 EVT OpVT = LHS.getValueType();
1985 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1986 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1987 default: assert(0 && "Unknown condition code action!");
1988 case TargetLowering::Legal:
1991 case TargetLowering::Expand: {
1992 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1995 default: assert(0 && "Don't know how to expand this condition!");
1996 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1997 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1998 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1999 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
2000 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
2001 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
2002 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
2003 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
2004 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
2005 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
2006 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
2007 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
2008 // FIXME: Implement more expansions.
2011 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
2012 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
2013 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
2021 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
2022 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
2023 /// a load from the stack slot to DestVT, extending it if needed.
2024 /// The resultant code need not be legal.
2025 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
2029 // Create the stack frame object.
2031 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
2032 getTypeForEVT(*DAG.getContext()));
2033 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
2035 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
2036 int SPFI = StackPtrFI->getIndex();
2037 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
2039 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
2040 unsigned SlotSize = SlotVT.getSizeInBits();
2041 unsigned DestSize = DestVT.getSizeInBits();
2042 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
2043 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
2045 // Emit a store to the stack slot. Use a truncstore if the input value is
2046 // later than DestVT.
2049 if (SrcSize > SlotSize)
2050 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
2051 PtrInfo, SlotVT, false, false, SrcAlign);
2053 assert(SrcSize == SlotSize && "Invalid store");
2054 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
2055 PtrInfo, false, false, SrcAlign);
2058 // Result is a load from the stack slot.
2059 if (SlotSize == DestSize)
2060 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
2061 false, false, DestAlign);
2063 assert(SlotSize < DestSize && "Unknown extension!");
2064 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
2065 PtrInfo, SlotVT, false, false, DestAlign);
2068 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
2069 DebugLoc dl = Node->getDebugLoc();
2070 // Create a vector sized/aligned stack slot, store the value to element #0,
2071 // then load the whole vector back out.
2072 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
2074 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
2075 int SPFI = StackPtrFI->getIndex();
2077 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
2079 MachinePointerInfo::getFixedStack(SPFI),
2080 Node->getValueType(0).getVectorElementType(),
2082 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
2083 MachinePointerInfo::getFixedStack(SPFI),
2088 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
2089 /// support the operation, but do support the resultant vector type.
2090 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
2091 unsigned NumElems = Node->getNumOperands();
2092 SDValue Value1, Value2;
2093 DebugLoc dl = Node->getDebugLoc();
2094 EVT VT = Node->getValueType(0);
2095 EVT OpVT = Node->getOperand(0).getValueType();
2096 EVT EltVT = VT.getVectorElementType();
2098 // If the only non-undef value is the low element, turn this into a
2099 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
2100 bool isOnlyLowElement = true;
2101 bool MoreThanTwoValues = false;
2102 bool isConstant = true;
2103 for (unsigned i = 0; i < NumElems; ++i) {
2104 SDValue V = Node->getOperand(i);
2105 if (V.getOpcode() == ISD::UNDEF)
2108 isOnlyLowElement = false;
2109 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
2112 if (!Value1.getNode()) {
2114 } else if (!Value2.getNode()) {
2117 } else if (V != Value1 && V != Value2) {
2118 MoreThanTwoValues = true;
2122 if (!Value1.getNode())
2123 return DAG.getUNDEF(VT);
2125 if (isOnlyLowElement)
2126 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
2128 // If all elements are constants, create a load from the constant pool.
2130 std::vector<Constant*> CV;
2131 for (unsigned i = 0, e = NumElems; i != e; ++i) {
2132 if (ConstantFPSDNode *V =
2133 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
2134 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
2135 } else if (ConstantSDNode *V =
2136 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
2138 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
2140 // If OpVT and EltVT don't match, EltVT is not legal and the
2141 // element values have been promoted/truncated earlier. Undo this;
2142 // we don't want a v16i8 to become a v16i32 for example.
2143 const ConstantInt *CI = V->getConstantIntValue();
2144 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2145 CI->getZExtValue()));
2148 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2149 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
2150 CV.push_back(UndefValue::get(OpNTy));
2153 Constant *CP = ConstantVector::get(CV);
2154 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
2155 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2156 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
2157 MachinePointerInfo::getConstantPool(),
2158 false, false, Alignment);
2161 if (!MoreThanTwoValues) {
2162 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2163 for (unsigned i = 0; i < NumElems; ++i) {
2164 SDValue V = Node->getOperand(i);
2165 if (V.getOpcode() == ISD::UNDEF)
2167 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2169 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2170 // Get the splatted value into the low element of a vector register.
2171 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2173 if (Value2.getNode())
2174 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2176 Vec2 = DAG.getUNDEF(VT);
2178 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2179 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2183 // Otherwise, we can't handle this case efficiently.
2184 return ExpandVectorBuildThroughStack(Node);
2187 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2188 // does not fit into a register, return the lo part and set the hi part to the
2189 // by-reg argument. If it does fit into a single register, return the result
2190 // and leave the Hi part unset.
2191 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2193 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
2194 // The input chain to this libcall is the entry node of the function.
2195 // Legalizing the call will automatically add the previous call to the
2197 SDValue InChain = DAG.getEntryNode();
2199 TargetLowering::ArgListTy Args;
2200 TargetLowering::ArgListEntry Entry;
2201 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2202 EVT ArgVT = Node->getOperand(i).getValueType();
2203 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2204 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2205 Entry.isSExt = isSigned;
2206 Entry.isZExt = !isSigned;
2207 Args.push_back(Entry);
2209 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2210 TLI.getPointerTy());
2212 // Splice the libcall in wherever FindInputOutputChains tells us to.
2213 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2215 // isTailCall may be true since the callee does not reference caller stack
2216 // frame. Check if it's in the right position.
2217 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
2218 std::pair<SDValue, SDValue> CallInfo =
2219 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2220 0, TLI.getLibcallCallingConv(LC), isTailCall,
2221 /*isReturnValueUsed=*/true,
2222 Callee, Args, DAG, Node->getDebugLoc());
2224 if (!CallInfo.second.getNode())
2225 // It's a tailcall, return the chain (which is the DAG root).
2226 return DAG.getRoot();
2228 // Legalize the call sequence, starting with the chain. This will advance
2229 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2230 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2231 LegalizeOp(CallInfo.second);
2232 return CallInfo.first;
2235 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
2236 /// and returning a result of type RetVT.
2237 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2238 const SDValue *Ops, unsigned NumOps,
2239 bool isSigned, DebugLoc dl) {
2240 TargetLowering::ArgListTy Args;
2241 Args.reserve(NumOps);
2243 TargetLowering::ArgListEntry Entry;
2244 for (unsigned i = 0; i != NumOps; ++i) {
2245 Entry.Node = Ops[i];
2246 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2247 Entry.isSExt = isSigned;
2248 Entry.isZExt = !isSigned;
2249 Args.push_back(Entry);
2251 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2252 TLI.getPointerTy());
2254 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2255 std::pair<SDValue,SDValue> CallInfo =
2256 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
2257 false, 0, TLI.getLibcallCallingConv(LC), false,
2258 /*isReturnValueUsed=*/true,
2259 Callee, Args, DAG, dl);
2261 // Legalize the call sequence, starting with the chain. This will advance
2262 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2263 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2264 LegalizeOp(CallInfo.second);
2266 return CallInfo.first;
2269 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2270 // ExpandLibCall except that the first operand is the in-chain.
2271 std::pair<SDValue, SDValue>
2272 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2275 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
2276 SDValue InChain = Node->getOperand(0);
2278 TargetLowering::ArgListTy Args;
2279 TargetLowering::ArgListEntry Entry;
2280 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2281 EVT ArgVT = Node->getOperand(i).getValueType();
2282 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2283 Entry.Node = Node->getOperand(i);
2285 Entry.isSExt = isSigned;
2286 Entry.isZExt = !isSigned;
2287 Args.push_back(Entry);
2289 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2290 TLI.getPointerTy());
2292 // Splice the libcall in wherever FindInputOutputChains tells us to.
2293 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2294 std::pair<SDValue, SDValue> CallInfo =
2295 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2296 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2297 /*isReturnValueUsed=*/true,
2298 Callee, Args, DAG, Node->getDebugLoc());
2300 // Legalize the call sequence, starting with the chain. This will advance
2301 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2302 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2303 LegalizeOp(CallInfo.second);
2307 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2308 RTLIB::Libcall Call_F32,
2309 RTLIB::Libcall Call_F64,
2310 RTLIB::Libcall Call_F80,
2311 RTLIB::Libcall Call_PPCF128) {
2313 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2314 default: assert(0 && "Unexpected request for libcall!");
2315 case MVT::f32: LC = Call_F32; break;
2316 case MVT::f64: LC = Call_F64; break;
2317 case MVT::f80: LC = Call_F80; break;
2318 case MVT::ppcf128: LC = Call_PPCF128; break;
2320 return ExpandLibCall(LC, Node, false);
2323 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2324 RTLIB::Libcall Call_I8,
2325 RTLIB::Libcall Call_I16,
2326 RTLIB::Libcall Call_I32,
2327 RTLIB::Libcall Call_I64,
2328 RTLIB::Libcall Call_I128) {
2330 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2331 default: assert(0 && "Unexpected request for libcall!");
2332 case MVT::i8: LC = Call_I8; break;
2333 case MVT::i16: LC = Call_I16; break;
2334 case MVT::i32: LC = Call_I32; break;
2335 case MVT::i64: LC = Call_I64; break;
2336 case MVT::i128: LC = Call_I128; break;
2338 return ExpandLibCall(LC, Node, isSigned);
2341 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2342 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2343 const TargetLowering &TLI) {
2345 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2346 default: assert(0 && "Unexpected request for libcall!");
2347 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2348 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2349 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2350 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2351 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2354 return TLI.getLibcallName(LC) != 0;
2357 /// UseDivRem - Only issue divrem libcall if both quotient and remainder are
2359 static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2360 unsigned OtherOpcode = 0;
2362 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2364 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2366 SDValue Op0 = Node->getOperand(0);
2367 SDValue Op1 = Node->getOperand(1);
2368 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2369 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2373 if (User->getOpcode() == OtherOpcode &&
2374 User->getOperand(0) == Op0 &&
2375 User->getOperand(1) == Op1)
2381 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2384 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2385 SmallVectorImpl<SDValue> &Results) {
2386 unsigned Opcode = Node->getOpcode();
2387 bool isSigned = Opcode == ISD::SDIVREM;
2390 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2391 default: assert(0 && "Unexpected request for libcall!");
2392 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2393 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2394 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2395 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2396 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2399 // The input chain to this libcall is the entry node of the function.
2400 // Legalizing the call will automatically add the previous call to the
2402 SDValue InChain = DAG.getEntryNode();
2404 EVT RetVT = Node->getValueType(0);
2405 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2407 TargetLowering::ArgListTy Args;
2408 TargetLowering::ArgListEntry Entry;
2409 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2410 EVT ArgVT = Node->getOperand(i).getValueType();
2411 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2412 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2413 Entry.isSExt = isSigned;
2414 Entry.isZExt = !isSigned;
2415 Args.push_back(Entry);
2418 // Also pass the return address of the remainder.
2419 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2421 Entry.Ty = RetTy->getPointerTo();
2422 Entry.isSExt = isSigned;
2423 Entry.isZExt = !isSigned;
2424 Args.push_back(Entry);
2426 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2427 TLI.getPointerTy());
2429 // Splice the libcall in wherever FindInputOutputChains tells us to.
2430 DebugLoc dl = Node->getDebugLoc();
2431 std::pair<SDValue, SDValue> CallInfo =
2432 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2433 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2434 /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
2436 // Legalize the call sequence, starting with the chain. This will advance
2437 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2438 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2439 LegalizeOp(CallInfo.second);
2441 // Remainder is loaded back from the stack frame.
2442 SDValue Rem = DAG.getLoad(RetVT, dl, LastCALLSEQ_END, FIPtr,
2443 MachinePointerInfo(), false, false, 0);
2444 Results.push_back(CallInfo.first);
2445 Results.push_back(Rem);
2448 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2449 /// INT_TO_FP operation of the specified operand when the target requests that
2450 /// we expand it. At this point, we know that the result and operand types are
2451 /// legal for the target.
2452 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2456 if (Op0.getValueType() == MVT::i32) {
2457 // simple 32-bit [signed|unsigned] integer to float/double expansion
2459 // Get the stack frame index of a 8 byte buffer.
2460 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2462 // word offset constant for Hi/Lo address computation
2463 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2464 // set up Hi and Lo (into buffer) address based on endian
2465 SDValue Hi = StackSlot;
2466 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2467 TLI.getPointerTy(), StackSlot, WordOff);
2468 if (TLI.isLittleEndian())
2471 // if signed map to unsigned space
2474 // constant used to invert sign bit (signed to unsigned mapping)
2475 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2476 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2480 // store the lo of the constructed double - based on integer input
2481 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2482 Op0Mapped, Lo, MachinePointerInfo(),
2484 // initial hi portion of constructed double
2485 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2486 // store the hi of the constructed double - biased exponent
2487 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2488 MachinePointerInfo(),
2490 // load the constructed double
2491 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2492 MachinePointerInfo(), false, false, 0);
2493 // FP constant to bias correct the final result
2494 SDValue Bias = DAG.getConstantFP(isSigned ?
2495 BitsToDouble(0x4330000080000000ULL) :
2496 BitsToDouble(0x4330000000000000ULL),
2498 // subtract the bias
2499 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2502 // handle final rounding
2503 if (DestVT == MVT::f64) {
2506 } else if (DestVT.bitsLT(MVT::f64)) {
2507 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2508 DAG.getIntPtrConstant(0));
2509 } else if (DestVT.bitsGT(MVT::f64)) {
2510 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2514 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2515 // Code below here assumes !isSigned without checking again.
2517 // Implementation of unsigned i64 to f64 following the algorithm in
2518 // __floatundidf in compiler_rt. This implementation has the advantage
2519 // of performing rounding correctly, both in the default rounding mode
2520 // and in all alternate rounding modes.
2521 // TODO: Generalize this for use with other types.
2522 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2524 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2525 SDValue TwoP84PlusTwoP52 =
2526 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2528 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2530 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2531 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2532 DAG.getConstant(32, MVT::i64));
2533 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2534 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2535 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2536 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2537 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2539 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2542 // Implementation of unsigned i64 to f32.
2543 // TODO: Generalize this for use with other types.
2544 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2545 // For unsigned conversions, convert them to signed conversions using the
2546 // algorithm from the x86_64 __floatundidf in compiler_rt.
2548 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2550 SDValue ShiftConst =
2551 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2552 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2553 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2554 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2555 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2557 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2558 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2560 // TODO: This really should be implemented using a branch rather than a
2561 // select. We happen to get lucky and machinesink does the right
2562 // thing most of the time. This would be a good candidate for a
2563 //pseudo-op, or, even better, for whole-function isel.
2564 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2565 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2566 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2569 // Otherwise, implement the fully general conversion.
2571 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2572 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2573 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2574 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2575 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2576 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2577 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2578 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2579 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2580 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2581 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2583 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2584 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2586 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2587 DAG.getConstant(32, SHVT));
2588 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2589 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2591 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2592 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2593 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2594 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2595 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2596 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2597 DAG.getIntPtrConstant(0));
2600 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2602 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2603 Op0, DAG.getConstant(0, Op0.getValueType()),
2605 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2606 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2607 SignSet, Four, Zero);
2609 // If the sign bit of the integer is set, the large number will be treated
2610 // as a negative number. To counteract this, the dynamic code adds an
2611 // offset depending on the data type.
2613 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2614 default: assert(0 && "Unsupported integer type!");
2615 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2616 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2617 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2618 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2620 if (TLI.isLittleEndian()) FF <<= 32;
2621 Constant *FudgeFactor = ConstantInt::get(
2622 Type::getInt64Ty(*DAG.getContext()), FF);
2624 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2625 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2626 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2627 Alignment = std::min(Alignment, 4u);
2629 if (DestVT == MVT::f32)
2630 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2631 MachinePointerInfo::getConstantPool(),
2632 false, false, Alignment);
2635 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2636 DAG.getEntryNode(), CPIdx,
2637 MachinePointerInfo::getConstantPool(),
2638 MVT::f32, false, false, Alignment));
2641 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2644 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2645 /// *INT_TO_FP operation of the specified operand when the target requests that
2646 /// we promote it. At this point, we know that the result and operand types are
2647 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2648 /// operation that takes a larger input.
2649 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2653 // First step, figure out the appropriate *INT_TO_FP operation to use.
2654 EVT NewInTy = LegalOp.getValueType();
2656 unsigned OpToUse = 0;
2658 // Scan for the appropriate larger type to use.
2660 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2661 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2663 // If the target supports SINT_TO_FP of this type, use it.
2664 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2665 OpToUse = ISD::SINT_TO_FP;
2668 if (isSigned) continue;
2670 // If the target supports UINT_TO_FP of this type, use it.
2671 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2672 OpToUse = ISD::UINT_TO_FP;
2676 // Otherwise, try a larger type.
2679 // Okay, we found the operation and type to use. Zero extend our input to the
2680 // desired type then run the operation on it.
2681 return DAG.getNode(OpToUse, dl, DestVT,
2682 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2683 dl, NewInTy, LegalOp));
2686 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2687 /// FP_TO_*INT operation of the specified operand when the target requests that
2688 /// we promote it. At this point, we know that the result and operand types are
2689 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2690 /// operation that returns a larger result.
2691 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2695 // First step, figure out the appropriate FP_TO*INT operation to use.
2696 EVT NewOutTy = DestVT;
2698 unsigned OpToUse = 0;
2700 // Scan for the appropriate larger type to use.
2702 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2703 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2705 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2706 OpToUse = ISD::FP_TO_SINT;
2710 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2711 OpToUse = ISD::FP_TO_UINT;
2715 // Otherwise, try a larger type.
2719 // Okay, we found the operation and type to use.
2720 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2722 // Truncate the result of the extended FP_TO_*INT operation to the desired
2724 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2727 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2729 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2730 EVT VT = Op.getValueType();
2731 EVT SHVT = TLI.getShiftAmountTy(VT);
2732 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2733 switch (VT.getSimpleVT().SimpleTy) {
2734 default: assert(0 && "Unhandled Expand type in BSWAP!");
2736 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2737 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2738 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2740 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2741 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2742 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2743 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2744 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2745 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2746 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2747 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2748 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2750 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2751 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2752 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2753 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2754 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2755 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2756 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2757 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2758 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2759 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2760 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2761 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2762 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2763 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2764 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2765 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2766 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2767 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2768 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2769 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2770 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2774 /// SplatByte - Distribute ByteVal over NumBits bits.
2775 // FIXME: Move this helper to a common place.
2776 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2777 APInt Val = APInt(NumBits, ByteVal);
2779 for (unsigned i = NumBits; i > 8; i >>= 1) {
2780 Val = (Val << Shift) | Val;
2786 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2788 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2791 default: assert(0 && "Cannot expand this yet!");
2793 EVT VT = Op.getValueType();
2794 EVT ShVT = TLI.getShiftAmountTy(VT);
2795 unsigned Len = VT.getSizeInBits();
2797 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2798 "CTPOP not implemented for this type.");
2800 // This is the "best" algorithm from
2801 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2803 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2804 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2805 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2806 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2808 // v = v - ((v >> 1) & 0x55555555...)
2809 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2810 DAG.getNode(ISD::AND, dl, VT,
2811 DAG.getNode(ISD::SRL, dl, VT, Op,
2812 DAG.getConstant(1, ShVT)),
2814 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2815 Op = DAG.getNode(ISD::ADD, dl, VT,
2816 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2817 DAG.getNode(ISD::AND, dl, VT,
2818 DAG.getNode(ISD::SRL, dl, VT, Op,
2819 DAG.getConstant(2, ShVT)),
2821 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2822 Op = DAG.getNode(ISD::AND, dl, VT,
2823 DAG.getNode(ISD::ADD, dl, VT, Op,
2824 DAG.getNode(ISD::SRL, dl, VT, Op,
2825 DAG.getConstant(4, ShVT))),
2827 // v = (v * 0x01010101...) >> (Len - 8)
2828 Op = DAG.getNode(ISD::SRL, dl, VT,
2829 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2830 DAG.getConstant(Len - 8, ShVT));
2835 // for now, we do this:
2836 // x = x | (x >> 1);
2837 // x = x | (x >> 2);
2839 // x = x | (x >>16);
2840 // x = x | (x >>32); // for 64-bit input
2841 // return popcount(~x);
2843 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2844 EVT VT = Op.getValueType();
2845 EVT ShVT = TLI.getShiftAmountTy(VT);
2846 unsigned len = VT.getSizeInBits();
2847 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2848 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2849 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2850 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2852 Op = DAG.getNOT(dl, Op, VT);
2853 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2856 // for now, we use: { return popcount(~x & (x - 1)); }
2857 // unless the target has ctlz but not ctpop, in which case we use:
2858 // { return 32 - nlz(~x & (x-1)); }
2859 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2860 EVT VT = Op.getValueType();
2861 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2862 DAG.getNOT(dl, Op, VT),
2863 DAG.getNode(ISD::SUB, dl, VT, Op,
2864 DAG.getConstant(1, VT)));
2865 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2866 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2867 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2868 return DAG.getNode(ISD::SUB, dl, VT,
2869 DAG.getConstant(VT.getSizeInBits(), VT),
2870 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2871 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2876 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2877 unsigned Opc = Node->getOpcode();
2878 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2883 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2885 case ISD::ATOMIC_SWAP:
2886 switch (VT.SimpleTy) {
2887 default: llvm_unreachable("Unexpected value type for atomic!");
2888 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2889 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2890 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2891 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2894 case ISD::ATOMIC_CMP_SWAP:
2895 switch (VT.SimpleTy) {
2896 default: llvm_unreachable("Unexpected value type for atomic!");
2897 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2898 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2899 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2900 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2903 case ISD::ATOMIC_LOAD_ADD:
2904 switch (VT.SimpleTy) {
2905 default: llvm_unreachable("Unexpected value type for atomic!");
2906 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2907 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2908 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2909 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2912 case ISD::ATOMIC_LOAD_SUB:
2913 switch (VT.SimpleTy) {
2914 default: llvm_unreachable("Unexpected value type for atomic!");
2915 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2916 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2917 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2918 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2921 case ISD::ATOMIC_LOAD_AND:
2922 switch (VT.SimpleTy) {
2923 default: llvm_unreachable("Unexpected value type for atomic!");
2924 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2925 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2926 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2927 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2930 case ISD::ATOMIC_LOAD_OR:
2931 switch (VT.SimpleTy) {
2932 default: llvm_unreachable("Unexpected value type for atomic!");
2933 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2934 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2935 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2936 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2939 case ISD::ATOMIC_LOAD_XOR:
2940 switch (VT.SimpleTy) {
2941 default: llvm_unreachable("Unexpected value type for atomic!");
2942 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2943 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2944 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2945 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2948 case ISD::ATOMIC_LOAD_NAND:
2949 switch (VT.SimpleTy) {
2950 default: llvm_unreachable("Unexpected value type for atomic!");
2951 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2952 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2953 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2954 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2959 return ExpandChainLibCall(LC, Node, false);
2962 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2963 SmallVectorImpl<SDValue> &Results) {
2964 DebugLoc dl = Node->getDebugLoc();
2965 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2966 switch (Node->getOpcode()) {
2970 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2971 Results.push_back(Tmp1);
2974 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2976 case ISD::FRAMEADDR:
2977 case ISD::RETURNADDR:
2978 case ISD::FRAME_TO_ARGS_OFFSET:
2979 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2981 case ISD::FLT_ROUNDS_:
2982 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2984 case ISD::EH_RETURN:
2988 case ISD::EH_SJLJ_LONGJMP:
2989 case ISD::EH_SJLJ_DISPATCHSETUP:
2990 // If the target didn't expand these, there's nothing to do, so just
2991 // preserve the chain and be done.
2992 Results.push_back(Node->getOperand(0));
2994 case ISD::EH_SJLJ_SETJMP:
2995 // If the target didn't expand this, just return 'zero' and preserve the
2997 Results.push_back(DAG.getConstant(0, MVT::i32));
2998 Results.push_back(Node->getOperand(0));
3000 case ISD::ATOMIC_FENCE:
3001 case ISD::MEMBARRIER: {
3002 // If the target didn't lower this, lower it to '__sync_synchronize()' call
3003 // FIXME: handle "fence singlethread" more efficiently.
3004 TargetLowering::ArgListTy Args;
3005 std::pair<SDValue, SDValue> CallResult =
3006 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
3007 false, false, false, false, 0, CallingConv::C,
3008 /*isTailCall=*/false,
3009 /*isReturnValueUsed=*/true,
3010 DAG.getExternalSymbol("__sync_synchronize",
3011 TLI.getPointerTy()),
3013 Results.push_back(CallResult.second);
3016 case ISD::ATOMIC_LOAD: {
3017 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3018 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
3019 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3020 cast<AtomicSDNode>(Node)->getMemoryVT(),
3021 Node->getOperand(0),
3022 Node->getOperand(1), Zero, Zero,
3023 cast<AtomicSDNode>(Node)->getMemOperand(),
3024 cast<AtomicSDNode>(Node)->getOrdering(),
3025 cast<AtomicSDNode>(Node)->getSynchScope());
3026 Results.push_back(Swap.getValue(0));
3027 Results.push_back(Swap.getValue(1));
3030 case ISD::ATOMIC_STORE: {
3031 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3032 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3033 cast<AtomicSDNode>(Node)->getMemoryVT(),
3034 Node->getOperand(0),
3035 Node->getOperand(1), Node->getOperand(2),
3036 cast<AtomicSDNode>(Node)->getMemOperand(),
3037 cast<AtomicSDNode>(Node)->getOrdering(),
3038 cast<AtomicSDNode>(Node)->getSynchScope());
3039 Results.push_back(Swap.getValue(1));
3042 // By default, atomic intrinsics are marked Legal and lowered. Targets
3043 // which don't support them directly, however, may want libcalls, in which
3044 // case they mark them Expand, and we get here.
3045 case ISD::ATOMIC_SWAP:
3046 case ISD::ATOMIC_LOAD_ADD:
3047 case ISD::ATOMIC_LOAD_SUB:
3048 case ISD::ATOMIC_LOAD_AND:
3049 case ISD::ATOMIC_LOAD_OR:
3050 case ISD::ATOMIC_LOAD_XOR:
3051 case ISD::ATOMIC_LOAD_NAND:
3052 case ISD::ATOMIC_LOAD_MIN:
3053 case ISD::ATOMIC_LOAD_MAX:
3054 case ISD::ATOMIC_LOAD_UMIN:
3055 case ISD::ATOMIC_LOAD_UMAX:
3056 case ISD::ATOMIC_CMP_SWAP: {
3057 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
3058 Results.push_back(Tmp.first);
3059 Results.push_back(Tmp.second);
3062 case ISD::DYNAMIC_STACKALLOC:
3063 ExpandDYNAMIC_STACKALLOC(Node, Results);
3065 case ISD::MERGE_VALUES:
3066 for (unsigned i = 0; i < Node->getNumValues(); i++)
3067 Results.push_back(Node->getOperand(i));
3070 EVT VT = Node->getValueType(0);
3072 Results.push_back(DAG.getConstant(0, VT));
3074 assert(VT.isFloatingPoint() && "Unknown value type!");
3075 Results.push_back(DAG.getConstantFP(0, VT));
3080 // If this operation is not supported, lower it to 'abort()' call
3081 TargetLowering::ArgListTy Args;
3082 std::pair<SDValue, SDValue> CallResult =
3083 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
3084 false, false, false, false, 0, CallingConv::C,
3085 /*isTailCall=*/false,
3086 /*isReturnValueUsed=*/true,
3087 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3089 Results.push_back(CallResult.second);
3094 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3095 Node->getValueType(0), dl);
3096 Results.push_back(Tmp1);
3098 case ISD::FP_EXTEND:
3099 Tmp1 = EmitStackConvert(Node->getOperand(0),
3100 Node->getOperand(0).getValueType(),
3101 Node->getValueType(0), dl);
3102 Results.push_back(Tmp1);
3104 case ISD::SIGN_EXTEND_INREG: {
3105 // NOTE: we could fall back on load/store here too for targets without
3106 // SAR. However, it is doubtful that any exist.
3107 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3108 EVT VT = Node->getValueType(0);
3109 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3112 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3113 ExtraVT.getScalarType().getSizeInBits();
3114 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3115 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3116 Node->getOperand(0), ShiftCst);
3117 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3118 Results.push_back(Tmp1);
3121 case ISD::FP_ROUND_INREG: {
3122 // The only way we can lower this is to turn it into a TRUNCSTORE,
3123 // EXTLOAD pair, targeting a temporary location (a stack slot).
3125 // NOTE: there is a choice here between constantly creating new stack
3126 // slots and always reusing the same one. We currently always create
3127 // new ones, as reuse may inhibit scheduling.
3128 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3129 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3130 Node->getValueType(0), dl);
3131 Results.push_back(Tmp1);
3134 case ISD::SINT_TO_FP:
3135 case ISD::UINT_TO_FP:
3136 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3137 Node->getOperand(0), Node->getValueType(0), dl);
3138 Results.push_back(Tmp1);
3140 case ISD::FP_TO_UINT: {
3141 SDValue True, False;
3142 EVT VT = Node->getOperand(0).getValueType();
3143 EVT NVT = Node->getValueType(0);
3144 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
3145 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3146 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3147 Tmp1 = DAG.getConstantFP(apf, VT);
3148 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
3149 Node->getOperand(0),
3151 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3152 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3153 DAG.getNode(ISD::FSUB, dl, VT,
3154 Node->getOperand(0), Tmp1));
3155 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3156 DAG.getConstant(x, NVT));
3157 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
3158 Results.push_back(Tmp1);
3162 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3163 EVT VT = Node->getValueType(0);
3164 Tmp1 = Node->getOperand(0);
3165 Tmp2 = Node->getOperand(1);
3166 unsigned Align = Node->getConstantOperandVal(3);
3168 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3169 MachinePointerInfo(V), false, false, 0);
3170 SDValue VAList = VAListLoad;
3172 if (Align > TLI.getMinStackArgumentAlignment()) {
3173 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3175 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3176 DAG.getConstant(Align - 1,
3177 TLI.getPointerTy()));
3179 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
3180 DAG.getConstant(-(int64_t)Align,
3181 TLI.getPointerTy()));
3184 // Increment the pointer, VAList, to the next vaarg
3185 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3186 DAG.getConstant(TLI.getTargetData()->
3187 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3188 TLI.getPointerTy()));
3189 // Store the incremented VAList to the legalized pointer
3190 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3191 MachinePointerInfo(V), false, false, 0);
3192 // Load the actual argument out of the pointer VAList
3193 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3195 Results.push_back(Results[0].getValue(1));
3199 // This defaults to loading a pointer from the input and storing it to the
3200 // output, returning the chain.
3201 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3202 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3203 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3204 Node->getOperand(2), MachinePointerInfo(VS),
3206 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3207 MachinePointerInfo(VD), false, false, 0);
3208 Results.push_back(Tmp1);
3211 case ISD::EXTRACT_VECTOR_ELT:
3212 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3213 // This must be an access of the only element. Return it.
3214 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3215 Node->getOperand(0));
3217 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3218 Results.push_back(Tmp1);
3220 case ISD::EXTRACT_SUBVECTOR:
3221 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3223 case ISD::INSERT_SUBVECTOR:
3224 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3226 case ISD::CONCAT_VECTORS: {
3227 Results.push_back(ExpandVectorBuildThroughStack(Node));
3230 case ISD::SCALAR_TO_VECTOR:
3231 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3233 case ISD::INSERT_VECTOR_ELT:
3234 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3235 Node->getOperand(1),
3236 Node->getOperand(2), dl));
3238 case ISD::VECTOR_SHUFFLE: {
3239 SmallVector<int, 8> Mask;
3240 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3242 EVT VT = Node->getValueType(0);
3243 EVT EltVT = VT.getVectorElementType();
3244 if (!TLI.isTypeLegal(EltVT))
3245 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3246 unsigned NumElems = VT.getVectorNumElements();
3247 SmallVector<SDValue, 8> Ops;
3248 for (unsigned i = 0; i != NumElems; ++i) {
3250 Ops.push_back(DAG.getUNDEF(EltVT));
3253 unsigned Idx = Mask[i];
3255 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3256 Node->getOperand(0),
3257 DAG.getIntPtrConstant(Idx)));
3259 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3260 Node->getOperand(1),
3261 DAG.getIntPtrConstant(Idx - NumElems)));
3263 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3264 Results.push_back(Tmp1);
3267 case ISD::EXTRACT_ELEMENT: {
3268 EVT OpTy = Node->getOperand(0).getValueType();
3269 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3271 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3272 DAG.getConstant(OpTy.getSizeInBits()/2,
3273 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3274 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3277 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3278 Node->getOperand(0));
3280 Results.push_back(Tmp1);
3283 case ISD::STACKSAVE:
3284 // Expand to CopyFromReg if the target set
3285 // StackPointerRegisterToSaveRestore.
3286 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3287 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3288 Node->getValueType(0)));
3289 Results.push_back(Results[0].getValue(1));
3291 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3292 Results.push_back(Node->getOperand(0));
3295 case ISD::STACKRESTORE:
3296 // Expand to CopyToReg if the target set
3297 // StackPointerRegisterToSaveRestore.
3298 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3299 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3300 Node->getOperand(1)));
3302 Results.push_back(Node->getOperand(0));
3305 case ISD::FCOPYSIGN:
3306 Results.push_back(ExpandFCOPYSIGN(Node));
3309 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3310 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3311 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3312 Node->getOperand(0));
3313 Results.push_back(Tmp1);
3316 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3317 EVT VT = Node->getValueType(0);
3318 Tmp1 = Node->getOperand(0);
3319 Tmp2 = DAG.getConstantFP(0.0, VT);
3320 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3321 Tmp1, Tmp2, ISD::SETUGT);
3322 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3323 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3324 Results.push_back(Tmp1);
3328 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3329 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
3332 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3333 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
3336 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3337 RTLIB::COS_F80, RTLIB::COS_PPCF128));
3340 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3341 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
3344 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3345 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
3348 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3349 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3352 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3353 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3356 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3357 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3360 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3361 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3364 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3365 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3368 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3369 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3372 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3373 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3375 case ISD::FNEARBYINT:
3376 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3377 RTLIB::NEARBYINT_F64,
3378 RTLIB::NEARBYINT_F80,
3379 RTLIB::NEARBYINT_PPCF128));
3382 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3383 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3386 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3387 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3390 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3391 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3394 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3395 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3398 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3399 RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
3401 case ISD::FP16_TO_FP32:
3402 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3404 case ISD::FP32_TO_FP16:
3405 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3407 case ISD::ConstantFP: {
3408 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3409 // Check to see if this FP immediate is already legal.
3410 // If this is a legal constant, turn it into a TargetConstantFP node.
3411 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3412 Results.push_back(SDValue(Node, 0));
3414 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
3417 case ISD::EHSELECTION: {
3418 unsigned Reg = TLI.getExceptionSelectorRegister();
3419 assert(Reg && "Can't expand to unknown register!");
3420 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3421 Node->getValueType(0)));
3422 Results.push_back(Results[0].getValue(1));
3425 case ISD::EXCEPTIONADDR: {
3426 unsigned Reg = TLI.getExceptionAddressRegister();
3427 assert(Reg && "Can't expand to unknown register!");
3428 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3429 Node->getValueType(0)));
3430 Results.push_back(Results[0].getValue(1));
3434 EVT VT = Node->getValueType(0);
3435 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3436 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3437 "Don't know how to expand this subtraction!");
3438 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3439 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3440 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
3441 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3446 EVT VT = Node->getValueType(0);
3447 SDVTList VTs = DAG.getVTList(VT, VT);
3448 bool isSigned = Node->getOpcode() == ISD::SREM;
3449 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3450 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3451 Tmp2 = Node->getOperand(0);
3452 Tmp3 = Node->getOperand(1);
3453 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3454 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3455 UseDivRem(Node, isSigned, false))) {
3456 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3457 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3459 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3460 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3461 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3462 } else if (isSigned)
3463 Tmp1 = ExpandIntLibCall(Node, true,
3465 RTLIB::SREM_I16, RTLIB::SREM_I32,
3466 RTLIB::SREM_I64, RTLIB::SREM_I128);
3468 Tmp1 = ExpandIntLibCall(Node, false,
3470 RTLIB::UREM_I16, RTLIB::UREM_I32,
3471 RTLIB::UREM_I64, RTLIB::UREM_I128);
3472 Results.push_back(Tmp1);
3477 bool isSigned = Node->getOpcode() == ISD::SDIV;
3478 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3479 EVT VT = Node->getValueType(0);
3480 SDVTList VTs = DAG.getVTList(VT, VT);
3481 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3482 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3483 UseDivRem(Node, isSigned, true)))
3484 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3485 Node->getOperand(1));
3487 Tmp1 = ExpandIntLibCall(Node, true,
3489 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3490 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3492 Tmp1 = ExpandIntLibCall(Node, false,
3494 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3495 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3496 Results.push_back(Tmp1);
3501 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3503 EVT VT = Node->getValueType(0);
3504 SDVTList VTs = DAG.getVTList(VT, VT);
3505 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3506 "If this wasn't legal, it shouldn't have been created!");
3507 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3508 Node->getOperand(1));
3509 Results.push_back(Tmp1.getValue(1));
3514 // Expand into divrem libcall
3515 ExpandDivRemLibCall(Node, Results);
3518 EVT VT = Node->getValueType(0);
3519 SDVTList VTs = DAG.getVTList(VT, VT);
3520 // See if multiply or divide can be lowered using two-result operations.
3521 // We just need the low half of the multiply; try both the signed
3522 // and unsigned forms. If the target supports both SMUL_LOHI and
3523 // UMUL_LOHI, form a preference by checking which forms of plain
3524 // MULH it supports.
3525 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3526 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3527 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3528 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3529 unsigned OpToUse = 0;
3530 if (HasSMUL_LOHI && !HasMULHS) {
3531 OpToUse = ISD::SMUL_LOHI;
3532 } else if (HasUMUL_LOHI && !HasMULHU) {
3533 OpToUse = ISD::UMUL_LOHI;
3534 } else if (HasSMUL_LOHI) {
3535 OpToUse = ISD::SMUL_LOHI;
3536 } else if (HasUMUL_LOHI) {
3537 OpToUse = ISD::UMUL_LOHI;
3540 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3541 Node->getOperand(1)));
3544 Tmp1 = ExpandIntLibCall(Node, false,
3546 RTLIB::MUL_I16, RTLIB::MUL_I32,
3547 RTLIB::MUL_I64, RTLIB::MUL_I128);
3548 Results.push_back(Tmp1);
3553 SDValue LHS = Node->getOperand(0);
3554 SDValue RHS = Node->getOperand(1);
3555 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3556 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3558 Results.push_back(Sum);
3559 EVT OType = Node->getValueType(1);
3561 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3563 // LHSSign -> LHS >= 0
3564 // RHSSign -> RHS >= 0
3565 // SumSign -> Sum >= 0
3568 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3570 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3572 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3573 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3574 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3575 Node->getOpcode() == ISD::SADDO ?
3576 ISD::SETEQ : ISD::SETNE);
3578 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3579 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3581 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3582 Results.push_back(Cmp);
3587 SDValue LHS = Node->getOperand(0);
3588 SDValue RHS = Node->getOperand(1);
3589 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3590 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3592 Results.push_back(Sum);
3593 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3594 Node->getOpcode () == ISD::UADDO ?
3595 ISD::SETULT : ISD::SETUGT));
3600 EVT VT = Node->getValueType(0);
3601 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3602 SDValue LHS = Node->getOperand(0);
3603 SDValue RHS = Node->getOperand(1);
3606 static const unsigned Ops[2][3] =
3607 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3608 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3609 bool isSigned = Node->getOpcode() == ISD::SMULO;
3610 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3611 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3612 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3613 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3614 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3616 TopHalf = BottomHalf.getValue(1);
3617 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3618 VT.getSizeInBits() * 2))) {
3619 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3620 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3621 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3622 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3623 DAG.getIntPtrConstant(0));
3624 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3625 DAG.getIntPtrConstant(1));
3627 // We can fall back to a libcall with an illegal type for the MUL if we
3628 // have a libcall big enough.
3629 // Also, we can fall back to a division in some cases, but that's a big
3630 // performance hit in the general case.
3631 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3632 if (WideVT == MVT::i16)
3633 LC = RTLIB::MUL_I16;
3634 else if (WideVT == MVT::i32)
3635 LC = RTLIB::MUL_I32;
3636 else if (WideVT == MVT::i64)
3637 LC = RTLIB::MUL_I64;
3638 else if (WideVT == MVT::i128)
3639 LC = RTLIB::MUL_I128;
3640 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3642 // The high part is obtained by SRA'ing all but one of the bits of low
3644 unsigned LoSize = VT.getSizeInBits();
3645 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3646 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3647 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3648 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3650 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3651 // pre-lowered to the correct types. This all depends upon WideVT not
3652 // being a legal type for the architecture and thus has to be split to
3654 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3655 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3656 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3657 DAG.getIntPtrConstant(0));
3658 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3659 DAG.getIntPtrConstant(1));
3663 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3664 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3665 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3666 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3669 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3670 DAG.getConstant(0, VT), ISD::SETNE);
3672 Results.push_back(BottomHalf);
3673 Results.push_back(TopHalf);
3676 case ISD::BUILD_PAIR: {
3677 EVT PairTy = Node->getValueType(0);
3678 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3679 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3680 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3681 DAG.getConstant(PairTy.getSizeInBits()/2,
3682 TLI.getShiftAmountTy(PairTy)));
3683 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3687 Tmp1 = Node->getOperand(0);
3688 Tmp2 = Node->getOperand(1);
3689 Tmp3 = Node->getOperand(2);
3690 if (Tmp1.getOpcode() == ISD::SETCC) {
3691 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3693 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3695 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3696 DAG.getConstant(0, Tmp1.getValueType()),
3697 Tmp2, Tmp3, ISD::SETNE);
3699 Results.push_back(Tmp1);
3702 SDValue Chain = Node->getOperand(0);
3703 SDValue Table = Node->getOperand(1);
3704 SDValue Index = Node->getOperand(2);
3706 EVT PTy = TLI.getPointerTy();
3708 const TargetData &TD = *TLI.getTargetData();
3709 unsigned EntrySize =
3710 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3712 Index = DAG.getNode(ISD::MUL, dl, PTy,
3713 Index, DAG.getConstant(EntrySize, PTy));
3714 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3716 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3717 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3718 MachinePointerInfo::getJumpTable(), MemVT,
3721 if (TM.getRelocationModel() == Reloc::PIC_) {
3722 // For PIC, the sequence is:
3723 // BRIND(load(Jumptable + index) + RelocBase)
3724 // RelocBase can be JumpTable, GOT or some sort of global base.
3725 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3726 TLI.getPICJumpTableRelocBase(Table, DAG));
3728 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3729 Results.push_back(Tmp1);
3733 // Expand brcond's setcc into its constituent parts and create a BR_CC
3735 Tmp1 = Node->getOperand(0);
3736 Tmp2 = Node->getOperand(1);
3737 if (Tmp2.getOpcode() == ISD::SETCC) {
3738 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3739 Tmp1, Tmp2.getOperand(2),
3740 Tmp2.getOperand(0), Tmp2.getOperand(1),
3741 Node->getOperand(2));
3743 // We test only the i1 bit. Skip the AND if UNDEF.
3744 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3745 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3746 DAG.getConstant(1, Tmp2.getValueType()));
3747 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3748 DAG.getCondCode(ISD::SETNE), Tmp3,
3749 DAG.getConstant(0, Tmp3.getValueType()),
3750 Node->getOperand(2));
3752 Results.push_back(Tmp1);
3755 Tmp1 = Node->getOperand(0);
3756 Tmp2 = Node->getOperand(1);
3757 Tmp3 = Node->getOperand(2);
3758 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3760 // If we expanded the SETCC into an AND/OR, return the new node
3761 if (Tmp2.getNode() == 0) {
3762 Results.push_back(Tmp1);
3766 // Otherwise, SETCC for the given comparison type must be completely
3767 // illegal; expand it into a SELECT_CC.
3768 EVT VT = Node->getValueType(0);
3769 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3770 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3771 Results.push_back(Tmp1);
3774 case ISD::SELECT_CC: {
3775 Tmp1 = Node->getOperand(0); // LHS
3776 Tmp2 = Node->getOperand(1); // RHS
3777 Tmp3 = Node->getOperand(2); // True
3778 Tmp4 = Node->getOperand(3); // False
3779 SDValue CC = Node->getOperand(4);
3781 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3782 Tmp1, Tmp2, CC, dl);
3784 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3785 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3786 CC = DAG.getCondCode(ISD::SETNE);
3787 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3789 Results.push_back(Tmp1);
3793 Tmp1 = Node->getOperand(0); // Chain
3794 Tmp2 = Node->getOperand(2); // LHS
3795 Tmp3 = Node->getOperand(3); // RHS
3796 Tmp4 = Node->getOperand(1); // CC
3798 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3799 Tmp2, Tmp3, Tmp4, dl);
3800 LastCALLSEQ_END = DAG.getEntryNode();
3802 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3803 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3804 Tmp4 = DAG.getCondCode(ISD::SETNE);
3805 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3806 Tmp3, Node->getOperand(4));
3807 Results.push_back(Tmp1);
3810 case ISD::GLOBAL_OFFSET_TABLE:
3811 case ISD::GlobalAddress:
3812 case ISD::GlobalTLSAddress:
3813 case ISD::ExternalSymbol:
3814 case ISD::ConstantPool:
3815 case ISD::JumpTable:
3816 case ISD::INTRINSIC_W_CHAIN:
3817 case ISD::INTRINSIC_WO_CHAIN:
3818 case ISD::INTRINSIC_VOID:
3819 // FIXME: Custom lowering for these operations shouldn't return null!
3820 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3821 Results.push_back(SDValue(Node, i));
3825 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3826 SmallVectorImpl<SDValue> &Results) {
3827 EVT OVT = Node->getValueType(0);
3828 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3829 Node->getOpcode() == ISD::SINT_TO_FP ||
3830 Node->getOpcode() == ISD::SETCC) {
3831 OVT = Node->getOperand(0).getValueType();
3833 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3834 DebugLoc dl = Node->getDebugLoc();
3835 SDValue Tmp1, Tmp2, Tmp3;
3836 switch (Node->getOpcode()) {
3840 // Zero extend the argument.
3841 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3842 // Perform the larger operation.
3843 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3844 if (Node->getOpcode() == ISD::CTTZ) {
3845 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3846 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3847 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3849 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3850 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3851 } else if (Node->getOpcode() == ISD::CTLZ) {
3852 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3853 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3854 DAG.getConstant(NVT.getSizeInBits() -
3855 OVT.getSizeInBits(), NVT));
3857 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3860 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3861 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3862 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3863 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3864 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3865 Results.push_back(Tmp1);
3868 case ISD::FP_TO_UINT:
3869 case ISD::FP_TO_SINT:
3870 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3871 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3872 Results.push_back(Tmp1);
3874 case ISD::UINT_TO_FP:
3875 case ISD::SINT_TO_FP:
3876 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3877 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3878 Results.push_back(Tmp1);
3883 unsigned ExtOp, TruncOp;
3884 if (OVT.isVector()) {
3885 ExtOp = ISD::BITCAST;
3886 TruncOp = ISD::BITCAST;
3888 assert(OVT.isInteger() && "Cannot promote logic operation");
3889 ExtOp = ISD::ANY_EXTEND;
3890 TruncOp = ISD::TRUNCATE;
3892 // Promote each of the values to the new type.
3893 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3894 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3895 // Perform the larger operation, then convert back
3896 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3897 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3901 unsigned ExtOp, TruncOp;
3902 if (Node->getValueType(0).isVector()) {
3903 ExtOp = ISD::BITCAST;
3904 TruncOp = ISD::BITCAST;
3905 } else if (Node->getValueType(0).isInteger()) {
3906 ExtOp = ISD::ANY_EXTEND;
3907 TruncOp = ISD::TRUNCATE;
3909 ExtOp = ISD::FP_EXTEND;
3910 TruncOp = ISD::FP_ROUND;
3912 Tmp1 = Node->getOperand(0);
3913 // Promote each of the values to the new type.
3914 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3915 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3916 // Perform the larger operation, then round down.
3917 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3918 if (TruncOp != ISD::FP_ROUND)
3919 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3921 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3922 DAG.getIntPtrConstant(0));
3923 Results.push_back(Tmp1);
3926 case ISD::VECTOR_SHUFFLE: {
3927 SmallVector<int, 8> Mask;
3928 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3930 // Cast the two input vectors.
3931 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3932 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3934 // Convert the shuffle mask to the right # elements.
3935 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3936 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3937 Results.push_back(Tmp1);
3941 unsigned ExtOp = ISD::FP_EXTEND;
3942 if (NVT.isInteger()) {
3943 ISD::CondCode CCCode =
3944 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3945 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3947 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3948 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3949 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3950 Tmp1, Tmp2, Node->getOperand(2)));
3956 // SelectionDAG::Legalize - This is the entry point for the file.
3958 void SelectionDAG::Legalize() {
3959 /// run - This is the main entry point to this class.
3961 SelectionDAGLegalize(*this).LegalizeDAG();