1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31 static unsigned translateShiftImm(unsigned imm) {
38 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
39 const MCSubtargetInfo &STI) :
41 // Initialize the set of available features.
42 setAvailableFeatures(STI.getFeatureBits());
45 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
46 return getInstructionName(Opcode);
49 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
50 OS << getRegisterName(RegNo);
53 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
55 unsigned Opcode = MI->getOpcode();
57 // Check for MOVs and print canonical forms, instead.
58 if (Opcode == ARM::MOVsr) {
59 // FIXME: Thumb variants?
60 const MCOperand &Dst = MI->getOperand(0);
61 const MCOperand &MO1 = MI->getOperand(1);
62 const MCOperand &MO2 = MI->getOperand(2);
63 const MCOperand &MO3 = MI->getOperand(3);
65 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
66 printSBitModifierOperand(MI, 6, O);
67 printPredicateOperand(MI, 4, O);
69 O << '\t' << getRegisterName(Dst.getReg())
70 << ", " << getRegisterName(MO1.getReg());
72 O << ", " << getRegisterName(MO2.getReg());
73 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
74 printAnnotation(O, Annot);
78 if (Opcode == ARM::MOVsi) {
79 // FIXME: Thumb variants?
80 const MCOperand &Dst = MI->getOperand(0);
81 const MCOperand &MO1 = MI->getOperand(1);
82 const MCOperand &MO2 = MI->getOperand(2);
84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
85 printSBitModifierOperand(MI, 5, O);
86 printPredicateOperand(MI, 3, O);
88 O << '\t' << getRegisterName(Dst.getReg())
89 << ", " << getRegisterName(MO1.getReg());
91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
92 printAnnotation(O, Annot);
96 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
97 printAnnotation(O, Annot);
103 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
104 MI->getOperand(0).getReg() == ARM::SP) {
106 printPredicateOperand(MI, 2, O);
107 if (Opcode == ARM::t2STMDB_UPD)
110 printRegisterList(MI, 4, O);
111 printAnnotation(O, Annot);
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
115 MI->getOperand(3).getImm() == -4) {
117 printPredicateOperand(MI, 4, O);
118 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
119 printAnnotation(O, Annot);
124 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
125 MI->getOperand(0).getReg() == ARM::SP) {
127 printPredicateOperand(MI, 2, O);
128 if (Opcode == ARM::t2LDMIA_UPD)
131 printRegisterList(MI, 4, O);
132 printAnnotation(O, Annot);
135 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
136 MI->getOperand(4).getImm() == 4) {
138 printPredicateOperand(MI, 5, O);
139 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
140 printAnnotation(O, Annot);
146 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
147 MI->getOperand(0).getReg() == ARM::SP) {
148 O << '\t' << "vpush";
149 printPredicateOperand(MI, 2, O);
151 printRegisterList(MI, 4, O);
152 printAnnotation(O, Annot);
157 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
158 MI->getOperand(0).getReg() == ARM::SP) {
160 printPredicateOperand(MI, 2, O);
162 printRegisterList(MI, 4, O);
163 printAnnotation(O, Annot);
167 if (Opcode == ARM::tLDMIA) {
168 bool Writeback = true;
169 unsigned BaseReg = MI->getOperand(0).getReg();
170 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
171 if (MI->getOperand(i).getReg() == BaseReg)
177 printPredicateOperand(MI, 1, O);
178 O << '\t' << getRegisterName(BaseReg);
179 if (Writeback) O << "!";
181 printRegisterList(MI, 3, O);
182 printAnnotation(O, Annot);
187 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
188 MI->getOperand(1).getReg() == ARM::R8) {
190 printPredicateOperand(MI, 2, O);
191 printAnnotation(O, Annot);
195 printInstruction(MI, O);
196 printAnnotation(O, Annot);
199 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
201 const MCOperand &Op = MI->getOperand(OpNo);
203 unsigned Reg = Op.getReg();
204 O << getRegisterName(Reg);
205 } else if (Op.isImm()) {
206 O << '#' << Op.getImm();
208 assert(Op.isExpr() && "unknown operand kind in printOperand");
209 // If a symbolic branch target was added as a constant expression then print
210 // that address in hex.
211 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
213 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
215 O.write_hex(Address);
218 // Otherwise, just print the expression.
224 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
226 const MCOperand &MO1 = MI->getOperand(OpNum);
229 else if (MO1.isImm())
230 O << "[pc, #" << MO1.getImm() << "]";
232 llvm_unreachable("Unknown LDR label operand?");
235 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
236 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
238 // REG REG 0,SH_OPC - e.g. R5, ROR R3
239 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
240 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
242 const MCOperand &MO1 = MI->getOperand(OpNum);
243 const MCOperand &MO2 = MI->getOperand(OpNum+1);
244 const MCOperand &MO3 = MI->getOperand(OpNum+2);
246 O << getRegisterName(MO1.getReg());
248 // Print the shift opc.
249 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
250 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
251 if (ShOpc == ARM_AM::rrx)
254 O << ' ' << getRegisterName(MO2.getReg());
255 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
258 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
260 const MCOperand &MO1 = MI->getOperand(OpNum);
261 const MCOperand &MO2 = MI->getOperand(OpNum+1);
263 O << getRegisterName(MO1.getReg());
265 // Print the shift opc.
266 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
267 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
268 if (ShOpc == ARM_AM::rrx)
270 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
274 //===--------------------------------------------------------------------===//
275 // Addressing Mode #2
276 //===--------------------------------------------------------------------===//
278 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
280 const MCOperand &MO1 = MI->getOperand(Op);
281 const MCOperand &MO2 = MI->getOperand(Op+1);
282 const MCOperand &MO3 = MI->getOperand(Op+2);
284 O << "[" << getRegisterName(MO1.getReg());
287 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
289 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
290 << ARM_AM::getAM2Offset(MO3.getImm());
296 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
297 << getRegisterName(MO2.getReg());
299 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
301 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
306 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
308 const MCOperand &MO1 = MI->getOperand(Op);
309 const MCOperand &MO2 = MI->getOperand(Op+1);
310 const MCOperand &MO3 = MI->getOperand(Op+2);
312 O << "[" << getRegisterName(MO1.getReg()) << "], ";
315 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
317 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
322 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
323 << getRegisterName(MO2.getReg());
325 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
327 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
331 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
333 const MCOperand &MO1 = MI->getOperand(Op);
334 const MCOperand &MO2 = MI->getOperand(Op+1);
335 O << "[" << getRegisterName(MO1.getReg()) << ", "
336 << getRegisterName(MO2.getReg()) << "]";
339 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
341 const MCOperand &MO1 = MI->getOperand(Op);
342 const MCOperand &MO2 = MI->getOperand(Op+1);
343 O << "[" << getRegisterName(MO1.getReg()) << ", "
344 << getRegisterName(MO2.getReg()) << ", lsl #1]";
347 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
349 const MCOperand &MO1 = MI->getOperand(Op);
351 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
352 printOperand(MI, Op, O);
356 const MCOperand &MO3 = MI->getOperand(Op+2);
357 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
359 if (IdxMode == ARMII::IndexModePost) {
360 printAM2PostIndexOp(MI, Op, O);
363 printAM2PreOrOffsetIndexOp(MI, Op, O);
366 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
369 const MCOperand &MO1 = MI->getOperand(OpNum);
370 const MCOperand &MO2 = MI->getOperand(OpNum+1);
373 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
375 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
380 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
381 << getRegisterName(MO1.getReg());
383 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
385 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
389 //===--------------------------------------------------------------------===//
390 // Addressing Mode #3
391 //===--------------------------------------------------------------------===//
393 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
395 const MCOperand &MO1 = MI->getOperand(Op);
396 const MCOperand &MO2 = MI->getOperand(Op+1);
397 const MCOperand &MO3 = MI->getOperand(Op+2);
399 O << "[" << getRegisterName(MO1.getReg()) << "], ";
402 O << (char)ARM_AM::getAM3Op(MO3.getImm())
403 << getRegisterName(MO2.getReg());
407 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
409 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
413 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
415 const MCOperand &MO1 = MI->getOperand(Op);
416 const MCOperand &MO2 = MI->getOperand(Op+1);
417 const MCOperand &MO3 = MI->getOperand(Op+2);
419 O << '[' << getRegisterName(MO1.getReg());
422 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
423 << getRegisterName(MO2.getReg()) << ']';
427 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
429 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
434 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
436 const MCOperand &MO3 = MI->getOperand(Op+2);
437 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
439 if (IdxMode == ARMII::IndexModePost) {
440 printAM3PostIndexOp(MI, Op, O);
443 printAM3PreOrOffsetIndexOp(MI, Op, O);
446 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
449 const MCOperand &MO1 = MI->getOperand(OpNum);
450 const MCOperand &MO2 = MI->getOperand(OpNum+1);
453 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
454 << getRegisterName(MO1.getReg());
458 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
460 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
464 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
467 const MCOperand &MO = MI->getOperand(OpNum);
468 unsigned Imm = MO.getImm();
469 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
472 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
474 const MCOperand &MO1 = MI->getOperand(OpNum);
475 const MCOperand &MO2 = MI->getOperand(OpNum+1);
477 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
480 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
483 const MCOperand &MO = MI->getOperand(OpNum);
484 unsigned Imm = MO.getImm();
485 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
489 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
491 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
493 O << ARM_AM::getAMSubModeStr(Mode);
496 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
498 const MCOperand &MO1 = MI->getOperand(OpNum);
499 const MCOperand &MO2 = MI->getOperand(OpNum+1);
501 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
502 printOperand(MI, OpNum, O);
506 O << "[" << getRegisterName(MO1.getReg());
508 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
509 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
510 if (ImmOffs || Op == ARM_AM::sub) {
512 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
518 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
520 const MCOperand &MO1 = MI->getOperand(OpNum);
521 const MCOperand &MO2 = MI->getOperand(OpNum+1);
523 O << "[" << getRegisterName(MO1.getReg());
525 // FIXME: Both darwin as and GNU as violate ARM docs here.
526 O << ", :" << (MO2.getImm() << 3);
531 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
533 const MCOperand &MO1 = MI->getOperand(OpNum);
534 O << "[" << getRegisterName(MO1.getReg()) << "]";
537 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
540 const MCOperand &MO = MI->getOperand(OpNum);
541 if (MO.getReg() == 0)
544 O << ", " << getRegisterName(MO.getReg());
547 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
550 const MCOperand &MO = MI->getOperand(OpNum);
551 uint32_t v = ~MO.getImm();
552 int32_t lsb = CountTrailingZeros_32(v);
553 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
554 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
555 O << '#' << lsb << ", #" << width;
558 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
560 unsigned val = MI->getOperand(OpNum).getImm();
561 O << ARM_MB::MemBOptToString(val);
564 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
566 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
567 bool isASR = (ShiftOp & (1 << 5)) != 0;
568 unsigned Amt = ShiftOp & 0x1f;
570 O << ", asr #" << (Amt == 0 ? 32 : Amt);
572 O << ", lsl #" << Amt;
575 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
577 unsigned Imm = MI->getOperand(OpNum).getImm();
580 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
581 O << ", lsl #" << Imm;
584 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
586 unsigned Imm = MI->getOperand(OpNum).getImm();
587 // A shift amount of 32 is encoded as 0.
590 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
591 O << ", asr #" << Imm;
594 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
597 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
598 if (i != OpNum) O << ", ";
599 O << getRegisterName(MI->getOperand(i).getReg());
604 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
606 const MCOperand &Op = MI->getOperand(OpNum);
613 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
615 const MCOperand &Op = MI->getOperand(OpNum);
616 O << ARM_PROC::IModToString(Op.getImm());
619 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
621 const MCOperand &Op = MI->getOperand(OpNum);
622 unsigned IFlags = Op.getImm();
623 for (int i=2; i >= 0; --i)
624 if (IFlags & (1 << i))
625 O << ARM_PROC::IFlagsToString(1 << i);
631 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
633 const MCOperand &Op = MI->getOperand(OpNum);
634 unsigned SpecRegRBit = Op.getImm() >> 4;
635 unsigned Mask = Op.getImm() & 0xf;
637 if (getAvailableFeatures() & ARM::FeatureMClass) {
638 switch (Op.getImm()) {
639 default: assert(0 && "Unexpected mask value!");
640 case 0: O << "apsr"; return;
641 case 1: O << "iapsr"; return;
642 case 2: O << "eapsr"; return;
643 case 3: O << "xpsr"; return;
644 case 5: O << "ipsr"; return;
645 case 6: O << "epsr"; return;
646 case 7: O << "iepsr"; return;
647 case 8: O << "msp"; return;
648 case 9: O << "psp"; return;
649 case 16: O << "primask"; return;
650 case 17: O << "basepri"; return;
651 case 18: O << "basepri_max"; return;
652 case 19: O << "faultmask"; return;
653 case 20: O << "control"; return;
657 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
658 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
659 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
663 case 4: O << "g"; return;
664 case 8: O << "nzcvq"; return;
665 case 12: O << "nzcvqg"; return;
667 llvm_unreachable("Unexpected mask value!");
677 if (Mask & 8) O << 'f';
678 if (Mask & 4) O << 's';
679 if (Mask & 2) O << 'x';
680 if (Mask & 1) O << 'c';
684 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
686 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
688 O << ARMCondCodeToString(CC);
691 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
694 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
695 O << ARMCondCodeToString(CC);
698 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
700 if (MI->getOperand(OpNum).getReg()) {
701 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
702 "Expect ARM CPSR register!");
707 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
709 O << MI->getOperand(OpNum).getImm();
712 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
714 O << "p" << MI->getOperand(OpNum).getImm();
717 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
719 O << "c" << MI->getOperand(OpNum).getImm();
722 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
724 O << "{" << MI->getOperand(OpNum).getImm() << "}";
727 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
729 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
732 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
734 O << "#" << MI->getOperand(OpNum).getImm() * 4;
737 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
739 unsigned Imm = MI->getOperand(OpNum).getImm();
740 O << "#" << (Imm == 0 ? 32 : Imm);
743 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
745 // (3 - the number of trailing zeros) is the number of then / else.
746 unsigned Mask = MI->getOperand(OpNum).getImm();
747 unsigned CondBit0 = Mask >> 4 & 1;
748 unsigned NumTZ = CountTrailingZeros_32(Mask);
749 assert(NumTZ <= 3 && "Invalid IT mask!");
750 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
751 bool T = ((Mask >> Pos) & 1) == CondBit0;
759 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
761 const MCOperand &MO1 = MI->getOperand(Op);
762 const MCOperand &MO2 = MI->getOperand(Op + 1);
764 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
765 printOperand(MI, Op, O);
769 O << "[" << getRegisterName(MO1.getReg());
770 if (unsigned RegNum = MO2.getReg())
771 O << ", " << getRegisterName(RegNum);
775 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
779 const MCOperand &MO1 = MI->getOperand(Op);
780 const MCOperand &MO2 = MI->getOperand(Op + 1);
782 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
783 printOperand(MI, Op, O);
787 O << "[" << getRegisterName(MO1.getReg());
788 if (unsigned ImmOffs = MO2.getImm())
789 O << ", #" << ImmOffs * Scale;
793 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
796 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
799 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
802 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
805 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
808 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
811 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
813 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
816 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
817 // register with shift forms.
819 // REG IMM, SH_OPC - e.g. R5, LSL #3
820 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
822 const MCOperand &MO1 = MI->getOperand(OpNum);
823 const MCOperand &MO2 = MI->getOperand(OpNum+1);
825 unsigned Reg = MO1.getReg();
826 O << getRegisterName(Reg);
828 // Print the shift opc.
829 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
830 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
831 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
832 if (ShOpc != ARM_AM::rrx)
833 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
836 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
838 const MCOperand &MO1 = MI->getOperand(OpNum);
839 const MCOperand &MO2 = MI->getOperand(OpNum+1);
841 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
842 printOperand(MI, OpNum, O);
846 O << "[" << getRegisterName(MO1.getReg());
848 int32_t OffImm = (int32_t)MO2.getImm();
849 bool isSub = OffImm < 0;
850 // Special value for #-0. All others are normal.
851 if (OffImm == INT32_MIN)
854 O << ", #-" << -OffImm;
856 O << ", #" << OffImm;
860 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
863 const MCOperand &MO1 = MI->getOperand(OpNum);
864 const MCOperand &MO2 = MI->getOperand(OpNum+1);
866 O << "[" << getRegisterName(MO1.getReg());
868 int32_t OffImm = (int32_t)MO2.getImm();
870 if (OffImm == INT32_MIN)
873 O << ", #-" << -OffImm;
875 O << ", #" << OffImm;
879 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
882 const MCOperand &MO1 = MI->getOperand(OpNum);
883 const MCOperand &MO2 = MI->getOperand(OpNum+1);
885 O << "[" << getRegisterName(MO1.getReg());
887 int32_t OffImm = (int32_t)MO2.getImm() / 4;
890 O << ", #-" << -OffImm * 4;
892 O << ", #" << OffImm * 4;
896 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
899 const MCOperand &MO1 = MI->getOperand(OpNum);
900 const MCOperand &MO2 = MI->getOperand(OpNum+1);
902 O << "[" << getRegisterName(MO1.getReg());
904 O << ", #" << MO2.getImm() * 4;
908 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
911 const MCOperand &MO1 = MI->getOperand(OpNum);
912 int32_t OffImm = (int32_t)MO1.getImm();
915 O << ", #-" << -OffImm;
917 O << ", #" << OffImm;
920 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
923 const MCOperand &MO1 = MI->getOperand(OpNum);
924 int32_t OffImm = (int32_t)MO1.getImm() / 4;
929 O << "#-" << -OffImm * 4;
931 O << "#" << OffImm * 4;
935 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
938 const MCOperand &MO1 = MI->getOperand(OpNum);
939 const MCOperand &MO2 = MI->getOperand(OpNum+1);
940 const MCOperand &MO3 = MI->getOperand(OpNum+2);
942 O << "[" << getRegisterName(MO1.getReg());
944 assert(MO2.getReg() && "Invalid so_reg load / store address!");
945 O << ", " << getRegisterName(MO2.getReg());
947 unsigned ShAmt = MO3.getImm();
949 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
950 O << ", lsl #" << ShAmt;
955 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
957 const MCOperand &MO = MI->getOperand(OpNum);
958 O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
961 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
963 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
965 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
966 O << "#0x" << utohexstr(Val);
969 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
971 unsigned Imm = MI->getOperand(OpNum).getImm();
975 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
977 unsigned Imm = MI->getOperand(OpNum).getImm();
982 default: assert (0 && "illegal ror immediate!");
983 case 1: O << "8"; break;
984 case 2: O << "16"; break;
985 case 3: O << "24"; break;
989 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
991 O << "[" << MI->getOperand(OpNum).getImm() << "]";