1 //===- MipsInstrFPU.td - Mips FPU Instruction Information --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44 [SDNPHasChain, SDNPOptInGlue]>;
45 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47 SDT_MipsExtractElementF64>;
49 // Operand for printing out a condition code.
50 let PrintMethod = "printFCCOperand" in
51 def condcode : Operand<i32>;
53 //===----------------------------------------------------------------------===//
54 // Feature predicates.
55 //===----------------------------------------------------------------------===//
57 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">;
58 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">;
59 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
60 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
62 //===----------------------------------------------------------------------===//
63 // Instruction Class Templates
65 // A set of multiclasses is used to address the register usage.
67 // S32 - single precision in 16 32bit even fp registers
68 // single precision in 32 32bit fp registers in SingleOnly mode
69 // S64 - single precision in 32 64bit fp registers (In64BitMode)
70 // D32 - double precision in 16 32bit even fp registers
71 // D64 - double precision in 32 64bit fp registers (In64BitMode)
73 // Only S32 and D32 are supported right now.
74 //===----------------------------------------------------------------------===//
77 class FPLoad<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
79 FFI<op, (outs RC:$ft), (ins MemOpnd:$base),
80 !strconcat(opstr, "\t$ft, $base"), [(set RC:$ft, (FOp addr:$base))]>;
83 class FPStore<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
85 FFI<op, (outs), (ins RC:$ft, MemOpnd:$base),
86 !strconcat(opstr, "\t$ft, $base"), [(store RC:$ft, addr:$base)]>;
88 // Instructions that convert an FP value to 32-bit fixed point.
89 multiclass FFR1_W_M<bits<6> funct, string opstr> {
90 def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
91 def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>,
92 Requires<[NotFP64bit]>;
93 def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>,
94 Requires<[IsFP64bit]>;
97 // Instructions that convert an FP value to 64-bit fixed point.
98 let Predicates = [IsFP64bit] in
99 multiclass FFR1_L_M<bits<6> funct, string opstr> {
100 def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
101 def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
104 // FP-to-FP conversion instructions.
105 multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
106 def _S : FFR1P<funct, 16, opstr, "s", FGR32, FGR32, OpNode>;
107 def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>,
108 Requires<[NotFP64bit]>;
109 def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>,
110 Requires<[IsFP64bit]>;
113 multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> {
114 let isCommutable = isComm in {
115 def _S : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>;
116 def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
117 Requires<[NotFP64bit]>;
118 def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
119 Requires<[IsFP64bit]>;
123 //===----------------------------------------------------------------------===//
124 // Floating Point Instructions
125 //===----------------------------------------------------------------------===//
126 defm ROUND_W : FFR1_W_M<0xc, "round">;
127 defm ROUND_L : FFR1_L_M<0x8, "round">;
128 defm TRUNC_W : FFR1_W_M<0xd, "trunc">;
129 defm TRUNC_L : FFR1_L_M<0x9, "trunc">;
130 defm CEIL_W : FFR1_W_M<0xe, "ceil">;
131 defm CEIL_L : FFR1_L_M<0xa, "ceil">;
132 defm FLOOR_W : FFR1_W_M<0xf, "floor">;
133 defm FLOOR_L : FFR1_L_M<0xb, "floor">;
134 defm CVT_W : FFR1_W_M<0x24, "cvt">;
135 defm CVT_L : FFR1_L_M<0x25, "cvt">;
137 def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
139 let Predicates = [NotFP64bit] in {
140 def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
141 def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>;
142 def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
145 let Predicates = [IsFP64bit] in {
146 def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
147 def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
148 def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
149 def CVT_D64_S : FFR1<0x21, 16, "cvt", "d.s", FGR64, FGR32>;
150 def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
153 defm FABS : FFR1P_M<0x5, "abs", fabs>;
154 defm FNEG : FFR1P_M<0x7, "neg", fneg>;
155 defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
157 // The odd-numbered registers are only referenced when doing loads,
158 // stores, and moves between floating-point and integer registers.
159 // When defining instructions, we reference all 32-bit registers,
160 // regardless of register aliasing.
162 /// Move Control Registers From/To CPU Registers
163 def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs),
164 "cfc1\t$rt, $fs", []>;
166 def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
167 "ctc1\t$fs, $rt", []>;
169 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
171 [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>;
173 def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
175 [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
178 def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
179 def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
180 Requires<[NotFP64bit]>;
181 def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
182 Requires<[IsFP64bit]>;
184 /// Floating Point Memory Instructions
185 let Predicates = [IsN64] in {
186 def LWC1_P8 : FPLoad<0x31, "lwc1", load, FGR32, mem64>;
187 def SWC1_P8 : FPStore<0x39, "swc1", store, FGR32, mem64>;
188 def LDC164_P8 : FPLoad<0x35, "ldc1", load, FGR64, mem64>;
189 def SDC164_P8 : FPStore<0x3d, "sdc1", store, FGR64, mem64>;
192 let Predicates = [NotN64] in {
193 def LWC1 : FPLoad<0x31, "lwc1", load, FGR32, mem>;
194 def SWC1 : FPStore<0x39, "swc1", store, FGR32, mem>;
195 let Predicates = [HasMips64] in {
196 def LDC164 : FPLoad<0x35, "ldc1", load, FGR64, mem>;
197 def SDC164 : FPStore<0x3d, "sdc1", store, FGR64, mem>;
199 let Predicates = [NotMips64] in {
200 def LDC1 : FPLoad<0x35, "ldc1", load, AFGR64, mem>;
201 def SDC1 : FPStore<0x3d, "sdc1", store, AFGR64, mem>;
205 /// Floating-point Aritmetic
206 defm FADD : FFR2P_M<0x10, "add", fadd, 1>;
207 defm FDIV : FFR2P_M<0x03, "div", fdiv>;
208 defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
209 defm FSUB : FFR2P_M<0x01, "sub", fsub>;
211 //===----------------------------------------------------------------------===//
212 // Floating Point Branch Codes
213 //===----------------------------------------------------------------------===//
214 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
215 // They must be kept in synch.
216 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
217 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
219 /// Floating Point Branch of False/True (Likely)
220 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
221 class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
222 (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
223 [(MipsFPBrcond op, bb:$dst)]>;
225 def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
226 def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
228 //===----------------------------------------------------------------------===//
229 // Floating Point Flag Conditions
230 //===----------------------------------------------------------------------===//
231 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
232 // They must be kept in synch.
233 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
234 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
235 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
236 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
237 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
238 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
239 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
240 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
241 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
242 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
243 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
244 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
245 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
246 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
247 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
248 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
250 /// Floating Point Compare
251 let Defs=[FCR31] in {
252 def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
254 [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
256 def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
258 [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>,
259 Requires<[NotFP64bit]>;
263 // Conditional moves:
264 // These instructions are expanded in
265 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
266 // conditional move instructions.
267 // flag:int, data:float
268 let usesCustomInserter = 1, Constraints = "$F = $dst" in
269 class CondMovIntFP<RegisterClass RC, bits<5> fmt, bits<6> func,
271 FFR<0x11, func, fmt, (outs RC:$dst), (ins RC:$T, CPURegs:$cond, RC:$F),
272 !strconcat(instr_asm, "\t$dst, $T, $cond"), []>;
274 def MOVZ_S : CondMovIntFP<FGR32, 16, 18, "movz.s">;
275 def MOVN_S : CondMovIntFP<FGR32, 16, 19, "movn.s">;
277 let Predicates = [NotFP64bit] in {
278 def MOVZ_D : CondMovIntFP<AFGR64, 17, 18, "movz.d">;
279 def MOVN_D : CondMovIntFP<AFGR64, 17, 19, "movn.d">;
282 defm : MovzPats<FGR32, MOVZ_S>;
283 defm : MovnPats<FGR32, MOVN_S>;
285 let Predicates = [NotFP64bit] in {
286 defm : MovzPats<AFGR64, MOVZ_D>;
287 defm : MovnPats<AFGR64, MOVN_D>;
290 let usesCustomInserter = 1, Uses = [FCR31], Constraints = "$F = $dst" in {
291 // flag:float, data:int
292 class CondMovFPInt<SDNode cmov, bits<1> tf, string instr_asm> :
293 FCMOV<tf, (outs CPURegs:$dst), (ins CPURegs:$T, CPURegs:$F),
294 !strconcat(instr_asm, "\t$dst, $T, $$fcc0"),
295 [(set CPURegs:$dst, (cmov CPURegs:$T, CPURegs:$F))]>;
297 // flag:float, data:float
298 class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
300 FFCMOV<fmt, tf, (outs RC:$dst), (ins RC:$T, RC:$F),
301 !strconcat(instr_asm, "\t$dst, $T, $$fcc0"),
302 [(set RC:$dst, (cmov RC:$T, RC:$F))]>;
305 def MOVT : CondMovFPInt<MipsCMovFP_T, 1, "movt">;
306 def MOVF : CondMovFPInt<MipsCMovFP_F, 0, "movf">;
307 def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
308 def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
310 let Predicates = [NotFP64bit] in {
311 def MOVT_D : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
312 def MOVF_D : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
315 //===----------------------------------------------------------------------===//
316 // Floating Point Pseudo-Instructions
317 //===----------------------------------------------------------------------===//
318 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
319 "# MOVCCRToCCR", []>;
321 // This pseudo instr gets expanded into 2 mtc1 instrs after register
324 MipsPseudo<(outs AFGR64:$dst),
325 (ins CPURegs:$lo, CPURegs:$hi), "",
326 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
328 // This pseudo instr gets expanded into 2 mfc1 instrs after register
330 // if n is 0, lower part of src is extracted.
331 // if n is 1, higher part of src is extracted.
332 def ExtractElementF64 :
333 MipsPseudo<(outs CPURegs:$dst),
334 (ins AFGR64:$src, i32imm:$n), "",
336 (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
338 //===----------------------------------------------------------------------===//
339 // Floating Point Patterns
340 //===----------------------------------------------------------------------===//
341 def fpimm0 : PatLeaf<(fpimm), [{
342 return N->isExactlyValue(+0.0);
345 def fpimm0neg : PatLeaf<(fpimm), [{
346 return N->isExactlyValue(-0.0);
349 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
350 def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
352 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
353 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
355 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
356 def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
358 let Predicates = [NotFP64bit] in {
359 def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
360 def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;