1 //===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MIPS register file
12 //===----------------------------------------------------------------------===//
13 let Namespace = "Mips" in {
14 def sub_fpeven : SubRegIndex;
15 def sub_fpodd : SubRegIndex;
16 def sub_32 : SubRegIndex;
19 // We have banks of 32 registers each.
20 class MipsReg<string n> : Register<n> {
22 let Namespace = "Mips";
25 class MipsRegWithSubRegs<string n, list<Register> subregs>
26 : RegisterWithSubRegs<n, subregs> {
28 let Namespace = "Mips";
32 class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
36 // Mips 64-bit CPU Registers
37 class Mips64GPRReg<bits<5> num, string n, list<Register> subregs>
38 : MipsRegWithSubRegs<n, subregs> {
40 let SubRegIndices = [sub_32];
43 // Mips 32-bit FPU Registers
44 class FPR<bits<5> num, string n> : MipsReg<n> {
48 // Mips 64-bit (aliased) FPU Registers
49 class AFPR<bits<5> num, string n, list<Register> subregs>
50 : MipsRegWithSubRegs<n, subregs> {
52 let SubRegIndices = [sub_fpeven, sub_fpodd];
55 class AFPR64<bits<5> num, string n, list<Register> subregs>
56 : MipsRegWithSubRegs<n, subregs> {
58 let SubRegIndices = [sub_32];
61 // Mips Hardware Registers
62 class HWR<bits<5> num, string n> : MipsReg<n> {
66 //===----------------------------------------------------------------------===//
68 //===----------------------------------------------------------------------===//
70 let Namespace = "Mips" in {
71 // FIXME: Fix DwarfRegNum.
73 // General Purpose Registers
74 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
75 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
76 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
77 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
78 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
79 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
80 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
81 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
82 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
83 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
84 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
85 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
86 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
87 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
88 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
89 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
90 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
91 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
92 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
93 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
94 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
95 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
96 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
97 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
98 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
99 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
100 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
101 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
102 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
103 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
104 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
105 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
107 // General Purpose 64-bit Registers
108 def ZERO_64 : Mips64GPRReg< 0, "ZERO", [ZERO]>;
109 def AT_64 : Mips64GPRReg< 1, "AT", [AT]>;
110 def V0_64 : Mips64GPRReg< 2, "2", [V0]>;
111 def V1_64 : Mips64GPRReg< 3, "3", [V1]>;
112 def A0_64 : Mips64GPRReg< 4, "4", [A0]>;
113 def A1_64 : Mips64GPRReg< 5, "5", [A1]>;
114 def A2_64 : Mips64GPRReg< 6, "6", [A2]>;
115 def A3_64 : Mips64GPRReg< 7, "7", [A3]>;
116 def T0_64 : Mips64GPRReg< 8, "8", [T0]>;
117 def T1_64 : Mips64GPRReg< 9, "9", [T1]>;
118 def T2_64 : Mips64GPRReg< 10, "10", [T2]>;
119 def T3_64 : Mips64GPRReg< 11, "11", [T3]>;
120 def T4_64 : Mips64GPRReg< 12, "12", [T4]>;
121 def T5_64 : Mips64GPRReg< 13, "13", [T5]>;
122 def T6_64 : Mips64GPRReg< 14, "14", [T6]>;
123 def T7_64 : Mips64GPRReg< 15, "15", [T7]>;
124 def S0_64 : Mips64GPRReg< 16, "16", [S0]>;
125 def S1_64 : Mips64GPRReg< 17, "17", [S1]>;
126 def S2_64 : Mips64GPRReg< 18, "18", [S2]>;
127 def S3_64 : Mips64GPRReg< 19, "19", [S3]>;
128 def S4_64 : Mips64GPRReg< 20, "20", [S4]>;
129 def S5_64 : Mips64GPRReg< 21, "21", [S5]>;
130 def S6_64 : Mips64GPRReg< 22, "22", [S6]>;
131 def S7_64 : Mips64GPRReg< 23, "23", [S7]>;
132 def T8_64 : Mips64GPRReg< 24, "24", [T8]>;
133 def T9_64 : Mips64GPRReg< 25, "25", [T9]>;
134 def K0_64 : Mips64GPRReg< 26, "26", [K0]>;
135 def K1_64 : Mips64GPRReg< 27, "27", [K1]>;
136 def GP_64 : Mips64GPRReg< 28, "GP", [GP]>;
137 def SP_64 : Mips64GPRReg< 29, "SP", [SP]>;
138 def FP_64 : Mips64GPRReg< 30, "FP", [FP]>;
139 def RA_64 : Mips64GPRReg< 31, "RA", [RA]>;
141 /// Mips Single point precision FPU Registers
142 def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
143 def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
144 def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>;
145 def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>;
146 def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>;
147 def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>;
148 def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>;
149 def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>;
150 def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>;
151 def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>;
152 def F10 : FPR<10, "F10">, DwarfRegNum<[42]>;
153 def F11 : FPR<11, "F11">, DwarfRegNum<[43]>;
154 def F12 : FPR<12, "F12">, DwarfRegNum<[44]>;
155 def F13 : FPR<13, "F13">, DwarfRegNum<[45]>;
156 def F14 : FPR<14, "F14">, DwarfRegNum<[46]>;
157 def F15 : FPR<15, "F15">, DwarfRegNum<[47]>;
158 def F16 : FPR<16, "F16">, DwarfRegNum<[48]>;
159 def F17 : FPR<17, "F17">, DwarfRegNum<[49]>;
160 def F18 : FPR<18, "F18">, DwarfRegNum<[50]>;
161 def F19 : FPR<19, "F19">, DwarfRegNum<[51]>;
162 def F20 : FPR<20, "F20">, DwarfRegNum<[52]>;
163 def F21 : FPR<21, "F21">, DwarfRegNum<[53]>;
164 def F22 : FPR<22, "F22">, DwarfRegNum<[54]>;
165 def F23 : FPR<23, "F23">, DwarfRegNum<[55]>;
166 def F24 : FPR<24, "F24">, DwarfRegNum<[56]>;
167 def F25 : FPR<25, "F25">, DwarfRegNum<[57]>;
168 def F26 : FPR<26, "F26">, DwarfRegNum<[58]>;
169 def F27 : FPR<27, "F27">, DwarfRegNum<[59]>;
170 def F28 : FPR<28, "F28">, DwarfRegNum<[60]>;
171 def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
172 def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
173 def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
175 /// Mips Double point precision FPU Registers (aliased
176 /// with the single precision to hold 64 bit values)
177 def D0 : AFPR< 0, "F0", [F0, F1]>;
178 def D1 : AFPR< 2, "F2", [F2, F3]>;
179 def D2 : AFPR< 4, "F4", [F4, F5]>;
180 def D3 : AFPR< 6, "F6", [F6, F7]>;
181 def D4 : AFPR< 8, "F8", [F8, F9]>;
182 def D5 : AFPR<10, "F10", [F10, F11]>;
183 def D6 : AFPR<12, "F12", [F12, F13]>;
184 def D7 : AFPR<14, "F14", [F14, F15]>;
185 def D8 : AFPR<16, "F16", [F16, F17]>;
186 def D9 : AFPR<18, "F18", [F18, F19]>;
187 def D10 : AFPR<20, "F20", [F20, F21]>;
188 def D11 : AFPR<22, "F22", [F22, F23]>;
189 def D12 : AFPR<24, "F24", [F24, F25]>;
190 def D13 : AFPR<26, "F26", [F26, F27]>;
191 def D14 : AFPR<28, "F28", [F28, F29]>;
192 def D15 : AFPR<30, "F30", [F30, F31]>;
194 /// Mips Double point precision FPU Registers in MFP64 mode.
195 def D0_64 : AFPR64<0, "F0", [F0]>;
196 def D1_64 : AFPR64<1, "F1", [F1]>;
197 def D2_64 : AFPR64<2, "F2", [F2]>;
198 def D3_64 : AFPR64<3, "F3", [F3]>;
199 def D4_64 : AFPR64<4, "F4", [F4]>;
200 def D5_64 : AFPR64<5, "F5", [F5]>;
201 def D6_64 : AFPR64<6, "F6", [F6]>;
202 def D7_64 : AFPR64<7, "F7", [F7]>;
203 def D8_64 : AFPR64<8, "F8", [F8]>;
204 def D9_64 : AFPR64<9, "F9", [F9]>;
205 def D10_64 : AFPR64<10, "F10", [F10]>;
206 def D11_64 : AFPR64<11, "F11", [F11]>;
207 def D12_64 : AFPR64<12, "F12", [F12]>;
208 def D13_64 : AFPR64<13, "F13", [F13]>;
209 def D14_64 : AFPR64<14, "F14", [F14]>;
210 def D15_64 : AFPR64<15, "F15", [F15]>;
211 def D16_64 : AFPR64<16, "F16", [F16]>;
212 def D17_64 : AFPR64<17, "F17", [F17]>;
213 def D18_64 : AFPR64<18, "F18", [F18]>;
214 def D19_64 : AFPR64<19, "F19", [F19]>;
215 def D20_64 : AFPR64<20, "F20", [F20]>;
216 def D21_64 : AFPR64<21, "F21", [F21]>;
217 def D22_64 : AFPR64<22, "F22", [F22]>;
218 def D23_64 : AFPR64<23, "F23", [F23]>;
219 def D24_64 : AFPR64<24, "F24", [F24]>;
220 def D25_64 : AFPR64<25, "F25", [F25]>;
221 def D26_64 : AFPR64<26, "F26", [F26]>;
222 def D27_64 : AFPR64<27, "F27", [F27]>;
223 def D28_64 : AFPR64<28, "F28", [F28]>;
224 def D29_64 : AFPR64<29, "F29", [F29]>;
225 def D30_64 : AFPR64<30, "F30", [F30]>;
226 def D31_64 : AFPR64<31, "F31", [F31]>;
229 def HI : Register<"hi">, DwarfRegNum<[64]>;
230 def LO : Register<"lo">, DwarfRegNum<[65]>;
232 let SubRegIndices = [sub_32] in {
233 def HI64 : RegisterWithSubRegs<"hi", [HI]>;
234 def LO64 : RegisterWithSubRegs<"lo", [LO]>;
237 // Status flags register
238 def FCR31 : Register<"31">;
240 // Hardware register $29
241 def HWR29 : Register<"29">;
244 //===----------------------------------------------------------------------===//
246 //===----------------------------------------------------------------------===//
248 def CPURegs : RegisterClass<"Mips", [i32], 32, (add
249 // Return Values and Arguments
250 V0, V1, A0, A1, A2, A3,
251 // Not preserved across procedure calls
252 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
254 S0, S1, S2, S3, S4, S5, S6, S7,
256 ZERO, AT, K0, K1, GP, SP, FP, RA)>;
258 def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add
259 // Return Values and Arguments
260 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
261 // Not preserved across procedure calls
262 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, T8_64, T9_64,
264 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
266 ZERO_64, AT_64, K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)> {
267 let SubRegClasses = [(CPURegs sub_32)];
271 // * FGR64 - 32 64-bit registers
272 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
275 // * FGR32 - 16 32-bit even registers
276 // * FGR32 - 32 32-bit registers (single float only mode)
277 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
279 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
280 // Return Values and Arguments
282 // Not preserved across procedure calls
283 D2, D3, D4, D5, D8, D9,
285 D10, D11, D12, D13, D14, D15)> {
286 let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
289 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> {
290 let SubRegClasses = [(FGR32 sub_32)];
293 // Condition Register for floating point operations
294 def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>;
297 def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>;
298 def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)> {
299 let SubRegClasses = [(HILO sub_32)];
302 // Hardware registers
303 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;