1 //===-- PTXISelDAGToDAG.cpp - A dag to dag inst selector for PTX ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the PTX target.
12 //===----------------------------------------------------------------------===//
15 #include "PTXMachineFunctionInfo.h"
16 #include "PTXTargetMachine.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
26 // PTXDAGToDAGISel - PTX specific code to select PTX machine
27 // instructions for SelectionDAG operations.
28 class PTXDAGToDAGISel : public SelectionDAGISel {
30 PTXDAGToDAGISel(PTXTargetMachine &TM, CodeGenOpt::Level OptLevel);
32 virtual const char *getPassName() const {
33 return "PTX DAG->DAG Pattern Instruction Selection";
36 SDNode *Select(SDNode *Node);
38 // Complex Pattern Selectors.
39 bool SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2);
40 bool SelectADDRri(SDValue &Addr, SDValue &Base, SDValue &Offset);
41 bool SelectADDRii(SDValue &Addr, SDValue &Base, SDValue &Offset);
42 bool SelectADDRlocal(SDValue &Addr, SDValue &Base, SDValue &Offset);
44 // Include the pieces auto'gened from the target description
45 #include "PTXGenDAGISel.inc"
48 // We need this only because we can't match intruction BRAdp
49 // pattern (PTXbrcond bb:$d, ...) in PTXInstrInfo.td
50 SDNode *SelectBRCOND(SDNode *Node);
52 SDNode *SelectREADPARAM(SDNode *Node);
53 SDNode *SelectWRITEPARAM(SDNode *Node);
54 SDNode *SelectFrameIndex(SDNode *Node);
56 bool isImm(const SDValue &operand);
57 bool SelectImm(const SDValue &operand, SDValue &imm);
59 const PTXSubtarget& getSubtarget() const;
60 }; // class PTXDAGToDAGISel
63 // createPTXISelDag - This pass converts a legalized DAG into a
64 // PTX-specific DAG, ready for instruction scheduling
65 FunctionPass *llvm::createPTXISelDag(PTXTargetMachine &TM,
66 CodeGenOpt::Level OptLevel) {
67 return new PTXDAGToDAGISel(TM, OptLevel);
70 PTXDAGToDAGISel::PTXDAGToDAGISel(PTXTargetMachine &TM,
71 CodeGenOpt::Level OptLevel)
72 : SelectionDAGISel(TM, OptLevel) {}
74 SDNode *PTXDAGToDAGISel::Select(SDNode *Node) {
75 switch (Node->getOpcode()) {
77 return SelectBRCOND(Node);
78 case PTXISD::READ_PARAM:
79 return SelectREADPARAM(Node);
80 case PTXISD::WRITE_PARAM:
81 return SelectWRITEPARAM(Node);
83 return SelectFrameIndex(Node);
85 return SelectCode(Node);
89 SDNode *PTXDAGToDAGISel::SelectBRCOND(SDNode *Node) {
90 assert(Node->getNumOperands() >= 3);
92 SDValue Chain = Node->getOperand(0);
93 SDValue Pred = Node->getOperand(1);
94 SDValue Target = Node->getOperand(2); // branch target
95 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::Normal, MVT::i32);
96 DebugLoc dl = Node->getDebugLoc();
98 assert(Target.getOpcode() == ISD::BasicBlock);
99 assert(Pred.getValueType() == MVT::i1);
102 SDValue Ops[] = { Target, Pred, PredOp, Chain };
103 return CurDAG->getMachineNode(PTX::BRAdp, dl, MVT::Other, Ops, 4);
106 SDNode *PTXDAGToDAGISel::SelectREADPARAM(SDNode *Node) {
107 SDValue Chain = Node->getOperand(0);
108 SDValue Index = Node->getOperand(1);
112 // Get the type of parameter we are reading
113 EVT VT = Node->getValueType(0);
114 assert(VT.isSimple() && "READ_PARAM only implemented for MVT types");
116 MVT Type = VT.getSimpleVT();
119 OpCode = PTX::READPARAMPRED;
120 else if (Type == MVT::i16)
121 OpCode = PTX::READPARAMI16;
122 else if (Type == MVT::i32)
123 OpCode = PTX::READPARAMI32;
124 else if (Type == MVT::i64)
125 OpCode = PTX::READPARAMI64;
126 else if (Type == MVT::f32)
127 OpCode = PTX::READPARAMF32;
129 assert(Type == MVT::f64 && "Unexpected type!");
130 OpCode = PTX::READPARAMF64;
133 SDValue Pred = CurDAG->getRegister(PTX::NoRegister, MVT::i1);
134 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::None, MVT::i32);
135 DebugLoc dl = Node->getDebugLoc();
137 SDValue Ops[] = { Index, Pred, PredOp, Chain };
138 return CurDAG->getMachineNode(OpCode, dl, VT, Ops, 4);
141 SDNode *PTXDAGToDAGISel::SelectWRITEPARAM(SDNode *Node) {
143 SDValue Chain = Node->getOperand(0);
144 SDValue Value = Node->getOperand(1);
148 //Node->dumpr(CurDAG);
150 // Get the type of parameter we are writing
151 EVT VT = Value->getValueType(0);
152 assert(VT.isSimple() && "WRITE_PARAM only implemented for MVT types");
154 MVT Type = VT.getSimpleVT();
157 OpCode = PTX::WRITEPARAMPRED;
158 else if (Type == MVT::i16)
159 OpCode = PTX::WRITEPARAMI16;
160 else if (Type == MVT::i32)
161 OpCode = PTX::WRITEPARAMI32;
162 else if (Type == MVT::i64)
163 OpCode = PTX::WRITEPARAMI64;
164 else if (Type == MVT::f32)
165 OpCode = PTX::WRITEPARAMF32;
166 else if (Type == MVT::f64)
167 OpCode = PTX::WRITEPARAMF64;
169 llvm_unreachable("Invalid type in SelectWRITEPARAM");
171 SDValue Pred = CurDAG->getRegister(PTX::NoRegister, MVT::i1);
172 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::None, MVT::i32);
173 DebugLoc dl = Node->getDebugLoc();
175 SDValue Ops[] = { Value, Pred, PredOp, Chain };
176 SDNode* Ret = CurDAG->getMachineNode(OpCode, dl, MVT::Other, Ops, 4);
178 //dbgs() << "SelectWRITEPARAM produced:\n\t";
179 //Ret->dumpr(CurDAG);
184 SDNode *PTXDAGToDAGISel::SelectFrameIndex(SDNode *Node) {
185 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
186 //dbgs() << "Selecting FrameIndex at index " << FI << "\n";
187 //SDValue TFI = CurDAG->getTargetFrameIndex(FI, Node->getValueType(0));
189 PTXMachineFunctionInfo *MFI = MF->getInfo<PTXMachineFunctionInfo>();
191 SDValue FrameSymbol = CurDAG->getTargetExternalSymbol(MFI->getFrameSymbol(FI),
192 Node->getValueType(0));
194 return FrameSymbol.getNode();
197 // Match memory operand of the form [reg+reg]
198 bool PTXDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2) {
199 if (Addr.getOpcode() != ISD::ADD || Addr.getNumOperands() < 2 ||
200 isImm(Addr.getOperand(0)) || isImm(Addr.getOperand(1)))
203 assert(Addr.getValueType().isSimple() && "Type must be simple");
206 R2 = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
211 // Match memory operand of the form [reg], [imm+reg], and [reg+imm]
212 bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
214 // FrameIndex addresses are handled separately
215 //errs() << "SelectADDRri: ";
216 //Addr.getNode()->dumpr();
217 if (isa<FrameIndexSDNode>(Addr)) {
218 //errs() << "Failure\n";
222 if (CurDAG->isBaseWithConstantOffset(Addr)) {
223 Base = Addr.getOperand(0);
224 if (isa<FrameIndexSDNode>(Base)) {
225 //errs() << "Failure\n";
228 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
229 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
230 //errs() << "Success\n";
234 /*if (Addr.getNumOperands() == 1) {
236 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
237 errs() << "Success\n";
241 //errs() << "SelectADDRri fails on: ";
242 //Addr.getNode()->dumpr();
245 //errs() << "Failure\n";
250 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
252 //errs() << "Success\n";
255 /*if (Addr.getOpcode() != ISD::ADD) {
256 // let SelectADDRii handle the [imm] case
261 assert(Addr.getValueType().isSimple() && "Type must be simple");
263 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
268 if (Addr.getNumOperands() < 2)
271 // let SelectADDRii handle the [imm+imm] case
272 if (isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1)))
275 // try [reg+imm] and [imm+reg]
276 for (int i = 0; i < 2; i ++)
277 if (SelectImm(Addr.getOperand(1-i), Offset)) {
278 Base = Addr.getOperand(i);
282 // neither [reg+imm] nor [imm+reg]
286 // Match memory operand of the form [imm+imm] and [imm]
287 bool PTXDAGToDAGISel::SelectADDRii(SDValue &Addr, SDValue &Base,
290 if (Addr.getOpcode() == ISD::ADD) {
291 return SelectImm(Addr.getOperand(0), Base) &&
292 SelectImm(Addr.getOperand(1), Offset);
296 if (SelectImm(Addr, Base)) {
297 assert(Addr.getValueType().isSimple() && "Type must be simple");
299 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
307 // Match memory operand of the form [reg], [imm+reg], and [reg+imm]
308 bool PTXDAGToDAGISel::SelectADDRlocal(SDValue &Addr, SDValue &Base,
310 //errs() << "SelectADDRlocal: ";
311 //Addr.getNode()->dumpr();
312 if (isa<FrameIndexSDNode>(Addr)) {
314 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
315 //errs() << "Success\n";
319 if (CurDAG->isBaseWithConstantOffset(Addr)) {
320 Base = Addr.getOperand(0);
321 if (!isa<FrameIndexSDNode>(Base)) {
322 //errs() << "Failure\n";
325 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
326 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
327 //errs() << "Offset: ";
328 //Offset.getNode()->dumpr();
329 //errs() << "Success\n";
333 //errs() << "Failure\n";
337 bool PTXDAGToDAGISel::isImm(const SDValue &operand) {
338 return ConstantSDNode::classof(operand.getNode());
341 bool PTXDAGToDAGISel::SelectImm(const SDValue &operand, SDValue &imm) {
342 SDNode *node = operand.getNode();
343 if (!ConstantSDNode::classof(node))
346 ConstantSDNode *CN = cast<ConstantSDNode>(node);
347 imm = CurDAG->getTargetConstant(*CN->getConstantIntValue(),
348 operand.getValueType());
352 const PTXSubtarget& PTXDAGToDAGISel::getSubtarget() const
354 return TM.getSubtarget<PTXSubtarget>();