1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/PPCBaseInfo.h"
16 #include "MCTargetDesc/PPCFixupKinds.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Support/ErrorHandling.h"
24 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
27 class PPCMCCodeEmitter : public MCCodeEmitter {
28 PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
29 void operator=(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
32 PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
36 ~PPCMCCodeEmitter() {}
38 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
39 SmallVectorImpl<MCFixup> &Fixups) const;
40 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
41 SmallVectorImpl<MCFixup> &Fixups) const;
42 unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
43 SmallVectorImpl<MCFixup> &Fixups) const;
44 unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
45 SmallVectorImpl<MCFixup> &Fixups) const;
46 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
47 SmallVectorImpl<MCFixup> &Fixups) const;
48 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
49 SmallVectorImpl<MCFixup> &Fixups) const;
50 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
51 SmallVectorImpl<MCFixup> &Fixups) const;
53 /// getMachineOpValue - Return binary encoding of operand. If the machine
54 /// operand requires relocation, record the relocation and return zero.
55 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
56 SmallVectorImpl<MCFixup> &Fixups) const;
58 // getBinaryCodeForInstr - TableGen'erated function for getting the
59 // binary encoding for an instruction.
60 unsigned getBinaryCodeForInstr(const MCInst &MI,
61 SmallVectorImpl<MCFixup> &Fixups) const;
62 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
63 SmallVectorImpl<MCFixup> &Fixups) const {
64 unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
66 // Output the constant in big endian byte order.
67 for (unsigned i = 0; i != 4; ++i) {
68 OS << (char)(Bits >> 24);
72 ++MCNumEmitted; // Keep track of the # of mi's emitted.
77 } // end anonymous namespace
79 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
80 const MCSubtargetInfo &STI,
82 return new PPCMCCodeEmitter(MCII, STI, Ctx);
85 unsigned PPCMCCodeEmitter::
86 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
87 SmallVectorImpl<MCFixup> &Fixups) const {
88 const MCOperand &MO = MI.getOperand(OpNo);
89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
91 // Add a fixup for the branch target.
92 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
93 (MCFixupKind)PPC::fixup_ppc_br24));
97 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
98 SmallVectorImpl<MCFixup> &Fixups) const {
99 const MCOperand &MO = MI.getOperand(OpNo);
100 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
102 // Add a fixup for the branch target.
103 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
104 (MCFixupKind)PPC::fixup_ppc_brcond14));
108 unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
109 SmallVectorImpl<MCFixup> &Fixups) const {
110 const MCOperand &MO = MI.getOperand(OpNo);
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
113 // Add a fixup for the branch target.
114 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
115 (MCFixupKind)PPC::fixup_ppc_ha16));
119 unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
120 SmallVectorImpl<MCFixup> &Fixups) const {
121 const MCOperand &MO = MI.getOperand(OpNo);
122 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
124 // Add a fixup for the branch target.
125 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
126 (MCFixupKind)PPC::fixup_ppc_lo16));
130 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
131 SmallVectorImpl<MCFixup> &Fixups) const {
132 // Encode (imm, reg) as a memri, which has the low 16-bits as the
133 // displacement and the next 5 bits as the register #.
134 assert(MI.getOperand(OpNo+1).isReg());
135 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
137 const MCOperand &MO = MI.getOperand(OpNo);
139 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
141 // Add a fixup for the displacement field.
142 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
143 (MCFixupKind)PPC::fixup_ppc_lo16));
148 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
149 SmallVectorImpl<MCFixup> &Fixups) const {
150 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
151 // displacement and the next 5 bits as the register #.
152 assert(MI.getOperand(OpNo+1).isReg());
153 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
155 const MCOperand &MO = MI.getOperand(OpNo);
157 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
159 // Add a fixup for the branch target.
160 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
161 (MCFixupKind)PPC::fixup_ppc_lo14));
166 unsigned PPCMCCodeEmitter::
167 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
168 SmallVectorImpl<MCFixup> &Fixups) const {
169 const MCOperand &MO = MI.getOperand(OpNo);
170 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
171 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
172 return 0x80 >> getPPCRegisterNumbering(MO.getReg());
176 unsigned PPCMCCodeEmitter::
177 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
178 SmallVectorImpl<MCFixup> &Fixups) const {
180 // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
181 // The GPR operand should come through here though.
182 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
183 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
184 return getPPCRegisterNumbering(MO.getReg());
188 "Relocation required in an instruction that we cannot encode!");
193 #include "PPCGenMCCodeEmitter.inc"