1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static SDValue Insert128BitVector(SDValue Result,
70 static SDValue Extract128BitVector(SDValue Vec,
75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
76 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
77 /// simple subregister reference. Idx is an index in the 128 bits we
78 /// want. It need not be aligned to a 128-bit bounday. That makes
79 /// lowering EXTRACT_VECTOR_ELT operations easier.
80 static SDValue Extract128BitVector(SDValue Vec,
84 EVT VT = Vec.getValueType();
85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
86 EVT ElVT = VT.getVectorElementType();
87 int Factor = VT.getSizeInBits()/128;
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 VT.getVectorNumElements()/Factor);
91 // Extract from UNDEF is UNDEF.
92 if (Vec.getOpcode() == ISD::UNDEF)
93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
95 if (isa<ConstantSDNode>(Idx)) {
96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
99 // we can match to VEXTRACTF128.
100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
102 // This is the index of the first element of the 128-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
117 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
118 /// sets things up to match to an AVX VINSERTF128 instruction or a
119 /// simple superregister reference. Idx is an index in the 128 bits
120 /// we want. It need not be aligned to a 128-bit bounday. That makes
121 /// lowering INSERT_VECTOR_ELT operations easier.
122 static SDValue Insert128BitVector(SDValue Result,
127 if (isa<ConstantSDNode>(Idx)) {
128 EVT VT = Vec.getValueType();
129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
131 EVT ElVT = VT.getVectorElementType();
132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
133 EVT ResultVT = Result.getValueType();
135 // Insert the relevant 128 bits.
136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
138 // This is the index of the first element of the 128-bit chunk
140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
152 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
154 bool is64Bit = Subtarget->is64Bit();
156 if (Subtarget->isTargetEnvMacho()) {
158 return new X8664_MachoTargetObjectFile();
159 return new TargetLoweringObjectFileMachO();
162 if (Subtarget->isTargetELF())
163 return new TargetLoweringObjectFileELF();
164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
165 return new TargetLoweringObjectFileCOFF();
166 llvm_unreachable("unknown subtarget type");
169 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<X86Subtarget>();
172 X86ScalarSSEf64 = Subtarget->hasXMMInt();
173 X86ScalarSSEf32 = Subtarget->hasXMM();
174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
176 RegInfo = TM.getRegisterInfo();
177 TD = getTargetData();
179 // Set up the TargetLowering object.
180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
183 setBooleanContents(ZeroOrOneBooleanContent);
184 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
187 // For 64-bit since we have so many registers use the ILP scheduler, for
188 // 32-bit code use the register pressure specific scheduling.
189 if (Subtarget->is64Bit())
190 setSchedulingPreference(Sched::ILP);
192 setSchedulingPreference(Sched::RegPressure);
193 setStackPointerRegisterToSaveRestore(X86StackPtr);
195 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
196 // Setup Windows compiler runtime calls.
197 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
198 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
199 setLibcallName(RTLIB::SREM_I64, "_allrem");
200 setLibcallName(RTLIB::UREM_I64, "_aullrem");
201 setLibcallName(RTLIB::MUL_I64, "_allmul");
202 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
203 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
204 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
209 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
210 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
213 if (Subtarget->isTargetDarwin()) {
214 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
215 setUseUnderscoreSetJmp(false);
216 setUseUnderscoreLongJmp(false);
217 } else if (Subtarget->isTargetMingw()) {
218 // MS runtime is weird: it exports _setjmp, but longjmp!
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(false);
222 setUseUnderscoreSetJmp(true);
223 setUseUnderscoreLongJmp(true);
226 // Set up the register classes.
227 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
228 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
229 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
230 if (Subtarget->is64Bit())
231 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
235 // We don't accept any truncstore of integer registers.
236 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
239 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
241 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
243 // SETOEQ and SETUNE require checking two conditions.
244 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
248 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
249 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
253 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
257 if (Subtarget->is64Bit()) {
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
260 } else if (!UseSoftFloat) {
261 // We have an algorithm for SSE2->double, and we turn this into a
262 // 64-bit FILD followed by conditional FADD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
264 // We have an algorithm for SSE2, and we turn this into a 64-bit
265 // FILD for other targets.
266 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
275 // SSE has no i16 to fp conversion, only i32
276 if (X86ScalarSSEf32) {
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 // f32 and f64 cases are Legal, f80 case is not
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
289 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
290 // are Legal, f80 is custom lowered.
291 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
292 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
294 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
296 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
299 if (X86ScalarSSEf32) {
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
301 // f32 and f64 cases are Legal, f80 case is not
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
308 // Handle FP_TO_UINT by promoting the destination to a larger signed
310 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
311 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
314 if (Subtarget->is64Bit()) {
315 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
317 } else if (!UseSoftFloat) {
318 // Since AVX is a superset of SSE3, only check for SSE here.
319 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
320 // Expand FP_TO_UINT into a select.
321 // FIXME: We would like to use a Custom expander here eventually to do
322 // the optimal thing for SSE vs. the default expansion in the legalizer.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
325 // With SSE3 we can use fisttpll to convert to a signed i64; without
326 // SSE, we're stuck with a fistpll.
327 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
330 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
331 if (!X86ScalarSSEf64) {
332 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
333 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
334 if (Subtarget->is64Bit()) {
335 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
336 // Without SSE, i64->f64 goes through memory.
337 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
341 // Scalar integer divide and remainder are lowered to use operations that
342 // produce two results, to match the available instructions. This exposes
343 // the two-result form to trivial CSE, which is able to combine x/y and x%y
344 // into a single instruction.
346 // Scalar integer multiply-high is also lowered to use two-result
347 // operations, to match the available instructions. However, plain multiply
348 // (low) operations are left as Legal, as there are single-result
349 // instructions for this in x86. Using the two-result multiply instructions
350 // when both high and low results are needed must be arranged by dagcombine.
351 for (unsigned i = 0, e = 4; i != e; ++i) {
353 setOperationAction(ISD::MULHS, VT, Expand);
354 setOperationAction(ISD::MULHU, VT, Expand);
355 setOperationAction(ISD::SDIV, VT, Expand);
356 setOperationAction(ISD::UDIV, VT, Expand);
357 setOperationAction(ISD::SREM, VT, Expand);
358 setOperationAction(ISD::UREM, VT, Expand);
360 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
361 setOperationAction(ISD::ADDC, VT, Custom);
362 setOperationAction(ISD::ADDE, VT, Custom);
363 setOperationAction(ISD::SUBC, VT, Custom);
364 setOperationAction(ISD::SUBE, VT, Custom);
367 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
368 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
369 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
370 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
371 if (Subtarget->is64Bit())
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
376 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f32 , Expand);
378 setOperationAction(ISD::FREM , MVT::f64 , Expand);
379 setOperationAction(ISD::FREM , MVT::f80 , Expand);
380 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
382 if (Subtarget->hasBMI()) {
383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
385 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
386 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
387 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
388 if (Subtarget->is64Bit())
389 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
392 if (Subtarget->hasLZCNT()) {
393 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
395 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
396 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
397 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
398 if (Subtarget->is64Bit())
399 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
402 if (Subtarget->hasPOPCNT()) {
403 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
405 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
406 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
407 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
408 if (Subtarget->is64Bit())
409 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
412 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
413 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
415 // These should be promoted to a larger select which is supported.
416 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
417 // X86 wants to expand cmov itself.
418 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
419 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
420 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
421 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
422 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
423 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
424 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
428 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
430 if (Subtarget->is64Bit()) {
431 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
432 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
434 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
437 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
440 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
441 if (Subtarget->is64Bit())
442 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
443 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
444 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
445 if (Subtarget->is64Bit()) {
446 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
447 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
448 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
449 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
452 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
453 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
454 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
455 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
456 if (Subtarget->is64Bit()) {
457 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
458 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
459 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
462 if (Subtarget->hasXMM())
463 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
465 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
466 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
468 // On X86 and X86-64, atomic operations are lowered to locked instructions.
469 // Locked instructions, in turn, have implicit fence semantics (all memory
470 // operations are flushed before issuing the locked instruction, and they
471 // are not buffered), so we can fold away the common pattern of
472 // fence-atomic-fence.
473 setShouldFoldAtomicFences(true);
475 // Expand certain atomics
476 for (unsigned i = 0, e = 4; i != e; ++i) {
478 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
479 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
480 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
483 if (!Subtarget->is64Bit()) {
484 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
485 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
486 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
487 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
488 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
489 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
490 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
491 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
494 if (Subtarget->hasCmpxchg16b()) {
495 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
498 // FIXME - use subtarget debug flags
499 if (!Subtarget->isTargetDarwin() &&
500 !Subtarget->isTargetELF() &&
501 !Subtarget->isTargetCygMing()) {
502 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
505 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
506 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
507 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
508 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
509 if (Subtarget->is64Bit()) {
510 setExceptionPointerRegister(X86::RAX);
511 setExceptionSelectorRegister(X86::RDX);
513 setExceptionPointerRegister(X86::EAX);
514 setExceptionSelectorRegister(X86::EDX);
516 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
517 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
519 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
520 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
522 setOperationAction(ISD::TRAP, MVT::Other, Legal);
524 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
525 setOperationAction(ISD::VASTART , MVT::Other, Custom);
526 setOperationAction(ISD::VAEND , MVT::Other, Expand);
527 if (Subtarget->is64Bit()) {
528 setOperationAction(ISD::VAARG , MVT::Other, Custom);
529 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
531 setOperationAction(ISD::VAARG , MVT::Other, Expand);
532 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
535 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
536 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
538 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
539 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
540 MVT::i64 : MVT::i32, Custom);
541 else if (EnableSegmentedStacks)
542 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
543 MVT::i64 : MVT::i32, Custom);
545 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
546 MVT::i64 : MVT::i32, Expand);
548 if (!UseSoftFloat && X86ScalarSSEf64) {
549 // f32 and f64 use SSE.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
552 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
554 // Use ANDPD to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f64, Custom);
556 setOperationAction(ISD::FABS , MVT::f32, Custom);
558 // Use XORP to simulate FNEG.
559 setOperationAction(ISD::FNEG , MVT::f64, Custom);
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 // Use ANDPD and ORPD to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // Lower this to FGETSIGNx86 plus an AND.
567 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
568 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
570 // We don't support sin/cos/fmod
571 setOperationAction(ISD::FSIN , MVT::f64, Expand);
572 setOperationAction(ISD::FCOS , MVT::f64, Expand);
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
576 // Expand FP immediates into loads from the stack, except for the special
578 addLegalFPImmediate(APFloat(+0.0)); // xorpd
579 addLegalFPImmediate(APFloat(+0.0f)); // xorps
580 } else if (!UseSoftFloat && X86ScalarSSEf32) {
581 // Use SSE for f32, x87 for f64.
582 // Set up the FP register classes.
583 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
584 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
586 // Use ANDPS to simulate FABS.
587 setOperationAction(ISD::FABS , MVT::f32, Custom);
589 // Use XORP to simulate FNEG.
590 setOperationAction(ISD::FNEG , MVT::f32, Custom);
592 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
594 // Use ANDPS and ORPS to simulate FCOPYSIGN.
595 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
598 // We don't support sin/cos/fmod
599 setOperationAction(ISD::FSIN , MVT::f32, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
602 // Special cases we handle for FP constants.
603 addLegalFPImmediate(APFloat(+0.0f)); // xorps
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
610 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
611 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
613 } else if (!UseSoftFloat) {
614 // f32 and f64 in x87.
615 // Set up the FP register classes.
616 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
617 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
619 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
620 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
621 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
625 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
626 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
628 addLegalFPImmediate(APFloat(+0.0)); // FLD0
629 addLegalFPImmediate(APFloat(+1.0)); // FLD1
630 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
631 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
632 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
633 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
634 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
635 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
638 // We don't support FMA.
639 setOperationAction(ISD::FMA, MVT::f64, Expand);
640 setOperationAction(ISD::FMA, MVT::f32, Expand);
642 // Long double always uses X87.
644 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
645 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
646 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
648 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
649 addLegalFPImmediate(TmpFlt); // FLD0
651 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
654 APFloat TmpFlt2(+1.0);
655 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
657 addLegalFPImmediate(TmpFlt2); // FLD1
658 TmpFlt2.changeSign();
659 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
663 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
664 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
667 setOperationAction(ISD::FMA, MVT::f80, Expand);
670 // Always use a library call for pow.
671 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
672 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
673 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
675 setOperationAction(ISD::FLOG, MVT::f80, Expand);
676 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
677 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
678 setOperationAction(ISD::FEXP, MVT::f80, Expand);
679 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
681 // First set operation action for all vector types to either promote
682 // (for widening) or expand (for scalarization). Then we will selectively
683 // turn on ones that can be effectively codegen'd.
684 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
685 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
686 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
701 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
703 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
704 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
736 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
741 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
742 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
743 setTruncStoreAction((MVT::SimpleValueType)VT,
744 (MVT::SimpleValueType)InnerVT, Expand);
745 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
746 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
747 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
750 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
751 // with -msoft-float, disable use of MMX as well.
752 if (!UseSoftFloat && Subtarget->hasMMX()) {
753 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
754 // No operations on x86mmx supported, everything uses intrinsics.
757 // MMX-sized vectors (other than x86mmx) are expected to be expanded
758 // into smaller operations.
759 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
760 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
761 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
762 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
763 setOperationAction(ISD::AND, MVT::v8i8, Expand);
764 setOperationAction(ISD::AND, MVT::v4i16, Expand);
765 setOperationAction(ISD::AND, MVT::v2i32, Expand);
766 setOperationAction(ISD::AND, MVT::v1i64, Expand);
767 setOperationAction(ISD::OR, MVT::v8i8, Expand);
768 setOperationAction(ISD::OR, MVT::v4i16, Expand);
769 setOperationAction(ISD::OR, MVT::v2i32, Expand);
770 setOperationAction(ISD::OR, MVT::v1i64, Expand);
771 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
772 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
773 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
774 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
776 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
777 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
778 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
781 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
782 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
783 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
784 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
785 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
786 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
787 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
789 if (!UseSoftFloat && Subtarget->hasXMM()) {
790 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
792 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
793 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
794 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
795 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
796 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
797 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
798 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
799 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
800 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
801 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
802 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
803 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
806 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
807 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
809 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
810 // registers cannot be used even for integer operations.
811 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
812 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
813 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
814 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
816 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
817 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
818 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
819 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
820 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
833 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
835 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
836 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
844 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
845 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
846 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
847 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
848 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
850 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
851 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
852 EVT VT = (MVT::SimpleValueType)i;
853 // Do not attempt to custom lower non-power-of-2 vectors
854 if (!isPowerOf2_32(VT.getVectorNumElements()))
856 // Do not attempt to custom lower non-128-bit vectors
857 if (!VT.is128BitVector())
859 setOperationAction(ISD::BUILD_VECTOR,
860 VT.getSimpleVT().SimpleTy, Custom);
861 setOperationAction(ISD::VECTOR_SHUFFLE,
862 VT.getSimpleVT().SimpleTy, Custom);
863 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
864 VT.getSimpleVT().SimpleTy, Custom);
867 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
868 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
869 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
870 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
871 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
872 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
874 if (Subtarget->is64Bit()) {
875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
876 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
879 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
880 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
881 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
884 // Do not attempt to promote non-128-bit vectors
885 if (!VT.is128BitVector())
888 setOperationAction(ISD::AND, SVT, Promote);
889 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
890 setOperationAction(ISD::OR, SVT, Promote);
891 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
892 setOperationAction(ISD::XOR, SVT, Promote);
893 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
894 setOperationAction(ISD::LOAD, SVT, Promote);
895 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
896 setOperationAction(ISD::SELECT, SVT, Promote);
897 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
900 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
902 // Custom lower v2i64 and v2f64 selects.
903 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
904 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
905 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
906 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
908 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
909 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
912 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
913 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
914 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
915 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
916 setOperationAction(ISD::FRINT, MVT::f32, Legal);
917 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
918 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
919 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
920 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
921 setOperationAction(ISD::FRINT, MVT::f64, Legal);
922 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
924 // FIXME: Do we need to handle scalar-to-vector here?
925 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
927 // Can turn SHL into an integer multiply.
928 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
929 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
931 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
932 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
933 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
934 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
935 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
937 // i8 and i16 vectors are custom , because the source register and source
938 // source memory operand types are not the same width. f32 vectors are
939 // custom since the immediate controlling the insert encodes additional
941 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
942 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
943 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
944 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
946 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
947 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
948 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
949 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
951 if (Subtarget->is64Bit()) {
952 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
953 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
957 if (Subtarget->hasXMMInt()) {
958 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
959 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
960 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
961 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
963 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
964 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
965 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
967 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
968 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
971 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
972 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
974 if (!UseSoftFloat && Subtarget->hasAVX()) {
975 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
976 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
977 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
978 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
979 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
980 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
982 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
983 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
984 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
986 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
987 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
988 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
989 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
990 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
991 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
993 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
994 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
995 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
996 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
997 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
998 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1000 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1001 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1002 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1004 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1005 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1006 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1007 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1008 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1009 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1011 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1012 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1013 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1014 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1016 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1017 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1018 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1019 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1021 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1022 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1024 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1025 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1026 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1027 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1029 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1030 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1031 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1033 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1034 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1035 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1036 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1038 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1039 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1040 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1041 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1043 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1044 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1045 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1048 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1049 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1050 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1051 // Don't lower v32i8 because there is no 128-bit byte mul
1053 // Custom lower several nodes for 256-bit types.
1054 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1055 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1056 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1059 // Extract subvector is special because the value type
1060 // (result) is 128-bit but the source is 256-bit wide.
1061 if (VT.is128BitVector())
1062 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1064 // Do not attempt to custom lower other non-256-bit vectors
1065 if (!VT.is256BitVector())
1068 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1069 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1070 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1071 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1072 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1073 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1076 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1077 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1078 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1081 // Do not attempt to promote non-256-bit vectors
1082 if (!VT.is256BitVector())
1085 setOperationAction(ISD::AND, SVT, Promote);
1086 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1087 setOperationAction(ISD::OR, SVT, Promote);
1088 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1089 setOperationAction(ISD::XOR, SVT, Promote);
1090 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1091 setOperationAction(ISD::LOAD, SVT, Promote);
1092 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1093 setOperationAction(ISD::SELECT, SVT, Promote);
1094 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1098 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1099 // of this type with custom code.
1100 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1101 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1102 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1105 // We want to custom lower some of our intrinsics.
1106 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1109 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1110 // handle type legalization for these operations here.
1112 // FIXME: We really should do custom legalization for addition and
1113 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1114 // than generic legalization for 64-bit multiplication-with-overflow, though.
1115 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1116 // Add/Sub/Mul with overflow operations are custom lowered.
1118 setOperationAction(ISD::SADDO, VT, Custom);
1119 setOperationAction(ISD::UADDO, VT, Custom);
1120 setOperationAction(ISD::SSUBO, VT, Custom);
1121 setOperationAction(ISD::USUBO, VT, Custom);
1122 setOperationAction(ISD::SMULO, VT, Custom);
1123 setOperationAction(ISD::UMULO, VT, Custom);
1126 // There are no 8-bit 3-address imul/mul instructions
1127 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1128 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1130 if (!Subtarget->is64Bit()) {
1131 // These libcalls are not available in 32-bit.
1132 setLibcallName(RTLIB::SHL_I128, 0);
1133 setLibcallName(RTLIB::SRL_I128, 0);
1134 setLibcallName(RTLIB::SRA_I128, 0);
1137 // We have target-specific dag combine patterns for the following nodes:
1138 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1139 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1140 setTargetDAGCombine(ISD::BUILD_VECTOR);
1141 setTargetDAGCombine(ISD::VSELECT);
1142 setTargetDAGCombine(ISD::SELECT);
1143 setTargetDAGCombine(ISD::SHL);
1144 setTargetDAGCombine(ISD::SRA);
1145 setTargetDAGCombine(ISD::SRL);
1146 setTargetDAGCombine(ISD::OR);
1147 setTargetDAGCombine(ISD::AND);
1148 setTargetDAGCombine(ISD::ADD);
1149 setTargetDAGCombine(ISD::FADD);
1150 setTargetDAGCombine(ISD::FSUB);
1151 setTargetDAGCombine(ISD::SUB);
1152 setTargetDAGCombine(ISD::LOAD);
1153 setTargetDAGCombine(ISD::STORE);
1154 setTargetDAGCombine(ISD::ZERO_EXTEND);
1155 setTargetDAGCombine(ISD::SINT_TO_FP);
1156 if (Subtarget->is64Bit())
1157 setTargetDAGCombine(ISD::MUL);
1159 computeRegisterProperties();
1161 // On Darwin, -Os means optimize for size without hurting performance,
1162 // do not reduce the limit.
1163 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1164 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1165 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1166 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1167 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1168 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1169 setPrefLoopAlignment(16);
1170 benefitFromCodePlacementOpt = true;
1172 setPrefFunctionAlignment(4);
1176 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1177 if (!VT.isVector()) return MVT::i8;
1178 return VT.changeVectorElementTypeToInteger();
1182 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1183 /// the desired ByVal argument alignment.
1184 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1187 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1188 if (VTy->getBitWidth() == 128)
1190 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1191 unsigned EltAlign = 0;
1192 getMaxByValAlign(ATy->getElementType(), EltAlign);
1193 if (EltAlign > MaxAlign)
1194 MaxAlign = EltAlign;
1195 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1196 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1197 unsigned EltAlign = 0;
1198 getMaxByValAlign(STy->getElementType(i), EltAlign);
1199 if (EltAlign > MaxAlign)
1200 MaxAlign = EltAlign;
1208 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1209 /// function arguments in the caller parameter area. For X86, aggregates
1210 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1211 /// are at 4-byte boundaries.
1212 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1213 if (Subtarget->is64Bit()) {
1214 // Max of 8 and alignment of type.
1215 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1222 if (Subtarget->hasXMM())
1223 getMaxByValAlign(Ty, Align);
1227 /// getOptimalMemOpType - Returns the target specific optimal type for load
1228 /// and store operations as a result of memset, memcpy, and memmove
1229 /// lowering. If DstAlign is zero that means it's safe to destination
1230 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1231 /// means there isn't a need to check it against alignment requirement,
1232 /// probably because the source does not need to be loaded. If
1233 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1234 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1235 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1236 /// constant so it does not need to be loaded.
1237 /// It returns EVT::Other if the type should be determined using generic
1238 /// target-independent logic.
1240 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1241 unsigned DstAlign, unsigned SrcAlign,
1242 bool NonScalarIntSafe,
1244 MachineFunction &MF) const {
1245 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1246 // linux. This is because the stack realignment code can't handle certain
1247 // cases like PR2962. This should be removed when PR2962 is fixed.
1248 const Function *F = MF.getFunction();
1249 if (NonScalarIntSafe &&
1250 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1252 (Subtarget->isUnalignedMemAccessFast() ||
1253 ((DstAlign == 0 || DstAlign >= 16) &&
1254 (SrcAlign == 0 || SrcAlign >= 16))) &&
1255 Subtarget->getStackAlignment() >= 16) {
1256 if (Subtarget->hasAVX() &&
1257 Subtarget->getStackAlignment() >= 32)
1259 if (Subtarget->hasXMMInt())
1261 if (Subtarget->hasXMM())
1263 } else if (!MemcpyStrSrc && Size >= 8 &&
1264 !Subtarget->is64Bit() &&
1265 Subtarget->getStackAlignment() >= 8 &&
1266 Subtarget->hasXMMInt()) {
1267 // Do not use f64 to lower memcpy if source is string constant. It's
1268 // better to use i32 to avoid the loads.
1272 if (Subtarget->is64Bit() && Size >= 8)
1277 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1278 /// current function. The returned value is a member of the
1279 /// MachineJumpTableInfo::JTEntryKind enum.
1280 unsigned X86TargetLowering::getJumpTableEncoding() const {
1281 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1283 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1284 Subtarget->isPICStyleGOT())
1285 return MachineJumpTableInfo::EK_Custom32;
1287 // Otherwise, use the normal jump table encoding heuristics.
1288 return TargetLowering::getJumpTableEncoding();
1292 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1293 const MachineBasicBlock *MBB,
1294 unsigned uid,MCContext &Ctx) const{
1295 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1296 Subtarget->isPICStyleGOT());
1297 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1299 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1300 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1303 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1305 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1306 SelectionDAG &DAG) const {
1307 if (!Subtarget->is64Bit())
1308 // This doesn't have DebugLoc associated with it, but is not really the
1309 // same as a Register.
1310 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1314 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1315 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1317 const MCExpr *X86TargetLowering::
1318 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1319 MCContext &Ctx) const {
1320 // X86-64 uses RIP relative addressing based on the jump table label.
1321 if (Subtarget->isPICStyleRIPRel())
1322 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1324 // Otherwise, the reference is relative to the PIC base.
1325 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1328 // FIXME: Why this routine is here? Move to RegInfo!
1329 std::pair<const TargetRegisterClass*, uint8_t>
1330 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1331 const TargetRegisterClass *RRC = 0;
1333 switch (VT.getSimpleVT().SimpleTy) {
1335 return TargetLowering::findRepresentativeClass(VT);
1336 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1337 RRC = (Subtarget->is64Bit()
1338 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1341 RRC = X86::VR64RegisterClass;
1343 case MVT::f32: case MVT::f64:
1344 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1345 case MVT::v4f32: case MVT::v2f64:
1346 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1348 RRC = X86::VR128RegisterClass;
1351 return std::make_pair(RRC, Cost);
1354 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1355 unsigned &Offset) const {
1356 if (!Subtarget->isTargetLinux())
1359 if (Subtarget->is64Bit()) {
1360 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1362 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1375 //===----------------------------------------------------------------------===//
1376 // Return Value Calling Convention Implementation
1377 //===----------------------------------------------------------------------===//
1379 #include "X86GenCallingConv.inc"
1382 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1383 MachineFunction &MF, bool isVarArg,
1384 const SmallVectorImpl<ISD::OutputArg> &Outs,
1385 LLVMContext &Context) const {
1386 SmallVector<CCValAssign, 16> RVLocs;
1387 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1389 return CCInfo.CheckReturn(Outs, RetCC_X86);
1393 X86TargetLowering::LowerReturn(SDValue Chain,
1394 CallingConv::ID CallConv, bool isVarArg,
1395 const SmallVectorImpl<ISD::OutputArg> &Outs,
1396 const SmallVectorImpl<SDValue> &OutVals,
1397 DebugLoc dl, SelectionDAG &DAG) const {
1398 MachineFunction &MF = DAG.getMachineFunction();
1399 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1401 SmallVector<CCValAssign, 16> RVLocs;
1402 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1403 RVLocs, *DAG.getContext());
1404 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1406 // Add the regs to the liveout set for the function.
1407 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1408 for (unsigned i = 0; i != RVLocs.size(); ++i)
1409 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1410 MRI.addLiveOut(RVLocs[i].getLocReg());
1414 SmallVector<SDValue, 6> RetOps;
1415 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1416 // Operand #1 = Bytes To Pop
1417 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1420 // Copy the result values into the output registers.
1421 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1422 CCValAssign &VA = RVLocs[i];
1423 assert(VA.isRegLoc() && "Can only return in registers!");
1424 SDValue ValToCopy = OutVals[i];
1425 EVT ValVT = ValToCopy.getValueType();
1427 // If this is x86-64, and we disabled SSE, we can't return FP values,
1428 // or SSE or MMX vectors.
1429 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1430 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1431 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1432 report_fatal_error("SSE register return with SSE disabled");
1434 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1435 // llvm-gcc has never done it right and no one has noticed, so this
1436 // should be OK for now.
1437 if (ValVT == MVT::f64 &&
1438 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1439 report_fatal_error("SSE2 register return with SSE2 disabled");
1441 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1442 // the RET instruction and handled by the FP Stackifier.
1443 if (VA.getLocReg() == X86::ST0 ||
1444 VA.getLocReg() == X86::ST1) {
1445 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1446 // change the value to the FP stack register class.
1447 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1448 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1449 RetOps.push_back(ValToCopy);
1450 // Don't emit a copytoreg.
1454 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1455 // which is returned in RAX / RDX.
1456 if (Subtarget->is64Bit()) {
1457 if (ValVT == MVT::x86mmx) {
1458 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1459 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1460 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1462 // If we don't have SSE2 available, convert to v4f32 so the generated
1463 // register is legal.
1464 if (!Subtarget->hasXMMInt())
1465 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1470 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1471 Flag = Chain.getValue(1);
1474 // The x86-64 ABI for returning structs by value requires that we copy
1475 // the sret argument into %rax for the return. We saved the argument into
1476 // a virtual register in the entry block, so now we copy the value out
1478 if (Subtarget->is64Bit() &&
1479 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1480 MachineFunction &MF = DAG.getMachineFunction();
1481 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1482 unsigned Reg = FuncInfo->getSRetReturnReg();
1484 "SRetReturnReg should have been set in LowerFormalArguments().");
1485 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1487 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1488 Flag = Chain.getValue(1);
1490 // RAX now acts like a return value.
1491 MRI.addLiveOut(X86::RAX);
1494 RetOps[0] = Chain; // Update chain.
1496 // Add the flag if we have it.
1498 RetOps.push_back(Flag);
1500 return DAG.getNode(X86ISD::RET_FLAG, dl,
1501 MVT::Other, &RetOps[0], RetOps.size());
1504 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1505 if (N->getNumValues() != 1)
1507 if (!N->hasNUsesOfValue(1, 0))
1510 SDNode *Copy = *N->use_begin();
1511 if (Copy->getOpcode() != ISD::CopyToReg &&
1512 Copy->getOpcode() != ISD::FP_EXTEND)
1515 bool HasRet = false;
1516 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1518 if (UI->getOpcode() != X86ISD::RET_FLAG)
1527 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1528 ISD::NodeType ExtendKind) const {
1530 // TODO: Is this also valid on 32-bit?
1531 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1532 ReturnMVT = MVT::i8;
1534 ReturnMVT = MVT::i32;
1536 EVT MinVT = getRegisterType(Context, ReturnMVT);
1537 return VT.bitsLT(MinVT) ? MinVT : VT;
1540 /// LowerCallResult - Lower the result values of a call into the
1541 /// appropriate copies out of appropriate physical registers.
1544 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1545 CallingConv::ID CallConv, bool isVarArg,
1546 const SmallVectorImpl<ISD::InputArg> &Ins,
1547 DebugLoc dl, SelectionDAG &DAG,
1548 SmallVectorImpl<SDValue> &InVals) const {
1550 // Assign locations to each value returned by this call.
1551 SmallVector<CCValAssign, 16> RVLocs;
1552 bool Is64Bit = Subtarget->is64Bit();
1553 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1554 getTargetMachine(), RVLocs, *DAG.getContext());
1555 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1557 // Copy all of the result registers out of their specified physreg.
1558 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1559 CCValAssign &VA = RVLocs[i];
1560 EVT CopyVT = VA.getValVT();
1562 // If this is x86-64, and we disabled SSE, we can't return FP values
1563 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1564 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1565 report_fatal_error("SSE register return with SSE disabled");
1570 // If this is a call to a function that returns an fp value on the floating
1571 // point stack, we must guarantee the the value is popped from the stack, so
1572 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1573 // if the return value is not used. We use the FpPOP_RETVAL instruction
1575 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1576 // If we prefer to use the value in xmm registers, copy it out as f80 and
1577 // use a truncate to move it from fp stack reg to xmm reg.
1578 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1579 SDValue Ops[] = { Chain, InFlag };
1580 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1581 MVT::Other, MVT::Glue, Ops, 2), 1);
1582 Val = Chain.getValue(0);
1584 // Round the f80 to the right size, which also moves it to the appropriate
1586 if (CopyVT != VA.getValVT())
1587 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1588 // This truncation won't change the value.
1589 DAG.getIntPtrConstant(1));
1591 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1592 CopyVT, InFlag).getValue(1);
1593 Val = Chain.getValue(0);
1595 InFlag = Chain.getValue(2);
1596 InVals.push_back(Val);
1603 //===----------------------------------------------------------------------===//
1604 // C & StdCall & Fast Calling Convention implementation
1605 //===----------------------------------------------------------------------===//
1606 // StdCall calling convention seems to be standard for many Windows' API
1607 // routines and around. It differs from C calling convention just a little:
1608 // callee should clean up the stack, not caller. Symbols should be also
1609 // decorated in some fancy way :) It doesn't support any vector arguments.
1610 // For info on fast calling convention see Fast Calling Convention (tail call)
1611 // implementation LowerX86_32FastCCCallTo.
1613 /// CallIsStructReturn - Determines whether a call uses struct return
1615 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1619 return Outs[0].Flags.isSRet();
1622 /// ArgsAreStructReturn - Determines whether a function uses struct
1623 /// return semantics.
1625 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1629 return Ins[0].Flags.isSRet();
1632 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1633 /// by "Src" to address "Dst" with size and alignment information specified by
1634 /// the specific parameter attribute. The copy will be passed as a byval
1635 /// function parameter.
1637 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1638 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1640 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1642 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1643 /*isVolatile*/false, /*AlwaysInline=*/true,
1644 MachinePointerInfo(), MachinePointerInfo());
1647 /// IsTailCallConvention - Return true if the calling convention is one that
1648 /// supports tail call optimization.
1649 static bool IsTailCallConvention(CallingConv::ID CC) {
1650 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1653 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1654 if (!CI->isTailCall())
1658 CallingConv::ID CalleeCC = CS.getCallingConv();
1659 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1665 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1666 /// a tailcall target by changing its ABI.
1667 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1668 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1672 X86TargetLowering::LowerMemArgument(SDValue Chain,
1673 CallingConv::ID CallConv,
1674 const SmallVectorImpl<ISD::InputArg> &Ins,
1675 DebugLoc dl, SelectionDAG &DAG,
1676 const CCValAssign &VA,
1677 MachineFrameInfo *MFI,
1679 // Create the nodes corresponding to a load from this parameter slot.
1680 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1681 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1682 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1685 // If value is passed by pointer we have address passed instead of the value
1687 if (VA.getLocInfo() == CCValAssign::Indirect)
1688 ValVT = VA.getLocVT();
1690 ValVT = VA.getValVT();
1692 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1693 // changed with more analysis.
1694 // In case of tail call optimization mark all arguments mutable. Since they
1695 // could be overwritten by lowering of arguments in case of a tail call.
1696 if (Flags.isByVal()) {
1697 unsigned Bytes = Flags.getByValSize();
1698 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1699 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1700 return DAG.getFrameIndex(FI, getPointerTy());
1702 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1703 VA.getLocMemOffset(), isImmutable);
1704 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1705 return DAG.getLoad(ValVT, dl, Chain, FIN,
1706 MachinePointerInfo::getFixedStack(FI),
1712 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1713 CallingConv::ID CallConv,
1715 const SmallVectorImpl<ISD::InputArg> &Ins,
1718 SmallVectorImpl<SDValue> &InVals)
1720 MachineFunction &MF = DAG.getMachineFunction();
1721 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1723 const Function* Fn = MF.getFunction();
1724 if (Fn->hasExternalLinkage() &&
1725 Subtarget->isTargetCygMing() &&
1726 Fn->getName() == "main")
1727 FuncInfo->setForceFramePointer(true);
1729 MachineFrameInfo *MFI = MF.getFrameInfo();
1730 bool Is64Bit = Subtarget->is64Bit();
1731 bool IsWin64 = Subtarget->isTargetWin64();
1733 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1734 "Var args not supported with calling convention fastcc or ghc");
1736 // Assign locations to all of the incoming arguments.
1737 SmallVector<CCValAssign, 16> ArgLocs;
1738 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1739 ArgLocs, *DAG.getContext());
1741 // Allocate shadow area for Win64
1743 CCInfo.AllocateStack(32, 8);
1746 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1748 unsigned LastVal = ~0U;
1750 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1751 CCValAssign &VA = ArgLocs[i];
1752 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1754 assert(VA.getValNo() != LastVal &&
1755 "Don't support value assigned to multiple locs yet");
1757 LastVal = VA.getValNo();
1759 if (VA.isRegLoc()) {
1760 EVT RegVT = VA.getLocVT();
1761 TargetRegisterClass *RC = NULL;
1762 if (RegVT == MVT::i32)
1763 RC = X86::GR32RegisterClass;
1764 else if (Is64Bit && RegVT == MVT::i64)
1765 RC = X86::GR64RegisterClass;
1766 else if (RegVT == MVT::f32)
1767 RC = X86::FR32RegisterClass;
1768 else if (RegVT == MVT::f64)
1769 RC = X86::FR64RegisterClass;
1770 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1771 RC = X86::VR256RegisterClass;
1772 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1773 RC = X86::VR128RegisterClass;
1774 else if (RegVT == MVT::x86mmx)
1775 RC = X86::VR64RegisterClass;
1777 llvm_unreachable("Unknown argument type!");
1779 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1780 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1782 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1783 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1785 if (VA.getLocInfo() == CCValAssign::SExt)
1786 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1787 DAG.getValueType(VA.getValVT()));
1788 else if (VA.getLocInfo() == CCValAssign::ZExt)
1789 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1790 DAG.getValueType(VA.getValVT()));
1791 else if (VA.getLocInfo() == CCValAssign::BCvt)
1792 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1794 if (VA.isExtInLoc()) {
1795 // Handle MMX values passed in XMM regs.
1796 if (RegVT.isVector()) {
1797 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1800 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1803 assert(VA.isMemLoc());
1804 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1807 // If value is passed via pointer - do a load.
1808 if (VA.getLocInfo() == CCValAssign::Indirect)
1809 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1810 MachinePointerInfo(), false, false, 0);
1812 InVals.push_back(ArgValue);
1815 // The x86-64 ABI for returning structs by value requires that we copy
1816 // the sret argument into %rax for the return. Save the argument into
1817 // a virtual register so that we can access it from the return points.
1818 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1819 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1820 unsigned Reg = FuncInfo->getSRetReturnReg();
1822 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1823 FuncInfo->setSRetReturnReg(Reg);
1825 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1826 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1829 unsigned StackSize = CCInfo.getNextStackOffset();
1830 // Align stack specially for tail calls.
1831 if (FuncIsMadeTailCallSafe(CallConv))
1832 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1834 // If the function takes variable number of arguments, make a frame index for
1835 // the start of the first vararg value... for expansion of llvm.va_start.
1837 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1838 CallConv != CallingConv::X86_ThisCall)) {
1839 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1842 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1844 // FIXME: We should really autogenerate these arrays
1845 static const unsigned GPR64ArgRegsWin64[] = {
1846 X86::RCX, X86::RDX, X86::R8, X86::R9
1848 static const unsigned GPR64ArgRegs64Bit[] = {
1849 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1851 static const unsigned XMMArgRegs64Bit[] = {
1852 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1853 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1855 const unsigned *GPR64ArgRegs;
1856 unsigned NumXMMRegs = 0;
1859 // The XMM registers which might contain var arg parameters are shadowed
1860 // in their paired GPR. So we only need to save the GPR to their home
1862 TotalNumIntRegs = 4;
1863 GPR64ArgRegs = GPR64ArgRegsWin64;
1865 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1866 GPR64ArgRegs = GPR64ArgRegs64Bit;
1868 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1870 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1873 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1874 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1875 "SSE register cannot be used when SSE is disabled!");
1876 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1877 "SSE register cannot be used when SSE is disabled!");
1878 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1879 // Kernel mode asks for SSE to be disabled, so don't push them
1881 TotalNumXMMRegs = 0;
1884 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1885 // Get to the caller-allocated home save location. Add 8 to account
1886 // for the return address.
1887 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1888 FuncInfo->setRegSaveFrameIndex(
1889 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1890 // Fixup to set vararg frame on shadow area (4 x i64).
1892 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1894 // For X86-64, if there are vararg parameters that are passed via
1895 // registers, then we must store them to their spots on the stack so they
1896 // may be loaded by deferencing the result of va_next.
1897 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1898 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1899 FuncInfo->setRegSaveFrameIndex(
1900 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1904 // Store the integer parameter registers.
1905 SmallVector<SDValue, 8> MemOps;
1906 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1908 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1909 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1910 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1911 DAG.getIntPtrConstant(Offset));
1912 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1913 X86::GR64RegisterClass);
1914 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1916 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1917 MachinePointerInfo::getFixedStack(
1918 FuncInfo->getRegSaveFrameIndex(), Offset),
1920 MemOps.push_back(Store);
1924 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1925 // Now store the XMM (fp + vector) parameter registers.
1926 SmallVector<SDValue, 11> SaveXMMOps;
1927 SaveXMMOps.push_back(Chain);
1929 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1930 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1931 SaveXMMOps.push_back(ALVal);
1933 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1934 FuncInfo->getRegSaveFrameIndex()));
1935 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1936 FuncInfo->getVarArgsFPOffset()));
1938 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1939 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1940 X86::VR128RegisterClass);
1941 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1942 SaveXMMOps.push_back(Val);
1944 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1946 &SaveXMMOps[0], SaveXMMOps.size()));
1949 if (!MemOps.empty())
1950 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1951 &MemOps[0], MemOps.size());
1955 // Some CCs need callee pop.
1956 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1957 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1959 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1960 // If this is an sret function, the return should pop the hidden pointer.
1961 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1962 FuncInfo->setBytesToPopOnReturn(4);
1966 // RegSaveFrameIndex is X86-64 only.
1967 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1968 if (CallConv == CallingConv::X86_FastCall ||
1969 CallConv == CallingConv::X86_ThisCall)
1970 // fastcc functions can't have varargs.
1971 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1974 FuncInfo->setArgumentStackSize(StackSize);
1980 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1981 SDValue StackPtr, SDValue Arg,
1982 DebugLoc dl, SelectionDAG &DAG,
1983 const CCValAssign &VA,
1984 ISD::ArgFlagsTy Flags) const {
1985 unsigned LocMemOffset = VA.getLocMemOffset();
1986 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1987 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1988 if (Flags.isByVal())
1989 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1991 return DAG.getStore(Chain, dl, Arg, PtrOff,
1992 MachinePointerInfo::getStack(LocMemOffset),
1996 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1997 /// optimization is performed and it is required.
1999 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2000 SDValue &OutRetAddr, SDValue Chain,
2001 bool IsTailCall, bool Is64Bit,
2002 int FPDiff, DebugLoc dl) const {
2003 // Adjust the Return address stack slot.
2004 EVT VT = getPointerTy();
2005 OutRetAddr = getReturnAddressFrameIndex(DAG);
2007 // Load the "old" Return address.
2008 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2010 return SDValue(OutRetAddr.getNode(), 1);
2013 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2014 /// optimization is performed and it is required (FPDiff!=0).
2016 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2017 SDValue Chain, SDValue RetAddrFrIdx,
2018 bool Is64Bit, int FPDiff, DebugLoc dl) {
2019 // Store the return address to the appropriate stack slot.
2020 if (!FPDiff) return Chain;
2021 // Calculate the new stack slot for the return address.
2022 int SlotSize = Is64Bit ? 8 : 4;
2023 int NewReturnAddrFI =
2024 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2025 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2026 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2027 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2028 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2034 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2035 CallingConv::ID CallConv, bool isVarArg,
2037 const SmallVectorImpl<ISD::OutputArg> &Outs,
2038 const SmallVectorImpl<SDValue> &OutVals,
2039 const SmallVectorImpl<ISD::InputArg> &Ins,
2040 DebugLoc dl, SelectionDAG &DAG,
2041 SmallVectorImpl<SDValue> &InVals) const {
2042 MachineFunction &MF = DAG.getMachineFunction();
2043 bool Is64Bit = Subtarget->is64Bit();
2044 bool IsWin64 = Subtarget->isTargetWin64();
2045 bool IsStructRet = CallIsStructReturn(Outs);
2046 bool IsSibcall = false;
2049 // Check if it's really possible to do a tail call.
2050 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2051 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2052 Outs, OutVals, Ins, DAG);
2054 // Sibcalls are automatically detected tailcalls which do not require
2056 if (!GuaranteedTailCallOpt && isTailCall)
2063 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2064 "Var args not supported with calling convention fastcc or ghc");
2066 // Analyze operands of the call, assigning locations to each operand.
2067 SmallVector<CCValAssign, 16> ArgLocs;
2068 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2069 ArgLocs, *DAG.getContext());
2071 // Allocate shadow area for Win64
2073 CCInfo.AllocateStack(32, 8);
2076 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2078 // Get a count of how many bytes are to be pushed on the stack.
2079 unsigned NumBytes = CCInfo.getNextStackOffset();
2081 // This is a sibcall. The memory operands are available in caller's
2082 // own caller's stack.
2084 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2085 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2088 if (isTailCall && !IsSibcall) {
2089 // Lower arguments at fp - stackoffset + fpdiff.
2090 unsigned NumBytesCallerPushed =
2091 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2092 FPDiff = NumBytesCallerPushed - NumBytes;
2094 // Set the delta of movement of the returnaddr stackslot.
2095 // But only set if delta is greater than previous delta.
2096 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2097 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2101 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2103 SDValue RetAddrFrIdx;
2104 // Load return address for tail calls.
2105 if (isTailCall && FPDiff)
2106 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2107 Is64Bit, FPDiff, dl);
2109 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2110 SmallVector<SDValue, 8> MemOpChains;
2113 // Walk the register/memloc assignments, inserting copies/loads. In the case
2114 // of tail call optimization arguments are handle later.
2115 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2116 CCValAssign &VA = ArgLocs[i];
2117 EVT RegVT = VA.getLocVT();
2118 SDValue Arg = OutVals[i];
2119 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2120 bool isByVal = Flags.isByVal();
2122 // Promote the value if needed.
2123 switch (VA.getLocInfo()) {
2124 default: llvm_unreachable("Unknown loc info!");
2125 case CCValAssign::Full: break;
2126 case CCValAssign::SExt:
2127 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2129 case CCValAssign::ZExt:
2130 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2132 case CCValAssign::AExt:
2133 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2134 // Special case: passing MMX values in XMM registers.
2135 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2136 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2137 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2139 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2141 case CCValAssign::BCvt:
2142 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2144 case CCValAssign::Indirect: {
2145 // Store the argument.
2146 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2147 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2148 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2149 MachinePointerInfo::getFixedStack(FI),
2156 if (VA.isRegLoc()) {
2157 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2158 if (isVarArg && IsWin64) {
2159 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2160 // shadow reg if callee is a varargs function.
2161 unsigned ShadowReg = 0;
2162 switch (VA.getLocReg()) {
2163 case X86::XMM0: ShadowReg = X86::RCX; break;
2164 case X86::XMM1: ShadowReg = X86::RDX; break;
2165 case X86::XMM2: ShadowReg = X86::R8; break;
2166 case X86::XMM3: ShadowReg = X86::R9; break;
2169 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2171 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2172 assert(VA.isMemLoc());
2173 if (StackPtr.getNode() == 0)
2174 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2175 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2176 dl, DAG, VA, Flags));
2180 if (!MemOpChains.empty())
2181 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2182 &MemOpChains[0], MemOpChains.size());
2184 // Build a sequence of copy-to-reg nodes chained together with token chain
2185 // and flag operands which copy the outgoing args into registers.
2187 // Tail call byval lowering might overwrite argument registers so in case of
2188 // tail call optimization the copies to registers are lowered later.
2190 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2191 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2192 RegsToPass[i].second, InFlag);
2193 InFlag = Chain.getValue(1);
2196 if (Subtarget->isPICStyleGOT()) {
2197 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2200 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2201 DAG.getNode(X86ISD::GlobalBaseReg,
2202 DebugLoc(), getPointerTy()),
2204 InFlag = Chain.getValue(1);
2206 // If we are tail calling and generating PIC/GOT style code load the
2207 // address of the callee into ECX. The value in ecx is used as target of
2208 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2209 // for tail calls on PIC/GOT architectures. Normally we would just put the
2210 // address of GOT into ebx and then call target@PLT. But for tail calls
2211 // ebx would be restored (since ebx is callee saved) before jumping to the
2214 // Note: The actual moving to ECX is done further down.
2215 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2216 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2217 !G->getGlobal()->hasProtectedVisibility())
2218 Callee = LowerGlobalAddress(Callee, DAG);
2219 else if (isa<ExternalSymbolSDNode>(Callee))
2220 Callee = LowerExternalSymbol(Callee, DAG);
2224 if (Is64Bit && isVarArg && !IsWin64) {
2225 // From AMD64 ABI document:
2226 // For calls that may call functions that use varargs or stdargs
2227 // (prototype-less calls or calls to functions containing ellipsis (...) in
2228 // the declaration) %al is used as hidden argument to specify the number
2229 // of SSE registers used. The contents of %al do not need to match exactly
2230 // the number of registers, but must be an ubound on the number of SSE
2231 // registers used and is in the range 0 - 8 inclusive.
2233 // Count the number of XMM registers allocated.
2234 static const unsigned XMMArgRegs[] = {
2235 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2236 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2238 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2239 assert((Subtarget->hasXMM() || !NumXMMRegs)
2240 && "SSE registers cannot be used when SSE is disabled");
2242 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2243 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2244 InFlag = Chain.getValue(1);
2248 // For tail calls lower the arguments to the 'real' stack slot.
2250 // Force all the incoming stack arguments to be loaded from the stack
2251 // before any new outgoing arguments are stored to the stack, because the
2252 // outgoing stack slots may alias the incoming argument stack slots, and
2253 // the alias isn't otherwise explicit. This is slightly more conservative
2254 // than necessary, because it means that each store effectively depends
2255 // on every argument instead of just those arguments it would clobber.
2256 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2258 SmallVector<SDValue, 8> MemOpChains2;
2261 // Do not flag preceding copytoreg stuff together with the following stuff.
2263 if (GuaranteedTailCallOpt) {
2264 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2265 CCValAssign &VA = ArgLocs[i];
2268 assert(VA.isMemLoc());
2269 SDValue Arg = OutVals[i];
2270 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2271 // Create frame index.
2272 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2273 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2274 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2275 FIN = DAG.getFrameIndex(FI, getPointerTy());
2277 if (Flags.isByVal()) {
2278 // Copy relative to framepointer.
2279 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2280 if (StackPtr.getNode() == 0)
2281 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2283 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2285 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2289 // Store relative to framepointer.
2290 MemOpChains2.push_back(
2291 DAG.getStore(ArgChain, dl, Arg, FIN,
2292 MachinePointerInfo::getFixedStack(FI),
2298 if (!MemOpChains2.empty())
2299 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2300 &MemOpChains2[0], MemOpChains2.size());
2302 // Copy arguments to their registers.
2303 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2304 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2305 RegsToPass[i].second, InFlag);
2306 InFlag = Chain.getValue(1);
2310 // Store the return address to the appropriate stack slot.
2311 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2315 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2316 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2317 // In the 64-bit large code model, we have to make all calls
2318 // through a register, since the call instruction's 32-bit
2319 // pc-relative offset may not be large enough to hold the whole
2321 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2322 // If the callee is a GlobalAddress node (quite common, every direct call
2323 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2326 // We should use extra load for direct calls to dllimported functions in
2328 const GlobalValue *GV = G->getGlobal();
2329 if (!GV->hasDLLImportLinkage()) {
2330 unsigned char OpFlags = 0;
2331 bool ExtraLoad = false;
2332 unsigned WrapperKind = ISD::DELETED_NODE;
2334 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2335 // external symbols most go through the PLT in PIC mode. If the symbol
2336 // has hidden or protected visibility, or if it is static or local, then
2337 // we don't need to use the PLT - we can directly call it.
2338 if (Subtarget->isTargetELF() &&
2339 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2340 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2341 OpFlags = X86II::MO_PLT;
2342 } else if (Subtarget->isPICStyleStubAny() &&
2343 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2344 (!Subtarget->getTargetTriple().isMacOSX() ||
2345 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2346 // PC-relative references to external symbols should go through $stub,
2347 // unless we're building with the leopard linker or later, which
2348 // automatically synthesizes these stubs.
2349 OpFlags = X86II::MO_DARWIN_STUB;
2350 } else if (Subtarget->isPICStyleRIPRel() &&
2351 isa<Function>(GV) &&
2352 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2353 // If the function is marked as non-lazy, generate an indirect call
2354 // which loads from the GOT directly. This avoids runtime overhead
2355 // at the cost of eager binding (and one extra byte of encoding).
2356 OpFlags = X86II::MO_GOTPCREL;
2357 WrapperKind = X86ISD::WrapperRIP;
2361 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2362 G->getOffset(), OpFlags);
2364 // Add a wrapper if needed.
2365 if (WrapperKind != ISD::DELETED_NODE)
2366 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2367 // Add extra indirection if needed.
2369 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2370 MachinePointerInfo::getGOT(),
2373 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2374 unsigned char OpFlags = 0;
2376 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2377 // external symbols should go through the PLT.
2378 if (Subtarget->isTargetELF() &&
2379 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2380 OpFlags = X86II::MO_PLT;
2381 } else if (Subtarget->isPICStyleStubAny() &&
2382 (!Subtarget->getTargetTriple().isMacOSX() ||
2383 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2384 // PC-relative references to external symbols should go through $stub,
2385 // unless we're building with the leopard linker or later, which
2386 // automatically synthesizes these stubs.
2387 OpFlags = X86II::MO_DARWIN_STUB;
2390 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2394 // Returns a chain & a flag for retval copy to use.
2395 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2396 SmallVector<SDValue, 8> Ops;
2398 if (!IsSibcall && isTailCall) {
2399 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2400 DAG.getIntPtrConstant(0, true), InFlag);
2401 InFlag = Chain.getValue(1);
2404 Ops.push_back(Chain);
2405 Ops.push_back(Callee);
2408 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2410 // Add argument registers to the end of the list so that they are known live
2412 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2413 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2414 RegsToPass[i].second.getValueType()));
2416 // Add an implicit use GOT pointer in EBX.
2417 if (!isTailCall && Subtarget->isPICStyleGOT())
2418 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2420 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2421 if (Is64Bit && isVarArg && !IsWin64)
2422 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2424 if (InFlag.getNode())
2425 Ops.push_back(InFlag);
2429 //// If this is the first return lowered for this function, add the regs
2430 //// to the liveout set for the function.
2431 // This isn't right, although it's probably harmless on x86; liveouts
2432 // should be computed from returns not tail calls. Consider a void
2433 // function making a tail call to a function returning int.
2434 return DAG.getNode(X86ISD::TC_RETURN, dl,
2435 NodeTys, &Ops[0], Ops.size());
2438 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2439 InFlag = Chain.getValue(1);
2441 // Create the CALLSEQ_END node.
2442 unsigned NumBytesForCalleeToPush;
2443 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2444 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2445 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2446 // If this is a call to a struct-return function, the callee
2447 // pops the hidden struct pointer, so we have to push it back.
2448 // This is common for Darwin/X86, Linux & Mingw32 targets.
2449 NumBytesForCalleeToPush = 4;
2451 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2453 // Returns a flag for retval copy to use.
2455 Chain = DAG.getCALLSEQ_END(Chain,
2456 DAG.getIntPtrConstant(NumBytes, true),
2457 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2460 InFlag = Chain.getValue(1);
2463 // Handle result values, copying them out of physregs into vregs that we
2465 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2466 Ins, dl, DAG, InVals);
2470 //===----------------------------------------------------------------------===//
2471 // Fast Calling Convention (tail call) implementation
2472 //===----------------------------------------------------------------------===//
2474 // Like std call, callee cleans arguments, convention except that ECX is
2475 // reserved for storing the tail called function address. Only 2 registers are
2476 // free for argument passing (inreg). Tail call optimization is performed
2478 // * tailcallopt is enabled
2479 // * caller/callee are fastcc
2480 // On X86_64 architecture with GOT-style position independent code only local
2481 // (within module) calls are supported at the moment.
2482 // To keep the stack aligned according to platform abi the function
2483 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2484 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2485 // If a tail called function callee has more arguments than the caller the
2486 // caller needs to make sure that there is room to move the RETADDR to. This is
2487 // achieved by reserving an area the size of the argument delta right after the
2488 // original REtADDR, but before the saved framepointer or the spilled registers
2489 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2501 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2502 /// for a 16 byte align requirement.
2504 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2505 SelectionDAG& DAG) const {
2506 MachineFunction &MF = DAG.getMachineFunction();
2507 const TargetMachine &TM = MF.getTarget();
2508 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2509 unsigned StackAlignment = TFI.getStackAlignment();
2510 uint64_t AlignMask = StackAlignment - 1;
2511 int64_t Offset = StackSize;
2512 uint64_t SlotSize = TD->getPointerSize();
2513 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2514 // Number smaller than 12 so just add the difference.
2515 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2517 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2518 Offset = ((~AlignMask) & Offset) + StackAlignment +
2519 (StackAlignment-SlotSize);
2524 /// MatchingStackOffset - Return true if the given stack call argument is
2525 /// already available in the same position (relatively) of the caller's
2526 /// incoming argument stack.
2528 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2529 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2530 const X86InstrInfo *TII) {
2531 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2533 if (Arg.getOpcode() == ISD::CopyFromReg) {
2534 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2535 if (!TargetRegisterInfo::isVirtualRegister(VR))
2537 MachineInstr *Def = MRI->getVRegDef(VR);
2540 if (!Flags.isByVal()) {
2541 if (!TII->isLoadFromStackSlot(Def, FI))
2544 unsigned Opcode = Def->getOpcode();
2545 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2546 Def->getOperand(1).isFI()) {
2547 FI = Def->getOperand(1).getIndex();
2548 Bytes = Flags.getByValSize();
2552 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2553 if (Flags.isByVal())
2554 // ByVal argument is passed in as a pointer but it's now being
2555 // dereferenced. e.g.
2556 // define @foo(%struct.X* %A) {
2557 // tail call @bar(%struct.X* byval %A)
2560 SDValue Ptr = Ld->getBasePtr();
2561 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2564 FI = FINode->getIndex();
2565 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2566 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2567 FI = FINode->getIndex();
2568 Bytes = Flags.getByValSize();
2572 assert(FI != INT_MAX);
2573 if (!MFI->isFixedObjectIndex(FI))
2575 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2578 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2579 /// for tail call optimization. Targets which want to do tail call
2580 /// optimization should implement this function.
2582 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2583 CallingConv::ID CalleeCC,
2585 bool isCalleeStructRet,
2586 bool isCallerStructRet,
2587 const SmallVectorImpl<ISD::OutputArg> &Outs,
2588 const SmallVectorImpl<SDValue> &OutVals,
2589 const SmallVectorImpl<ISD::InputArg> &Ins,
2590 SelectionDAG& DAG) const {
2591 if (!IsTailCallConvention(CalleeCC) &&
2592 CalleeCC != CallingConv::C)
2595 // If -tailcallopt is specified, make fastcc functions tail-callable.
2596 const MachineFunction &MF = DAG.getMachineFunction();
2597 const Function *CallerF = DAG.getMachineFunction().getFunction();
2598 CallingConv::ID CallerCC = CallerF->getCallingConv();
2599 bool CCMatch = CallerCC == CalleeCC;
2601 if (GuaranteedTailCallOpt) {
2602 if (IsTailCallConvention(CalleeCC) && CCMatch)
2607 // Look for obvious safe cases to perform tail call optimization that do not
2608 // require ABI changes. This is what gcc calls sibcall.
2610 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2611 // emit a special epilogue.
2612 if (RegInfo->needsStackRealignment(MF))
2615 // Also avoid sibcall optimization if either caller or callee uses struct
2616 // return semantics.
2617 if (isCalleeStructRet || isCallerStructRet)
2620 // An stdcall caller is expected to clean up its arguments; the callee
2621 // isn't going to do that.
2622 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2625 // Do not sibcall optimize vararg calls unless all arguments are passed via
2627 if (isVarArg && !Outs.empty()) {
2629 // Optimizing for varargs on Win64 is unlikely to be safe without
2630 // additional testing.
2631 if (Subtarget->isTargetWin64())
2634 SmallVector<CCValAssign, 16> ArgLocs;
2635 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2636 getTargetMachine(), ArgLocs, *DAG.getContext());
2638 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2639 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2640 if (!ArgLocs[i].isRegLoc())
2644 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2645 // Therefore if it's not used by the call it is not safe to optimize this into
2647 bool Unused = false;
2648 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2655 SmallVector<CCValAssign, 16> RVLocs;
2656 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2657 getTargetMachine(), RVLocs, *DAG.getContext());
2658 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2659 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2660 CCValAssign &VA = RVLocs[i];
2661 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2666 // If the calling conventions do not match, then we'd better make sure the
2667 // results are returned in the same way as what the caller expects.
2669 SmallVector<CCValAssign, 16> RVLocs1;
2670 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2671 getTargetMachine(), RVLocs1, *DAG.getContext());
2672 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2674 SmallVector<CCValAssign, 16> RVLocs2;
2675 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2676 getTargetMachine(), RVLocs2, *DAG.getContext());
2677 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2679 if (RVLocs1.size() != RVLocs2.size())
2681 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2682 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2684 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2686 if (RVLocs1[i].isRegLoc()) {
2687 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2690 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2696 // If the callee takes no arguments then go on to check the results of the
2698 if (!Outs.empty()) {
2699 // Check if stack adjustment is needed. For now, do not do this if any
2700 // argument is passed on the stack.
2701 SmallVector<CCValAssign, 16> ArgLocs;
2702 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2703 getTargetMachine(), ArgLocs, *DAG.getContext());
2705 // Allocate shadow area for Win64
2706 if (Subtarget->isTargetWin64()) {
2707 CCInfo.AllocateStack(32, 8);
2710 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2711 if (CCInfo.getNextStackOffset()) {
2712 MachineFunction &MF = DAG.getMachineFunction();
2713 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2716 // Check if the arguments are already laid out in the right way as
2717 // the caller's fixed stack objects.
2718 MachineFrameInfo *MFI = MF.getFrameInfo();
2719 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2720 const X86InstrInfo *TII =
2721 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2723 CCValAssign &VA = ArgLocs[i];
2724 SDValue Arg = OutVals[i];
2725 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2726 if (VA.getLocInfo() == CCValAssign::Indirect)
2728 if (!VA.isRegLoc()) {
2729 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2736 // If the tailcall address may be in a register, then make sure it's
2737 // possible to register allocate for it. In 32-bit, the call address can
2738 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2739 // callee-saved registers are restored. These happen to be the same
2740 // registers used to pass 'inreg' arguments so watch out for those.
2741 if (!Subtarget->is64Bit() &&
2742 !isa<GlobalAddressSDNode>(Callee) &&
2743 !isa<ExternalSymbolSDNode>(Callee)) {
2744 unsigned NumInRegs = 0;
2745 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2746 CCValAssign &VA = ArgLocs[i];
2749 unsigned Reg = VA.getLocReg();
2752 case X86::EAX: case X86::EDX: case X86::ECX:
2753 if (++NumInRegs == 3)
2765 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2766 return X86::createFastISel(funcInfo);
2770 //===----------------------------------------------------------------------===//
2771 // Other Lowering Hooks
2772 //===----------------------------------------------------------------------===//
2774 static bool MayFoldLoad(SDValue Op) {
2775 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2778 static bool MayFoldIntoStore(SDValue Op) {
2779 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2782 static bool isTargetShuffle(unsigned Opcode) {
2784 default: return false;
2785 case X86ISD::PSHUFD:
2786 case X86ISD::PSHUFHW:
2787 case X86ISD::PSHUFLW:
2788 case X86ISD::SHUFPD:
2789 case X86ISD::PALIGN:
2790 case X86ISD::SHUFPS:
2791 case X86ISD::MOVLHPS:
2792 case X86ISD::MOVLHPD:
2793 case X86ISD::MOVHLPS:
2794 case X86ISD::MOVLPS:
2795 case X86ISD::MOVLPD:
2796 case X86ISD::MOVSHDUP:
2797 case X86ISD::MOVSLDUP:
2798 case X86ISD::MOVDDUP:
2801 case X86ISD::UNPCKLPS:
2802 case X86ISD::UNPCKLPD:
2803 case X86ISD::VUNPCKLPSY:
2804 case X86ISD::VUNPCKLPDY:
2805 case X86ISD::PUNPCKLWD:
2806 case X86ISD::PUNPCKLBW:
2807 case X86ISD::PUNPCKLDQ:
2808 case X86ISD::PUNPCKLQDQ:
2809 case X86ISD::UNPCKHPS:
2810 case X86ISD::UNPCKHPD:
2811 case X86ISD::VUNPCKHPSY:
2812 case X86ISD::VUNPCKHPDY:
2813 case X86ISD::PUNPCKHWD:
2814 case X86ISD::PUNPCKHBW:
2815 case X86ISD::PUNPCKHDQ:
2816 case X86ISD::PUNPCKHQDQ:
2817 case X86ISD::VPERMILPS:
2818 case X86ISD::VPERMILPSY:
2819 case X86ISD::VPERMILPD:
2820 case X86ISD::VPERMILPDY:
2821 case X86ISD::VPERM2F128:
2827 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2828 SDValue V1, SelectionDAG &DAG) {
2830 default: llvm_unreachable("Unknown x86 shuffle node");
2831 case X86ISD::MOVSHDUP:
2832 case X86ISD::MOVSLDUP:
2833 case X86ISD::MOVDDUP:
2834 return DAG.getNode(Opc, dl, VT, V1);
2840 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2841 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2843 default: llvm_unreachable("Unknown x86 shuffle node");
2844 case X86ISD::PSHUFD:
2845 case X86ISD::PSHUFHW:
2846 case X86ISD::PSHUFLW:
2847 case X86ISD::VPERMILPS:
2848 case X86ISD::VPERMILPSY:
2849 case X86ISD::VPERMILPD:
2850 case X86ISD::VPERMILPDY:
2851 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2857 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2858 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2860 default: llvm_unreachable("Unknown x86 shuffle node");
2861 case X86ISD::PALIGN:
2862 case X86ISD::SHUFPD:
2863 case X86ISD::SHUFPS:
2864 case X86ISD::VPERM2F128:
2865 return DAG.getNode(Opc, dl, VT, V1, V2,
2866 DAG.getConstant(TargetMask, MVT::i8));
2871 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2872 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2874 default: llvm_unreachable("Unknown x86 shuffle node");
2875 case X86ISD::MOVLHPS:
2876 case X86ISD::MOVLHPD:
2877 case X86ISD::MOVHLPS:
2878 case X86ISD::MOVLPS:
2879 case X86ISD::MOVLPD:
2882 case X86ISD::UNPCKLPS:
2883 case X86ISD::UNPCKLPD:
2884 case X86ISD::VUNPCKLPSY:
2885 case X86ISD::VUNPCKLPDY:
2886 case X86ISD::PUNPCKLWD:
2887 case X86ISD::PUNPCKLBW:
2888 case X86ISD::PUNPCKLDQ:
2889 case X86ISD::PUNPCKLQDQ:
2890 case X86ISD::UNPCKHPS:
2891 case X86ISD::UNPCKHPD:
2892 case X86ISD::VUNPCKHPSY:
2893 case X86ISD::VUNPCKHPDY:
2894 case X86ISD::PUNPCKHWD:
2895 case X86ISD::PUNPCKHBW:
2896 case X86ISD::PUNPCKHDQ:
2897 case X86ISD::PUNPCKHQDQ:
2898 return DAG.getNode(Opc, dl, VT, V1, V2);
2903 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2904 MachineFunction &MF = DAG.getMachineFunction();
2905 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2906 int ReturnAddrIndex = FuncInfo->getRAIndex();
2908 if (ReturnAddrIndex == 0) {
2909 // Set up a frame object for the return address.
2910 uint64_t SlotSize = TD->getPointerSize();
2911 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2913 FuncInfo->setRAIndex(ReturnAddrIndex);
2916 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2920 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2921 bool hasSymbolicDisplacement) {
2922 // Offset should fit into 32 bit immediate field.
2923 if (!isInt<32>(Offset))
2926 // If we don't have a symbolic displacement - we don't have any extra
2928 if (!hasSymbolicDisplacement)
2931 // FIXME: Some tweaks might be needed for medium code model.
2932 if (M != CodeModel::Small && M != CodeModel::Kernel)
2935 // For small code model we assume that latest object is 16MB before end of 31
2936 // bits boundary. We may also accept pretty large negative constants knowing
2937 // that all objects are in the positive half of address space.
2938 if (M == CodeModel::Small && Offset < 16*1024*1024)
2941 // For kernel code model we know that all object resist in the negative half
2942 // of 32bits address space. We may not accept negative offsets, since they may
2943 // be just off and we may accept pretty large positive ones.
2944 if (M == CodeModel::Kernel && Offset > 0)
2950 /// isCalleePop - Determines whether the callee is required to pop its
2951 /// own arguments. Callee pop is necessary to support tail calls.
2952 bool X86::isCalleePop(CallingConv::ID CallingConv,
2953 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2957 switch (CallingConv) {
2960 case CallingConv::X86_StdCall:
2962 case CallingConv::X86_FastCall:
2964 case CallingConv::X86_ThisCall:
2966 case CallingConv::Fast:
2968 case CallingConv::GHC:
2973 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2974 /// specific condition code, returning the condition code and the LHS/RHS of the
2975 /// comparison to make.
2976 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2977 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2979 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2980 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2981 // X > -1 -> X == 0, jump !sign.
2982 RHS = DAG.getConstant(0, RHS.getValueType());
2983 return X86::COND_NS;
2984 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2985 // X < 0 -> X == 0, jump on sign.
2987 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2989 RHS = DAG.getConstant(0, RHS.getValueType());
2990 return X86::COND_LE;
2994 switch (SetCCOpcode) {
2995 default: llvm_unreachable("Invalid integer condition!");
2996 case ISD::SETEQ: return X86::COND_E;
2997 case ISD::SETGT: return X86::COND_G;
2998 case ISD::SETGE: return X86::COND_GE;
2999 case ISD::SETLT: return X86::COND_L;
3000 case ISD::SETLE: return X86::COND_LE;
3001 case ISD::SETNE: return X86::COND_NE;
3002 case ISD::SETULT: return X86::COND_B;
3003 case ISD::SETUGT: return X86::COND_A;
3004 case ISD::SETULE: return X86::COND_BE;
3005 case ISD::SETUGE: return X86::COND_AE;
3009 // First determine if it is required or is profitable to flip the operands.
3011 // If LHS is a foldable load, but RHS is not, flip the condition.
3012 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3013 !ISD::isNON_EXTLoad(RHS.getNode())) {
3014 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3015 std::swap(LHS, RHS);
3018 switch (SetCCOpcode) {
3024 std::swap(LHS, RHS);
3028 // On a floating point condition, the flags are set as follows:
3030 // 0 | 0 | 0 | X > Y
3031 // 0 | 0 | 1 | X < Y
3032 // 1 | 0 | 0 | X == Y
3033 // 1 | 1 | 1 | unordered
3034 switch (SetCCOpcode) {
3035 default: llvm_unreachable("Condcode should be pre-legalized away");
3037 case ISD::SETEQ: return X86::COND_E;
3038 case ISD::SETOLT: // flipped
3040 case ISD::SETGT: return X86::COND_A;
3041 case ISD::SETOLE: // flipped
3043 case ISD::SETGE: return X86::COND_AE;
3044 case ISD::SETUGT: // flipped
3046 case ISD::SETLT: return X86::COND_B;
3047 case ISD::SETUGE: // flipped
3049 case ISD::SETLE: return X86::COND_BE;
3051 case ISD::SETNE: return X86::COND_NE;
3052 case ISD::SETUO: return X86::COND_P;
3053 case ISD::SETO: return X86::COND_NP;
3055 case ISD::SETUNE: return X86::COND_INVALID;
3059 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3060 /// code. Current x86 isa includes the following FP cmov instructions:
3061 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3062 static bool hasFPCMov(unsigned X86CC) {
3078 /// isFPImmLegal - Returns true if the target can instruction select the
3079 /// specified FP immediate natively. If false, the legalizer will
3080 /// materialize the FP immediate as a load from a constant pool.
3081 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3082 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3083 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3089 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3090 /// the specified range (L, H].
3091 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3092 return (Val < 0) || (Val >= Low && Val < Hi);
3095 /// isUndefOrInRange - Return true if every element in Mask, begining
3096 /// from position Pos and ending in Pos+Size, falls within the specified
3097 /// range (L, L+Pos]. or is undef.
3098 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3099 int Pos, int Size, int Low, int Hi) {
3100 for (int i = Pos, e = Pos+Size; i != e; ++i)
3101 if (!isUndefOrInRange(Mask[i], Low, Hi))
3106 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3107 /// specified value.
3108 static bool isUndefOrEqual(int Val, int CmpVal) {
3109 if (Val < 0 || Val == CmpVal)
3114 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3115 /// from position Pos and ending in Pos+Size, falls within the specified
3116 /// sequential range (L, L+Pos]. or is undef.
3117 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3118 int Pos, int Size, int Low) {
3119 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3120 if (!isUndefOrEqual(Mask[i], Low))
3125 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3126 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3127 /// the second operand.
3128 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3129 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3130 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3131 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3132 return (Mask[0] < 2 && Mask[1] < 2);
3136 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3137 SmallVector<int, 8> M;
3139 return ::isPSHUFDMask(M, N->getValueType(0));
3142 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3143 /// is suitable for input to PSHUFHW.
3144 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3145 if (VT != MVT::v8i16)
3148 // Lower quadword copied in order or undef.
3149 for (int i = 0; i != 4; ++i)
3150 if (Mask[i] >= 0 && Mask[i] != i)
3153 // Upper quadword shuffled.
3154 for (int i = 4; i != 8; ++i)
3155 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3161 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3162 SmallVector<int, 8> M;
3164 return ::isPSHUFHWMask(M, N->getValueType(0));
3167 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3168 /// is suitable for input to PSHUFLW.
3169 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3170 if (VT != MVT::v8i16)
3173 // Upper quadword copied in order.
3174 for (int i = 4; i != 8; ++i)
3175 if (Mask[i] >= 0 && Mask[i] != i)
3178 // Lower quadword shuffled.
3179 for (int i = 0; i != 4; ++i)
3186 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3187 SmallVector<int, 8> M;
3189 return ::isPSHUFLWMask(M, N->getValueType(0));
3192 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3193 /// is suitable for input to PALIGNR.
3194 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3195 bool hasSSSE3OrAVX) {
3196 int i, e = VT.getVectorNumElements();
3197 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3200 // Do not handle v2i64 / v2f64 shuffles with palignr.
3201 if (e < 4 || !hasSSSE3OrAVX)
3204 for (i = 0; i != e; ++i)
3208 // All undef, not a palignr.
3212 // Make sure we're shifting in the right direction.
3216 int s = Mask[i] - i;
3218 // Check the rest of the elements to see if they are consecutive.
3219 for (++i; i != e; ++i) {
3221 if (m >= 0 && m != s+i)
3227 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
3228 /// specifies a shuffle of elements that is suitable for input to 256-bit
3230 static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3231 const X86Subtarget *Subtarget) {
3232 int NumElems = VT.getVectorNumElements();
3234 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3240 // VSHUFPSY divides the resulting vector into 4 chunks.
3241 // The sources are also splitted into 4 chunks, and each destination
3242 // chunk must come from a different source chunk.
3244 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3245 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3247 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3248 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3250 int QuarterSize = NumElems/4;
3251 int HalfSize = QuarterSize*2;
3252 for (int i = 0; i < QuarterSize; ++i)
3253 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3255 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3256 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3259 // The mask of the second half must be the same as the first but with
3260 // the appropriate offsets. This works in the same way as VPERMILPS
3261 // works with masks.
3262 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
3263 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3265 int FstHalfIdx = i-HalfSize;
3266 if (Mask[FstHalfIdx] < 0)
3268 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3271 for (int i = QuarterSize*3; i < NumElems; ++i) {
3272 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3274 int FstHalfIdx = i-HalfSize;
3275 if (Mask[FstHalfIdx] < 0)
3277 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3285 /// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle
3286 /// the specified VECTOR_MASK mask with VSHUFPSY instruction.
3287 static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) {
3288 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3289 EVT VT = SVOp->getValueType(0);
3290 int NumElems = VT.getVectorNumElements();
3292 assert(NumElems == 8 && VT.getSizeInBits() == 256 &&
3293 "Only supports v8i32 and v8f32 types");
3295 int HalfSize = NumElems/2;
3297 for (int i = 0; i != NumElems ; ++i) {
3298 if (SVOp->getMaskElt(i) < 0)
3300 // The mask of the first half must be equal to the second one.
3301 unsigned Shamt = (i%HalfSize)*2;
3302 unsigned Elt = SVOp->getMaskElt(i) % HalfSize;
3303 Mask |= Elt << Shamt;
3309 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
3310 /// specifies a shuffle of elements that is suitable for input to 256-bit
3311 /// VSHUFPDY. This shuffle doesn't have the same restriction as the PS
3312 /// version and the mask of the second half isn't binded with the first
3314 static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3315 const X86Subtarget *Subtarget) {
3316 int NumElems = VT.getVectorNumElements();
3318 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3324 // VSHUFPSY divides the resulting vector into 4 chunks.
3325 // The sources are also splitted into 4 chunks, and each destination
3326 // chunk must come from a different source chunk.
3328 // SRC1 => X3 X2 X1 X0
3329 // SRC2 => Y3 Y2 Y1 Y0
3331 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0
3333 int QuarterSize = NumElems/4;
3334 int HalfSize = QuarterSize*2;
3335 for (int i = 0; i < QuarterSize; ++i)
3336 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3338 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3339 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3341 for (int i = QuarterSize*2; i < QuarterSize*3; ++i)
3342 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3344 for (int i = QuarterSize*3; i < NumElems; ++i)
3345 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3351 /// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle
3352 /// the specified VECTOR_MASK mask with VSHUFPDY instruction.
3353 static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
3354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3355 EVT VT = SVOp->getValueType(0);
3356 int NumElems = VT.getVectorNumElements();
3358 assert(NumElems == 4 && VT.getSizeInBits() == 256 &&
3359 "Only supports v4i64 and v4f64 types");
3361 int HalfSize = NumElems/2;
3363 for (int i = 0; i != NumElems ; ++i) {
3364 if (SVOp->getMaskElt(i) < 0)
3366 int Elt = SVOp->getMaskElt(i) % HalfSize;
3373 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3374 /// specifies a shuffle of elements that is suitable for input to 128-bit
3375 /// SHUFPS and SHUFPD.
3376 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3377 int NumElems = VT.getVectorNumElements();
3379 if (VT.getSizeInBits() != 128)
3382 if (NumElems != 2 && NumElems != 4)
3385 int Half = NumElems / 2;
3386 for (int i = 0; i < Half; ++i)
3387 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3389 for (int i = Half; i < NumElems; ++i)
3390 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3396 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3397 SmallVector<int, 8> M;
3399 return ::isSHUFPMask(M, N->getValueType(0));
3402 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3403 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3404 /// half elements to come from vector 1 (which would equal the dest.) and
3405 /// the upper half to come from vector 2.
3406 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3407 int NumElems = VT.getVectorNumElements();
3409 if (NumElems != 2 && NumElems != 4)
3412 int Half = NumElems / 2;
3413 for (int i = 0; i < Half; ++i)
3414 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3416 for (int i = Half; i < NumElems; ++i)
3417 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3422 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3423 SmallVector<int, 8> M;
3425 return isCommutedSHUFPMask(M, N->getValueType(0));
3428 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3429 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3430 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3431 EVT VT = N->getValueType(0);
3432 unsigned NumElems = VT.getVectorNumElements();
3434 if (VT.getSizeInBits() != 128)
3440 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3441 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3442 isUndefOrEqual(N->getMaskElt(1), 7) &&
3443 isUndefOrEqual(N->getMaskElt(2), 2) &&
3444 isUndefOrEqual(N->getMaskElt(3), 3);
3447 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3448 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3450 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3451 EVT VT = N->getValueType(0);
3452 unsigned NumElems = VT.getVectorNumElements();
3454 if (VT.getSizeInBits() != 128)
3460 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3461 isUndefOrEqual(N->getMaskElt(1), 3) &&
3462 isUndefOrEqual(N->getMaskElt(2), 2) &&
3463 isUndefOrEqual(N->getMaskElt(3), 3);
3466 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3467 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3468 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3469 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3471 if (NumElems != 2 && NumElems != 4)
3474 for (unsigned i = 0; i < NumElems/2; ++i)
3475 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3478 for (unsigned i = NumElems/2; i < NumElems; ++i)
3479 if (!isUndefOrEqual(N->getMaskElt(i), i))
3485 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3486 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3487 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3488 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3490 if ((NumElems != 2 && NumElems != 4)
3491 || N->getValueType(0).getSizeInBits() > 128)
3494 for (unsigned i = 0; i < NumElems/2; ++i)
3495 if (!isUndefOrEqual(N->getMaskElt(i), i))
3498 for (unsigned i = 0; i < NumElems/2; ++i)
3499 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3505 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3506 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3507 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3508 bool V2IsSplat = false) {
3509 int NumElts = VT.getVectorNumElements();
3511 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3512 "Unsupported vector type for unpckh");
3514 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3517 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3518 // independently on 128-bit lanes.
3519 unsigned NumLanes = VT.getSizeInBits()/128;
3520 unsigned NumLaneElts = NumElts/NumLanes;
3523 unsigned End = NumLaneElts;
3524 for (unsigned s = 0; s < NumLanes; ++s) {
3525 for (unsigned i = Start, j = s * NumLaneElts;
3529 int BitI1 = Mask[i+1];
3530 if (!isUndefOrEqual(BitI, j))
3533 if (!isUndefOrEqual(BitI1, NumElts))
3536 if (!isUndefOrEqual(BitI1, j + NumElts))
3540 // Process the next 128 bits.
3541 Start += NumLaneElts;
3548 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3549 SmallVector<int, 8> M;
3551 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3554 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3555 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3556 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3557 bool V2IsSplat = false) {
3558 int NumElts = VT.getVectorNumElements();
3560 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3561 "Unsupported vector type for unpckh");
3563 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3566 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3567 // independently on 128-bit lanes.
3568 unsigned NumLanes = VT.getSizeInBits()/128;
3569 unsigned NumLaneElts = NumElts/NumLanes;
3572 unsigned End = NumLaneElts;
3573 for (unsigned l = 0; l != NumLanes; ++l) {
3574 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3575 i != End; i += 2, ++j) {
3577 int BitI1 = Mask[i+1];
3578 if (!isUndefOrEqual(BitI, j))
3581 if (isUndefOrEqual(BitI1, NumElts))
3584 if (!isUndefOrEqual(BitI1, j+NumElts))
3588 // Process the next 128 bits.
3589 Start += NumLaneElts;
3595 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3596 SmallVector<int, 8> M;
3598 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3601 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3602 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3604 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3605 int NumElems = VT.getVectorNumElements();
3606 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3609 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3610 // FIXME: Need a better way to get rid of this, there's no latency difference
3611 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3612 // the former later. We should also remove the "_undef" special mask.
3613 if (NumElems == 4 && VT.getSizeInBits() == 256)
3616 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3617 // independently on 128-bit lanes.
3618 unsigned NumLanes = VT.getSizeInBits() / 128;
3619 unsigned NumLaneElts = NumElems / NumLanes;
3621 for (unsigned s = 0; s < NumLanes; ++s) {
3622 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3623 i != NumLaneElts * (s + 1);
3626 int BitI1 = Mask[i+1];
3628 if (!isUndefOrEqual(BitI, j))
3630 if (!isUndefOrEqual(BitI1, j))
3638 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3639 SmallVector<int, 8> M;
3641 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3644 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3645 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3647 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3648 int NumElems = VT.getVectorNumElements();
3649 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3652 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3654 int BitI1 = Mask[i+1];
3655 if (!isUndefOrEqual(BitI, j))
3657 if (!isUndefOrEqual(BitI1, j))
3663 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3664 SmallVector<int, 8> M;
3666 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3669 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3670 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3671 /// MOVSD, and MOVD, i.e. setting the lowest element.
3672 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3673 if (VT.getVectorElementType().getSizeInBits() < 32)
3676 int NumElts = VT.getVectorNumElements();
3678 if (!isUndefOrEqual(Mask[0], NumElts))
3681 for (int i = 1; i < NumElts; ++i)
3682 if (!isUndefOrEqual(Mask[i], i))
3688 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3689 SmallVector<int, 8> M;
3691 return ::isMOVLMask(M, N->getValueType(0));
3694 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3695 /// as permutations between 128-bit chunks or halves. As an example: this
3697 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3698 /// The first half comes from the second half of V1 and the second half from the
3699 /// the second half of V2.
3700 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3701 const X86Subtarget *Subtarget) {
3702 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3705 // The shuffle result is divided into half A and half B. In total the two
3706 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3707 // B must come from C, D, E or F.
3708 int HalfSize = VT.getVectorNumElements()/2;
3709 bool MatchA = false, MatchB = false;
3711 // Check if A comes from one of C, D, E, F.
3712 for (int Half = 0; Half < 4; ++Half) {
3713 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3719 // Check if B comes from one of C, D, E, F.
3720 for (int Half = 0; Half < 4; ++Half) {
3721 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3727 return MatchA && MatchB;
3730 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3731 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3732 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3733 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3734 EVT VT = SVOp->getValueType(0);
3736 int HalfSize = VT.getVectorNumElements()/2;
3738 int FstHalf = 0, SndHalf = 0;
3739 for (int i = 0; i < HalfSize; ++i) {
3740 if (SVOp->getMaskElt(i) > 0) {
3741 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3745 for (int i = HalfSize; i < HalfSize*2; ++i) {
3746 if (SVOp->getMaskElt(i) > 0) {
3747 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3752 return (FstHalf | (SndHalf << 4));
3755 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3756 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3757 /// Note that VPERMIL mask matching is different depending whether theunderlying
3758 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3759 /// to the same elements of the low, but to the higher half of the source.
3760 /// In VPERMILPD the two lanes could be shuffled independently of each other
3761 /// with the same restriction that lanes can't be crossed.
3762 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3763 const X86Subtarget *Subtarget) {
3764 int NumElts = VT.getVectorNumElements();
3765 int NumLanes = VT.getSizeInBits()/128;
3767 if (!Subtarget->hasAVX())
3770 // Only match 256-bit with 64-bit types
3771 if (VT.getSizeInBits() != 256 || NumElts != 4)
3774 // The mask on the high lane is independent of the low. Both can match
3775 // any element in inside its own lane, but can't cross.
3776 int LaneSize = NumElts/NumLanes;
3777 for (int l = 0; l < NumLanes; ++l)
3778 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3779 int LaneStart = l*LaneSize;
3780 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3787 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3788 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3789 /// Note that VPERMIL mask matching is different depending whether theunderlying
3790 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3791 /// to the same elements of the low, but to the higher half of the source.
3792 /// In VPERMILPD the two lanes could be shuffled independently of each other
3793 /// with the same restriction that lanes can't be crossed.
3794 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3795 const X86Subtarget *Subtarget) {
3796 unsigned NumElts = VT.getVectorNumElements();
3797 unsigned NumLanes = VT.getSizeInBits()/128;
3799 if (!Subtarget->hasAVX())
3802 // Only match 256-bit with 32-bit types
3803 if (VT.getSizeInBits() != 256 || NumElts != 8)
3806 // The mask on the high lane should be the same as the low. Actually,
3807 // they can differ if any of the corresponding index in a lane is undef
3808 // and the other stays in range.
3809 int LaneSize = NumElts/NumLanes;
3810 for (int i = 0; i < LaneSize; ++i) {
3811 int HighElt = i+LaneSize;
3812 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3813 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3815 if (!HighValid || !LowValid)
3817 if (Mask[i] < 0 || Mask[HighElt] < 0)
3819 if (Mask[HighElt]-Mask[i] != LaneSize)
3826 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3827 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3828 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3830 EVT VT = SVOp->getValueType(0);
3832 int NumElts = VT.getVectorNumElements();
3833 int NumLanes = VT.getSizeInBits()/128;
3834 int LaneSize = NumElts/NumLanes;
3836 // Although the mask is equal for both lanes do it twice to get the cases
3837 // where a mask will match because the same mask element is undef on the
3838 // first half but valid on the second. This would get pathological cases
3839 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3841 for (int l = 0; l < NumLanes; ++l) {
3842 for (int i = 0; i < LaneSize; ++i) {
3843 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3846 if (MaskElt >= LaneSize)
3847 MaskElt -= LaneSize;
3848 Mask |= MaskElt << (i*2);
3855 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3856 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3857 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3858 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3859 EVT VT = SVOp->getValueType(0);
3861 int NumElts = VT.getVectorNumElements();
3862 int NumLanes = VT.getSizeInBits()/128;
3865 int LaneSize = NumElts/NumLanes;
3866 for (int l = 0; l < NumLanes; ++l)
3867 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3868 int MaskElt = SVOp->getMaskElt(i);
3871 Mask |= (MaskElt-l*LaneSize) << i;
3877 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3878 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3879 /// element of vector 2 and the other elements to come from vector 1 in order.
3880 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3881 bool V2IsSplat = false, bool V2IsUndef = false) {
3882 int NumOps = VT.getVectorNumElements();
3883 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3886 if (!isUndefOrEqual(Mask[0], 0))
3889 for (int i = 1; i < NumOps; ++i)
3890 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3891 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3892 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3898 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3899 bool V2IsUndef = false) {
3900 SmallVector<int, 8> M;
3902 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3905 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3906 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3907 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3908 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3909 const X86Subtarget *Subtarget) {
3910 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3913 // The second vector must be undef
3914 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3917 EVT VT = N->getValueType(0);
3918 unsigned NumElems = VT.getVectorNumElements();
3920 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3921 (VT.getSizeInBits() == 256 && NumElems != 8))
3924 // "i+1" is the value the indexed mask element must have
3925 for (unsigned i = 0; i < NumElems; i += 2)
3926 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3927 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3933 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3934 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3935 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3936 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3937 const X86Subtarget *Subtarget) {
3938 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3941 // The second vector must be undef
3942 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3945 EVT VT = N->getValueType(0);
3946 unsigned NumElems = VT.getVectorNumElements();
3948 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3949 (VT.getSizeInBits() == 256 && NumElems != 8))
3952 // "i" is the value the indexed mask element must have
3953 for (unsigned i = 0; i < NumElems; i += 2)
3954 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3955 !isUndefOrEqual(N->getMaskElt(i+1), i))
3961 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3962 /// specifies a shuffle of elements that is suitable for input to 256-bit
3963 /// version of MOVDDUP.
3964 static bool isMOVDDUPYMask(ShuffleVectorSDNode *N,
3965 const X86Subtarget *Subtarget) {
3966 EVT VT = N->getValueType(0);
3967 int NumElts = VT.getVectorNumElements();
3968 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF;
3970 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 ||
3971 !V2IsUndef || NumElts != 4)
3974 for (int i = 0; i != NumElts/2; ++i)
3975 if (!isUndefOrEqual(N->getMaskElt(i), 0))
3977 for (int i = NumElts/2; i != NumElts; ++i)
3978 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2))
3983 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3984 /// specifies a shuffle of elements that is suitable for input to 128-bit
3985 /// version of MOVDDUP.
3986 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3987 EVT VT = N->getValueType(0);
3989 if (VT.getSizeInBits() != 128)
3992 int e = VT.getVectorNumElements() / 2;
3993 for (int i = 0; i < e; ++i)
3994 if (!isUndefOrEqual(N->getMaskElt(i), i))
3996 for (int i = 0; i < e; ++i)
3997 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
4002 /// isVEXTRACTF128Index - Return true if the specified
4003 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4004 /// suitable for input to VEXTRACTF128.
4005 bool X86::isVEXTRACTF128Index(SDNode *N) {
4006 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4009 // The index should be aligned on a 128-bit boundary.
4011 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4013 unsigned VL = N->getValueType(0).getVectorNumElements();
4014 unsigned VBits = N->getValueType(0).getSizeInBits();
4015 unsigned ElSize = VBits / VL;
4016 bool Result = (Index * ElSize) % 128 == 0;
4021 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4022 /// operand specifies a subvector insert that is suitable for input to
4024 bool X86::isVINSERTF128Index(SDNode *N) {
4025 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4028 // The index should be aligned on a 128-bit boundary.
4030 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4032 unsigned VL = N->getValueType(0).getVectorNumElements();
4033 unsigned VBits = N->getValueType(0).getSizeInBits();
4034 unsigned ElSize = VBits / VL;
4035 bool Result = (Index * ElSize) % 128 == 0;
4040 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4041 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4042 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
4043 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4044 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
4046 unsigned Shift = (NumOperands == 4) ? 2 : 1;
4048 for (int i = 0; i < NumOperands; ++i) {
4049 int Val = SVOp->getMaskElt(NumOperands-i-1);
4050 if (Val < 0) Val = 0;
4051 if (Val >= NumOperands) Val -= NumOperands;
4053 if (i != NumOperands - 1)
4059 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4060 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4061 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
4062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4064 // 8 nodes, but we only care about the last 4.
4065 for (unsigned i = 7; i >= 4; --i) {
4066 int Val = SVOp->getMaskElt(i);
4075 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4076 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4077 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
4078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4080 // 8 nodes, but we only care about the first 4.
4081 for (int i = 3; i >= 0; --i) {
4082 int Val = SVOp->getMaskElt(i);
4091 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4092 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4093 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
4094 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4095 EVT VVT = N->getValueType(0);
4096 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
4100 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
4101 Val = SVOp->getMaskElt(i);
4105 assert(Val - i > 0 && "PALIGNR imm should be positive");
4106 return (Val - i) * EltSize;
4109 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4110 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4112 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4113 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4114 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4117 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4119 EVT VecVT = N->getOperand(0).getValueType();
4120 EVT ElVT = VecVT.getVectorElementType();
4122 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4123 return Index / NumElemsPerChunk;
4126 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4127 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4129 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4130 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4131 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4134 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4136 EVT VecVT = N->getValueType(0);
4137 EVT ElVT = VecVT.getVectorElementType();
4139 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4140 return Index / NumElemsPerChunk;
4143 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4145 bool X86::isZeroNode(SDValue Elt) {
4146 return ((isa<ConstantSDNode>(Elt) &&
4147 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4148 (isa<ConstantFPSDNode>(Elt) &&
4149 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4152 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4153 /// their permute mask.
4154 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4155 SelectionDAG &DAG) {
4156 EVT VT = SVOp->getValueType(0);
4157 unsigned NumElems = VT.getVectorNumElements();
4158 SmallVector<int, 8> MaskVec;
4160 for (unsigned i = 0; i != NumElems; ++i) {
4161 int idx = SVOp->getMaskElt(i);
4163 MaskVec.push_back(idx);
4164 else if (idx < (int)NumElems)
4165 MaskVec.push_back(idx + NumElems);
4167 MaskVec.push_back(idx - NumElems);
4169 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4170 SVOp->getOperand(0), &MaskVec[0]);
4173 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4174 /// the two vector operands have swapped position.
4175 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
4176 unsigned NumElems = VT.getVectorNumElements();
4177 for (unsigned i = 0; i != NumElems; ++i) {
4181 else if (idx < (int)NumElems)
4182 Mask[i] = idx + NumElems;
4184 Mask[i] = idx - NumElems;
4188 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4189 /// match movhlps. The lower half elements should come from upper half of
4190 /// V1 (and in order), and the upper half elements should come from the upper
4191 /// half of V2 (and in order).
4192 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4193 EVT VT = Op->getValueType(0);
4194 if (VT.getSizeInBits() != 128)
4196 if (VT.getVectorNumElements() != 4)
4198 for (unsigned i = 0, e = 2; i != e; ++i)
4199 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4201 for (unsigned i = 2; i != 4; ++i)
4202 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4207 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4208 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4210 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4211 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4213 N = N->getOperand(0).getNode();
4214 if (!ISD::isNON_EXTLoad(N))
4217 *LD = cast<LoadSDNode>(N);
4221 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4222 /// match movlp{s|d}. The lower half elements should come from lower half of
4223 /// V1 (and in order), and the upper half elements should come from the upper
4224 /// half of V2 (and in order). And since V1 will become the source of the
4225 /// MOVLP, it must be either a vector load or a scalar load to vector.
4226 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4227 ShuffleVectorSDNode *Op) {
4228 EVT VT = Op->getValueType(0);
4229 if (VT.getSizeInBits() != 128)
4232 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4234 // Is V2 is a vector load, don't do this transformation. We will try to use
4235 // load folding shufps op.
4236 if (ISD::isNON_EXTLoad(V2))
4239 unsigned NumElems = VT.getVectorNumElements();
4241 if (NumElems != 2 && NumElems != 4)
4243 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4244 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4246 for (unsigned i = NumElems/2; i != NumElems; ++i)
4247 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4252 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4254 static bool isSplatVector(SDNode *N) {
4255 if (N->getOpcode() != ISD::BUILD_VECTOR)
4258 SDValue SplatValue = N->getOperand(0);
4259 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4260 if (N->getOperand(i) != SplatValue)
4265 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4266 /// to an zero vector.
4267 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4268 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4269 SDValue V1 = N->getOperand(0);
4270 SDValue V2 = N->getOperand(1);
4271 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4272 for (unsigned i = 0; i != NumElems; ++i) {
4273 int Idx = N->getMaskElt(i);
4274 if (Idx >= (int)NumElems) {
4275 unsigned Opc = V2.getOpcode();
4276 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4278 if (Opc != ISD::BUILD_VECTOR ||
4279 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4281 } else if (Idx >= 0) {
4282 unsigned Opc = V1.getOpcode();
4283 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4285 if (Opc != ISD::BUILD_VECTOR ||
4286 !X86::isZeroNode(V1.getOperand(Idx)))
4293 /// getZeroVector - Returns a vector of specified type with all zero elements.
4295 static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG,
4297 assert(VT.isVector() && "Expected a vector type");
4299 // Always build SSE zero vectors as <4 x i32> bitcasted
4300 // to their dest type. This ensures they get CSE'd.
4302 if (VT.getSizeInBits() == 128) { // SSE
4303 if (HasXMMInt) { // SSE2
4304 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4305 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4307 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4308 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4310 } else if (VT.getSizeInBits() == 256) { // AVX
4311 // 256-bit logic and arithmetic instructions in AVX are
4312 // all floating-point, no support for integer ops. Default
4313 // to emitting fp zeroed vectors then.
4314 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4315 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4316 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4318 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4321 /// getOnesVector - Returns a vector of specified type with all bits set.
4322 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4323 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4324 /// original type, ensuring they get CSE'd.
4325 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4326 assert(VT.isVector() && "Expected a vector type");
4327 assert((VT.is128BitVector() || VT.is256BitVector())
4328 && "Expected a 128-bit or 256-bit vector type");
4330 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4331 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4332 Cst, Cst, Cst, Cst);
4334 if (VT.is256BitVector()) {
4335 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4336 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4337 Vec = Insert128BitVector(InsV, Vec,
4338 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4341 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4344 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4345 /// that point to V2 points to its first element.
4346 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4347 EVT VT = SVOp->getValueType(0);
4348 unsigned NumElems = VT.getVectorNumElements();
4350 bool Changed = false;
4351 SmallVector<int, 8> MaskVec;
4352 SVOp->getMask(MaskVec);
4354 for (unsigned i = 0; i != NumElems; ++i) {
4355 if (MaskVec[i] > (int)NumElems) {
4356 MaskVec[i] = NumElems;
4361 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4362 SVOp->getOperand(1), &MaskVec[0]);
4363 return SDValue(SVOp, 0);
4366 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4367 /// operation of specified width.
4368 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4370 unsigned NumElems = VT.getVectorNumElements();
4371 SmallVector<int, 8> Mask;
4372 Mask.push_back(NumElems);
4373 for (unsigned i = 1; i != NumElems; ++i)
4375 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4378 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4379 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4381 unsigned NumElems = VT.getVectorNumElements();
4382 SmallVector<int, 8> Mask;
4383 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4385 Mask.push_back(i + NumElems);
4387 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4390 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4391 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4393 unsigned NumElems = VT.getVectorNumElements();
4394 unsigned Half = NumElems/2;
4395 SmallVector<int, 8> Mask;
4396 for (unsigned i = 0; i != Half; ++i) {
4397 Mask.push_back(i + Half);
4398 Mask.push_back(i + NumElems + Half);
4400 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4403 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4404 // a generic shuffle instruction because the target has no such instructions.
4405 // Generate shuffles which repeat i16 and i8 several times until they can be
4406 // represented by v4f32 and then be manipulated by target suported shuffles.
4407 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4408 EVT VT = V.getValueType();
4409 int NumElems = VT.getVectorNumElements();
4410 DebugLoc dl = V.getDebugLoc();
4412 while (NumElems > 4) {
4413 if (EltNo < NumElems/2) {
4414 V = getUnpackl(DAG, dl, VT, V, V);
4416 V = getUnpackh(DAG, dl, VT, V, V);
4417 EltNo -= NumElems/2;
4424 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4425 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4426 EVT VT = V.getValueType();
4427 DebugLoc dl = V.getDebugLoc();
4428 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4429 && "Vector size not supported");
4431 if (VT.getSizeInBits() == 128) {
4432 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4433 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4434 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4437 // To use VPERMILPS to splat scalars, the second half of indicies must
4438 // refer to the higher part, which is a duplication of the lower one,
4439 // because VPERMILPS can only handle in-lane permutations.
4440 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4441 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4443 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4444 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4448 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4451 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4452 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4453 EVT SrcVT = SV->getValueType(0);
4454 SDValue V1 = SV->getOperand(0);
4455 DebugLoc dl = SV->getDebugLoc();
4457 int EltNo = SV->getSplatIndex();
4458 int NumElems = SrcVT.getVectorNumElements();
4459 unsigned Size = SrcVT.getSizeInBits();
4461 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4462 "Unknown how to promote splat for type");
4464 // Extract the 128-bit part containing the splat element and update
4465 // the splat element index when it refers to the higher register.
4467 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4468 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4470 EltNo -= NumElems/2;
4473 // All i16 and i8 vector types can't be used directly by a generic shuffle
4474 // instruction because the target has no such instruction. Generate shuffles
4475 // which repeat i16 and i8 several times until they fit in i32, and then can
4476 // be manipulated by target suported shuffles.
4477 EVT EltVT = SrcVT.getVectorElementType();
4478 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4479 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4481 // Recreate the 256-bit vector and place the same 128-bit vector
4482 // into the low and high part. This is necessary because we want
4483 // to use VPERM* to shuffle the vectors
4485 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4486 DAG.getConstant(0, MVT::i32), DAG, dl);
4487 V1 = Insert128BitVector(InsV, V1,
4488 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4491 return getLegalSplat(DAG, V1, EltNo);
4494 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4495 /// vector of zero or undef vector. This produces a shuffle where the low
4496 /// element of V2 is swizzled into the zero/undef vector, landing at element
4497 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4498 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4499 bool isZero, bool HasXMMInt,
4500 SelectionDAG &DAG) {
4501 EVT VT = V2.getValueType();
4503 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4504 unsigned NumElems = VT.getVectorNumElements();
4505 SmallVector<int, 16> MaskVec;
4506 for (unsigned i = 0; i != NumElems; ++i)
4507 // If this is the insertion idx, put the low elt of V2 here.
4508 MaskVec.push_back(i == Idx ? NumElems : i);
4509 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4512 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4513 /// element of the result of the vector shuffle.
4514 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4517 return SDValue(); // Limit search depth.
4519 SDValue V = SDValue(N, 0);
4520 EVT VT = V.getValueType();
4521 unsigned Opcode = V.getOpcode();
4523 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4524 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4525 Index = SV->getMaskElt(Index);
4528 return DAG.getUNDEF(VT.getVectorElementType());
4530 int NumElems = VT.getVectorNumElements();
4531 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4532 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4535 // Recurse into target specific vector shuffles to find scalars.
4536 if (isTargetShuffle(Opcode)) {
4537 int NumElems = VT.getVectorNumElements();
4538 SmallVector<unsigned, 16> ShuffleMask;
4542 case X86ISD::SHUFPS:
4543 case X86ISD::SHUFPD:
4544 ImmN = N->getOperand(N->getNumOperands()-1);
4545 DecodeSHUFPSMask(NumElems,
4546 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4549 case X86ISD::PUNPCKHBW:
4550 case X86ISD::PUNPCKHWD:
4551 case X86ISD::PUNPCKHDQ:
4552 case X86ISD::PUNPCKHQDQ:
4553 DecodePUNPCKHMask(NumElems, ShuffleMask);
4555 case X86ISD::UNPCKHPS:
4556 case X86ISD::UNPCKHPD:
4557 case X86ISD::VUNPCKHPSY:
4558 case X86ISD::VUNPCKHPDY:
4559 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4561 case X86ISD::PUNPCKLBW:
4562 case X86ISD::PUNPCKLWD:
4563 case X86ISD::PUNPCKLDQ:
4564 case X86ISD::PUNPCKLQDQ:
4565 DecodePUNPCKLMask(VT, ShuffleMask);
4567 case X86ISD::UNPCKLPS:
4568 case X86ISD::UNPCKLPD:
4569 case X86ISD::VUNPCKLPSY:
4570 case X86ISD::VUNPCKLPDY:
4571 DecodeUNPCKLPMask(VT, ShuffleMask);
4573 case X86ISD::MOVHLPS:
4574 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4576 case X86ISD::MOVLHPS:
4577 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4579 case X86ISD::PSHUFD:
4580 ImmN = N->getOperand(N->getNumOperands()-1);
4581 DecodePSHUFMask(NumElems,
4582 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4585 case X86ISD::PSHUFHW:
4586 ImmN = N->getOperand(N->getNumOperands()-1);
4587 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4590 case X86ISD::PSHUFLW:
4591 ImmN = N->getOperand(N->getNumOperands()-1);
4592 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4596 case X86ISD::MOVSD: {
4597 // The index 0 always comes from the first element of the second source,
4598 // this is why MOVSS and MOVSD are used in the first place. The other
4599 // elements come from the other positions of the first source vector.
4600 unsigned OpNum = (Index == 0) ? 1 : 0;
4601 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4604 case X86ISD::VPERMILPS:
4605 ImmN = N->getOperand(N->getNumOperands()-1);
4606 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4609 case X86ISD::VPERMILPSY:
4610 ImmN = N->getOperand(N->getNumOperands()-1);
4611 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4614 case X86ISD::VPERMILPD:
4615 ImmN = N->getOperand(N->getNumOperands()-1);
4616 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4619 case X86ISD::VPERMILPDY:
4620 ImmN = N->getOperand(N->getNumOperands()-1);
4621 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4624 case X86ISD::VPERM2F128:
4625 ImmN = N->getOperand(N->getNumOperands()-1);
4626 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4629 case X86ISD::MOVDDUP:
4630 case X86ISD::MOVLHPD:
4631 case X86ISD::MOVLPD:
4632 case X86ISD::MOVLPS:
4633 case X86ISD::MOVSHDUP:
4634 case X86ISD::MOVSLDUP:
4635 case X86ISD::PALIGN:
4636 return SDValue(); // Not yet implemented.
4638 assert(0 && "unknown target shuffle node");
4642 Index = ShuffleMask[Index];
4644 return DAG.getUNDEF(VT.getVectorElementType());
4646 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4647 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4651 // Actual nodes that may contain scalar elements
4652 if (Opcode == ISD::BITCAST) {
4653 V = V.getOperand(0);
4654 EVT SrcVT = V.getValueType();
4655 unsigned NumElems = VT.getVectorNumElements();
4657 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4661 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4662 return (Index == 0) ? V.getOperand(0)
4663 : DAG.getUNDEF(VT.getVectorElementType());
4665 if (V.getOpcode() == ISD::BUILD_VECTOR)
4666 return V.getOperand(Index);
4671 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4672 /// shuffle operation which come from a consecutively from a zero. The
4673 /// search can start in two different directions, from left or right.
4675 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4676 bool ZerosFromLeft, SelectionDAG &DAG) {
4679 while (i < NumElems) {
4680 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4681 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4682 if (!(Elt.getNode() &&
4683 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4691 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4692 /// MaskE correspond consecutively to elements from one of the vector operands,
4693 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4695 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4696 int OpIdx, int NumElems, unsigned &OpNum) {
4697 bool SeenV1 = false;
4698 bool SeenV2 = false;
4700 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4701 int Idx = SVOp->getMaskElt(i);
4702 // Ignore undef indicies
4711 // Only accept consecutive elements from the same vector
4712 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4716 OpNum = SeenV1 ? 0 : 1;
4720 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4721 /// logical left shift of a vector.
4722 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4723 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4724 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4725 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4726 false /* check zeros from right */, DAG);
4732 // Considering the elements in the mask that are not consecutive zeros,
4733 // check if they consecutively come from only one of the source vectors.
4735 // V1 = {X, A, B, C} 0
4737 // vector_shuffle V1, V2 <1, 2, 3, X>
4739 if (!isShuffleMaskConsecutive(SVOp,
4740 0, // Mask Start Index
4741 NumElems-NumZeros-1, // Mask End Index
4742 NumZeros, // Where to start looking in the src vector
4743 NumElems, // Number of elements in vector
4744 OpSrc)) // Which source operand ?
4749 ShVal = SVOp->getOperand(OpSrc);
4753 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4754 /// logical left shift of a vector.
4755 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4756 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4757 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4758 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4759 true /* check zeros from left */, DAG);
4765 // Considering the elements in the mask that are not consecutive zeros,
4766 // check if they consecutively come from only one of the source vectors.
4768 // 0 { A, B, X, X } = V2
4770 // vector_shuffle V1, V2 <X, X, 4, 5>
4772 if (!isShuffleMaskConsecutive(SVOp,
4773 NumZeros, // Mask Start Index
4774 NumElems-1, // Mask End Index
4775 0, // Where to start looking in the src vector
4776 NumElems, // Number of elements in vector
4777 OpSrc)) // Which source operand ?
4782 ShVal = SVOp->getOperand(OpSrc);
4786 /// isVectorShift - Returns true if the shuffle can be implemented as a
4787 /// logical left or right shift of a vector.
4788 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4789 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4790 // Although the logic below support any bitwidth size, there are no
4791 // shift instructions which handle more than 128-bit vectors.
4792 if (SVOp->getValueType(0).getSizeInBits() > 128)
4795 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4796 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4802 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4804 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4805 unsigned NumNonZero, unsigned NumZero,
4807 const TargetLowering &TLI) {
4811 DebugLoc dl = Op.getDebugLoc();
4814 for (unsigned i = 0; i < 16; ++i) {
4815 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4816 if (ThisIsNonZero && First) {
4818 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4820 V = DAG.getUNDEF(MVT::v8i16);
4825 SDValue ThisElt(0, 0), LastElt(0, 0);
4826 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4827 if (LastIsNonZero) {
4828 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4829 MVT::i16, Op.getOperand(i-1));
4831 if (ThisIsNonZero) {
4832 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4833 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4834 ThisElt, DAG.getConstant(8, MVT::i8));
4836 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4840 if (ThisElt.getNode())
4841 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4842 DAG.getIntPtrConstant(i/2));
4846 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4849 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4851 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4852 unsigned NumNonZero, unsigned NumZero,
4854 const TargetLowering &TLI) {
4858 DebugLoc dl = Op.getDebugLoc();
4861 for (unsigned i = 0; i < 8; ++i) {
4862 bool isNonZero = (NonZeros & (1 << i)) != 0;
4866 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4868 V = DAG.getUNDEF(MVT::v8i16);
4871 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4872 MVT::v8i16, V, Op.getOperand(i),
4873 DAG.getIntPtrConstant(i));
4880 /// getVShift - Return a vector logical shift node.
4882 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4883 unsigned NumBits, SelectionDAG &DAG,
4884 const TargetLowering &TLI, DebugLoc dl) {
4885 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4886 EVT ShVT = MVT::v2i64;
4887 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4888 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4889 return DAG.getNode(ISD::BITCAST, dl, VT,
4890 DAG.getNode(Opc, dl, ShVT, SrcOp,
4891 DAG.getConstant(NumBits,
4892 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4896 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4897 SelectionDAG &DAG) const {
4899 // Check if the scalar load can be widened into a vector load. And if
4900 // the address is "base + cst" see if the cst can be "absorbed" into
4901 // the shuffle mask.
4902 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4903 SDValue Ptr = LD->getBasePtr();
4904 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4906 EVT PVT = LD->getValueType(0);
4907 if (PVT != MVT::i32 && PVT != MVT::f32)
4912 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4913 FI = FINode->getIndex();
4915 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4916 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4917 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4918 Offset = Ptr.getConstantOperandVal(1);
4919 Ptr = Ptr.getOperand(0);
4924 // FIXME: 256-bit vector instructions don't require a strict alignment,
4925 // improve this code to support it better.
4926 unsigned RequiredAlign = VT.getSizeInBits()/8;
4927 SDValue Chain = LD->getChain();
4928 // Make sure the stack object alignment is at least 16 or 32.
4929 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4930 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4931 if (MFI->isFixedObjectIndex(FI)) {
4932 // Can't change the alignment. FIXME: It's possible to compute
4933 // the exact stack offset and reference FI + adjust offset instead.
4934 // If someone *really* cares about this. That's the way to implement it.
4937 MFI->setObjectAlignment(FI, RequiredAlign);
4941 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4942 // Ptr + (Offset & ~15).
4945 if ((Offset % RequiredAlign) & 3)
4947 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4949 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4950 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4952 int EltNo = (Offset - StartOffset) >> 2;
4953 int NumElems = VT.getVectorNumElements();
4955 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4956 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4957 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4958 LD->getPointerInfo().getWithOffset(StartOffset),
4961 // Canonicalize it to a v4i32 or v8i32 shuffle.
4962 SmallVector<int, 8> Mask;
4963 for (int i = 0; i < NumElems; ++i)
4964 Mask.push_back(EltNo);
4966 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4967 return DAG.getNode(ISD::BITCAST, dl, NVT,
4968 DAG.getVectorShuffle(CanonVT, dl, V1,
4969 DAG.getUNDEF(CanonVT),&Mask[0]));
4975 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4976 /// vector of type 'VT', see if the elements can be replaced by a single large
4977 /// load which has the same value as a build_vector whose operands are 'elts'.
4979 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4981 /// FIXME: we'd also like to handle the case where the last elements are zero
4982 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4983 /// There's even a handy isZeroNode for that purpose.
4984 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4985 DebugLoc &DL, SelectionDAG &DAG) {
4986 EVT EltVT = VT.getVectorElementType();
4987 unsigned NumElems = Elts.size();
4989 LoadSDNode *LDBase = NULL;
4990 unsigned LastLoadedElt = -1U;
4992 // For each element in the initializer, see if we've found a load or an undef.
4993 // If we don't find an initial load element, or later load elements are
4994 // non-consecutive, bail out.
4995 for (unsigned i = 0; i < NumElems; ++i) {
4996 SDValue Elt = Elts[i];
4998 if (!Elt.getNode() ||
4999 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5002 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5004 LDBase = cast<LoadSDNode>(Elt.getNode());
5008 if (Elt.getOpcode() == ISD::UNDEF)
5011 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5012 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5017 // If we have found an entire vector of loads and undefs, then return a large
5018 // load of the entire vector width starting at the base pointer. If we found
5019 // consecutive loads for the low half, generate a vzext_load node.
5020 if (LastLoadedElt == NumElems - 1) {
5021 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5022 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5023 LDBase->getPointerInfo(),
5024 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
5025 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5026 LDBase->getPointerInfo(),
5027 LDBase->isVolatile(), LDBase->isNonTemporal(),
5028 LDBase->getAlignment());
5029 } else if (NumElems == 4 && LastLoadedElt == 1 &&
5030 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5031 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5032 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5034 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5035 LDBase->getPointerInfo(),
5036 LDBase->getAlignment(),
5037 false/*isVolatile*/, true/*ReadMem*/,
5039 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5045 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5046 DebugLoc dl = Op.getDebugLoc();
5048 EVT VT = Op.getValueType();
5049 EVT ExtVT = VT.getVectorElementType();
5050 unsigned NumElems = Op.getNumOperands();
5052 // Vectors containing all zeros can be matched by pxor and xorps later
5053 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5054 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5055 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5056 if (Op.getValueType() == MVT::v4i32 ||
5057 Op.getValueType() == MVT::v8i32)
5060 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl);
5063 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5064 // vectors or broken into v4i32 operations on 256-bit vectors.
5065 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5066 if (Op.getValueType() == MVT::v4i32)
5069 return getOnesVector(Op.getValueType(), DAG, dl);
5072 unsigned EVTBits = ExtVT.getSizeInBits();
5074 unsigned NumZero = 0;
5075 unsigned NumNonZero = 0;
5076 unsigned NonZeros = 0;
5077 bool IsAllConstants = true;
5078 SmallSet<SDValue, 8> Values;
5079 for (unsigned i = 0; i < NumElems; ++i) {
5080 SDValue Elt = Op.getOperand(i);
5081 if (Elt.getOpcode() == ISD::UNDEF)
5084 if (Elt.getOpcode() != ISD::Constant &&
5085 Elt.getOpcode() != ISD::ConstantFP)
5086 IsAllConstants = false;
5087 if (X86::isZeroNode(Elt))
5090 NonZeros |= (1 << i);
5095 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5096 if (NumNonZero == 0)
5097 return DAG.getUNDEF(VT);
5099 // Special case for single non-zero, non-undef, element.
5100 if (NumNonZero == 1) {
5101 unsigned Idx = CountTrailingZeros_32(NonZeros);
5102 SDValue Item = Op.getOperand(Idx);
5104 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5105 // the value are obviously zero, truncate the value to i32 and do the
5106 // insertion that way. Only do this if the value is non-constant or if the
5107 // value is a constant being inserted into element 0. It is cheaper to do
5108 // a constant pool load than it is to do a movd + shuffle.
5109 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5110 (!IsAllConstants || Idx == 0)) {
5111 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5113 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5114 EVT VecVT = MVT::v4i32;
5115 unsigned VecElts = 4;
5117 // Truncate the value (which may itself be a constant) to i32, and
5118 // convert it to a vector with movd (S2V+shuffle to zero extend).
5119 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5120 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5121 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5122 Subtarget->hasXMMInt(), DAG);
5124 // Now we have our 32-bit value zero extended in the low element of
5125 // a vector. If Idx != 0, swizzle it into place.
5127 SmallVector<int, 4> Mask;
5128 Mask.push_back(Idx);
5129 for (unsigned i = 1; i != VecElts; ++i)
5131 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5132 DAG.getUNDEF(Item.getValueType()),
5135 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5139 // If we have a constant or non-constant insertion into the low element of
5140 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5141 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5142 // depending on what the source datatype is.
5145 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5146 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5147 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5148 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5149 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5150 return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(),
5152 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5153 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5154 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5155 EVT MiddleVT = MVT::v4i32;
5156 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5157 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5158 Subtarget->hasXMMInt(), DAG);
5159 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5163 // Is it a vector logical left shift?
5164 if (NumElems == 2 && Idx == 1 &&
5165 X86::isZeroNode(Op.getOperand(0)) &&
5166 !X86::isZeroNode(Op.getOperand(1))) {
5167 unsigned NumBits = VT.getSizeInBits();
5168 return getVShift(true, VT,
5169 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5170 VT, Op.getOperand(1)),
5171 NumBits/2, DAG, *this, dl);
5174 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5177 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5178 // is a non-constant being inserted into an element other than the low one,
5179 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5180 // movd/movss) to move this into the low element, then shuffle it into
5182 if (EVTBits == 32) {
5183 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5185 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5186 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5187 Subtarget->hasXMMInt(), DAG);
5188 SmallVector<int, 8> MaskVec;
5189 for (unsigned i = 0; i < NumElems; i++)
5190 MaskVec.push_back(i == Idx ? 0 : 1);
5191 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5195 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5196 if (Values.size() == 1) {
5197 if (EVTBits == 32) {
5198 // Instead of a shuffle like this:
5199 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5200 // Check if it's possible to issue this instead.
5201 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5202 unsigned Idx = CountTrailingZeros_32(NonZeros);
5203 SDValue Item = Op.getOperand(Idx);
5204 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5205 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5210 // A vector full of immediates; various special cases are already
5211 // handled, so this is best done with a single constant-pool load.
5215 // For AVX-length vectors, build the individual 128-bit pieces and use
5216 // shuffles to put them in place.
5217 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5218 SmallVector<SDValue, 32> V;
5219 for (unsigned i = 0; i < NumElems; ++i)
5220 V.push_back(Op.getOperand(i));
5222 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5224 // Build both the lower and upper subvector.
5225 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5226 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5229 // Recreate the wider vector with the lower and upper part.
5230 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5231 DAG.getConstant(0, MVT::i32), DAG, dl);
5232 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5236 // Let legalizer expand 2-wide build_vectors.
5237 if (EVTBits == 64) {
5238 if (NumNonZero == 1) {
5239 // One half is zero or undef.
5240 unsigned Idx = CountTrailingZeros_32(NonZeros);
5241 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5242 Op.getOperand(Idx));
5243 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5244 Subtarget->hasXMMInt(), DAG);
5249 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5250 if (EVTBits == 8 && NumElems == 16) {
5251 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5253 if (V.getNode()) return V;
5256 if (EVTBits == 16 && NumElems == 8) {
5257 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5259 if (V.getNode()) return V;
5262 // If element VT is == 32 bits, turn it into a number of shuffles.
5263 SmallVector<SDValue, 8> V;
5265 if (NumElems == 4 && NumZero > 0) {
5266 for (unsigned i = 0; i < 4; ++i) {
5267 bool isZero = !(NonZeros & (1 << i));
5269 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
5271 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5274 for (unsigned i = 0; i < 2; ++i) {
5275 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5278 V[i] = V[i*2]; // Must be a zero vector.
5281 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5284 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5287 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5292 SmallVector<int, 8> MaskVec;
5293 bool Reverse = (NonZeros & 0x3) == 2;
5294 for (unsigned i = 0; i < 2; ++i)
5295 MaskVec.push_back(Reverse ? 1-i : i);
5296 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5297 for (unsigned i = 0; i < 2; ++i)
5298 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5299 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5302 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5303 // Check for a build vector of consecutive loads.
5304 for (unsigned i = 0; i < NumElems; ++i)
5305 V[i] = Op.getOperand(i);
5307 // Check for elements which are consecutive loads.
5308 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5312 // For SSE 4.1, use insertps to put the high elements into the low element.
5313 if (getSubtarget()->hasSSE41() || getSubtarget()->hasAVX()) {
5315 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5316 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5318 Result = DAG.getUNDEF(VT);
5320 for (unsigned i = 1; i < NumElems; ++i) {
5321 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5322 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5323 Op.getOperand(i), DAG.getIntPtrConstant(i));
5328 // Otherwise, expand into a number of unpckl*, start by extending each of
5329 // our (non-undef) elements to the full vector width with the element in the
5330 // bottom slot of the vector (which generates no code for SSE).
5331 for (unsigned i = 0; i < NumElems; ++i) {
5332 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5333 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5335 V[i] = DAG.getUNDEF(VT);
5338 // Next, we iteratively mix elements, e.g. for v4f32:
5339 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5340 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5341 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5342 unsigned EltStride = NumElems >> 1;
5343 while (EltStride != 0) {
5344 for (unsigned i = 0; i < EltStride; ++i) {
5345 // If V[i+EltStride] is undef and this is the first round of mixing,
5346 // then it is safe to just drop this shuffle: V[i] is already in the
5347 // right place, the one element (since it's the first round) being
5348 // inserted as undef can be dropped. This isn't safe for successive
5349 // rounds because they will permute elements within both vectors.
5350 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5351 EltStride == NumElems/2)
5354 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5363 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5364 // them in a MMX register. This is better than doing a stack convert.
5365 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5366 DebugLoc dl = Op.getDebugLoc();
5367 EVT ResVT = Op.getValueType();
5369 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5370 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5372 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5373 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5374 InVec = Op.getOperand(1);
5375 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5376 unsigned NumElts = ResVT.getVectorNumElements();
5377 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5378 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5379 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5381 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5382 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5383 Mask[0] = 0; Mask[1] = 2;
5384 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5386 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5389 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5390 // to create 256-bit vectors from two other 128-bit ones.
5391 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5392 DebugLoc dl = Op.getDebugLoc();
5393 EVT ResVT = Op.getValueType();
5395 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5397 SDValue V1 = Op.getOperand(0);
5398 SDValue V2 = Op.getOperand(1);
5399 unsigned NumElems = ResVT.getVectorNumElements();
5401 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5402 DAG.getConstant(0, MVT::i32), DAG, dl);
5403 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5408 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5409 EVT ResVT = Op.getValueType();
5411 assert(Op.getNumOperands() == 2);
5412 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5413 "Unsupported CONCAT_VECTORS for value type");
5415 // We support concatenate two MMX registers and place them in a MMX register.
5416 // This is better than doing a stack convert.
5417 if (ResVT.is128BitVector())
5418 return LowerMMXCONCAT_VECTORS(Op, DAG);
5420 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5421 // from two other 128-bit ones.
5422 return LowerAVXCONCAT_VECTORS(Op, DAG);
5425 // v8i16 shuffles - Prefer shuffles in the following order:
5426 // 1. [all] pshuflw, pshufhw, optional move
5427 // 2. [ssse3] 1 x pshufb
5428 // 3. [ssse3] 2 x pshufb + 1 x por
5429 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5431 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5432 SelectionDAG &DAG) const {
5433 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5434 SDValue V1 = SVOp->getOperand(0);
5435 SDValue V2 = SVOp->getOperand(1);
5436 DebugLoc dl = SVOp->getDebugLoc();
5437 SmallVector<int, 8> MaskVals;
5439 // Determine if more than 1 of the words in each of the low and high quadwords
5440 // of the result come from the same quadword of one of the two inputs. Undef
5441 // mask values count as coming from any quadword, for better codegen.
5442 SmallVector<unsigned, 4> LoQuad(4);
5443 SmallVector<unsigned, 4> HiQuad(4);
5444 BitVector InputQuads(4);
5445 for (unsigned i = 0; i < 8; ++i) {
5446 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5447 int EltIdx = SVOp->getMaskElt(i);
5448 MaskVals.push_back(EltIdx);
5457 InputQuads.set(EltIdx / 4);
5460 int BestLoQuad = -1;
5461 unsigned MaxQuad = 1;
5462 for (unsigned i = 0; i < 4; ++i) {
5463 if (LoQuad[i] > MaxQuad) {
5465 MaxQuad = LoQuad[i];
5469 int BestHiQuad = -1;
5471 for (unsigned i = 0; i < 4; ++i) {
5472 if (HiQuad[i] > MaxQuad) {
5474 MaxQuad = HiQuad[i];
5478 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5479 // of the two input vectors, shuffle them into one input vector so only a
5480 // single pshufb instruction is necessary. If There are more than 2 input
5481 // quads, disable the next transformation since it does not help SSSE3.
5482 bool V1Used = InputQuads[0] || InputQuads[1];
5483 bool V2Used = InputQuads[2] || InputQuads[3];
5484 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) {
5485 if (InputQuads.count() == 2 && V1Used && V2Used) {
5486 BestLoQuad = InputQuads.find_first();
5487 BestHiQuad = InputQuads.find_next(BestLoQuad);
5489 if (InputQuads.count() > 2) {
5495 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5496 // the shuffle mask. If a quad is scored as -1, that means that it contains
5497 // words from all 4 input quadwords.
5499 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5500 SmallVector<int, 8> MaskV;
5501 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5502 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5503 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5504 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5505 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5506 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5508 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5509 // source words for the shuffle, to aid later transformations.
5510 bool AllWordsInNewV = true;
5511 bool InOrder[2] = { true, true };
5512 for (unsigned i = 0; i != 8; ++i) {
5513 int idx = MaskVals[i];
5515 InOrder[i/4] = false;
5516 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5518 AllWordsInNewV = false;
5522 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5523 if (AllWordsInNewV) {
5524 for (int i = 0; i != 8; ++i) {
5525 int idx = MaskVals[i];
5528 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5529 if ((idx != i) && idx < 4)
5531 if ((idx != i) && idx > 3)
5540 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5541 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5542 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5543 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5544 unsigned TargetMask = 0;
5545 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5546 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5547 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5548 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5549 V1 = NewV.getOperand(0);
5550 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5554 // If we have SSSE3, and all words of the result are from 1 input vector,
5555 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5556 // is present, fall back to case 4.
5557 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) {
5558 SmallVector<SDValue,16> pshufbMask;
5560 // If we have elements from both input vectors, set the high bit of the
5561 // shuffle mask element to zero out elements that come from V2 in the V1
5562 // mask, and elements that come from V1 in the V2 mask, so that the two
5563 // results can be OR'd together.
5564 bool TwoInputs = V1Used && V2Used;
5565 for (unsigned i = 0; i != 8; ++i) {
5566 int EltIdx = MaskVals[i] * 2;
5567 if (TwoInputs && (EltIdx >= 16)) {
5568 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5569 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5572 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5573 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5575 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5576 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5577 DAG.getNode(ISD::BUILD_VECTOR, dl,
5578 MVT::v16i8, &pshufbMask[0], 16));
5580 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5582 // Calculate the shuffle mask for the second input, shuffle it, and
5583 // OR it with the first shuffled input.
5585 for (unsigned i = 0; i != 8; ++i) {
5586 int EltIdx = MaskVals[i] * 2;
5588 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5589 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5592 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5593 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5595 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5596 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5597 DAG.getNode(ISD::BUILD_VECTOR, dl,
5598 MVT::v16i8, &pshufbMask[0], 16));
5599 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5600 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5603 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5604 // and update MaskVals with new element order.
5605 BitVector InOrder(8);
5606 if (BestLoQuad >= 0) {
5607 SmallVector<int, 8> MaskV;
5608 for (int i = 0; i != 4; ++i) {
5609 int idx = MaskVals[i];
5611 MaskV.push_back(-1);
5613 } else if ((idx / 4) == BestLoQuad) {
5614 MaskV.push_back(idx & 3);
5617 MaskV.push_back(-1);
5620 for (unsigned i = 4; i != 8; ++i)
5622 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5625 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE &&
5626 (Subtarget->hasSSSE3() || Subtarget->hasAVX()))
5627 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5629 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5633 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5634 // and update MaskVals with the new element order.
5635 if (BestHiQuad >= 0) {
5636 SmallVector<int, 8> MaskV;
5637 for (unsigned i = 0; i != 4; ++i)
5639 for (unsigned i = 4; i != 8; ++i) {
5640 int idx = MaskVals[i];
5642 MaskV.push_back(-1);
5644 } else if ((idx / 4) == BestHiQuad) {
5645 MaskV.push_back((idx & 3) + 4);
5648 MaskV.push_back(-1);
5651 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5654 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE &&
5655 (Subtarget->hasSSSE3() || Subtarget->hasAVX()))
5656 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5658 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5662 // In case BestHi & BestLo were both -1, which means each quadword has a word
5663 // from each of the four input quadwords, calculate the InOrder bitvector now
5664 // before falling through to the insert/extract cleanup.
5665 if (BestLoQuad == -1 && BestHiQuad == -1) {
5667 for (int i = 0; i != 8; ++i)
5668 if (MaskVals[i] < 0 || MaskVals[i] == i)
5672 // The other elements are put in the right place using pextrw and pinsrw.
5673 for (unsigned i = 0; i != 8; ++i) {
5676 int EltIdx = MaskVals[i];
5679 SDValue ExtOp = (EltIdx < 8)
5680 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5681 DAG.getIntPtrConstant(EltIdx))
5682 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5683 DAG.getIntPtrConstant(EltIdx - 8));
5684 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5685 DAG.getIntPtrConstant(i));
5690 // v16i8 shuffles - Prefer shuffles in the following order:
5691 // 1. [ssse3] 1 x pshufb
5692 // 2. [ssse3] 2 x pshufb + 1 x por
5693 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5695 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5697 const X86TargetLowering &TLI) {
5698 SDValue V1 = SVOp->getOperand(0);
5699 SDValue V2 = SVOp->getOperand(1);
5700 DebugLoc dl = SVOp->getDebugLoc();
5701 SmallVector<int, 16> MaskVals;
5702 SVOp->getMask(MaskVals);
5704 // If we have SSSE3, case 1 is generated when all result bytes come from
5705 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5706 // present, fall back to case 3.
5707 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5710 for (unsigned i = 0; i < 16; ++i) {
5711 int EltIdx = MaskVals[i];
5720 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5721 if (TLI.getSubtarget()->hasSSSE3() || TLI.getSubtarget()->hasAVX()) {
5722 SmallVector<SDValue,16> pshufbMask;
5724 // If all result elements are from one input vector, then only translate
5725 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5727 // Otherwise, we have elements from both input vectors, and must zero out
5728 // elements that come from V2 in the first mask, and V1 in the second mask
5729 // so that we can OR them together.
5730 bool TwoInputs = !(V1Only || V2Only);
5731 for (unsigned i = 0; i != 16; ++i) {
5732 int EltIdx = MaskVals[i];
5733 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5734 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5737 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5739 // If all the elements are from V2, assign it to V1 and return after
5740 // building the first pshufb.
5743 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5744 DAG.getNode(ISD::BUILD_VECTOR, dl,
5745 MVT::v16i8, &pshufbMask[0], 16));
5749 // Calculate the shuffle mask for the second input, shuffle it, and
5750 // OR it with the first shuffled input.
5752 for (unsigned i = 0; i != 16; ++i) {
5753 int EltIdx = MaskVals[i];
5755 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5758 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5760 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5761 DAG.getNode(ISD::BUILD_VECTOR, dl,
5762 MVT::v16i8, &pshufbMask[0], 16));
5763 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5766 // No SSSE3 - Calculate in place words and then fix all out of place words
5767 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5768 // the 16 different words that comprise the two doublequadword input vectors.
5769 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5770 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5771 SDValue NewV = V2Only ? V2 : V1;
5772 for (int i = 0; i != 8; ++i) {
5773 int Elt0 = MaskVals[i*2];
5774 int Elt1 = MaskVals[i*2+1];
5776 // This word of the result is all undef, skip it.
5777 if (Elt0 < 0 && Elt1 < 0)
5780 // This word of the result is already in the correct place, skip it.
5781 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5783 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5786 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5787 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5790 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5791 // using a single extract together, load it and store it.
5792 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5793 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5794 DAG.getIntPtrConstant(Elt1 / 2));
5795 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5796 DAG.getIntPtrConstant(i));
5800 // If Elt1 is defined, extract it from the appropriate source. If the
5801 // source byte is not also odd, shift the extracted word left 8 bits
5802 // otherwise clear the bottom 8 bits if we need to do an or.
5804 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5805 DAG.getIntPtrConstant(Elt1 / 2));
5806 if ((Elt1 & 1) == 0)
5807 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5809 TLI.getShiftAmountTy(InsElt.getValueType())));
5811 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5812 DAG.getConstant(0xFF00, MVT::i16));
5814 // If Elt0 is defined, extract it from the appropriate source. If the
5815 // source byte is not also even, shift the extracted word right 8 bits. If
5816 // Elt1 was also defined, OR the extracted values together before
5817 // inserting them in the result.
5819 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5820 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5821 if ((Elt0 & 1) != 0)
5822 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5824 TLI.getShiftAmountTy(InsElt0.getValueType())));
5826 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5827 DAG.getConstant(0x00FF, MVT::i16));
5828 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5831 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5832 DAG.getIntPtrConstant(i));
5834 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5837 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5838 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5839 /// done when every pair / quad of shuffle mask elements point to elements in
5840 /// the right sequence. e.g.
5841 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5843 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5844 SelectionDAG &DAG, DebugLoc dl) {
5845 EVT VT = SVOp->getValueType(0);
5846 SDValue V1 = SVOp->getOperand(0);
5847 SDValue V2 = SVOp->getOperand(1);
5848 unsigned NumElems = VT.getVectorNumElements();
5849 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5851 switch (VT.getSimpleVT().SimpleTy) {
5852 default: assert(false && "Unexpected!");
5853 case MVT::v4f32: NewVT = MVT::v2f64; break;
5854 case MVT::v4i32: NewVT = MVT::v2i64; break;
5855 case MVT::v8i16: NewVT = MVT::v4i32; break;
5856 case MVT::v16i8: NewVT = MVT::v4i32; break;
5859 int Scale = NumElems / NewWidth;
5860 SmallVector<int, 8> MaskVec;
5861 for (unsigned i = 0; i < NumElems; i += Scale) {
5863 for (int j = 0; j < Scale; ++j) {
5864 int EltIdx = SVOp->getMaskElt(i+j);
5868 StartIdx = EltIdx - (EltIdx % Scale);
5869 if (EltIdx != StartIdx + j)
5873 MaskVec.push_back(-1);
5875 MaskVec.push_back(StartIdx / Scale);
5878 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5879 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5880 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5883 /// getVZextMovL - Return a zero-extending vector move low node.
5885 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5886 SDValue SrcOp, SelectionDAG &DAG,
5887 const X86Subtarget *Subtarget, DebugLoc dl) {
5888 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5889 LoadSDNode *LD = NULL;
5890 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5891 LD = dyn_cast<LoadSDNode>(SrcOp);
5893 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5895 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5896 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5897 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5898 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5899 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5901 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5902 return DAG.getNode(ISD::BITCAST, dl, VT,
5903 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5904 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5912 return DAG.getNode(ISD::BITCAST, dl, VT,
5913 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5914 DAG.getNode(ISD::BITCAST, dl,
5918 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5919 /// shuffle node referes to only one lane in the sources.
5920 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5921 EVT VT = SVOp->getValueType(0);
5922 int NumElems = VT.getVectorNumElements();
5923 int HalfSize = NumElems/2;
5924 SmallVector<int, 16> M;
5926 bool MatchA = false, MatchB = false;
5928 for (int l = 0; l < NumElems*2; l += HalfSize) {
5929 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5935 for (int l = 0; l < NumElems*2; l += HalfSize) {
5936 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5942 return MatchA && MatchB;
5945 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5946 /// which could not be matched by any known target speficic shuffle
5948 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5949 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5950 // If each half of a vector shuffle node referes to only one lane in the
5951 // source vectors, extract each used 128-bit lane and shuffle them using
5952 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5953 // the work to the legalizer.
5954 DebugLoc dl = SVOp->getDebugLoc();
5955 EVT VT = SVOp->getValueType(0);
5956 int NumElems = VT.getVectorNumElements();
5957 int HalfSize = NumElems/2;
5959 // Extract the reference for each half
5960 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5961 int FstVecOpNum = 0, SndVecOpNum = 0;
5962 for (int i = 0; i < HalfSize; ++i) {
5963 int Elt = SVOp->getMaskElt(i);
5964 if (SVOp->getMaskElt(i) < 0)
5966 FstVecOpNum = Elt/NumElems;
5967 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5970 for (int i = HalfSize; i < NumElems; ++i) {
5971 int Elt = SVOp->getMaskElt(i);
5972 if (SVOp->getMaskElt(i) < 0)
5974 SndVecOpNum = Elt/NumElems;
5975 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5979 // Extract the subvectors
5980 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5981 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5982 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5983 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5985 // Generate 128-bit shuffles
5986 SmallVector<int, 16> MaskV1, MaskV2;
5987 for (int i = 0; i < HalfSize; ++i) {
5988 int Elt = SVOp->getMaskElt(i);
5989 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5991 for (int i = HalfSize; i < NumElems; ++i) {
5992 int Elt = SVOp->getMaskElt(i);
5993 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5996 EVT NVT = V1.getValueType();
5997 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5998 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
6000 // Concatenate the result back
6001 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
6002 DAG.getConstant(0, MVT::i32), DAG, dl);
6003 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
6010 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6011 /// 4 elements, and match them with several different shuffle types.
6013 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6014 SDValue V1 = SVOp->getOperand(0);
6015 SDValue V2 = SVOp->getOperand(1);
6016 DebugLoc dl = SVOp->getDebugLoc();
6017 EVT VT = SVOp->getValueType(0);
6019 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6021 SmallVector<std::pair<int, int>, 8> Locs;
6023 SmallVector<int, 8> Mask1(4U, -1);
6024 SmallVector<int, 8> PermMask;
6025 SVOp->getMask(PermMask);
6029 for (unsigned i = 0; i != 4; ++i) {
6030 int Idx = PermMask[i];
6032 Locs[i] = std::make_pair(-1, -1);
6034 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6036 Locs[i] = std::make_pair(0, NumLo);
6040 Locs[i] = std::make_pair(1, NumHi);
6042 Mask1[2+NumHi] = Idx;
6048 if (NumLo <= 2 && NumHi <= 2) {
6049 // If no more than two elements come from either vector. This can be
6050 // implemented with two shuffles. First shuffle gather the elements.
6051 // The second shuffle, which takes the first shuffle as both of its
6052 // vector operands, put the elements into the right order.
6053 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6055 SmallVector<int, 8> Mask2(4U, -1);
6057 for (unsigned i = 0; i != 4; ++i) {
6058 if (Locs[i].first == -1)
6061 unsigned Idx = (i < 2) ? 0 : 4;
6062 Idx += Locs[i].first * 2 + Locs[i].second;
6067 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6068 } else if (NumLo == 3 || NumHi == 3) {
6069 // Otherwise, we must have three elements from one vector, call it X, and
6070 // one element from the other, call it Y. First, use a shufps to build an
6071 // intermediate vector with the one element from Y and the element from X
6072 // that will be in the same half in the final destination (the indexes don't
6073 // matter). Then, use a shufps to build the final vector, taking the half
6074 // containing the element from Y from the intermediate, and the other half
6077 // Normalize it so the 3 elements come from V1.
6078 CommuteVectorShuffleMask(PermMask, VT);
6082 // Find the element from V2.
6084 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6085 int Val = PermMask[HiIndex];
6092 Mask1[0] = PermMask[HiIndex];
6094 Mask1[2] = PermMask[HiIndex^1];
6096 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6099 Mask1[0] = PermMask[0];
6100 Mask1[1] = PermMask[1];
6101 Mask1[2] = HiIndex & 1 ? 6 : 4;
6102 Mask1[3] = HiIndex & 1 ? 4 : 6;
6103 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6105 Mask1[0] = HiIndex & 1 ? 2 : 0;
6106 Mask1[1] = HiIndex & 1 ? 0 : 2;
6107 Mask1[2] = PermMask[2];
6108 Mask1[3] = PermMask[3];
6113 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6117 // Break it into (shuffle shuffle_hi, shuffle_lo).
6120 SmallVector<int,8> LoMask(4U, -1);
6121 SmallVector<int,8> HiMask(4U, -1);
6123 SmallVector<int,8> *MaskPtr = &LoMask;
6124 unsigned MaskIdx = 0;
6127 for (unsigned i = 0; i != 4; ++i) {
6134 int Idx = PermMask[i];
6136 Locs[i] = std::make_pair(-1, -1);
6137 } else if (Idx < 4) {
6138 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6139 (*MaskPtr)[LoIdx] = Idx;
6142 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6143 (*MaskPtr)[HiIdx] = Idx;
6148 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6149 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6150 SmallVector<int, 8> MaskOps;
6151 for (unsigned i = 0; i != 4; ++i) {
6152 if (Locs[i].first == -1) {
6153 MaskOps.push_back(-1);
6155 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6156 MaskOps.push_back(Idx);
6159 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6162 static bool MayFoldVectorLoad(SDValue V) {
6163 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6164 V = V.getOperand(0);
6165 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6166 V = V.getOperand(0);
6172 // FIXME: the version above should always be used. Since there's
6173 // a bug where several vector shuffles can't be folded because the
6174 // DAG is not updated during lowering and a node claims to have two
6175 // uses while it only has one, use this version, and let isel match
6176 // another instruction if the load really happens to have more than
6177 // one use. Remove this version after this bug get fixed.
6178 // rdar://8434668, PR8156
6179 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6180 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6181 V = V.getOperand(0);
6182 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6183 V = V.getOperand(0);
6184 if (ISD::isNormalLoad(V.getNode()))
6189 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6190 /// a vector extract, and if both can be later optimized into a single load.
6191 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6192 /// here because otherwise a target specific shuffle node is going to be
6193 /// emitted for this shuffle, and the optimization not done.
6194 /// FIXME: This is probably not the best approach, but fix the problem
6195 /// until the right path is decided.
6197 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6198 const TargetLowering &TLI) {
6199 EVT VT = V.getValueType();
6200 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6202 // Be sure that the vector shuffle is present in a pattern like this:
6203 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6207 SDNode *N = *V.getNode()->use_begin();
6208 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6211 SDValue EltNo = N->getOperand(1);
6212 if (!isa<ConstantSDNode>(EltNo))
6215 // If the bit convert changed the number of elements, it is unsafe
6216 // to examine the mask.
6217 bool HasShuffleIntoBitcast = false;
6218 if (V.getOpcode() == ISD::BITCAST) {
6219 EVT SrcVT = V.getOperand(0).getValueType();
6220 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6222 V = V.getOperand(0);
6223 HasShuffleIntoBitcast = true;
6226 // Select the input vector, guarding against out of range extract vector.
6227 unsigned NumElems = VT.getVectorNumElements();
6228 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6229 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6230 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6232 // Skip one more bit_convert if necessary
6233 if (V.getOpcode() == ISD::BITCAST)
6234 V = V.getOperand(0);
6236 if (ISD::isNormalLoad(V.getNode())) {
6237 // Is the original load suitable?
6238 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6240 // FIXME: avoid the multi-use bug that is preventing lots of
6241 // of foldings to be detected, this is still wrong of course, but
6242 // give the temporary desired behavior, and if it happens that
6243 // the load has real more uses, during isel it will not fold, and
6244 // will generate poor code.
6245 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6248 if (!HasShuffleIntoBitcast)
6251 // If there's a bitcast before the shuffle, check if the load type and
6252 // alignment is valid.
6253 unsigned Align = LN0->getAlignment();
6255 TLI.getTargetData()->getABITypeAlignment(
6256 VT.getTypeForEVT(*DAG.getContext()));
6258 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6266 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6267 EVT VT = Op.getValueType();
6269 // Canonizalize to v2f64.
6270 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6271 return DAG.getNode(ISD::BITCAST, dl, VT,
6272 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6277 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6279 SDValue V1 = Op.getOperand(0);
6280 SDValue V2 = Op.getOperand(1);
6281 EVT VT = Op.getValueType();
6283 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6285 if (HasXMMInt && VT == MVT::v2f64)
6286 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6288 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6289 return DAG.getNode(ISD::BITCAST, dl, VT,
6290 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6291 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6292 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6296 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6297 SDValue V1 = Op.getOperand(0);
6298 SDValue V2 = Op.getOperand(1);
6299 EVT VT = Op.getValueType();
6301 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6302 "unsupported shuffle type");
6304 if (V2.getOpcode() == ISD::UNDEF)
6308 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6311 static inline unsigned getSHUFPOpcode(EVT VT) {
6312 switch(VT.getSimpleVT().SimpleTy) {
6313 case MVT::v8i32: // Use fp unit for int unpack.
6315 case MVT::v4i32: // Use fp unit for int unpack.
6316 case MVT::v4f32: return X86ISD::SHUFPS;
6317 case MVT::v4i64: // Use fp unit for int unpack.
6319 case MVT::v2i64: // Use fp unit for int unpack.
6320 case MVT::v2f64: return X86ISD::SHUFPD;
6322 llvm_unreachable("Unknown type for shufp*");
6328 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) {
6329 SDValue V1 = Op.getOperand(0);
6330 SDValue V2 = Op.getOperand(1);
6331 EVT VT = Op.getValueType();
6332 unsigned NumElems = VT.getVectorNumElements();
6334 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6335 // operand of these instructions is only memory, so check if there's a
6336 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6338 bool CanFoldLoad = false;
6340 // Trivial case, when V2 comes from a load.
6341 if (MayFoldVectorLoad(V2))
6344 // When V1 is a load, it can be folded later into a store in isel, example:
6345 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6347 // (MOVLPSmr addr:$src1, VR128:$src2)
6348 // So, recognize this potential and also use MOVLPS or MOVLPD
6349 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6352 // Both of them can't be memory operations though.
6353 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6354 CanFoldLoad = false;
6357 if (HasXMMInt && NumElems == 2)
6358 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6361 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6365 // movl and movlp will both match v2i64, but v2i64 is never matched by
6366 // movl earlier because we make it strict to avoid messing with the movlp load
6367 // folding logic (see the code above getMOVLP call). Match it here then,
6368 // this is horrible, but will stay like this until we move all shuffle
6369 // matching to x86 specific nodes. Note that for the 1st condition all
6370 // types are matched with movsd.
6372 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6373 // as to remove this logic from here, as much as possible
6374 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6375 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6376 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6379 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6381 // Invert the operand order and use SHUFPS to match it.
6382 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6383 X86::getShuffleSHUFImmediate(SVOp), DAG);
6386 static inline unsigned getUNPCKLOpcode(EVT VT) {
6387 switch(VT.getSimpleVT().SimpleTy) {
6388 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6389 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6390 case MVT::v4f32: return X86ISD::UNPCKLPS;
6391 case MVT::v2f64: return X86ISD::UNPCKLPD;
6392 case MVT::v8i32: // Use fp unit for int unpack.
6393 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6394 case MVT::v4i64: // Use fp unit for int unpack.
6395 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6396 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6397 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6399 llvm_unreachable("Unknown type for unpckl");
6404 static inline unsigned getUNPCKHOpcode(EVT VT) {
6405 switch(VT.getSimpleVT().SimpleTy) {
6406 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6407 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6408 case MVT::v4f32: return X86ISD::UNPCKHPS;
6409 case MVT::v2f64: return X86ISD::UNPCKHPD;
6410 case MVT::v8i32: // Use fp unit for int unpack.
6411 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6412 case MVT::v4i64: // Use fp unit for int unpack.
6413 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6414 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6415 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6417 llvm_unreachable("Unknown type for unpckh");
6422 static inline unsigned getVPERMILOpcode(EVT VT) {
6423 switch(VT.getSimpleVT().SimpleTy) {
6425 case MVT::v4f32: return X86ISD::VPERMILPS;
6427 case MVT::v2f64: return X86ISD::VPERMILPD;
6429 case MVT::v8f32: return X86ISD::VPERMILPSY;
6431 case MVT::v4f64: return X86ISD::VPERMILPDY;
6433 llvm_unreachable("Unknown type for vpermil");
6438 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6439 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6440 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6441 static bool isVectorBroadcast(SDValue &Op) {
6442 EVT VT = Op.getValueType();
6443 bool Is256 = VT.getSizeInBits() == 256;
6445 assert((VT.getSizeInBits() == 128 || Is256) &&
6446 "Unsupported type for vbroadcast node");
6449 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6450 V = V.getOperand(0);
6452 if (Is256 && !(V.hasOneUse() &&
6453 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6454 V.getOperand(0).getOpcode() == ISD::UNDEF))
6458 V = V.getOperand(1);
6463 // Check the source scalar_to_vector type. 256-bit broadcasts are
6464 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6465 // for 32-bit scalars.
6466 if (V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6469 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6470 if (ScalarSize != 32 && ScalarSize != 64)
6472 if (!Is256 && ScalarSize == 64)
6475 V = V.getOperand(0);
6476 if (!MayFoldLoad(V))
6479 // Return the load node
6485 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6486 const TargetLowering &TLI,
6487 const X86Subtarget *Subtarget) {
6488 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6489 EVT VT = Op.getValueType();
6490 DebugLoc dl = Op.getDebugLoc();
6491 SDValue V1 = Op.getOperand(0);
6492 SDValue V2 = Op.getOperand(1);
6494 if (isZeroShuffle(SVOp))
6495 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
6497 // Handle splat operations
6498 if (SVOp->isSplat()) {
6499 unsigned NumElem = VT.getVectorNumElements();
6500 int Size = VT.getSizeInBits();
6501 // Special case, this is the only place now where it's allowed to return
6502 // a vector_shuffle operation without using a target specific node, because
6503 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6504 // this be moved to DAGCombine instead?
6505 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6508 // Use vbroadcast whenever the splat comes from a foldable load
6509 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6510 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6512 // Handle splats by matching through known shuffle masks
6513 if ((Size == 128 && NumElem <= 4) ||
6514 (Size == 256 && NumElem < 8))
6517 // All remaning splats are promoted to target supported vector shuffles.
6518 return PromoteSplat(SVOp, DAG);
6521 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6523 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6524 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6525 if (NewOp.getNode())
6526 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6527 } else if ((VT == MVT::v4i32 ||
6528 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) {
6529 // FIXME: Figure out a cleaner way to do this.
6530 // Try to make use of movq to zero out the top part.
6531 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6532 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6533 if (NewOp.getNode()) {
6534 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6535 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6536 DAG, Subtarget, dl);
6538 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6539 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6540 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6541 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6542 DAG, Subtarget, dl);
6549 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6550 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6551 SDValue V1 = Op.getOperand(0);
6552 SDValue V2 = Op.getOperand(1);
6553 EVT VT = Op.getValueType();
6554 DebugLoc dl = Op.getDebugLoc();
6555 unsigned NumElems = VT.getVectorNumElements();
6556 bool isMMX = VT.getSizeInBits() == 64;
6557 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6558 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6559 bool V1IsSplat = false;
6560 bool V2IsSplat = false;
6561 bool HasXMMInt = Subtarget->hasXMMInt();
6562 MachineFunction &MF = DAG.getMachineFunction();
6563 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6565 // Shuffle operations on MMX not supported.
6569 // Vector shuffle lowering takes 3 steps:
6571 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6572 // narrowing and commutation of operands should be handled.
6573 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6575 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6576 // so the shuffle can be broken into other shuffles and the legalizer can
6577 // try the lowering again.
6579 // The general ideia is that no vector_shuffle operation should be left to
6580 // be matched during isel, all of them must be converted to a target specific
6583 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6584 // narrowing and commutation of operands should be handled. The actual code
6585 // doesn't include all of those, work in progress...
6586 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6587 if (NewOp.getNode())
6590 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6591 // unpckh_undef). Only use pshufd if speed is more important than size.
6592 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6593 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6594 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6595 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6597 if (X86::isMOVDDUPMask(SVOp) &&
6598 (Subtarget->hasSSE3() || Subtarget->hasAVX()) &&
6599 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6600 return getMOVDDup(Op, dl, V1, DAG);
6602 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6603 return getMOVHighToLow(Op, dl, DAG);
6605 // Use to match splats
6606 if (HasXMMInt && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6607 (VT == MVT::v2f64 || VT == MVT::v2i64))
6608 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6610 if (X86::isPSHUFDMask(SVOp)) {
6611 // The actual implementation will match the mask in the if above and then
6612 // during isel it can match several different instructions, not only pshufd
6613 // as its name says, sad but true, emulate the behavior for now...
6614 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6615 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6617 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6619 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32))
6620 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6622 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6626 // Check if this can be converted into a logical shift.
6627 bool isLeft = false;
6630 bool isShift = getSubtarget()->hasXMMInt() &&
6631 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6632 if (isShift && ShVal.hasOneUse()) {
6633 // If the shifted value has multiple uses, it may be cheaper to use
6634 // v_set0 + movlhps or movhlps, etc.
6635 EVT EltVT = VT.getVectorElementType();
6636 ShAmt *= EltVT.getSizeInBits();
6637 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6640 if (X86::isMOVLMask(SVOp)) {
6643 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6644 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6645 if (!X86::isMOVLPMask(SVOp)) {
6646 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64))
6647 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6649 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6650 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6654 // FIXME: fold these into legal mask.
6655 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6656 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt);
6658 if (X86::isMOVHLPSMask(SVOp))
6659 return getMOVHighToLow(Op, dl, DAG);
6661 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6662 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6664 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6665 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6667 if (X86::isMOVLPMask(SVOp))
6668 return getMOVLP(Op, dl, DAG, HasXMMInt);
6670 if (ShouldXformToMOVHLPS(SVOp) ||
6671 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6672 return CommuteVectorShuffle(SVOp, DAG);
6675 // No better options. Use a vshl / vsrl.
6676 EVT EltVT = VT.getVectorElementType();
6677 ShAmt *= EltVT.getSizeInBits();
6678 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6681 bool Commuted = false;
6682 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6683 // 1,1,1,1 -> v8i16 though.
6684 V1IsSplat = isSplatVector(V1.getNode());
6685 V2IsSplat = isSplatVector(V2.getNode());
6687 // Canonicalize the splat or undef, if present, to be on the RHS.
6688 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6689 Op = CommuteVectorShuffle(SVOp, DAG);
6690 SVOp = cast<ShuffleVectorSDNode>(Op);
6691 V1 = SVOp->getOperand(0);
6692 V2 = SVOp->getOperand(1);
6693 std::swap(V1IsSplat, V2IsSplat);
6694 std::swap(V1IsUndef, V2IsUndef);
6698 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6699 // Shuffling low element of v1 into undef, just return v1.
6702 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6703 // the instruction selector will not match, so get a canonical MOVL with
6704 // swapped operands to undo the commute.
6705 return getMOVL(DAG, dl, VT, V2, V1);
6708 if (X86::isUNPCKLMask(SVOp))
6709 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6711 if (X86::isUNPCKHMask(SVOp))
6712 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6715 // Normalize mask so all entries that point to V2 points to its first
6716 // element then try to match unpck{h|l} again. If match, return a
6717 // new vector_shuffle with the corrected mask.
6718 SDValue NewMask = NormalizeMask(SVOp, DAG);
6719 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6720 if (NSVOp != SVOp) {
6721 if (X86::isUNPCKLMask(NSVOp, true)) {
6723 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6730 // Commute is back and try unpck* again.
6731 // FIXME: this seems wrong.
6732 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6733 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6735 if (X86::isUNPCKLMask(NewSVOp))
6736 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6738 if (X86::isUNPCKHMask(NewSVOp))
6739 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6742 // Normalize the node to match x86 shuffle ops if needed
6743 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6744 return CommuteVectorShuffle(SVOp, DAG);
6746 // The checks below are all present in isShuffleMaskLegal, but they are
6747 // inlined here right now to enable us to directly emit target specific
6748 // nodes, and remove one by one until they don't return Op anymore.
6749 SmallVector<int, 16> M;
6752 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()))
6753 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6754 X86::getShufflePALIGNRImmediate(SVOp),
6757 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6758 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6759 if (VT == MVT::v2f64)
6760 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6761 if (VT == MVT::v2i64)
6762 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6765 if (isPSHUFHWMask(M, VT))
6766 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6767 X86::getShufflePSHUFHWImmediate(SVOp),
6770 if (isPSHUFLWMask(M, VT))
6771 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6772 X86::getShufflePSHUFLWImmediate(SVOp),
6775 if (isSHUFPMask(M, VT))
6776 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6777 X86::getShuffleSHUFImmediate(SVOp), DAG);
6779 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6780 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6781 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6782 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6784 //===--------------------------------------------------------------------===//
6785 // Generate target specific nodes for 128 or 256-bit shuffles only
6786 // supported in the AVX instruction set.
6789 // Handle VMOVDDUPY permutations
6790 if (isMOVDDUPYMask(SVOp, Subtarget))
6791 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6793 // Handle VPERMILPS* permutations
6794 if (isVPERMILPSMask(M, VT, Subtarget))
6795 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6796 getShuffleVPERMILPSImmediate(SVOp), DAG);
6798 // Handle VPERMILPD* permutations
6799 if (isVPERMILPDMask(M, VT, Subtarget))
6800 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6801 getShuffleVPERMILPDImmediate(SVOp), DAG);
6803 // Handle VPERM2F128 permutations
6804 if (isVPERM2F128Mask(M, VT, Subtarget))
6805 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6806 getShuffleVPERM2F128Immediate(SVOp), DAG);
6808 // Handle VSHUFPSY permutations
6809 if (isVSHUFPSYMask(M, VT, Subtarget))
6810 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6811 getShuffleVSHUFPSYImmediate(SVOp), DAG);
6813 // Handle VSHUFPDY permutations
6814 if (isVSHUFPDYMask(M, VT, Subtarget))
6815 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6816 getShuffleVSHUFPDYImmediate(SVOp), DAG);
6818 //===--------------------------------------------------------------------===//
6819 // Since no target specific shuffle was selected for this generic one,
6820 // lower it into other known shuffles. FIXME: this isn't true yet, but
6821 // this is the plan.
6824 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6825 if (VT == MVT::v8i16) {
6826 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6827 if (NewOp.getNode())
6831 if (VT == MVT::v16i8) {
6832 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6833 if (NewOp.getNode())
6837 // Handle all 128-bit wide vectors with 4 elements, and match them with
6838 // several different shuffle types.
6839 if (NumElems == 4 && VT.getSizeInBits() == 128)
6840 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6842 // Handle general 256-bit shuffles
6843 if (VT.is256BitVector())
6844 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6850 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6851 SelectionDAG &DAG) const {
6852 EVT VT = Op.getValueType();
6853 DebugLoc dl = Op.getDebugLoc();
6855 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6858 if (VT.getSizeInBits() == 8) {
6859 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6860 Op.getOperand(0), Op.getOperand(1));
6861 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6862 DAG.getValueType(VT));
6863 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6864 } else if (VT.getSizeInBits() == 16) {
6865 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6866 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6868 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6869 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6870 DAG.getNode(ISD::BITCAST, dl,
6874 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6875 Op.getOperand(0), Op.getOperand(1));
6876 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6877 DAG.getValueType(VT));
6878 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6879 } else if (VT == MVT::f32) {
6880 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6881 // the result back to FR32 register. It's only worth matching if the
6882 // result has a single use which is a store or a bitcast to i32. And in
6883 // the case of a store, it's not worth it if the index is a constant 0,
6884 // because a MOVSSmr can be used instead, which is smaller and faster.
6885 if (!Op.hasOneUse())
6887 SDNode *User = *Op.getNode()->use_begin();
6888 if ((User->getOpcode() != ISD::STORE ||
6889 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6890 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6891 (User->getOpcode() != ISD::BITCAST ||
6892 User->getValueType(0) != MVT::i32))
6894 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6895 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6898 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6899 } else if (VT == MVT::i32) {
6900 // ExtractPS works with constant index.
6901 if (isa<ConstantSDNode>(Op.getOperand(1)))
6909 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6910 SelectionDAG &DAG) const {
6911 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6914 SDValue Vec = Op.getOperand(0);
6915 EVT VecVT = Vec.getValueType();
6917 // If this is a 256-bit vector result, first extract the 128-bit vector and
6918 // then extract the element from the 128-bit vector.
6919 if (VecVT.getSizeInBits() == 256) {
6920 DebugLoc dl = Op.getNode()->getDebugLoc();
6921 unsigned NumElems = VecVT.getVectorNumElements();
6922 SDValue Idx = Op.getOperand(1);
6923 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6925 // Get the 128-bit vector.
6926 bool Upper = IdxVal >= NumElems/2;
6927 Vec = Extract128BitVector(Vec,
6928 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6930 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6931 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6934 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6936 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6937 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6942 EVT VT = Op.getValueType();
6943 DebugLoc dl = Op.getDebugLoc();
6944 // TODO: handle v16i8.
6945 if (VT.getSizeInBits() == 16) {
6946 SDValue Vec = Op.getOperand(0);
6947 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6949 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6950 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6951 DAG.getNode(ISD::BITCAST, dl,
6954 // Transform it so it match pextrw which produces a 32-bit result.
6955 EVT EltVT = MVT::i32;
6956 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6957 Op.getOperand(0), Op.getOperand(1));
6958 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6959 DAG.getValueType(VT));
6960 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6961 } else if (VT.getSizeInBits() == 32) {
6962 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6966 // SHUFPS the element to the lowest double word, then movss.
6967 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6968 EVT VVT = Op.getOperand(0).getValueType();
6969 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6970 DAG.getUNDEF(VVT), Mask);
6971 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6972 DAG.getIntPtrConstant(0));
6973 } else if (VT.getSizeInBits() == 64) {
6974 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6975 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6976 // to match extract_elt for f64.
6977 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6981 // UNPCKHPD the element to the lowest double word, then movsd.
6982 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6983 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6984 int Mask[2] = { 1, -1 };
6985 EVT VVT = Op.getOperand(0).getValueType();
6986 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6987 DAG.getUNDEF(VVT), Mask);
6988 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6989 DAG.getIntPtrConstant(0));
6996 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6997 SelectionDAG &DAG) const {
6998 EVT VT = Op.getValueType();
6999 EVT EltVT = VT.getVectorElementType();
7000 DebugLoc dl = Op.getDebugLoc();
7002 SDValue N0 = Op.getOperand(0);
7003 SDValue N1 = Op.getOperand(1);
7004 SDValue N2 = Op.getOperand(2);
7006 if (VT.getSizeInBits() == 256)
7009 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7010 isa<ConstantSDNode>(N2)) {
7012 if (VT == MVT::v8i16)
7013 Opc = X86ISD::PINSRW;
7014 else if (VT == MVT::v16i8)
7015 Opc = X86ISD::PINSRB;
7017 Opc = X86ISD::PINSRB;
7019 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7021 if (N1.getValueType() != MVT::i32)
7022 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7023 if (N2.getValueType() != MVT::i32)
7024 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7025 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7026 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7027 // Bits [7:6] of the constant are the source select. This will always be
7028 // zero here. The DAG Combiner may combine an extract_elt index into these
7029 // bits. For example (insert (extract, 3), 2) could be matched by putting
7030 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7031 // Bits [5:4] of the constant are the destination select. This is the
7032 // value of the incoming immediate.
7033 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7034 // combine either bitwise AND or insert of float 0.0 to set these bits.
7035 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7036 // Create this as a scalar to vector..
7037 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7038 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7039 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
7040 // PINSR* works with constant index.
7047 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7048 EVT VT = Op.getValueType();
7049 EVT EltVT = VT.getVectorElementType();
7051 DebugLoc dl = Op.getDebugLoc();
7052 SDValue N0 = Op.getOperand(0);
7053 SDValue N1 = Op.getOperand(1);
7054 SDValue N2 = Op.getOperand(2);
7056 // If this is a 256-bit vector result, first extract the 128-bit vector,
7057 // insert the element into the extracted half and then place it back.
7058 if (VT.getSizeInBits() == 256) {
7059 if (!isa<ConstantSDNode>(N2))
7062 // Get the desired 128-bit vector half.
7063 unsigned NumElems = VT.getVectorNumElements();
7064 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7065 bool Upper = IdxVal >= NumElems/2;
7066 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
7067 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
7069 // Insert the element into the desired half.
7070 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
7071 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
7073 // Insert the changed part back to the 256-bit vector
7074 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
7077 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
7078 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7080 if (EltVT == MVT::i8)
7083 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7084 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7085 // as its second argument.
7086 if (N1.getValueType() != MVT::i32)
7087 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7088 if (N2.getValueType() != MVT::i32)
7089 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7090 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7096 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7097 LLVMContext *Context = DAG.getContext();
7098 DebugLoc dl = Op.getDebugLoc();
7099 EVT OpVT = Op.getValueType();
7101 // If this is a 256-bit vector result, first insert into a 128-bit
7102 // vector and then insert into the 256-bit vector.
7103 if (OpVT.getSizeInBits() > 128) {
7104 // Insert into a 128-bit vector.
7105 EVT VT128 = EVT::getVectorVT(*Context,
7106 OpVT.getVectorElementType(),
7107 OpVT.getVectorNumElements() / 2);
7109 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7111 // Insert the 128-bit vector.
7112 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7113 DAG.getConstant(0, MVT::i32),
7117 if (Op.getValueType() == MVT::v1i64 &&
7118 Op.getOperand(0).getValueType() == MVT::i64)
7119 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7121 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7122 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7123 "Expected an SSE type!");
7124 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7125 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7128 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7129 // a simple subregister reference or explicit instructions to grab
7130 // upper bits of a vector.
7132 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7133 if (Subtarget->hasAVX()) {
7134 DebugLoc dl = Op.getNode()->getDebugLoc();
7135 SDValue Vec = Op.getNode()->getOperand(0);
7136 SDValue Idx = Op.getNode()->getOperand(1);
7138 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7139 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7140 return Extract128BitVector(Vec, Idx, DAG, dl);
7146 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7147 // simple superregister reference or explicit instructions to insert
7148 // the upper bits of a vector.
7150 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7151 if (Subtarget->hasAVX()) {
7152 DebugLoc dl = Op.getNode()->getDebugLoc();
7153 SDValue Vec = Op.getNode()->getOperand(0);
7154 SDValue SubVec = Op.getNode()->getOperand(1);
7155 SDValue Idx = Op.getNode()->getOperand(2);
7157 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7158 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7159 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7165 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7166 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7167 // one of the above mentioned nodes. It has to be wrapped because otherwise
7168 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7169 // be used to form addressing mode. These wrapped nodes will be selected
7172 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7173 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7175 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7177 unsigned char OpFlag = 0;
7178 unsigned WrapperKind = X86ISD::Wrapper;
7179 CodeModel::Model M = getTargetMachine().getCodeModel();
7181 if (Subtarget->isPICStyleRIPRel() &&
7182 (M == CodeModel::Small || M == CodeModel::Kernel))
7183 WrapperKind = X86ISD::WrapperRIP;
7184 else if (Subtarget->isPICStyleGOT())
7185 OpFlag = X86II::MO_GOTOFF;
7186 else if (Subtarget->isPICStyleStubPIC())
7187 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7189 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7191 CP->getOffset(), OpFlag);
7192 DebugLoc DL = CP->getDebugLoc();
7193 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7194 // With PIC, the address is actually $g + Offset.
7196 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7197 DAG.getNode(X86ISD::GlobalBaseReg,
7198 DebugLoc(), getPointerTy()),
7205 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7206 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7208 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7210 unsigned char OpFlag = 0;
7211 unsigned WrapperKind = X86ISD::Wrapper;
7212 CodeModel::Model M = getTargetMachine().getCodeModel();
7214 if (Subtarget->isPICStyleRIPRel() &&
7215 (M == CodeModel::Small || M == CodeModel::Kernel))
7216 WrapperKind = X86ISD::WrapperRIP;
7217 else if (Subtarget->isPICStyleGOT())
7218 OpFlag = X86II::MO_GOTOFF;
7219 else if (Subtarget->isPICStyleStubPIC())
7220 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7222 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7224 DebugLoc DL = JT->getDebugLoc();
7225 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7227 // With PIC, the address is actually $g + Offset.
7229 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7230 DAG.getNode(X86ISD::GlobalBaseReg,
7231 DebugLoc(), getPointerTy()),
7238 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7239 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7241 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7243 unsigned char OpFlag = 0;
7244 unsigned WrapperKind = X86ISD::Wrapper;
7245 CodeModel::Model M = getTargetMachine().getCodeModel();
7247 if (Subtarget->isPICStyleRIPRel() &&
7248 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7249 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7250 OpFlag = X86II::MO_GOTPCREL;
7251 WrapperKind = X86ISD::WrapperRIP;
7252 } else if (Subtarget->isPICStyleGOT()) {
7253 OpFlag = X86II::MO_GOT;
7254 } else if (Subtarget->isPICStyleStubPIC()) {
7255 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7256 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7257 OpFlag = X86II::MO_DARWIN_NONLAZY;
7260 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7262 DebugLoc DL = Op.getDebugLoc();
7263 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7266 // With PIC, the address is actually $g + Offset.
7267 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7268 !Subtarget->is64Bit()) {
7269 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7270 DAG.getNode(X86ISD::GlobalBaseReg,
7271 DebugLoc(), getPointerTy()),
7275 // For symbols that require a load from a stub to get the address, emit the
7277 if (isGlobalStubReference(OpFlag))
7278 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7279 MachinePointerInfo::getGOT(), false, false, 0);
7285 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7286 // Create the TargetBlockAddressAddress node.
7287 unsigned char OpFlags =
7288 Subtarget->ClassifyBlockAddressReference();
7289 CodeModel::Model M = getTargetMachine().getCodeModel();
7290 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7291 DebugLoc dl = Op.getDebugLoc();
7292 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7293 /*isTarget=*/true, OpFlags);
7295 if (Subtarget->isPICStyleRIPRel() &&
7296 (M == CodeModel::Small || M == CodeModel::Kernel))
7297 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7299 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7301 // With PIC, the address is actually $g + Offset.
7302 if (isGlobalRelativeToPICBase(OpFlags)) {
7303 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7304 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7312 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7314 SelectionDAG &DAG) const {
7315 // Create the TargetGlobalAddress node, folding in the constant
7316 // offset if it is legal.
7317 unsigned char OpFlags =
7318 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7319 CodeModel::Model M = getTargetMachine().getCodeModel();
7321 if (OpFlags == X86II::MO_NO_FLAG &&
7322 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7323 // A direct static reference to a global.
7324 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7327 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7330 if (Subtarget->isPICStyleRIPRel() &&
7331 (M == CodeModel::Small || M == CodeModel::Kernel))
7332 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7334 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7336 // With PIC, the address is actually $g + Offset.
7337 if (isGlobalRelativeToPICBase(OpFlags)) {
7338 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7339 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7343 // For globals that require a load from a stub to get the address, emit the
7345 if (isGlobalStubReference(OpFlags))
7346 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7347 MachinePointerInfo::getGOT(), false, false, 0);
7349 // If there was a non-zero offset that we didn't fold, create an explicit
7352 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7353 DAG.getConstant(Offset, getPointerTy()));
7359 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7360 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7361 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7362 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7366 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7367 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7368 unsigned char OperandFlags) {
7369 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7370 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7371 DebugLoc dl = GA->getDebugLoc();
7372 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7373 GA->getValueType(0),
7377 SDValue Ops[] = { Chain, TGA, *InFlag };
7378 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7380 SDValue Ops[] = { Chain, TGA };
7381 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7384 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7385 MFI->setAdjustsStack(true);
7387 SDValue Flag = Chain.getValue(1);
7388 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7391 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7393 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7396 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7397 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7398 DAG.getNode(X86ISD::GlobalBaseReg,
7399 DebugLoc(), PtrVT), InFlag);
7400 InFlag = Chain.getValue(1);
7402 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7405 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7407 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7409 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7410 X86::RAX, X86II::MO_TLSGD);
7413 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7414 // "local exec" model.
7415 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7416 const EVT PtrVT, TLSModel::Model model,
7418 DebugLoc dl = GA->getDebugLoc();
7420 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7421 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7422 is64Bit ? 257 : 256));
7424 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7425 DAG.getIntPtrConstant(0),
7426 MachinePointerInfo(Ptr), false, false, 0);
7428 unsigned char OperandFlags = 0;
7429 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7431 unsigned WrapperKind = X86ISD::Wrapper;
7432 if (model == TLSModel::LocalExec) {
7433 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7434 } else if (is64Bit) {
7435 assert(model == TLSModel::InitialExec);
7436 OperandFlags = X86II::MO_GOTTPOFF;
7437 WrapperKind = X86ISD::WrapperRIP;
7439 assert(model == TLSModel::InitialExec);
7440 OperandFlags = X86II::MO_INDNTPOFF;
7443 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7445 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7446 GA->getValueType(0),
7447 GA->getOffset(), OperandFlags);
7448 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7450 if (model == TLSModel::InitialExec)
7451 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7452 MachinePointerInfo::getGOT(), false, false, 0);
7454 // The address of the thread local variable is the add of the thread
7455 // pointer with the offset of the variable.
7456 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7460 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7462 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7463 const GlobalValue *GV = GA->getGlobal();
7465 if (Subtarget->isTargetELF()) {
7466 // TODO: implement the "local dynamic" model
7467 // TODO: implement the "initial exec"model for pic executables
7469 // If GV is an alias then use the aliasee for determining
7470 // thread-localness.
7471 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7472 GV = GA->resolveAliasedGlobal(false);
7474 TLSModel::Model model
7475 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7478 case TLSModel::GeneralDynamic:
7479 case TLSModel::LocalDynamic: // not implemented
7480 if (Subtarget->is64Bit())
7481 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7482 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7484 case TLSModel::InitialExec:
7485 case TLSModel::LocalExec:
7486 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7487 Subtarget->is64Bit());
7489 } else if (Subtarget->isTargetDarwin()) {
7490 // Darwin only has one model of TLS. Lower to that.
7491 unsigned char OpFlag = 0;
7492 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7493 X86ISD::WrapperRIP : X86ISD::Wrapper;
7495 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7497 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7498 !Subtarget->is64Bit();
7500 OpFlag = X86II::MO_TLVP_PIC_BASE;
7502 OpFlag = X86II::MO_TLVP;
7503 DebugLoc DL = Op.getDebugLoc();
7504 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7505 GA->getValueType(0),
7506 GA->getOffset(), OpFlag);
7507 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7509 // With PIC32, the address is actually $g + Offset.
7511 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7512 DAG.getNode(X86ISD::GlobalBaseReg,
7513 DebugLoc(), getPointerTy()),
7516 // Lowering the machine isd will make sure everything is in the right
7518 SDValue Chain = DAG.getEntryNode();
7519 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7520 SDValue Args[] = { Chain, Offset };
7521 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7523 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7524 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7525 MFI->setAdjustsStack(true);
7527 // And our return value (tls address) is in the standard call return value
7529 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7530 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7535 "TLS not implemented for this target.");
7537 llvm_unreachable("Unreachable");
7542 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7543 /// take a 2 x i32 value to shift plus a shift amount.
7544 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7545 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7546 EVT VT = Op.getValueType();
7547 unsigned VTBits = VT.getSizeInBits();
7548 DebugLoc dl = Op.getDebugLoc();
7549 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7550 SDValue ShOpLo = Op.getOperand(0);
7551 SDValue ShOpHi = Op.getOperand(1);
7552 SDValue ShAmt = Op.getOperand(2);
7553 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7554 DAG.getConstant(VTBits - 1, MVT::i8))
7555 : DAG.getConstant(0, VT);
7558 if (Op.getOpcode() == ISD::SHL_PARTS) {
7559 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7560 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7562 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7563 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7566 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7567 DAG.getConstant(VTBits, MVT::i8));
7568 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7569 AndNode, DAG.getConstant(0, MVT::i8));
7572 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7573 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7574 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7576 if (Op.getOpcode() == ISD::SHL_PARTS) {
7577 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7578 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7580 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7581 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7584 SDValue Ops[2] = { Lo, Hi };
7585 return DAG.getMergeValues(Ops, 2, dl);
7588 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7589 SelectionDAG &DAG) const {
7590 EVT SrcVT = Op.getOperand(0).getValueType();
7592 if (SrcVT.isVector())
7595 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7596 "Unknown SINT_TO_FP to lower!");
7598 // These are really Legal; return the operand so the caller accepts it as
7600 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7602 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7603 Subtarget->is64Bit()) {
7607 DebugLoc dl = Op.getDebugLoc();
7608 unsigned Size = SrcVT.getSizeInBits()/8;
7609 MachineFunction &MF = DAG.getMachineFunction();
7610 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7611 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7612 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7614 MachinePointerInfo::getFixedStack(SSFI),
7616 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7619 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7621 SelectionDAG &DAG) const {
7623 DebugLoc DL = Op.getDebugLoc();
7625 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7627 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7629 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7631 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7633 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7634 MachineMemOperand *MMO;
7636 int SSFI = FI->getIndex();
7638 DAG.getMachineFunction()
7639 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7640 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7642 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7643 StackSlot = StackSlot.getOperand(1);
7645 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7646 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7648 Tys, Ops, array_lengthof(Ops),
7652 Chain = Result.getValue(1);
7653 SDValue InFlag = Result.getValue(2);
7655 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7656 // shouldn't be necessary except that RFP cannot be live across
7657 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7658 MachineFunction &MF = DAG.getMachineFunction();
7659 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7660 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7661 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7662 Tys = DAG.getVTList(MVT::Other);
7664 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7666 MachineMemOperand *MMO =
7667 DAG.getMachineFunction()
7668 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7669 MachineMemOperand::MOStore, SSFISize, SSFISize);
7671 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7672 Ops, array_lengthof(Ops),
7673 Op.getValueType(), MMO);
7674 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7675 MachinePointerInfo::getFixedStack(SSFI),
7682 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7683 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7684 SelectionDAG &DAG) const {
7685 // This algorithm is not obvious. Here it is in C code, more or less:
7687 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7688 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7689 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7691 // Copy ints to xmm registers.
7692 __m128i xh = _mm_cvtsi32_si128( hi );
7693 __m128i xl = _mm_cvtsi32_si128( lo );
7695 // Combine into low half of a single xmm register.
7696 __m128i x = _mm_unpacklo_epi32( xh, xl );
7700 // Merge in appropriate exponents to give the integer bits the right
7702 x = _mm_unpacklo_epi32( x, exp );
7704 // Subtract away the biases to deal with the IEEE-754 double precision
7706 d = _mm_sub_pd( (__m128d) x, bias );
7708 // All conversions up to here are exact. The correctly rounded result is
7709 // calculated using the current rounding mode using the following
7711 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7712 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7713 // store doesn't really need to be here (except
7714 // maybe to zero the other double)
7719 DebugLoc dl = Op.getDebugLoc();
7720 LLVMContext *Context = DAG.getContext();
7722 // Build some magic constants.
7723 std::vector<Constant*> CV0;
7724 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7725 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7726 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7727 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7728 Constant *C0 = ConstantVector::get(CV0);
7729 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7731 std::vector<Constant*> CV1;
7733 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7735 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7736 Constant *C1 = ConstantVector::get(CV1);
7737 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7739 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7740 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7742 DAG.getIntPtrConstant(1)));
7743 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7744 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7746 DAG.getIntPtrConstant(0)));
7747 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7748 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7749 MachinePointerInfo::getConstantPool(),
7751 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7752 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7753 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7754 MachinePointerInfo::getConstantPool(),
7756 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7758 // Add the halves; easiest way is to swap them into another reg first.
7759 int ShufMask[2] = { 1, -1 };
7760 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7761 DAG.getUNDEF(MVT::v2f64), ShufMask);
7762 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7763 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7764 DAG.getIntPtrConstant(0));
7767 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7768 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7769 SelectionDAG &DAG) const {
7770 DebugLoc dl = Op.getDebugLoc();
7771 // FP constant to bias correct the final result.
7772 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7775 // Load the 32-bit value into an XMM register.
7776 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7779 // Zero out the upper parts of the register.
7780 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(),
7783 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7784 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7785 DAG.getIntPtrConstant(0));
7787 // Or the load with the bias.
7788 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7789 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7790 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7792 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7793 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7794 MVT::v2f64, Bias)));
7795 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7796 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7797 DAG.getIntPtrConstant(0));
7799 // Subtract the bias.
7800 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7802 // Handle final rounding.
7803 EVT DestVT = Op.getValueType();
7805 if (DestVT.bitsLT(MVT::f64)) {
7806 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7807 DAG.getIntPtrConstant(0));
7808 } else if (DestVT.bitsGT(MVT::f64)) {
7809 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7812 // Handle final rounding.
7816 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7817 SelectionDAG &DAG) const {
7818 SDValue N0 = Op.getOperand(0);
7819 DebugLoc dl = Op.getDebugLoc();
7821 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7822 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7823 // the optimization here.
7824 if (DAG.SignBitIsZero(N0))
7825 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7827 EVT SrcVT = N0.getValueType();
7828 EVT DstVT = Op.getValueType();
7829 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7830 return LowerUINT_TO_FP_i64(Op, DAG);
7831 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7832 return LowerUINT_TO_FP_i32(Op, DAG);
7834 // Make a 64-bit buffer, and use it to build an FILD.
7835 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7836 if (SrcVT == MVT::i32) {
7837 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7838 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7839 getPointerTy(), StackSlot, WordOff);
7840 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7841 StackSlot, MachinePointerInfo(),
7843 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7844 OffsetSlot, MachinePointerInfo(),
7846 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7850 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7851 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7852 StackSlot, MachinePointerInfo(),
7854 // For i64 source, we need to add the appropriate power of 2 if the input
7855 // was negative. This is the same as the optimization in
7856 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7857 // we must be careful to do the computation in x87 extended precision, not
7858 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7859 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7860 MachineMemOperand *MMO =
7861 DAG.getMachineFunction()
7862 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7863 MachineMemOperand::MOLoad, 8, 8);
7865 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7866 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7867 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7870 APInt FF(32, 0x5F800000ULL);
7872 // Check whether the sign bit is set.
7873 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7874 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7877 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7878 SDValue FudgePtr = DAG.getConstantPool(
7879 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7882 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7883 SDValue Zero = DAG.getIntPtrConstant(0);
7884 SDValue Four = DAG.getIntPtrConstant(4);
7885 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7887 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7889 // Load the value out, extending it from f32 to f80.
7890 // FIXME: Avoid the extend by constructing the right constant pool?
7891 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7892 FudgePtr, MachinePointerInfo::getConstantPool(),
7893 MVT::f32, false, false, 4);
7894 // Extend everything to 80 bits to force it to be done on x87.
7895 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7896 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7899 std::pair<SDValue,SDValue> X86TargetLowering::
7900 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7901 DebugLoc DL = Op.getDebugLoc();
7903 EVT DstTy = Op.getValueType();
7906 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7910 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7911 DstTy.getSimpleVT() >= MVT::i16 &&
7912 "Unknown FP_TO_SINT to lower!");
7914 // These are really Legal.
7915 if (DstTy == MVT::i32 &&
7916 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7917 return std::make_pair(SDValue(), SDValue());
7918 if (Subtarget->is64Bit() &&
7919 DstTy == MVT::i64 &&
7920 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7921 return std::make_pair(SDValue(), SDValue());
7923 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7925 MachineFunction &MF = DAG.getMachineFunction();
7926 unsigned MemSize = DstTy.getSizeInBits()/8;
7927 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7928 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7933 switch (DstTy.getSimpleVT().SimpleTy) {
7934 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7935 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7936 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7937 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7940 SDValue Chain = DAG.getEntryNode();
7941 SDValue Value = Op.getOperand(0);
7942 EVT TheVT = Op.getOperand(0).getValueType();
7943 if (isScalarFPTypeInSSEReg(TheVT)) {
7944 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7945 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7946 MachinePointerInfo::getFixedStack(SSFI),
7948 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7950 Chain, StackSlot, DAG.getValueType(TheVT)
7953 MachineMemOperand *MMO =
7954 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7955 MachineMemOperand::MOLoad, MemSize, MemSize);
7956 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7958 Chain = Value.getValue(1);
7959 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7960 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7963 MachineMemOperand *MMO =
7964 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7965 MachineMemOperand::MOStore, MemSize, MemSize);
7967 // Build the FP_TO_INT*_IN_MEM
7968 SDValue Ops[] = { Chain, Value, StackSlot };
7969 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7970 Ops, 3, DstTy, MMO);
7972 return std::make_pair(FIST, StackSlot);
7975 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7976 SelectionDAG &DAG) const {
7977 if (Op.getValueType().isVector())
7980 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7981 SDValue FIST = Vals.first, StackSlot = Vals.second;
7982 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7983 if (FIST.getNode() == 0) return Op;
7986 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7987 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7990 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7991 SelectionDAG &DAG) const {
7992 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7993 SDValue FIST = Vals.first, StackSlot = Vals.second;
7994 assert(FIST.getNode() && "Unexpected failure");
7997 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7998 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
8001 SDValue X86TargetLowering::LowerFABS(SDValue Op,
8002 SelectionDAG &DAG) const {
8003 LLVMContext *Context = DAG.getContext();
8004 DebugLoc dl = Op.getDebugLoc();
8005 EVT VT = Op.getValueType();
8008 EltVT = VT.getVectorElementType();
8009 std::vector<Constant*> CV;
8010 if (EltVT == MVT::f64) {
8011 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
8015 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
8021 Constant *C = ConstantVector::get(CV);
8022 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8023 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8024 MachinePointerInfo::getConstantPool(),
8026 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8029 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8030 LLVMContext *Context = DAG.getContext();
8031 DebugLoc dl = Op.getDebugLoc();
8032 EVT VT = Op.getValueType();
8035 EltVT = VT.getVectorElementType();
8036 std::vector<Constant*> CV;
8037 if (EltVT == MVT::f64) {
8038 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8042 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8048 Constant *C = ConstantVector::get(CV);
8049 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8050 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8051 MachinePointerInfo::getConstantPool(),
8053 if (VT.isVector()) {
8054 return DAG.getNode(ISD::BITCAST, dl, VT,
8055 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
8056 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8058 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
8060 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8064 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8065 LLVMContext *Context = DAG.getContext();
8066 SDValue Op0 = Op.getOperand(0);
8067 SDValue Op1 = Op.getOperand(1);
8068 DebugLoc dl = Op.getDebugLoc();
8069 EVT VT = Op.getValueType();
8070 EVT SrcVT = Op1.getValueType();
8072 // If second operand is smaller, extend it first.
8073 if (SrcVT.bitsLT(VT)) {
8074 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8077 // And if it is bigger, shrink it first.
8078 if (SrcVT.bitsGT(VT)) {
8079 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8083 // At this point the operands and the result should have the same
8084 // type, and that won't be f80 since that is not custom lowered.
8086 // First get the sign bit of second operand.
8087 std::vector<Constant*> CV;
8088 if (SrcVT == MVT::f64) {
8089 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8090 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8092 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8093 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8094 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8095 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8097 Constant *C = ConstantVector::get(CV);
8098 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8099 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8100 MachinePointerInfo::getConstantPool(),
8102 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8104 // Shift sign bit right or left if the two operands have different types.
8105 if (SrcVT.bitsGT(VT)) {
8106 // Op0 is MVT::f32, Op1 is MVT::f64.
8107 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8108 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8109 DAG.getConstant(32, MVT::i32));
8110 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8111 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8112 DAG.getIntPtrConstant(0));
8115 // Clear first operand sign bit.
8117 if (VT == MVT::f64) {
8118 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8119 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8121 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8122 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8123 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8124 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8126 C = ConstantVector::get(CV);
8127 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8128 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8129 MachinePointerInfo::getConstantPool(),
8131 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8133 // Or the value with the sign bit.
8134 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8137 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8138 SDValue N0 = Op.getOperand(0);
8139 DebugLoc dl = Op.getDebugLoc();
8140 EVT VT = Op.getValueType();
8142 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8143 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8144 DAG.getConstant(1, VT));
8145 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8148 /// Emit nodes that will be selected as "test Op0,Op0", or something
8150 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8151 SelectionDAG &DAG) const {
8152 DebugLoc dl = Op.getDebugLoc();
8154 // CF and OF aren't always set the way we want. Determine which
8155 // of these we need.
8156 bool NeedCF = false;
8157 bool NeedOF = false;
8160 case X86::COND_A: case X86::COND_AE:
8161 case X86::COND_B: case X86::COND_BE:
8164 case X86::COND_G: case X86::COND_GE:
8165 case X86::COND_L: case X86::COND_LE:
8166 case X86::COND_O: case X86::COND_NO:
8171 // See if we can use the EFLAGS value from the operand instead of
8172 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8173 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8174 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8175 // Emit a CMP with 0, which is the TEST pattern.
8176 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8177 DAG.getConstant(0, Op.getValueType()));
8179 unsigned Opcode = 0;
8180 unsigned NumOperands = 0;
8181 switch (Op.getNode()->getOpcode()) {
8183 // Due to an isel shortcoming, be conservative if this add is likely to be
8184 // selected as part of a load-modify-store instruction. When the root node
8185 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8186 // uses of other nodes in the match, such as the ADD in this case. This
8187 // leads to the ADD being left around and reselected, with the result being
8188 // two adds in the output. Alas, even if none our users are stores, that
8189 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8190 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8191 // climbing the DAG back to the root, and it doesn't seem to be worth the
8193 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8194 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8195 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
8198 if (ConstantSDNode *C =
8199 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8200 // An add of one will be selected as an INC.
8201 if (C->getAPIntValue() == 1) {
8202 Opcode = X86ISD::INC;
8207 // An add of negative one (subtract of one) will be selected as a DEC.
8208 if (C->getAPIntValue().isAllOnesValue()) {
8209 Opcode = X86ISD::DEC;
8215 // Otherwise use a regular EFLAGS-setting add.
8216 Opcode = X86ISD::ADD;
8220 // If the primary and result isn't used, don't bother using X86ISD::AND,
8221 // because a TEST instruction will be better.
8222 bool NonFlagUse = false;
8223 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8224 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8226 unsigned UOpNo = UI.getOperandNo();
8227 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8228 // Look pass truncate.
8229 UOpNo = User->use_begin().getOperandNo();
8230 User = *User->use_begin();
8233 if (User->getOpcode() != ISD::BRCOND &&
8234 User->getOpcode() != ISD::SETCC &&
8235 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8248 // Due to the ISEL shortcoming noted above, be conservative if this op is
8249 // likely to be selected as part of a load-modify-store instruction.
8250 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8251 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8252 if (UI->getOpcode() == ISD::STORE)
8255 // Otherwise use a regular EFLAGS-setting instruction.
8256 switch (Op.getNode()->getOpcode()) {
8257 default: llvm_unreachable("unexpected operator!");
8258 case ISD::SUB: Opcode = X86ISD::SUB; break;
8259 case ISD::OR: Opcode = X86ISD::OR; break;
8260 case ISD::XOR: Opcode = X86ISD::XOR; break;
8261 case ISD::AND: Opcode = X86ISD::AND; break;
8273 return SDValue(Op.getNode(), 1);
8280 // Emit a CMP with 0, which is the TEST pattern.
8281 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8282 DAG.getConstant(0, Op.getValueType()));
8284 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8285 SmallVector<SDValue, 4> Ops;
8286 for (unsigned i = 0; i != NumOperands; ++i)
8287 Ops.push_back(Op.getOperand(i));
8289 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8290 DAG.ReplaceAllUsesWith(Op, New);
8291 return SDValue(New.getNode(), 1);
8294 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8296 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8297 SelectionDAG &DAG) const {
8298 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8299 if (C->getAPIntValue() == 0)
8300 return EmitTest(Op0, X86CC, DAG);
8302 DebugLoc dl = Op0.getDebugLoc();
8303 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8306 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8307 /// if it's possible.
8308 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8309 DebugLoc dl, SelectionDAG &DAG) const {
8310 SDValue Op0 = And.getOperand(0);
8311 SDValue Op1 = And.getOperand(1);
8312 if (Op0.getOpcode() == ISD::TRUNCATE)
8313 Op0 = Op0.getOperand(0);
8314 if (Op1.getOpcode() == ISD::TRUNCATE)
8315 Op1 = Op1.getOperand(0);
8318 if (Op1.getOpcode() == ISD::SHL)
8319 std::swap(Op0, Op1);
8320 if (Op0.getOpcode() == ISD::SHL) {
8321 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8322 if (And00C->getZExtValue() == 1) {
8323 // If we looked past a truncate, check that it's only truncating away
8325 unsigned BitWidth = Op0.getValueSizeInBits();
8326 unsigned AndBitWidth = And.getValueSizeInBits();
8327 if (BitWidth > AndBitWidth) {
8328 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8329 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8330 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8334 RHS = Op0.getOperand(1);
8336 } else if (Op1.getOpcode() == ISD::Constant) {
8337 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8338 SDValue AndLHS = Op0;
8339 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8340 LHS = AndLHS.getOperand(0);
8341 RHS = AndLHS.getOperand(1);
8345 if (LHS.getNode()) {
8346 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8347 // instruction. Since the shift amount is in-range-or-undefined, we know
8348 // that doing a bittest on the i32 value is ok. We extend to i32 because
8349 // the encoding for the i16 version is larger than the i32 version.
8350 // Also promote i16 to i32 for performance / code size reason.
8351 if (LHS.getValueType() == MVT::i8 ||
8352 LHS.getValueType() == MVT::i16)
8353 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8355 // If the operand types disagree, extend the shift amount to match. Since
8356 // BT ignores high bits (like shifts) we can use anyextend.
8357 if (LHS.getValueType() != RHS.getValueType())
8358 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8360 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8361 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8362 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8363 DAG.getConstant(Cond, MVT::i8), BT);
8369 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8371 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8373 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8374 SDValue Op0 = Op.getOperand(0);
8375 SDValue Op1 = Op.getOperand(1);
8376 DebugLoc dl = Op.getDebugLoc();
8377 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8379 // Optimize to BT if possible.
8380 // Lower (X & (1 << N)) == 0 to BT(X, N).
8381 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8382 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8383 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8384 Op1.getOpcode() == ISD::Constant &&
8385 cast<ConstantSDNode>(Op1)->isNullValue() &&
8386 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8387 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8388 if (NewSetCC.getNode())
8392 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8394 if (Op1.getOpcode() == ISD::Constant &&
8395 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8396 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8397 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8399 // If the input is a setcc, then reuse the input setcc or use a new one with
8400 // the inverted condition.
8401 if (Op0.getOpcode() == X86ISD::SETCC) {
8402 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8403 bool Invert = (CC == ISD::SETNE) ^
8404 cast<ConstantSDNode>(Op1)->isNullValue();
8405 if (!Invert) return Op0;
8407 CCode = X86::GetOppositeBranchCondition(CCode);
8408 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8409 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8413 bool isFP = Op1.getValueType().isFloatingPoint();
8414 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8415 if (X86CC == X86::COND_INVALID)
8418 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8419 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8420 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8423 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8424 // ones, and then concatenate the result back.
8425 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8426 EVT VT = Op.getValueType();
8428 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8429 "Unsupported value type for operation");
8431 int NumElems = VT.getVectorNumElements();
8432 DebugLoc dl = Op.getDebugLoc();
8433 SDValue CC = Op.getOperand(2);
8434 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8435 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8437 // Extract the LHS vectors
8438 SDValue LHS = Op.getOperand(0);
8439 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8440 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8442 // Extract the RHS vectors
8443 SDValue RHS = Op.getOperand(1);
8444 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8445 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8447 // Issue the operation on the smaller types and concatenate the result back
8448 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8449 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8450 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8451 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8452 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8456 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8458 SDValue Op0 = Op.getOperand(0);
8459 SDValue Op1 = Op.getOperand(1);
8460 SDValue CC = Op.getOperand(2);
8461 EVT VT = Op.getValueType();
8462 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8463 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8464 DebugLoc dl = Op.getDebugLoc();
8468 EVT EltVT = Op0.getValueType().getVectorElementType();
8469 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8471 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8474 // SSE Condition code mapping:
8483 switch (SetCCOpcode) {
8486 case ISD::SETEQ: SSECC = 0; break;
8488 case ISD::SETGT: Swap = true; // Fallthrough
8490 case ISD::SETOLT: SSECC = 1; break;
8492 case ISD::SETGE: Swap = true; // Fallthrough
8494 case ISD::SETOLE: SSECC = 2; break;
8495 case ISD::SETUO: SSECC = 3; break;
8497 case ISD::SETNE: SSECC = 4; break;
8498 case ISD::SETULE: Swap = true;
8499 case ISD::SETUGE: SSECC = 5; break;
8500 case ISD::SETULT: Swap = true;
8501 case ISD::SETUGT: SSECC = 6; break;
8502 case ISD::SETO: SSECC = 7; break;
8505 std::swap(Op0, Op1);
8507 // In the two special cases we can't handle, emit two comparisons.
8509 if (SetCCOpcode == ISD::SETUEQ) {
8511 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8512 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8513 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8515 else if (SetCCOpcode == ISD::SETONE) {
8517 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8518 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8519 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8521 llvm_unreachable("Illegal FP comparison");
8523 // Handle all other FP comparisons here.
8524 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8527 // Break 256-bit integer vector compare into smaller ones.
8528 if (!isFP && VT.getSizeInBits() == 256)
8529 return Lower256IntVSETCC(Op, DAG);
8531 // We are handling one of the integer comparisons here. Since SSE only has
8532 // GT and EQ comparisons for integer, swapping operands and multiple
8533 // operations may be required for some comparisons.
8534 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8535 bool Swap = false, Invert = false, FlipSigns = false;
8537 switch (VT.getSimpleVT().SimpleTy) {
8539 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8540 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8541 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8542 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8545 switch (SetCCOpcode) {
8547 case ISD::SETNE: Invert = true;
8548 case ISD::SETEQ: Opc = EQOpc; break;
8549 case ISD::SETLT: Swap = true;
8550 case ISD::SETGT: Opc = GTOpc; break;
8551 case ISD::SETGE: Swap = true;
8552 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8553 case ISD::SETULT: Swap = true;
8554 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8555 case ISD::SETUGE: Swap = true;
8556 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8559 std::swap(Op0, Op1);
8561 // Check that the operation in question is available (most are plain SSE2,
8562 // but PCMPGTQ and PCMPEQQ have different requirements).
8563 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42() && !Subtarget->hasAVX())
8565 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41() && !Subtarget->hasAVX())
8568 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8569 // bits of the inputs before performing those operations.
8571 EVT EltVT = VT.getVectorElementType();
8572 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8574 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8575 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8577 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8578 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8581 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8583 // If the logical-not of the result is required, perform that now.
8585 Result = DAG.getNOT(dl, Result, VT);
8590 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8591 static bool isX86LogicalCmp(SDValue Op) {
8592 unsigned Opc = Op.getNode()->getOpcode();
8593 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8595 if (Op.getResNo() == 1 &&
8596 (Opc == X86ISD::ADD ||
8597 Opc == X86ISD::SUB ||
8598 Opc == X86ISD::ADC ||
8599 Opc == X86ISD::SBB ||
8600 Opc == X86ISD::SMUL ||
8601 Opc == X86ISD::UMUL ||
8602 Opc == X86ISD::INC ||
8603 Opc == X86ISD::DEC ||
8604 Opc == X86ISD::OR ||
8605 Opc == X86ISD::XOR ||
8606 Opc == X86ISD::AND))
8609 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8615 static bool isZero(SDValue V) {
8616 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8617 return C && C->isNullValue();
8620 static bool isAllOnes(SDValue V) {
8621 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8622 return C && C->isAllOnesValue();
8625 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8626 bool addTest = true;
8627 SDValue Cond = Op.getOperand(0);
8628 SDValue Op1 = Op.getOperand(1);
8629 SDValue Op2 = Op.getOperand(2);
8630 DebugLoc DL = Op.getDebugLoc();
8633 if (Cond.getOpcode() == ISD::SETCC) {
8634 SDValue NewCond = LowerSETCC(Cond, DAG);
8635 if (NewCond.getNode())
8639 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8640 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8641 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8642 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8643 if (Cond.getOpcode() == X86ISD::SETCC &&
8644 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8645 isZero(Cond.getOperand(1).getOperand(1))) {
8646 SDValue Cmp = Cond.getOperand(1);
8648 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8650 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8651 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8652 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8654 SDValue CmpOp0 = Cmp.getOperand(0);
8655 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8656 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8658 SDValue Res = // Res = 0 or -1.
8659 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8660 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8662 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8663 Res = DAG.getNOT(DL, Res, Res.getValueType());
8665 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8666 if (N2C == 0 || !N2C->isNullValue())
8667 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8672 // Look past (and (setcc_carry (cmp ...)), 1).
8673 if (Cond.getOpcode() == ISD::AND &&
8674 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8675 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8676 if (C && C->getAPIntValue() == 1)
8677 Cond = Cond.getOperand(0);
8680 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8681 // setting operand in place of the X86ISD::SETCC.
8682 if (Cond.getOpcode() == X86ISD::SETCC ||
8683 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8684 CC = Cond.getOperand(0);
8686 SDValue Cmp = Cond.getOperand(1);
8687 unsigned Opc = Cmp.getOpcode();
8688 EVT VT = Op.getValueType();
8690 bool IllegalFPCMov = false;
8691 if (VT.isFloatingPoint() && !VT.isVector() &&
8692 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8693 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8695 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8696 Opc == X86ISD::BT) { // FIXME
8703 // Look pass the truncate.
8704 if (Cond.getOpcode() == ISD::TRUNCATE)
8705 Cond = Cond.getOperand(0);
8707 // We know the result of AND is compared against zero. Try to match
8709 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8710 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8711 if (NewSetCC.getNode()) {
8712 CC = NewSetCC.getOperand(0);
8713 Cond = NewSetCC.getOperand(1);
8720 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8721 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8724 // a < b ? -1 : 0 -> RES = ~setcc_carry
8725 // a < b ? 0 : -1 -> RES = setcc_carry
8726 // a >= b ? -1 : 0 -> RES = setcc_carry
8727 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8728 if (Cond.getOpcode() == X86ISD::CMP) {
8729 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8731 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8732 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8733 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8734 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8735 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8736 return DAG.getNOT(DL, Res, Res.getValueType());
8741 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8742 // condition is true.
8743 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8744 SDValue Ops[] = { Op2, Op1, CC, Cond };
8745 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8748 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8749 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8750 // from the AND / OR.
8751 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8752 Opc = Op.getOpcode();
8753 if (Opc != ISD::OR && Opc != ISD::AND)
8755 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8756 Op.getOperand(0).hasOneUse() &&
8757 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8758 Op.getOperand(1).hasOneUse());
8761 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8762 // 1 and that the SETCC node has a single use.
8763 static bool isXor1OfSetCC(SDValue Op) {
8764 if (Op.getOpcode() != ISD::XOR)
8766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8767 if (N1C && N1C->getAPIntValue() == 1) {
8768 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8769 Op.getOperand(0).hasOneUse();
8774 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8775 bool addTest = true;
8776 SDValue Chain = Op.getOperand(0);
8777 SDValue Cond = Op.getOperand(1);
8778 SDValue Dest = Op.getOperand(2);
8779 DebugLoc dl = Op.getDebugLoc();
8782 if (Cond.getOpcode() == ISD::SETCC) {
8783 SDValue NewCond = LowerSETCC(Cond, DAG);
8784 if (NewCond.getNode())
8788 // FIXME: LowerXALUO doesn't handle these!!
8789 else if (Cond.getOpcode() == X86ISD::ADD ||
8790 Cond.getOpcode() == X86ISD::SUB ||
8791 Cond.getOpcode() == X86ISD::SMUL ||
8792 Cond.getOpcode() == X86ISD::UMUL)
8793 Cond = LowerXALUO(Cond, DAG);
8796 // Look pass (and (setcc_carry (cmp ...)), 1).
8797 if (Cond.getOpcode() == ISD::AND &&
8798 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8799 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8800 if (C && C->getAPIntValue() == 1)
8801 Cond = Cond.getOperand(0);
8804 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8805 // setting operand in place of the X86ISD::SETCC.
8806 if (Cond.getOpcode() == X86ISD::SETCC ||
8807 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8808 CC = Cond.getOperand(0);
8810 SDValue Cmp = Cond.getOperand(1);
8811 unsigned Opc = Cmp.getOpcode();
8812 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8813 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8817 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8821 // These can only come from an arithmetic instruction with overflow,
8822 // e.g. SADDO, UADDO.
8823 Cond = Cond.getNode()->getOperand(1);
8830 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8831 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8832 if (CondOpc == ISD::OR) {
8833 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8834 // two branches instead of an explicit OR instruction with a
8836 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8837 isX86LogicalCmp(Cmp)) {
8838 CC = Cond.getOperand(0).getOperand(0);
8839 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8840 Chain, Dest, CC, Cmp);
8841 CC = Cond.getOperand(1).getOperand(0);
8845 } else { // ISD::AND
8846 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8847 // two branches instead of an explicit AND instruction with a
8848 // separate test. However, we only do this if this block doesn't
8849 // have a fall-through edge, because this requires an explicit
8850 // jmp when the condition is false.
8851 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8852 isX86LogicalCmp(Cmp) &&
8853 Op.getNode()->hasOneUse()) {
8854 X86::CondCode CCode =
8855 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8856 CCode = X86::GetOppositeBranchCondition(CCode);
8857 CC = DAG.getConstant(CCode, MVT::i8);
8858 SDNode *User = *Op.getNode()->use_begin();
8859 // Look for an unconditional branch following this conditional branch.
8860 // We need this because we need to reverse the successors in order
8861 // to implement FCMP_OEQ.
8862 if (User->getOpcode() == ISD::BR) {
8863 SDValue FalseBB = User->getOperand(1);
8865 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8866 assert(NewBR == User);
8870 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8871 Chain, Dest, CC, Cmp);
8872 X86::CondCode CCode =
8873 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8874 CCode = X86::GetOppositeBranchCondition(CCode);
8875 CC = DAG.getConstant(CCode, MVT::i8);
8881 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8882 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8883 // It should be transformed during dag combiner except when the condition
8884 // is set by a arithmetics with overflow node.
8885 X86::CondCode CCode =
8886 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8887 CCode = X86::GetOppositeBranchCondition(CCode);
8888 CC = DAG.getConstant(CCode, MVT::i8);
8889 Cond = Cond.getOperand(0).getOperand(1);
8895 // Look pass the truncate.
8896 if (Cond.getOpcode() == ISD::TRUNCATE)
8897 Cond = Cond.getOperand(0);
8899 // We know the result of AND is compared against zero. Try to match
8901 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8902 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8903 if (NewSetCC.getNode()) {
8904 CC = NewSetCC.getOperand(0);
8905 Cond = NewSetCC.getOperand(1);
8912 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8913 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8915 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8916 Chain, Dest, CC, Cond);
8920 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8921 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8922 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8923 // that the guard pages used by the OS virtual memory manager are allocated in
8924 // correct sequence.
8926 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8927 SelectionDAG &DAG) const {
8928 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8929 EnableSegmentedStacks) &&
8930 "This should be used only on Windows targets or when segmented stacks "
8932 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8933 DebugLoc dl = Op.getDebugLoc();
8936 SDValue Chain = Op.getOperand(0);
8937 SDValue Size = Op.getOperand(1);
8938 // FIXME: Ensure alignment here
8940 bool Is64Bit = Subtarget->is64Bit();
8941 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8943 if (EnableSegmentedStacks) {
8944 MachineFunction &MF = DAG.getMachineFunction();
8945 MachineRegisterInfo &MRI = MF.getRegInfo();
8948 // The 64 bit implementation of segmented stacks needs to clobber both r10
8949 // r11. This makes it impossible to use it along with nested parameters.
8950 const Function *F = MF.getFunction();
8952 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8954 if (I->hasNestAttr())
8955 report_fatal_error("Cannot use segmented stacks with functions that "
8956 "have nested arguments.");
8959 const TargetRegisterClass *AddrRegClass =
8960 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8961 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8962 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8963 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8964 DAG.getRegister(Vreg, SPTy));
8965 SDValue Ops1[2] = { Value, Chain };
8966 return DAG.getMergeValues(Ops1, 2, dl);
8969 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8971 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8972 Flag = Chain.getValue(1);
8973 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8975 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8976 Flag = Chain.getValue(1);
8978 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8980 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8981 return DAG.getMergeValues(Ops1, 2, dl);
8985 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8986 MachineFunction &MF = DAG.getMachineFunction();
8987 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8989 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8990 DebugLoc DL = Op.getDebugLoc();
8992 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8993 // vastart just stores the address of the VarArgsFrameIndex slot into the
8994 // memory location argument.
8995 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8997 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8998 MachinePointerInfo(SV), false, false, 0);
9002 // gp_offset (0 - 6 * 8)
9003 // fp_offset (48 - 48 + 8 * 16)
9004 // overflow_arg_area (point to parameters coming in memory).
9006 SmallVector<SDValue, 8> MemOps;
9007 SDValue FIN = Op.getOperand(1);
9009 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9010 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9012 FIN, MachinePointerInfo(SV), false, false, 0);
9013 MemOps.push_back(Store);
9016 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9017 FIN, DAG.getIntPtrConstant(4));
9018 Store = DAG.getStore(Op.getOperand(0), DL,
9019 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9021 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9022 MemOps.push_back(Store);
9024 // Store ptr to overflow_arg_area
9025 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9026 FIN, DAG.getIntPtrConstant(4));
9027 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9029 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9030 MachinePointerInfo(SV, 8),
9032 MemOps.push_back(Store);
9034 // Store ptr to reg_save_area.
9035 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9036 FIN, DAG.getIntPtrConstant(8));
9037 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9039 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9040 MachinePointerInfo(SV, 16), false, false, 0);
9041 MemOps.push_back(Store);
9042 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9043 &MemOps[0], MemOps.size());
9046 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9047 assert(Subtarget->is64Bit() &&
9048 "LowerVAARG only handles 64-bit va_arg!");
9049 assert((Subtarget->isTargetLinux() ||
9050 Subtarget->isTargetDarwin()) &&
9051 "Unhandled target in LowerVAARG");
9052 assert(Op.getNode()->getNumOperands() == 4);
9053 SDValue Chain = Op.getOperand(0);
9054 SDValue SrcPtr = Op.getOperand(1);
9055 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9056 unsigned Align = Op.getConstantOperandVal(3);
9057 DebugLoc dl = Op.getDebugLoc();
9059 EVT ArgVT = Op.getNode()->getValueType(0);
9060 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9061 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9064 // Decide which area this value should be read from.
9065 // TODO: Implement the AMD64 ABI in its entirety. This simple
9066 // selection mechanism works only for the basic types.
9067 if (ArgVT == MVT::f80) {
9068 llvm_unreachable("va_arg for f80 not yet implemented");
9069 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9070 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9071 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9072 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9074 llvm_unreachable("Unhandled argument type in LowerVAARG");
9078 // Sanity Check: Make sure using fp_offset makes sense.
9079 assert(!UseSoftFloat &&
9080 !(DAG.getMachineFunction()
9081 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9082 Subtarget->hasXMM());
9085 // Insert VAARG_64 node into the DAG
9086 // VAARG_64 returns two values: Variable Argument Address, Chain
9087 SmallVector<SDValue, 11> InstOps;
9088 InstOps.push_back(Chain);
9089 InstOps.push_back(SrcPtr);
9090 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9091 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9092 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9093 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9094 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9095 VTs, &InstOps[0], InstOps.size(),
9097 MachinePointerInfo(SV),
9102 Chain = VAARG.getValue(1);
9104 // Load the next argument and return it
9105 return DAG.getLoad(ArgVT, dl,
9108 MachinePointerInfo(),
9112 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9113 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9114 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9115 SDValue Chain = Op.getOperand(0);
9116 SDValue DstPtr = Op.getOperand(1);
9117 SDValue SrcPtr = Op.getOperand(2);
9118 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9119 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9120 DebugLoc DL = Op.getDebugLoc();
9122 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9123 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9125 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9129 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9130 DebugLoc dl = Op.getDebugLoc();
9131 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9133 default: return SDValue(); // Don't custom lower most intrinsics.
9134 // Comparison intrinsics.
9135 case Intrinsic::x86_sse_comieq_ss:
9136 case Intrinsic::x86_sse_comilt_ss:
9137 case Intrinsic::x86_sse_comile_ss:
9138 case Intrinsic::x86_sse_comigt_ss:
9139 case Intrinsic::x86_sse_comige_ss:
9140 case Intrinsic::x86_sse_comineq_ss:
9141 case Intrinsic::x86_sse_ucomieq_ss:
9142 case Intrinsic::x86_sse_ucomilt_ss:
9143 case Intrinsic::x86_sse_ucomile_ss:
9144 case Intrinsic::x86_sse_ucomigt_ss:
9145 case Intrinsic::x86_sse_ucomige_ss:
9146 case Intrinsic::x86_sse_ucomineq_ss:
9147 case Intrinsic::x86_sse2_comieq_sd:
9148 case Intrinsic::x86_sse2_comilt_sd:
9149 case Intrinsic::x86_sse2_comile_sd:
9150 case Intrinsic::x86_sse2_comigt_sd:
9151 case Intrinsic::x86_sse2_comige_sd:
9152 case Intrinsic::x86_sse2_comineq_sd:
9153 case Intrinsic::x86_sse2_ucomieq_sd:
9154 case Intrinsic::x86_sse2_ucomilt_sd:
9155 case Intrinsic::x86_sse2_ucomile_sd:
9156 case Intrinsic::x86_sse2_ucomigt_sd:
9157 case Intrinsic::x86_sse2_ucomige_sd:
9158 case Intrinsic::x86_sse2_ucomineq_sd: {
9160 ISD::CondCode CC = ISD::SETCC_INVALID;
9163 case Intrinsic::x86_sse_comieq_ss:
9164 case Intrinsic::x86_sse2_comieq_sd:
9168 case Intrinsic::x86_sse_comilt_ss:
9169 case Intrinsic::x86_sse2_comilt_sd:
9173 case Intrinsic::x86_sse_comile_ss:
9174 case Intrinsic::x86_sse2_comile_sd:
9178 case Intrinsic::x86_sse_comigt_ss:
9179 case Intrinsic::x86_sse2_comigt_sd:
9183 case Intrinsic::x86_sse_comige_ss:
9184 case Intrinsic::x86_sse2_comige_sd:
9188 case Intrinsic::x86_sse_comineq_ss:
9189 case Intrinsic::x86_sse2_comineq_sd:
9193 case Intrinsic::x86_sse_ucomieq_ss:
9194 case Intrinsic::x86_sse2_ucomieq_sd:
9195 Opc = X86ISD::UCOMI;
9198 case Intrinsic::x86_sse_ucomilt_ss:
9199 case Intrinsic::x86_sse2_ucomilt_sd:
9200 Opc = X86ISD::UCOMI;
9203 case Intrinsic::x86_sse_ucomile_ss:
9204 case Intrinsic::x86_sse2_ucomile_sd:
9205 Opc = X86ISD::UCOMI;
9208 case Intrinsic::x86_sse_ucomigt_ss:
9209 case Intrinsic::x86_sse2_ucomigt_sd:
9210 Opc = X86ISD::UCOMI;
9213 case Intrinsic::x86_sse_ucomige_ss:
9214 case Intrinsic::x86_sse2_ucomige_sd:
9215 Opc = X86ISD::UCOMI;
9218 case Intrinsic::x86_sse_ucomineq_ss:
9219 case Intrinsic::x86_sse2_ucomineq_sd:
9220 Opc = X86ISD::UCOMI;
9225 SDValue LHS = Op.getOperand(1);
9226 SDValue RHS = Op.getOperand(2);
9227 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9228 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9229 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9230 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9231 DAG.getConstant(X86CC, MVT::i8), Cond);
9232 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9234 // Arithmetic intrinsics.
9235 case Intrinsic::x86_sse3_hadd_ps:
9236 case Intrinsic::x86_sse3_hadd_pd:
9237 case Intrinsic::x86_avx_hadd_ps_256:
9238 case Intrinsic::x86_avx_hadd_pd_256:
9239 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9240 Op.getOperand(1), Op.getOperand(2));
9241 case Intrinsic::x86_sse3_hsub_ps:
9242 case Intrinsic::x86_sse3_hsub_pd:
9243 case Intrinsic::x86_avx_hsub_ps_256:
9244 case Intrinsic::x86_avx_hsub_pd_256:
9245 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9246 Op.getOperand(1), Op.getOperand(2));
9247 // ptest and testp intrinsics. The intrinsic these come from are designed to
9248 // return an integer value, not just an instruction so lower it to the ptest
9249 // or testp pattern and a setcc for the result.
9250 case Intrinsic::x86_sse41_ptestz:
9251 case Intrinsic::x86_sse41_ptestc:
9252 case Intrinsic::x86_sse41_ptestnzc:
9253 case Intrinsic::x86_avx_ptestz_256:
9254 case Intrinsic::x86_avx_ptestc_256:
9255 case Intrinsic::x86_avx_ptestnzc_256:
9256 case Intrinsic::x86_avx_vtestz_ps:
9257 case Intrinsic::x86_avx_vtestc_ps:
9258 case Intrinsic::x86_avx_vtestnzc_ps:
9259 case Intrinsic::x86_avx_vtestz_pd:
9260 case Intrinsic::x86_avx_vtestc_pd:
9261 case Intrinsic::x86_avx_vtestnzc_pd:
9262 case Intrinsic::x86_avx_vtestz_ps_256:
9263 case Intrinsic::x86_avx_vtestc_ps_256:
9264 case Intrinsic::x86_avx_vtestnzc_ps_256:
9265 case Intrinsic::x86_avx_vtestz_pd_256:
9266 case Intrinsic::x86_avx_vtestc_pd_256:
9267 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9268 bool IsTestPacked = false;
9271 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9272 case Intrinsic::x86_avx_vtestz_ps:
9273 case Intrinsic::x86_avx_vtestz_pd:
9274 case Intrinsic::x86_avx_vtestz_ps_256:
9275 case Intrinsic::x86_avx_vtestz_pd_256:
9276 IsTestPacked = true; // Fallthrough
9277 case Intrinsic::x86_sse41_ptestz:
9278 case Intrinsic::x86_avx_ptestz_256:
9280 X86CC = X86::COND_E;
9282 case Intrinsic::x86_avx_vtestc_ps:
9283 case Intrinsic::x86_avx_vtestc_pd:
9284 case Intrinsic::x86_avx_vtestc_ps_256:
9285 case Intrinsic::x86_avx_vtestc_pd_256:
9286 IsTestPacked = true; // Fallthrough
9287 case Intrinsic::x86_sse41_ptestc:
9288 case Intrinsic::x86_avx_ptestc_256:
9290 X86CC = X86::COND_B;
9292 case Intrinsic::x86_avx_vtestnzc_ps:
9293 case Intrinsic::x86_avx_vtestnzc_pd:
9294 case Intrinsic::x86_avx_vtestnzc_ps_256:
9295 case Intrinsic::x86_avx_vtestnzc_pd_256:
9296 IsTestPacked = true; // Fallthrough
9297 case Intrinsic::x86_sse41_ptestnzc:
9298 case Intrinsic::x86_avx_ptestnzc_256:
9300 X86CC = X86::COND_A;
9304 SDValue LHS = Op.getOperand(1);
9305 SDValue RHS = Op.getOperand(2);
9306 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9307 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9308 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9309 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9310 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9313 // Fix vector shift instructions where the last operand is a non-immediate
9315 case Intrinsic::x86_sse2_pslli_w:
9316 case Intrinsic::x86_sse2_pslli_d:
9317 case Intrinsic::x86_sse2_pslli_q:
9318 case Intrinsic::x86_sse2_psrli_w:
9319 case Intrinsic::x86_sse2_psrli_d:
9320 case Intrinsic::x86_sse2_psrli_q:
9321 case Intrinsic::x86_sse2_psrai_w:
9322 case Intrinsic::x86_sse2_psrai_d:
9323 case Intrinsic::x86_mmx_pslli_w:
9324 case Intrinsic::x86_mmx_pslli_d:
9325 case Intrinsic::x86_mmx_pslli_q:
9326 case Intrinsic::x86_mmx_psrli_w:
9327 case Intrinsic::x86_mmx_psrli_d:
9328 case Intrinsic::x86_mmx_psrli_q:
9329 case Intrinsic::x86_mmx_psrai_w:
9330 case Intrinsic::x86_mmx_psrai_d: {
9331 SDValue ShAmt = Op.getOperand(2);
9332 if (isa<ConstantSDNode>(ShAmt))
9335 unsigned NewIntNo = 0;
9336 EVT ShAmtVT = MVT::v4i32;
9338 case Intrinsic::x86_sse2_pslli_w:
9339 NewIntNo = Intrinsic::x86_sse2_psll_w;
9341 case Intrinsic::x86_sse2_pslli_d:
9342 NewIntNo = Intrinsic::x86_sse2_psll_d;
9344 case Intrinsic::x86_sse2_pslli_q:
9345 NewIntNo = Intrinsic::x86_sse2_psll_q;
9347 case Intrinsic::x86_sse2_psrli_w:
9348 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9350 case Intrinsic::x86_sse2_psrli_d:
9351 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9353 case Intrinsic::x86_sse2_psrli_q:
9354 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9356 case Intrinsic::x86_sse2_psrai_w:
9357 NewIntNo = Intrinsic::x86_sse2_psra_w;
9359 case Intrinsic::x86_sse2_psrai_d:
9360 NewIntNo = Intrinsic::x86_sse2_psra_d;
9363 ShAmtVT = MVT::v2i32;
9365 case Intrinsic::x86_mmx_pslli_w:
9366 NewIntNo = Intrinsic::x86_mmx_psll_w;
9368 case Intrinsic::x86_mmx_pslli_d:
9369 NewIntNo = Intrinsic::x86_mmx_psll_d;
9371 case Intrinsic::x86_mmx_pslli_q:
9372 NewIntNo = Intrinsic::x86_mmx_psll_q;
9374 case Intrinsic::x86_mmx_psrli_w:
9375 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9377 case Intrinsic::x86_mmx_psrli_d:
9378 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9380 case Intrinsic::x86_mmx_psrli_q:
9381 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9383 case Intrinsic::x86_mmx_psrai_w:
9384 NewIntNo = Intrinsic::x86_mmx_psra_w;
9386 case Intrinsic::x86_mmx_psrai_d:
9387 NewIntNo = Intrinsic::x86_mmx_psra_d;
9389 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9395 // The vector shift intrinsics with scalars uses 32b shift amounts but
9396 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9400 ShOps[1] = DAG.getConstant(0, MVT::i32);
9401 if (ShAmtVT == MVT::v4i32) {
9402 ShOps[2] = DAG.getUNDEF(MVT::i32);
9403 ShOps[3] = DAG.getUNDEF(MVT::i32);
9404 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9406 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9407 // FIXME this must be lowered to get rid of the invalid type.
9410 EVT VT = Op.getValueType();
9411 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9412 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9413 DAG.getConstant(NewIntNo, MVT::i32),
9414 Op.getOperand(1), ShAmt);
9419 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9420 SelectionDAG &DAG) const {
9421 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9422 MFI->setReturnAddressIsTaken(true);
9424 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9425 DebugLoc dl = Op.getDebugLoc();
9428 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9430 DAG.getConstant(TD->getPointerSize(),
9431 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9432 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9433 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9435 MachinePointerInfo(), false, false, 0);
9438 // Just load the return address.
9439 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9440 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9441 RetAddrFI, MachinePointerInfo(), false, false, 0);
9444 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9445 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9446 MFI->setFrameAddressIsTaken(true);
9448 EVT VT = Op.getValueType();
9449 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9450 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9451 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9452 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9454 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9455 MachinePointerInfo(),
9460 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9461 SelectionDAG &DAG) const {
9462 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9465 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9466 MachineFunction &MF = DAG.getMachineFunction();
9467 SDValue Chain = Op.getOperand(0);
9468 SDValue Offset = Op.getOperand(1);
9469 SDValue Handler = Op.getOperand(2);
9470 DebugLoc dl = Op.getDebugLoc();
9472 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9473 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9475 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9477 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9478 DAG.getIntPtrConstant(TD->getPointerSize()));
9479 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9480 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9482 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9483 MF.getRegInfo().addLiveOut(StoreAddrReg);
9485 return DAG.getNode(X86ISD::EH_RETURN, dl,
9487 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9490 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9491 SelectionDAG &DAG) const {
9492 return Op.getOperand(0);
9495 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9496 SelectionDAG &DAG) const {
9497 SDValue Root = Op.getOperand(0);
9498 SDValue Trmp = Op.getOperand(1); // trampoline
9499 SDValue FPtr = Op.getOperand(2); // nested function
9500 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9501 DebugLoc dl = Op.getDebugLoc();
9503 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9505 if (Subtarget->is64Bit()) {
9506 SDValue OutChains[6];
9508 // Large code-model.
9509 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9510 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9512 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9513 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9515 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9517 // Load the pointer to the nested function into R11.
9518 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9519 SDValue Addr = Trmp;
9520 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9521 Addr, MachinePointerInfo(TrmpAddr),
9524 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9525 DAG.getConstant(2, MVT::i64));
9526 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9527 MachinePointerInfo(TrmpAddr, 2),
9530 // Load the 'nest' parameter value into R10.
9531 // R10 is specified in X86CallingConv.td
9532 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9533 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9534 DAG.getConstant(10, MVT::i64));
9535 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9536 Addr, MachinePointerInfo(TrmpAddr, 10),
9539 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9540 DAG.getConstant(12, MVT::i64));
9541 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9542 MachinePointerInfo(TrmpAddr, 12),
9545 // Jump to the nested function.
9546 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9547 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9548 DAG.getConstant(20, MVT::i64));
9549 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9550 Addr, MachinePointerInfo(TrmpAddr, 20),
9553 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9554 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9555 DAG.getConstant(22, MVT::i64));
9556 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9557 MachinePointerInfo(TrmpAddr, 22),
9560 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9562 const Function *Func =
9563 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9564 CallingConv::ID CC = Func->getCallingConv();
9569 llvm_unreachable("Unsupported calling convention");
9570 case CallingConv::C:
9571 case CallingConv::X86_StdCall: {
9572 // Pass 'nest' parameter in ECX.
9573 // Must be kept in sync with X86CallingConv.td
9576 // Check that ECX wasn't needed by an 'inreg' parameter.
9577 FunctionType *FTy = Func->getFunctionType();
9578 const AttrListPtr &Attrs = Func->getAttributes();
9580 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9581 unsigned InRegCount = 0;
9584 for (FunctionType::param_iterator I = FTy->param_begin(),
9585 E = FTy->param_end(); I != E; ++I, ++Idx)
9586 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9587 // FIXME: should only count parameters that are lowered to integers.
9588 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9590 if (InRegCount > 2) {
9591 report_fatal_error("Nest register in use - reduce number of inreg"
9597 case CallingConv::X86_FastCall:
9598 case CallingConv::X86_ThisCall:
9599 case CallingConv::Fast:
9600 // Pass 'nest' parameter in EAX.
9601 // Must be kept in sync with X86CallingConv.td
9606 SDValue OutChains[4];
9609 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9610 DAG.getConstant(10, MVT::i32));
9611 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9613 // This is storing the opcode for MOV32ri.
9614 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9615 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9616 OutChains[0] = DAG.getStore(Root, dl,
9617 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9618 Trmp, MachinePointerInfo(TrmpAddr),
9621 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9622 DAG.getConstant(1, MVT::i32));
9623 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9624 MachinePointerInfo(TrmpAddr, 1),
9627 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9628 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9629 DAG.getConstant(5, MVT::i32));
9630 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9631 MachinePointerInfo(TrmpAddr, 5),
9634 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9635 DAG.getConstant(6, MVT::i32));
9636 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9637 MachinePointerInfo(TrmpAddr, 6),
9640 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9644 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9645 SelectionDAG &DAG) const {
9647 The rounding mode is in bits 11:10 of FPSR, and has the following
9654 FLT_ROUNDS, on the other hand, expects the following:
9661 To perform the conversion, we do:
9662 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9665 MachineFunction &MF = DAG.getMachineFunction();
9666 const TargetMachine &TM = MF.getTarget();
9667 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9668 unsigned StackAlignment = TFI.getStackAlignment();
9669 EVT VT = Op.getValueType();
9670 DebugLoc DL = Op.getDebugLoc();
9672 // Save FP Control Word to stack slot
9673 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9674 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9677 MachineMemOperand *MMO =
9678 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9679 MachineMemOperand::MOStore, 2, 2);
9681 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9682 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9683 DAG.getVTList(MVT::Other),
9684 Ops, 2, MVT::i16, MMO);
9686 // Load FP Control Word from stack slot
9687 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9688 MachinePointerInfo(), false, false, 0);
9690 // Transform as necessary
9692 DAG.getNode(ISD::SRL, DL, MVT::i16,
9693 DAG.getNode(ISD::AND, DL, MVT::i16,
9694 CWD, DAG.getConstant(0x800, MVT::i16)),
9695 DAG.getConstant(11, MVT::i8));
9697 DAG.getNode(ISD::SRL, DL, MVT::i16,
9698 DAG.getNode(ISD::AND, DL, MVT::i16,
9699 CWD, DAG.getConstant(0x400, MVT::i16)),
9700 DAG.getConstant(9, MVT::i8));
9703 DAG.getNode(ISD::AND, DL, MVT::i16,
9704 DAG.getNode(ISD::ADD, DL, MVT::i16,
9705 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9706 DAG.getConstant(1, MVT::i16)),
9707 DAG.getConstant(3, MVT::i16));
9710 return DAG.getNode((VT.getSizeInBits() < 16 ?
9711 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9714 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9715 EVT VT = Op.getValueType();
9717 unsigned NumBits = VT.getSizeInBits();
9718 DebugLoc dl = Op.getDebugLoc();
9720 Op = Op.getOperand(0);
9721 if (VT == MVT::i8) {
9722 // Zero extend to i32 since there is not an i8 bsr.
9724 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9727 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9728 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9729 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9731 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9734 DAG.getConstant(NumBits+NumBits-1, OpVT),
9735 DAG.getConstant(X86::COND_E, MVT::i8),
9738 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9740 // Finally xor with NumBits-1.
9741 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9744 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9748 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9749 EVT VT = Op.getValueType();
9751 unsigned NumBits = VT.getSizeInBits();
9752 DebugLoc dl = Op.getDebugLoc();
9754 Op = Op.getOperand(0);
9755 if (VT == MVT::i8) {
9757 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9760 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9761 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9762 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9764 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9767 DAG.getConstant(NumBits, OpVT),
9768 DAG.getConstant(X86::COND_E, MVT::i8),
9771 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9774 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9778 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9779 // ones, and then concatenate the result back.
9780 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9781 EVT VT = Op.getValueType();
9783 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9784 "Unsupported value type for operation");
9786 int NumElems = VT.getVectorNumElements();
9787 DebugLoc dl = Op.getDebugLoc();
9788 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9789 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9791 // Extract the LHS vectors
9792 SDValue LHS = Op.getOperand(0);
9793 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9794 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9796 // Extract the RHS vectors
9797 SDValue RHS = Op.getOperand(1);
9798 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9799 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9801 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9802 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9804 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9805 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9806 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9809 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9810 assert(Op.getValueType().getSizeInBits() == 256 &&
9811 Op.getValueType().isInteger() &&
9812 "Only handle AVX 256-bit vector integer operation");
9813 return Lower256IntArith(Op, DAG);
9816 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9817 assert(Op.getValueType().getSizeInBits() == 256 &&
9818 Op.getValueType().isInteger() &&
9819 "Only handle AVX 256-bit vector integer operation");
9820 return Lower256IntArith(Op, DAG);
9823 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9824 EVT VT = Op.getValueType();
9826 // Decompose 256-bit ops into smaller 128-bit ops.
9827 if (VT.getSizeInBits() == 256)
9828 return Lower256IntArith(Op, DAG);
9830 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9831 DebugLoc dl = Op.getDebugLoc();
9833 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9834 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9835 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9836 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9837 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9839 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9840 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9841 // return AloBlo + AloBhi + AhiBlo;
9843 SDValue A = Op.getOperand(0);
9844 SDValue B = Op.getOperand(1);
9846 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9847 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9848 A, DAG.getConstant(32, MVT::i32));
9849 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9850 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9851 B, DAG.getConstant(32, MVT::i32));
9852 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9853 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9855 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9856 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9858 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9859 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9861 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9862 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9863 AloBhi, DAG.getConstant(32, MVT::i32));
9864 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9865 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9866 AhiBlo, DAG.getConstant(32, MVT::i32));
9867 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9868 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9872 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9874 EVT VT = Op.getValueType();
9875 DebugLoc dl = Op.getDebugLoc();
9876 SDValue R = Op.getOperand(0);
9877 SDValue Amt = Op.getOperand(1);
9878 LLVMContext *Context = DAG.getContext();
9880 if (!Subtarget->hasXMMInt())
9883 // Decompose 256-bit shifts into smaller 128-bit shifts.
9884 if (VT.getSizeInBits() == 256) {
9885 int NumElems = VT.getVectorNumElements();
9886 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9887 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9889 // Extract the two vectors
9890 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9891 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9894 // Recreate the shift amount vectors
9896 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9897 // Constant shift amount
9898 SmallVector<SDValue, 4> Amt1Csts;
9899 SmallVector<SDValue, 4> Amt2Csts;
9900 for (int i = 0; i < NumElems/2; ++i)
9901 Amt1Csts.push_back(Amt->getOperand(i));
9902 for (int i = NumElems/2; i < NumElems; ++i)
9903 Amt2Csts.push_back(Amt->getOperand(i));
9905 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9906 &Amt1Csts[0], NumElems/2);
9907 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9908 &Amt2Csts[0], NumElems/2);
9910 // Variable shift amount
9911 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9912 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9916 // Issue new vector shifts for the smaller types
9917 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9918 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9920 // Concatenate the result back
9921 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9924 // Optimize shl/srl/sra with constant shift amount.
9925 if (isSplatVector(Amt.getNode())) {
9926 SDValue SclrAmt = Amt->getOperand(0);
9927 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9928 uint64_t ShiftAmt = C->getZExtValue();
9930 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9931 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9932 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9933 R, DAG.getConstant(ShiftAmt, MVT::i32));
9935 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9936 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9937 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9938 R, DAG.getConstant(ShiftAmt, MVT::i32));
9940 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9941 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9942 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9943 R, DAG.getConstant(ShiftAmt, MVT::i32));
9945 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9946 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9947 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9948 R, DAG.getConstant(ShiftAmt, MVT::i32));
9950 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9951 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9952 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9953 R, DAG.getConstant(ShiftAmt, MVT::i32));
9955 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9956 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9957 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9958 R, DAG.getConstant(ShiftAmt, MVT::i32));
9960 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9961 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9962 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9963 R, DAG.getConstant(ShiftAmt, MVT::i32));
9965 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9966 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9967 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9968 R, DAG.getConstant(ShiftAmt, MVT::i32));
9972 // Lower SHL with variable shift amount.
9973 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9974 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9975 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9976 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9978 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9980 std::vector<Constant*> CV(4, CI);
9981 Constant *C = ConstantVector::get(CV);
9982 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9983 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9984 MachinePointerInfo::getConstantPool(),
9987 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9988 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9989 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9990 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9992 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9994 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9995 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9996 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9998 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9999 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
10001 std::vector<Constant*> CVM1(16, CM1);
10002 std::vector<Constant*> CVM2(16, CM2);
10003 Constant *C = ConstantVector::get(CVM1);
10004 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10005 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10006 MachinePointerInfo::getConstantPool(),
10009 // r = pblendv(r, psllw(r & (char16)15, 4), a);
10010 M = DAG.getNode(ISD::AND, dl, VT, R, M);
10011 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10012 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10013 DAG.getConstant(4, MVT::i32));
10014 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
10016 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10018 C = ConstantVector::get(CVM2);
10019 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10020 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10021 MachinePointerInfo::getConstantPool(),
10024 // r = pblendv(r, psllw(r & (char16)63, 2), a);
10025 M = DAG.getNode(ISD::AND, dl, VT, R, M);
10026 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10027 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10028 DAG.getConstant(2, MVT::i32));
10029 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
10031 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10033 // return pblendv(r, r+r, a);
10034 R = DAG.getNode(ISD::VSELECT, dl, VT, Op,
10035 R, DAG.getNode(ISD::ADD, dl, VT, R, R));
10041 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10042 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10043 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10044 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10045 // has only one use.
10046 SDNode *N = Op.getNode();
10047 SDValue LHS = N->getOperand(0);
10048 SDValue RHS = N->getOperand(1);
10049 unsigned BaseOp = 0;
10051 DebugLoc DL = Op.getDebugLoc();
10052 switch (Op.getOpcode()) {
10053 default: llvm_unreachable("Unknown ovf instruction!");
10055 // A subtract of one will be selected as a INC. Note that INC doesn't
10056 // set CF, so we can't do this for UADDO.
10057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10059 BaseOp = X86ISD::INC;
10060 Cond = X86::COND_O;
10063 BaseOp = X86ISD::ADD;
10064 Cond = X86::COND_O;
10067 BaseOp = X86ISD::ADD;
10068 Cond = X86::COND_B;
10071 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10072 // set CF, so we can't do this for USUBO.
10073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10075 BaseOp = X86ISD::DEC;
10076 Cond = X86::COND_O;
10079 BaseOp = X86ISD::SUB;
10080 Cond = X86::COND_O;
10083 BaseOp = X86ISD::SUB;
10084 Cond = X86::COND_B;
10087 BaseOp = X86ISD::SMUL;
10088 Cond = X86::COND_O;
10090 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10091 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10093 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10096 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10097 DAG.getConstant(X86::COND_O, MVT::i32),
10098 SDValue(Sum.getNode(), 2));
10100 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10104 // Also sets EFLAGS.
10105 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10106 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10109 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10110 DAG.getConstant(Cond, MVT::i32),
10111 SDValue(Sum.getNode(), 1));
10113 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10116 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
10117 DebugLoc dl = Op.getDebugLoc();
10118 SDNode* Node = Op.getNode();
10119 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
10120 EVT VT = Node->getValueType(0);
10121 if (Subtarget->hasXMMInt() && VT.isVector()) {
10122 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10123 ExtraVT.getScalarType().getSizeInBits();
10124 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10126 unsigned SHLIntrinsicsID = 0;
10127 unsigned SRAIntrinsicsID = 0;
10128 switch (VT.getSimpleVT().SimpleTy) {
10132 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10133 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10137 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10138 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10143 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10144 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10145 Node->getOperand(0), ShAmt);
10147 // In case of 1 bit sext, no need to shr
10148 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
10150 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10151 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10159 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10160 DebugLoc dl = Op.getDebugLoc();
10162 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10163 // There isn't any reason to disable it if the target processor supports it.
10164 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) {
10165 SDValue Chain = Op.getOperand(0);
10166 SDValue Zero = DAG.getConstant(0, MVT::i32);
10168 DAG.getRegister(X86::ESP, MVT::i32), // Base
10169 DAG.getTargetConstant(1, MVT::i8), // Scale
10170 DAG.getRegister(0, MVT::i32), // Index
10171 DAG.getTargetConstant(0, MVT::i32), // Disp
10172 DAG.getRegister(0, MVT::i32), // Segment.
10177 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10178 array_lengthof(Ops));
10179 return SDValue(Res, 0);
10182 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10184 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10186 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10187 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10188 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10189 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10191 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10192 if (!Op1 && !Op2 && !Op3 && Op4)
10193 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10195 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10196 if (Op1 && !Op2 && !Op3 && !Op4)
10197 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10199 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10201 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10204 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10205 SelectionDAG &DAG) const {
10206 DebugLoc dl = Op.getDebugLoc();
10207 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10208 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10209 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10210 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10212 // The only fence that needs an instruction is a sequentially-consistent
10213 // cross-thread fence.
10214 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10215 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10216 // no-sse2). There isn't any reason to disable it if the target processor
10218 if (Subtarget->hasXMMInt() || Subtarget->is64Bit())
10219 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10221 SDValue Chain = Op.getOperand(0);
10222 SDValue Zero = DAG.getConstant(0, MVT::i32);
10224 DAG.getRegister(X86::ESP, MVT::i32), // Base
10225 DAG.getTargetConstant(1, MVT::i8), // Scale
10226 DAG.getRegister(0, MVT::i32), // Index
10227 DAG.getTargetConstant(0, MVT::i32), // Disp
10228 DAG.getRegister(0, MVT::i32), // Segment.
10233 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10234 array_lengthof(Ops));
10235 return SDValue(Res, 0);
10238 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10239 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10243 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10244 EVT T = Op.getValueType();
10245 DebugLoc DL = Op.getDebugLoc();
10248 switch(T.getSimpleVT().SimpleTy) {
10250 assert(false && "Invalid value type!");
10251 case MVT::i8: Reg = X86::AL; size = 1; break;
10252 case MVT::i16: Reg = X86::AX; size = 2; break;
10253 case MVT::i32: Reg = X86::EAX; size = 4; break;
10255 assert(Subtarget->is64Bit() && "Node not type legal!");
10256 Reg = X86::RAX; size = 8;
10259 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10260 Op.getOperand(2), SDValue());
10261 SDValue Ops[] = { cpIn.getValue(0),
10264 DAG.getTargetConstant(size, MVT::i8),
10265 cpIn.getValue(1) };
10266 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10267 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10268 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10271 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10275 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10276 SelectionDAG &DAG) const {
10277 assert(Subtarget->is64Bit() && "Result not type legalized?");
10278 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10279 SDValue TheChain = Op.getOperand(0);
10280 DebugLoc dl = Op.getDebugLoc();
10281 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10282 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10283 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10285 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10286 DAG.getConstant(32, MVT::i8));
10288 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10291 return DAG.getMergeValues(Ops, 2, dl);
10294 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10295 SelectionDAG &DAG) const {
10296 EVT SrcVT = Op.getOperand(0).getValueType();
10297 EVT DstVT = Op.getValueType();
10298 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() &&
10299 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10300 assert((DstVT == MVT::i64 ||
10301 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10302 "Unexpected custom BITCAST");
10303 // i64 <=> MMX conversions are Legal.
10304 if (SrcVT==MVT::i64 && DstVT.isVector())
10306 if (DstVT==MVT::i64 && SrcVT.isVector())
10308 // MMX <=> MMX conversions are Legal.
10309 if (SrcVT.isVector() && DstVT.isVector())
10311 // All other conversions need to be expanded.
10315 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10316 SDNode *Node = Op.getNode();
10317 DebugLoc dl = Node->getDebugLoc();
10318 EVT T = Node->getValueType(0);
10319 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10320 DAG.getConstant(0, T), Node->getOperand(2));
10321 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10322 cast<AtomicSDNode>(Node)->getMemoryVT(),
10323 Node->getOperand(0),
10324 Node->getOperand(1), negOp,
10325 cast<AtomicSDNode>(Node)->getSrcValue(),
10326 cast<AtomicSDNode>(Node)->getAlignment(),
10327 cast<AtomicSDNode>(Node)->getOrdering(),
10328 cast<AtomicSDNode>(Node)->getSynchScope());
10331 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10332 SDNode *Node = Op.getNode();
10333 DebugLoc dl = Node->getDebugLoc();
10334 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10336 // Convert seq_cst store -> xchg
10337 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10338 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10339 // (The only way to get a 16-byte store is cmpxchg16b)
10340 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10341 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10342 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10343 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10344 cast<AtomicSDNode>(Node)->getMemoryVT(),
10345 Node->getOperand(0),
10346 Node->getOperand(1), Node->getOperand(2),
10347 cast<AtomicSDNode>(Node)->getMemOperand(),
10348 cast<AtomicSDNode>(Node)->getOrdering(),
10349 cast<AtomicSDNode>(Node)->getSynchScope());
10350 return Swap.getValue(1);
10352 // Other atomic stores have a simple pattern.
10356 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10357 EVT VT = Op.getNode()->getValueType(0);
10359 // Let legalize expand this if it isn't a legal type yet.
10360 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10363 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10366 bool ExtraOp = false;
10367 switch (Op.getOpcode()) {
10368 default: assert(0 && "Invalid code");
10369 case ISD::ADDC: Opc = X86ISD::ADD; break;
10370 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10371 case ISD::SUBC: Opc = X86ISD::SUB; break;
10372 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10376 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10378 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10379 Op.getOperand(1), Op.getOperand(2));
10382 /// LowerOperation - Provide custom lowering hooks for some operations.
10384 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10385 switch (Op.getOpcode()) {
10386 default: llvm_unreachable("Should not custom lower this!");
10387 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10388 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10389 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10390 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10391 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10392 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10393 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10394 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10395 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10396 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10397 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10398 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10399 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10400 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10401 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10402 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10403 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10404 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10405 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10406 case ISD::SHL_PARTS:
10407 case ISD::SRA_PARTS:
10408 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10409 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10410 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10411 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10412 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10413 case ISD::FABS: return LowerFABS(Op, DAG);
10414 case ISD::FNEG: return LowerFNEG(Op, DAG);
10415 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10416 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10417 case ISD::SETCC: return LowerSETCC(Op, DAG);
10418 case ISD::SELECT: return LowerSELECT(Op, DAG);
10419 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10420 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10421 case ISD::VASTART: return LowerVASTART(Op, DAG);
10422 case ISD::VAARG: return LowerVAARG(Op, DAG);
10423 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10424 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10425 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10426 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10427 case ISD::FRAME_TO_ARGS_OFFSET:
10428 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10429 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10430 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10431 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10432 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10433 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10434 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10435 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10436 case ISD::MUL: return LowerMUL(Op, DAG);
10439 case ISD::SHL: return LowerShift(Op, DAG);
10445 case ISD::UMULO: return LowerXALUO(Op, DAG);
10446 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10447 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10451 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10452 case ISD::ADD: return LowerADD(Op, DAG);
10453 case ISD::SUB: return LowerSUB(Op, DAG);
10457 static void ReplaceATOMIC_LOAD(SDNode *Node,
10458 SmallVectorImpl<SDValue> &Results,
10459 SelectionDAG &DAG) {
10460 DebugLoc dl = Node->getDebugLoc();
10461 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10463 // Convert wide load -> cmpxchg8b/cmpxchg16b
10464 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10465 // (The only way to get a 16-byte load is cmpxchg16b)
10466 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10467 SDValue Zero = DAG.getConstant(0, VT);
10468 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10469 Node->getOperand(0),
10470 Node->getOperand(1), Zero, Zero,
10471 cast<AtomicSDNode>(Node)->getMemOperand(),
10472 cast<AtomicSDNode>(Node)->getOrdering(),
10473 cast<AtomicSDNode>(Node)->getSynchScope());
10474 Results.push_back(Swap.getValue(0));
10475 Results.push_back(Swap.getValue(1));
10478 void X86TargetLowering::
10479 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10480 SelectionDAG &DAG, unsigned NewOp) const {
10481 DebugLoc dl = Node->getDebugLoc();
10482 assert (Node->getValueType(0) == MVT::i64 &&
10483 "Only know how to expand i64 atomics");
10485 SDValue Chain = Node->getOperand(0);
10486 SDValue In1 = Node->getOperand(1);
10487 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10488 Node->getOperand(2), DAG.getIntPtrConstant(0));
10489 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10490 Node->getOperand(2), DAG.getIntPtrConstant(1));
10491 SDValue Ops[] = { Chain, In1, In2L, In2H };
10492 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10494 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10495 cast<MemSDNode>(Node)->getMemOperand());
10496 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10497 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10498 Results.push_back(Result.getValue(2));
10501 /// ReplaceNodeResults - Replace a node with an illegal result type
10502 /// with a new node built out of custom code.
10503 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10504 SmallVectorImpl<SDValue>&Results,
10505 SelectionDAG &DAG) const {
10506 DebugLoc dl = N->getDebugLoc();
10507 switch (N->getOpcode()) {
10509 assert(false && "Do not know how to custom type legalize this operation!");
10511 case ISD::SIGN_EXTEND_INREG:
10516 // We don't want to expand or promote these.
10518 case ISD::FP_TO_SINT: {
10519 std::pair<SDValue,SDValue> Vals =
10520 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10521 SDValue FIST = Vals.first, StackSlot = Vals.second;
10522 if (FIST.getNode() != 0) {
10523 EVT VT = N->getValueType(0);
10524 // Return a load from the stack slot.
10525 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10526 MachinePointerInfo(), false, false, 0));
10530 case ISD::READCYCLECOUNTER: {
10531 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10532 SDValue TheChain = N->getOperand(0);
10533 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10534 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10536 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10538 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10539 SDValue Ops[] = { eax, edx };
10540 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10541 Results.push_back(edx.getValue(1));
10544 case ISD::ATOMIC_CMP_SWAP: {
10545 EVT T = N->getValueType(0);
10546 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10547 bool Regs64bit = T == MVT::i128;
10548 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10549 SDValue cpInL, cpInH;
10550 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10551 DAG.getConstant(0, HalfT));
10552 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10553 DAG.getConstant(1, HalfT));
10554 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10555 Regs64bit ? X86::RAX : X86::EAX,
10557 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10558 Regs64bit ? X86::RDX : X86::EDX,
10559 cpInH, cpInL.getValue(1));
10560 SDValue swapInL, swapInH;
10561 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10562 DAG.getConstant(0, HalfT));
10563 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10564 DAG.getConstant(1, HalfT));
10565 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10566 Regs64bit ? X86::RBX : X86::EBX,
10567 swapInL, cpInH.getValue(1));
10568 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10569 Regs64bit ? X86::RCX : X86::ECX,
10570 swapInH, swapInL.getValue(1));
10571 SDValue Ops[] = { swapInH.getValue(0),
10573 swapInH.getValue(1) };
10574 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10575 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10576 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10577 X86ISD::LCMPXCHG8_DAG;
10578 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10580 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10581 Regs64bit ? X86::RAX : X86::EAX,
10582 HalfT, Result.getValue(1));
10583 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10584 Regs64bit ? X86::RDX : X86::EDX,
10585 HalfT, cpOutL.getValue(2));
10586 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10587 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10588 Results.push_back(cpOutH.getValue(1));
10591 case ISD::ATOMIC_LOAD_ADD:
10592 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10594 case ISD::ATOMIC_LOAD_AND:
10595 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10597 case ISD::ATOMIC_LOAD_NAND:
10598 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10600 case ISD::ATOMIC_LOAD_OR:
10601 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10603 case ISD::ATOMIC_LOAD_SUB:
10604 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10606 case ISD::ATOMIC_LOAD_XOR:
10607 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10609 case ISD::ATOMIC_SWAP:
10610 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10612 case ISD::ATOMIC_LOAD:
10613 ReplaceATOMIC_LOAD(N, Results, DAG);
10617 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10619 default: return NULL;
10620 case X86ISD::BSF: return "X86ISD::BSF";
10621 case X86ISD::BSR: return "X86ISD::BSR";
10622 case X86ISD::SHLD: return "X86ISD::SHLD";
10623 case X86ISD::SHRD: return "X86ISD::SHRD";
10624 case X86ISD::FAND: return "X86ISD::FAND";
10625 case X86ISD::FOR: return "X86ISD::FOR";
10626 case X86ISD::FXOR: return "X86ISD::FXOR";
10627 case X86ISD::FSRL: return "X86ISD::FSRL";
10628 case X86ISD::FILD: return "X86ISD::FILD";
10629 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10630 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10631 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10632 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10633 case X86ISD::FLD: return "X86ISD::FLD";
10634 case X86ISD::FST: return "X86ISD::FST";
10635 case X86ISD::CALL: return "X86ISD::CALL";
10636 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10637 case X86ISD::BT: return "X86ISD::BT";
10638 case X86ISD::CMP: return "X86ISD::CMP";
10639 case X86ISD::COMI: return "X86ISD::COMI";
10640 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10641 case X86ISD::SETCC: return "X86ISD::SETCC";
10642 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10643 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10644 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10645 case X86ISD::CMOV: return "X86ISD::CMOV";
10646 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10647 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10648 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10649 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10650 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10651 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10652 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10653 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10654 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10655 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10656 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10657 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10658 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10659 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10660 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10661 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10662 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10663 case X86ISD::FMAX: return "X86ISD::FMAX";
10664 case X86ISD::FMIN: return "X86ISD::FMIN";
10665 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10666 case X86ISD::FRCP: return "X86ISD::FRCP";
10667 case X86ISD::FHADD: return "X86ISD::FHADD";
10668 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10669 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10670 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10671 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10672 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10673 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10674 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10675 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10676 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10677 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10678 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10679 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10680 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10681 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10682 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10683 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10684 case X86ISD::VSHL: return "X86ISD::VSHL";
10685 case X86ISD::VSRL: return "X86ISD::VSRL";
10686 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10687 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10688 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10689 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10690 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10691 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10692 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10693 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10694 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10695 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10696 case X86ISD::ADD: return "X86ISD::ADD";
10697 case X86ISD::SUB: return "X86ISD::SUB";
10698 case X86ISD::ADC: return "X86ISD::ADC";
10699 case X86ISD::SBB: return "X86ISD::SBB";
10700 case X86ISD::SMUL: return "X86ISD::SMUL";
10701 case X86ISD::UMUL: return "X86ISD::UMUL";
10702 case X86ISD::INC: return "X86ISD::INC";
10703 case X86ISD::DEC: return "X86ISD::DEC";
10704 case X86ISD::OR: return "X86ISD::OR";
10705 case X86ISD::XOR: return "X86ISD::XOR";
10706 case X86ISD::AND: return "X86ISD::AND";
10707 case X86ISD::ANDN: return "X86ISD::ANDN";
10708 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10709 case X86ISD::PTEST: return "X86ISD::PTEST";
10710 case X86ISD::TESTP: return "X86ISD::TESTP";
10711 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10712 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10713 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10714 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10715 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10716 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10717 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10718 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10719 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10720 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10721 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10722 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10723 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10724 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10725 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10726 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10727 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10728 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10729 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10730 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10731 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10732 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10733 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10734 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10735 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10736 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10737 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10738 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10739 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10740 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10741 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10742 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10743 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10744 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10745 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10746 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10747 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10748 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10749 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10750 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10751 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10752 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10753 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10754 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10755 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
10759 // isLegalAddressingMode - Return true if the addressing mode represented
10760 // by AM is legal for this target, for a load/store of the specified type.
10761 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10763 // X86 supports extremely general addressing modes.
10764 CodeModel::Model M = getTargetMachine().getCodeModel();
10765 Reloc::Model R = getTargetMachine().getRelocationModel();
10767 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10768 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10773 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10775 // If a reference to this global requires an extra load, we can't fold it.
10776 if (isGlobalStubReference(GVFlags))
10779 // If BaseGV requires a register for the PIC base, we cannot also have a
10780 // BaseReg specified.
10781 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10784 // If lower 4G is not available, then we must use rip-relative addressing.
10785 if ((M != CodeModel::Small || R != Reloc::Static) &&
10786 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10790 switch (AM.Scale) {
10796 // These scales always work.
10801 // These scales are formed with basereg+scalereg. Only accept if there is
10806 default: // Other stuff never works.
10814 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10815 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10817 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10818 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10819 if (NumBits1 <= NumBits2)
10824 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10825 if (!VT1.isInteger() || !VT2.isInteger())
10827 unsigned NumBits1 = VT1.getSizeInBits();
10828 unsigned NumBits2 = VT2.getSizeInBits();
10829 if (NumBits1 <= NumBits2)
10834 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10835 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10836 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10839 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10840 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10841 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10844 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10845 // i16 instructions are longer (0x66 prefix) and potentially slower.
10846 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10849 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10850 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10851 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10852 /// are assumed to be legal.
10854 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10856 // Very little shuffling can be done for 64-bit vectors right now.
10857 if (VT.getSizeInBits() == 64)
10858 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX());
10860 // FIXME: pshufb, blends, shifts.
10861 return (VT.getVectorNumElements() == 2 ||
10862 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10863 isMOVLMask(M, VT) ||
10864 isSHUFPMask(M, VT) ||
10865 isPSHUFDMask(M, VT) ||
10866 isPSHUFHWMask(M, VT) ||
10867 isPSHUFLWMask(M, VT) ||
10868 isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()) ||
10869 isUNPCKLMask(M, VT) ||
10870 isUNPCKHMask(M, VT) ||
10871 isUNPCKL_v_undef_Mask(M, VT) ||
10872 isUNPCKH_v_undef_Mask(M, VT));
10876 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10878 unsigned NumElts = VT.getVectorNumElements();
10879 // FIXME: This collection of masks seems suspect.
10882 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10883 return (isMOVLMask(Mask, VT) ||
10884 isCommutedMOVLMask(Mask, VT, true) ||
10885 isSHUFPMask(Mask, VT) ||
10886 isCommutedSHUFPMask(Mask, VT));
10891 //===----------------------------------------------------------------------===//
10892 // X86 Scheduler Hooks
10893 //===----------------------------------------------------------------------===//
10895 // private utility function
10896 MachineBasicBlock *
10897 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10898 MachineBasicBlock *MBB,
10905 TargetRegisterClass *RC,
10906 bool invSrc) const {
10907 // For the atomic bitwise operator, we generate
10910 // ld t1 = [bitinstr.addr]
10911 // op t2 = t1, [bitinstr.val]
10913 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10915 // fallthrough -->nextMBB
10916 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10917 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10918 MachineFunction::iterator MBBIter = MBB;
10921 /// First build the CFG
10922 MachineFunction *F = MBB->getParent();
10923 MachineBasicBlock *thisMBB = MBB;
10924 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10925 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10926 F->insert(MBBIter, newMBB);
10927 F->insert(MBBIter, nextMBB);
10929 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10930 nextMBB->splice(nextMBB->begin(), thisMBB,
10931 llvm::next(MachineBasicBlock::iterator(bInstr)),
10933 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10935 // Update thisMBB to fall through to newMBB
10936 thisMBB->addSuccessor(newMBB);
10938 // newMBB jumps to itself and fall through to nextMBB
10939 newMBB->addSuccessor(nextMBB);
10940 newMBB->addSuccessor(newMBB);
10942 // Insert instructions into newMBB based on incoming instruction
10943 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10944 "unexpected number of operands");
10945 DebugLoc dl = bInstr->getDebugLoc();
10946 MachineOperand& destOper = bInstr->getOperand(0);
10947 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10948 int numArgs = bInstr->getNumOperands() - 1;
10949 for (int i=0; i < numArgs; ++i)
10950 argOpers[i] = &bInstr->getOperand(i+1);
10952 // x86 address has 4 operands: base, index, scale, and displacement
10953 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10954 int valArgIndx = lastAddrIndx + 1;
10956 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10957 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10958 for (int i=0; i <= lastAddrIndx; ++i)
10959 (*MIB).addOperand(*argOpers[i]);
10961 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10963 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10968 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10969 assert((argOpers[valArgIndx]->isReg() ||
10970 argOpers[valArgIndx]->isImm()) &&
10971 "invalid operand");
10972 if (argOpers[valArgIndx]->isReg())
10973 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10975 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10977 (*MIB).addOperand(*argOpers[valArgIndx]);
10979 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10982 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10983 for (int i=0; i <= lastAddrIndx; ++i)
10984 (*MIB).addOperand(*argOpers[i]);
10986 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10987 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10988 bInstr->memoperands_end());
10990 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10991 MIB.addReg(EAXreg);
10994 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10996 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11000 // private utility function: 64 bit atomics on 32 bit host.
11001 MachineBasicBlock *
11002 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11003 MachineBasicBlock *MBB,
11008 bool invSrc) const {
11009 // For the atomic bitwise operator, we generate
11010 // thisMBB (instructions are in pairs, except cmpxchg8b)
11011 // ld t1,t2 = [bitinstr.addr]
11013 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11014 // op t5, t6 <- out1, out2, [bitinstr.val]
11015 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11016 // mov ECX, EBX <- t5, t6
11017 // mov EAX, EDX <- t1, t2
11018 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11019 // mov t3, t4 <- EAX, EDX
11021 // result in out1, out2
11022 // fallthrough -->nextMBB
11024 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11025 const unsigned LoadOpc = X86::MOV32rm;
11026 const unsigned NotOpc = X86::NOT32r;
11027 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11028 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11029 MachineFunction::iterator MBBIter = MBB;
11032 /// First build the CFG
11033 MachineFunction *F = MBB->getParent();
11034 MachineBasicBlock *thisMBB = MBB;
11035 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11036 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11037 F->insert(MBBIter, newMBB);
11038 F->insert(MBBIter, nextMBB);
11040 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11041 nextMBB->splice(nextMBB->begin(), thisMBB,
11042 llvm::next(MachineBasicBlock::iterator(bInstr)),
11044 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11046 // Update thisMBB to fall through to newMBB
11047 thisMBB->addSuccessor(newMBB);
11049 // newMBB jumps to itself and fall through to nextMBB
11050 newMBB->addSuccessor(nextMBB);
11051 newMBB->addSuccessor(newMBB);
11053 DebugLoc dl = bInstr->getDebugLoc();
11054 // Insert instructions into newMBB based on incoming instruction
11055 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11056 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11057 "unexpected number of operands");
11058 MachineOperand& dest1Oper = bInstr->getOperand(0);
11059 MachineOperand& dest2Oper = bInstr->getOperand(1);
11060 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11061 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11062 argOpers[i] = &bInstr->getOperand(i+2);
11064 // We use some of the operands multiple times, so conservatively just
11065 // clear any kill flags that might be present.
11066 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11067 argOpers[i]->setIsKill(false);
11070 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11071 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11073 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11074 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11075 for (int i=0; i <= lastAddrIndx; ++i)
11076 (*MIB).addOperand(*argOpers[i]);
11077 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11078 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11079 // add 4 to displacement.
11080 for (int i=0; i <= lastAddrIndx-2; ++i)
11081 (*MIB).addOperand(*argOpers[i]);
11082 MachineOperand newOp3 = *(argOpers[3]);
11083 if (newOp3.isImm())
11084 newOp3.setImm(newOp3.getImm()+4);
11086 newOp3.setOffset(newOp3.getOffset()+4);
11087 (*MIB).addOperand(newOp3);
11088 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11090 // t3/4 are defined later, at the bottom of the loop
11091 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11092 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11093 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11094 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11095 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11096 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11098 // The subsequent operations should be using the destination registers of
11099 //the PHI instructions.
11101 t1 = F->getRegInfo().createVirtualRegister(RC);
11102 t2 = F->getRegInfo().createVirtualRegister(RC);
11103 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11104 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11106 t1 = dest1Oper.getReg();
11107 t2 = dest2Oper.getReg();
11110 int valArgIndx = lastAddrIndx + 1;
11111 assert((argOpers[valArgIndx]->isReg() ||
11112 argOpers[valArgIndx]->isImm()) &&
11113 "invalid operand");
11114 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11115 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11116 if (argOpers[valArgIndx]->isReg())
11117 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11119 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11120 if (regOpcL != X86::MOV32rr)
11122 (*MIB).addOperand(*argOpers[valArgIndx]);
11123 assert(argOpers[valArgIndx + 1]->isReg() ==
11124 argOpers[valArgIndx]->isReg());
11125 assert(argOpers[valArgIndx + 1]->isImm() ==
11126 argOpers[valArgIndx]->isImm());
11127 if (argOpers[valArgIndx + 1]->isReg())
11128 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11130 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11131 if (regOpcH != X86::MOV32rr)
11133 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11135 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11137 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11140 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11142 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11145 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11146 for (int i=0; i <= lastAddrIndx; ++i)
11147 (*MIB).addOperand(*argOpers[i]);
11149 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11150 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11151 bInstr->memoperands_end());
11153 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11154 MIB.addReg(X86::EAX);
11155 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11156 MIB.addReg(X86::EDX);
11159 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11161 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11165 // private utility function
11166 MachineBasicBlock *
11167 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11168 MachineBasicBlock *MBB,
11169 unsigned cmovOpc) const {
11170 // For the atomic min/max operator, we generate
11173 // ld t1 = [min/max.addr]
11174 // mov t2 = [min/max.val]
11176 // cmov[cond] t2 = t1
11178 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11180 // fallthrough -->nextMBB
11182 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11183 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11184 MachineFunction::iterator MBBIter = MBB;
11187 /// First build the CFG
11188 MachineFunction *F = MBB->getParent();
11189 MachineBasicBlock *thisMBB = MBB;
11190 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11191 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11192 F->insert(MBBIter, newMBB);
11193 F->insert(MBBIter, nextMBB);
11195 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11196 nextMBB->splice(nextMBB->begin(), thisMBB,
11197 llvm::next(MachineBasicBlock::iterator(mInstr)),
11199 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11201 // Update thisMBB to fall through to newMBB
11202 thisMBB->addSuccessor(newMBB);
11204 // newMBB jumps to newMBB and fall through to nextMBB
11205 newMBB->addSuccessor(nextMBB);
11206 newMBB->addSuccessor(newMBB);
11208 DebugLoc dl = mInstr->getDebugLoc();
11209 // Insert instructions into newMBB based on incoming instruction
11210 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11211 "unexpected number of operands");
11212 MachineOperand& destOper = mInstr->getOperand(0);
11213 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11214 int numArgs = mInstr->getNumOperands() - 1;
11215 for (int i=0; i < numArgs; ++i)
11216 argOpers[i] = &mInstr->getOperand(i+1);
11218 // x86 address has 4 operands: base, index, scale, and displacement
11219 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11220 int valArgIndx = lastAddrIndx + 1;
11222 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11223 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11224 for (int i=0; i <= lastAddrIndx; ++i)
11225 (*MIB).addOperand(*argOpers[i]);
11227 // We only support register and immediate values
11228 assert((argOpers[valArgIndx]->isReg() ||
11229 argOpers[valArgIndx]->isImm()) &&
11230 "invalid operand");
11232 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11233 if (argOpers[valArgIndx]->isReg())
11234 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11236 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11237 (*MIB).addOperand(*argOpers[valArgIndx]);
11239 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11242 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11247 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11248 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11252 // Cmp and exchange if none has modified the memory location
11253 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11254 for (int i=0; i <= lastAddrIndx; ++i)
11255 (*MIB).addOperand(*argOpers[i]);
11257 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11258 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11259 mInstr->memoperands_end());
11261 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11262 MIB.addReg(X86::EAX);
11265 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11267 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11271 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11272 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11273 // in the .td file.
11274 MachineBasicBlock *
11275 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11276 unsigned numArgs, bool memArg) const {
11277 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
11278 "Target must have SSE4.2 or AVX features enabled");
11280 DebugLoc dl = MI->getDebugLoc();
11281 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11283 if (!Subtarget->hasAVX()) {
11285 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11287 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11290 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11292 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11295 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11296 for (unsigned i = 0; i < numArgs; ++i) {
11297 MachineOperand &Op = MI->getOperand(i+1);
11298 if (!(Op.isReg() && Op.isImplicit()))
11299 MIB.addOperand(Op);
11301 BuildMI(*BB, MI, dl,
11302 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11303 MI->getOperand(0).getReg())
11304 .addReg(X86::XMM0);
11306 MI->eraseFromParent();
11310 MachineBasicBlock *
11311 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11312 DebugLoc dl = MI->getDebugLoc();
11313 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11315 // Address into RAX/EAX, other two args into ECX, EDX.
11316 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11317 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11318 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11319 for (int i = 0; i < X86::AddrNumOperands; ++i)
11320 MIB.addOperand(MI->getOperand(i));
11322 unsigned ValOps = X86::AddrNumOperands;
11323 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11324 .addReg(MI->getOperand(ValOps).getReg());
11325 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11326 .addReg(MI->getOperand(ValOps+1).getReg());
11328 // The instruction doesn't actually take any operands though.
11329 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11331 MI->eraseFromParent(); // The pseudo is gone now.
11335 MachineBasicBlock *
11336 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11337 DebugLoc dl = MI->getDebugLoc();
11338 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11340 // First arg in ECX, the second in EAX.
11341 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11342 .addReg(MI->getOperand(0).getReg());
11343 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11344 .addReg(MI->getOperand(1).getReg());
11346 // The instruction doesn't actually take any operands though.
11347 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11349 MI->eraseFromParent(); // The pseudo is gone now.
11353 MachineBasicBlock *
11354 X86TargetLowering::EmitVAARG64WithCustomInserter(
11356 MachineBasicBlock *MBB) const {
11357 // Emit va_arg instruction on X86-64.
11359 // Operands to this pseudo-instruction:
11360 // 0 ) Output : destination address (reg)
11361 // 1-5) Input : va_list address (addr, i64mem)
11362 // 6 ) ArgSize : Size (in bytes) of vararg type
11363 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11364 // 8 ) Align : Alignment of type
11365 // 9 ) EFLAGS (implicit-def)
11367 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11368 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11370 unsigned DestReg = MI->getOperand(0).getReg();
11371 MachineOperand &Base = MI->getOperand(1);
11372 MachineOperand &Scale = MI->getOperand(2);
11373 MachineOperand &Index = MI->getOperand(3);
11374 MachineOperand &Disp = MI->getOperand(4);
11375 MachineOperand &Segment = MI->getOperand(5);
11376 unsigned ArgSize = MI->getOperand(6).getImm();
11377 unsigned ArgMode = MI->getOperand(7).getImm();
11378 unsigned Align = MI->getOperand(8).getImm();
11380 // Memory Reference
11381 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11382 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11383 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11385 // Machine Information
11386 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11387 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11388 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11389 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11390 DebugLoc DL = MI->getDebugLoc();
11392 // struct va_list {
11395 // i64 overflow_area (address)
11396 // i64 reg_save_area (address)
11398 // sizeof(va_list) = 24
11399 // alignment(va_list) = 8
11401 unsigned TotalNumIntRegs = 6;
11402 unsigned TotalNumXMMRegs = 8;
11403 bool UseGPOffset = (ArgMode == 1);
11404 bool UseFPOffset = (ArgMode == 2);
11405 unsigned MaxOffset = TotalNumIntRegs * 8 +
11406 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11408 /* Align ArgSize to a multiple of 8 */
11409 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11410 bool NeedsAlign = (Align > 8);
11412 MachineBasicBlock *thisMBB = MBB;
11413 MachineBasicBlock *overflowMBB;
11414 MachineBasicBlock *offsetMBB;
11415 MachineBasicBlock *endMBB;
11417 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11418 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11419 unsigned OffsetReg = 0;
11421 if (!UseGPOffset && !UseFPOffset) {
11422 // If we only pull from the overflow region, we don't create a branch.
11423 // We don't need to alter control flow.
11424 OffsetDestReg = 0; // unused
11425 OverflowDestReg = DestReg;
11428 overflowMBB = thisMBB;
11431 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11432 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11433 // If not, pull from overflow_area. (branch to overflowMBB)
11438 // offsetMBB overflowMBB
11443 // Registers for the PHI in endMBB
11444 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11445 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11447 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11448 MachineFunction *MF = MBB->getParent();
11449 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11450 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11451 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11453 MachineFunction::iterator MBBIter = MBB;
11456 // Insert the new basic blocks
11457 MF->insert(MBBIter, offsetMBB);
11458 MF->insert(MBBIter, overflowMBB);
11459 MF->insert(MBBIter, endMBB);
11461 // Transfer the remainder of MBB and its successor edges to endMBB.
11462 endMBB->splice(endMBB->begin(), thisMBB,
11463 llvm::next(MachineBasicBlock::iterator(MI)),
11465 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11467 // Make offsetMBB and overflowMBB successors of thisMBB
11468 thisMBB->addSuccessor(offsetMBB);
11469 thisMBB->addSuccessor(overflowMBB);
11471 // endMBB is a successor of both offsetMBB and overflowMBB
11472 offsetMBB->addSuccessor(endMBB);
11473 overflowMBB->addSuccessor(endMBB);
11475 // Load the offset value into a register
11476 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11477 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11481 .addDisp(Disp, UseFPOffset ? 4 : 0)
11482 .addOperand(Segment)
11483 .setMemRefs(MMOBegin, MMOEnd);
11485 // Check if there is enough room left to pull this argument.
11486 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11488 .addImm(MaxOffset + 8 - ArgSizeA8);
11490 // Branch to "overflowMBB" if offset >= max
11491 // Fall through to "offsetMBB" otherwise
11492 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11493 .addMBB(overflowMBB);
11496 // In offsetMBB, emit code to use the reg_save_area.
11498 assert(OffsetReg != 0);
11500 // Read the reg_save_area address.
11501 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11502 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11507 .addOperand(Segment)
11508 .setMemRefs(MMOBegin, MMOEnd);
11510 // Zero-extend the offset
11511 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11512 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11515 .addImm(X86::sub_32bit);
11517 // Add the offset to the reg_save_area to get the final address.
11518 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11519 .addReg(OffsetReg64)
11520 .addReg(RegSaveReg);
11522 // Compute the offset for the next argument
11523 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11524 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11526 .addImm(UseFPOffset ? 16 : 8);
11528 // Store it back into the va_list.
11529 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11533 .addDisp(Disp, UseFPOffset ? 4 : 0)
11534 .addOperand(Segment)
11535 .addReg(NextOffsetReg)
11536 .setMemRefs(MMOBegin, MMOEnd);
11539 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11544 // Emit code to use overflow area
11547 // Load the overflow_area address into a register.
11548 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11549 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11554 .addOperand(Segment)
11555 .setMemRefs(MMOBegin, MMOEnd);
11557 // If we need to align it, do so. Otherwise, just copy the address
11558 // to OverflowDestReg.
11560 // Align the overflow address
11561 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11562 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11564 // aligned_addr = (addr + (align-1)) & ~(align-1)
11565 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11566 .addReg(OverflowAddrReg)
11569 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11571 .addImm(~(uint64_t)(Align-1));
11573 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11574 .addReg(OverflowAddrReg);
11577 // Compute the next overflow address after this argument.
11578 // (the overflow address should be kept 8-byte aligned)
11579 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11580 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11581 .addReg(OverflowDestReg)
11582 .addImm(ArgSizeA8);
11584 // Store the new overflow address.
11585 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11590 .addOperand(Segment)
11591 .addReg(NextAddrReg)
11592 .setMemRefs(MMOBegin, MMOEnd);
11594 // If we branched, emit the PHI to the front of endMBB.
11596 BuildMI(*endMBB, endMBB->begin(), DL,
11597 TII->get(X86::PHI), DestReg)
11598 .addReg(OffsetDestReg).addMBB(offsetMBB)
11599 .addReg(OverflowDestReg).addMBB(overflowMBB);
11602 // Erase the pseudo instruction
11603 MI->eraseFromParent();
11608 MachineBasicBlock *
11609 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11611 MachineBasicBlock *MBB) const {
11612 // Emit code to save XMM registers to the stack. The ABI says that the
11613 // number of registers to save is given in %al, so it's theoretically
11614 // possible to do an indirect jump trick to avoid saving all of them,
11615 // however this code takes a simpler approach and just executes all
11616 // of the stores if %al is non-zero. It's less code, and it's probably
11617 // easier on the hardware branch predictor, and stores aren't all that
11618 // expensive anyway.
11620 // Create the new basic blocks. One block contains all the XMM stores,
11621 // and one block is the final destination regardless of whether any
11622 // stores were performed.
11623 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11624 MachineFunction *F = MBB->getParent();
11625 MachineFunction::iterator MBBIter = MBB;
11627 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11628 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11629 F->insert(MBBIter, XMMSaveMBB);
11630 F->insert(MBBIter, EndMBB);
11632 // Transfer the remainder of MBB and its successor edges to EndMBB.
11633 EndMBB->splice(EndMBB->begin(), MBB,
11634 llvm::next(MachineBasicBlock::iterator(MI)),
11636 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11638 // The original block will now fall through to the XMM save block.
11639 MBB->addSuccessor(XMMSaveMBB);
11640 // The XMMSaveMBB will fall through to the end block.
11641 XMMSaveMBB->addSuccessor(EndMBB);
11643 // Now add the instructions.
11644 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11645 DebugLoc DL = MI->getDebugLoc();
11647 unsigned CountReg = MI->getOperand(0).getReg();
11648 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11649 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11651 if (!Subtarget->isTargetWin64()) {
11652 // If %al is 0, branch around the XMM save block.
11653 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11654 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11655 MBB->addSuccessor(EndMBB);
11658 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11659 // In the XMM save block, save all the XMM argument registers.
11660 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11661 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11662 MachineMemOperand *MMO =
11663 F->getMachineMemOperand(
11664 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11665 MachineMemOperand::MOStore,
11666 /*Size=*/16, /*Align=*/16);
11667 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11668 .addFrameIndex(RegSaveFrameIndex)
11669 .addImm(/*Scale=*/1)
11670 .addReg(/*IndexReg=*/0)
11671 .addImm(/*Disp=*/Offset)
11672 .addReg(/*Segment=*/0)
11673 .addReg(MI->getOperand(i).getReg())
11674 .addMemOperand(MMO);
11677 MI->eraseFromParent(); // The pseudo instruction is gone now.
11682 MachineBasicBlock *
11683 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11684 MachineBasicBlock *BB) const {
11685 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11686 DebugLoc DL = MI->getDebugLoc();
11688 // To "insert" a SELECT_CC instruction, we actually have to insert the
11689 // diamond control-flow pattern. The incoming instruction knows the
11690 // destination vreg to set, the condition code register to branch on, the
11691 // true/false values to select between, and a branch opcode to use.
11692 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11693 MachineFunction::iterator It = BB;
11699 // cmpTY ccX, r1, r2
11701 // fallthrough --> copy0MBB
11702 MachineBasicBlock *thisMBB = BB;
11703 MachineFunction *F = BB->getParent();
11704 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11705 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11706 F->insert(It, copy0MBB);
11707 F->insert(It, sinkMBB);
11709 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11710 // live into the sink and copy blocks.
11711 if (!MI->killsRegister(X86::EFLAGS)) {
11712 copy0MBB->addLiveIn(X86::EFLAGS);
11713 sinkMBB->addLiveIn(X86::EFLAGS);
11716 // Transfer the remainder of BB and its successor edges to sinkMBB.
11717 sinkMBB->splice(sinkMBB->begin(), BB,
11718 llvm::next(MachineBasicBlock::iterator(MI)),
11720 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11722 // Add the true and fallthrough blocks as its successors.
11723 BB->addSuccessor(copy0MBB);
11724 BB->addSuccessor(sinkMBB);
11726 // Create the conditional branch instruction.
11728 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11729 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11732 // %FalseValue = ...
11733 // # fallthrough to sinkMBB
11734 copy0MBB->addSuccessor(sinkMBB);
11737 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11739 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11740 TII->get(X86::PHI), MI->getOperand(0).getReg())
11741 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11742 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11744 MI->eraseFromParent(); // The pseudo instruction is gone now.
11748 MachineBasicBlock *
11749 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11750 bool Is64Bit) const {
11751 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11752 DebugLoc DL = MI->getDebugLoc();
11753 MachineFunction *MF = BB->getParent();
11754 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11756 assert(EnableSegmentedStacks);
11758 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
11759 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
11762 // ... [Till the alloca]
11763 // If stacklet is not large enough, jump to mallocMBB
11766 // Allocate by subtracting from RSP
11767 // Jump to continueMBB
11770 // Allocate by call to runtime
11774 // [rest of original BB]
11777 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11778 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11779 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11781 MachineRegisterInfo &MRI = MF->getRegInfo();
11782 const TargetRegisterClass *AddrRegClass =
11783 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
11785 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11786 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11787 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
11788 sizeVReg = MI->getOperand(1).getReg(),
11789 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
11791 MachineFunction::iterator MBBIter = BB;
11794 MF->insert(MBBIter, bumpMBB);
11795 MF->insert(MBBIter, mallocMBB);
11796 MF->insert(MBBIter, continueMBB);
11798 continueMBB->splice(continueMBB->begin(), BB, llvm::next
11799 (MachineBasicBlock::iterator(MI)), BB->end());
11800 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
11802 // Add code to the main basic block to check if the stack limit has been hit,
11803 // and if so, jump to mallocMBB otherwise to bumpMBB.
11804 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
11805 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg)
11806 .addReg(tmpSPVReg).addReg(sizeVReg);
11807 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
11808 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
11809 .addReg(tmpSPVReg);
11810 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
11812 // bumpMBB simply decreases the stack pointer, since we know the current
11813 // stacklet has enough space.
11814 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
11815 .addReg(tmpSPVReg);
11816 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
11817 .addReg(tmpSPVReg);
11818 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11820 // Calls into a routine in libgcc to allocate more space from the heap.
11822 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
11824 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
11825 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
11827 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
11829 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
11830 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
11831 .addExternalSymbol("__morestack_allocate_stack_space");
11835 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
11838 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
11839 .addReg(Is64Bit ? X86::RAX : X86::EAX);
11840 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11842 // Set up the CFG correctly.
11843 BB->addSuccessor(bumpMBB);
11844 BB->addSuccessor(mallocMBB);
11845 mallocMBB->addSuccessor(continueMBB);
11846 bumpMBB->addSuccessor(continueMBB);
11848 // Take care of the PHI nodes.
11849 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
11850 MI->getOperand(0).getReg())
11851 .addReg(mallocPtrVReg).addMBB(mallocMBB)
11852 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
11854 // Delete the original pseudo instruction.
11855 MI->eraseFromParent();
11858 return continueMBB;
11861 MachineBasicBlock *
11862 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11863 MachineBasicBlock *BB) const {
11864 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11865 DebugLoc DL = MI->getDebugLoc();
11867 assert(!Subtarget->isTargetEnvMacho());
11869 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11870 // non-trivial part is impdef of ESP.
11872 if (Subtarget->isTargetWin64()) {
11873 if (Subtarget->isTargetCygMing()) {
11874 // ___chkstk(Mingw64):
11875 // Clobbers R10, R11, RAX and EFLAGS.
11877 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11878 .addExternalSymbol("___chkstk")
11879 .addReg(X86::RAX, RegState::Implicit)
11880 .addReg(X86::RSP, RegState::Implicit)
11881 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11882 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11883 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11885 // __chkstk(MSVCRT): does not update stack pointer.
11886 // Clobbers R10, R11 and EFLAGS.
11887 // FIXME: RAX(allocated size) might be reused and not killed.
11888 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11889 .addExternalSymbol("__chkstk")
11890 .addReg(X86::RAX, RegState::Implicit)
11891 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11892 // RAX has the offset to subtracted from RSP.
11893 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11898 const char *StackProbeSymbol =
11899 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11901 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11902 .addExternalSymbol(StackProbeSymbol)
11903 .addReg(X86::EAX, RegState::Implicit)
11904 .addReg(X86::ESP, RegState::Implicit)
11905 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11906 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11907 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11910 MI->eraseFromParent(); // The pseudo instruction is gone now.
11914 MachineBasicBlock *
11915 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11916 MachineBasicBlock *BB) const {
11917 // This is pretty easy. We're taking the value that we received from
11918 // our load from the relocation, sticking it in either RDI (x86-64)
11919 // or EAX and doing an indirect call. The return value will then
11920 // be in the normal return register.
11921 const X86InstrInfo *TII
11922 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11923 DebugLoc DL = MI->getDebugLoc();
11924 MachineFunction *F = BB->getParent();
11926 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11927 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11929 if (Subtarget->is64Bit()) {
11930 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11931 TII->get(X86::MOV64rm), X86::RDI)
11933 .addImm(0).addReg(0)
11934 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11935 MI->getOperand(3).getTargetFlags())
11937 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11938 addDirectMem(MIB, X86::RDI);
11939 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11940 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11941 TII->get(X86::MOV32rm), X86::EAX)
11943 .addImm(0).addReg(0)
11944 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11945 MI->getOperand(3).getTargetFlags())
11947 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11948 addDirectMem(MIB, X86::EAX);
11950 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11951 TII->get(X86::MOV32rm), X86::EAX)
11952 .addReg(TII->getGlobalBaseReg(F))
11953 .addImm(0).addReg(0)
11954 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11955 MI->getOperand(3).getTargetFlags())
11957 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11958 addDirectMem(MIB, X86::EAX);
11961 MI->eraseFromParent(); // The pseudo instruction is gone now.
11965 MachineBasicBlock *
11966 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11967 MachineBasicBlock *BB) const {
11968 switch (MI->getOpcode()) {
11969 default: assert(0 && "Unexpected instr type to insert");
11970 case X86::TAILJMPd64:
11971 case X86::TAILJMPr64:
11972 case X86::TAILJMPm64:
11973 assert(0 && "TAILJMP64 would not be touched here.");
11974 case X86::TCRETURNdi64:
11975 case X86::TCRETURNri64:
11976 case X86::TCRETURNmi64:
11977 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11978 // On AMD64, additional defs should be added before register allocation.
11979 if (!Subtarget->isTargetWin64()) {
11980 MI->addRegisterDefined(X86::RSI);
11981 MI->addRegisterDefined(X86::RDI);
11982 MI->addRegisterDefined(X86::XMM6);
11983 MI->addRegisterDefined(X86::XMM7);
11984 MI->addRegisterDefined(X86::XMM8);
11985 MI->addRegisterDefined(X86::XMM9);
11986 MI->addRegisterDefined(X86::XMM10);
11987 MI->addRegisterDefined(X86::XMM11);
11988 MI->addRegisterDefined(X86::XMM12);
11989 MI->addRegisterDefined(X86::XMM13);
11990 MI->addRegisterDefined(X86::XMM14);
11991 MI->addRegisterDefined(X86::XMM15);
11994 case X86::WIN_ALLOCA:
11995 return EmitLoweredWinAlloca(MI, BB);
11996 case X86::SEG_ALLOCA_32:
11997 return EmitLoweredSegAlloca(MI, BB, false);
11998 case X86::SEG_ALLOCA_64:
11999 return EmitLoweredSegAlloca(MI, BB, true);
12000 case X86::TLSCall_32:
12001 case X86::TLSCall_64:
12002 return EmitLoweredTLSCall(MI, BB);
12003 case X86::CMOV_GR8:
12004 case X86::CMOV_FR32:
12005 case X86::CMOV_FR64:
12006 case X86::CMOV_V4F32:
12007 case X86::CMOV_V2F64:
12008 case X86::CMOV_V2I64:
12009 case X86::CMOV_V8F32:
12010 case X86::CMOV_V4F64:
12011 case X86::CMOV_V4I64:
12012 case X86::CMOV_GR16:
12013 case X86::CMOV_GR32:
12014 case X86::CMOV_RFP32:
12015 case X86::CMOV_RFP64:
12016 case X86::CMOV_RFP80:
12017 return EmitLoweredSelect(MI, BB);
12019 case X86::FP32_TO_INT16_IN_MEM:
12020 case X86::FP32_TO_INT32_IN_MEM:
12021 case X86::FP32_TO_INT64_IN_MEM:
12022 case X86::FP64_TO_INT16_IN_MEM:
12023 case X86::FP64_TO_INT32_IN_MEM:
12024 case X86::FP64_TO_INT64_IN_MEM:
12025 case X86::FP80_TO_INT16_IN_MEM:
12026 case X86::FP80_TO_INT32_IN_MEM:
12027 case X86::FP80_TO_INT64_IN_MEM: {
12028 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12029 DebugLoc DL = MI->getDebugLoc();
12031 // Change the floating point control register to use "round towards zero"
12032 // mode when truncating to an integer value.
12033 MachineFunction *F = BB->getParent();
12034 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12035 addFrameReference(BuildMI(*BB, MI, DL,
12036 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12038 // Load the old value of the high byte of the control word...
12040 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12041 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12044 // Set the high part to be round to zero...
12045 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12048 // Reload the modified control word now...
12049 addFrameReference(BuildMI(*BB, MI, DL,
12050 TII->get(X86::FLDCW16m)), CWFrameIdx);
12052 // Restore the memory image of control word to original value
12053 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12056 // Get the X86 opcode to use.
12058 switch (MI->getOpcode()) {
12059 default: llvm_unreachable("illegal opcode!");
12060 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12061 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12062 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12063 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12064 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12065 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12066 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12067 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12068 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12072 MachineOperand &Op = MI->getOperand(0);
12074 AM.BaseType = X86AddressMode::RegBase;
12075 AM.Base.Reg = Op.getReg();
12077 AM.BaseType = X86AddressMode::FrameIndexBase;
12078 AM.Base.FrameIndex = Op.getIndex();
12080 Op = MI->getOperand(1);
12082 AM.Scale = Op.getImm();
12083 Op = MI->getOperand(2);
12085 AM.IndexReg = Op.getImm();
12086 Op = MI->getOperand(3);
12087 if (Op.isGlobal()) {
12088 AM.GV = Op.getGlobal();
12090 AM.Disp = Op.getImm();
12092 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12093 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12095 // Reload the original control word now.
12096 addFrameReference(BuildMI(*BB, MI, DL,
12097 TII->get(X86::FLDCW16m)), CWFrameIdx);
12099 MI->eraseFromParent(); // The pseudo instruction is gone now.
12102 // String/text processing lowering.
12103 case X86::PCMPISTRM128REG:
12104 case X86::VPCMPISTRM128REG:
12105 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12106 case X86::PCMPISTRM128MEM:
12107 case X86::VPCMPISTRM128MEM:
12108 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12109 case X86::PCMPESTRM128REG:
12110 case X86::VPCMPESTRM128REG:
12111 return EmitPCMP(MI, BB, 5, false /* in mem */);
12112 case X86::PCMPESTRM128MEM:
12113 case X86::VPCMPESTRM128MEM:
12114 return EmitPCMP(MI, BB, 5, true /* in mem */);
12116 // Thread synchronization.
12118 return EmitMonitor(MI, BB);
12120 return EmitMwait(MI, BB);
12122 // Atomic Lowering.
12123 case X86::ATOMAND32:
12124 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12125 X86::AND32ri, X86::MOV32rm,
12127 X86::NOT32r, X86::EAX,
12128 X86::GR32RegisterClass);
12129 case X86::ATOMOR32:
12130 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12131 X86::OR32ri, X86::MOV32rm,
12133 X86::NOT32r, X86::EAX,
12134 X86::GR32RegisterClass);
12135 case X86::ATOMXOR32:
12136 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12137 X86::XOR32ri, X86::MOV32rm,
12139 X86::NOT32r, X86::EAX,
12140 X86::GR32RegisterClass);
12141 case X86::ATOMNAND32:
12142 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12143 X86::AND32ri, X86::MOV32rm,
12145 X86::NOT32r, X86::EAX,
12146 X86::GR32RegisterClass, true);
12147 case X86::ATOMMIN32:
12148 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12149 case X86::ATOMMAX32:
12150 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12151 case X86::ATOMUMIN32:
12152 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12153 case X86::ATOMUMAX32:
12154 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12156 case X86::ATOMAND16:
12157 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12158 X86::AND16ri, X86::MOV16rm,
12160 X86::NOT16r, X86::AX,
12161 X86::GR16RegisterClass);
12162 case X86::ATOMOR16:
12163 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12164 X86::OR16ri, X86::MOV16rm,
12166 X86::NOT16r, X86::AX,
12167 X86::GR16RegisterClass);
12168 case X86::ATOMXOR16:
12169 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12170 X86::XOR16ri, X86::MOV16rm,
12172 X86::NOT16r, X86::AX,
12173 X86::GR16RegisterClass);
12174 case X86::ATOMNAND16:
12175 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12176 X86::AND16ri, X86::MOV16rm,
12178 X86::NOT16r, X86::AX,
12179 X86::GR16RegisterClass, true);
12180 case X86::ATOMMIN16:
12181 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12182 case X86::ATOMMAX16:
12183 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12184 case X86::ATOMUMIN16:
12185 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12186 case X86::ATOMUMAX16:
12187 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12189 case X86::ATOMAND8:
12190 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12191 X86::AND8ri, X86::MOV8rm,
12193 X86::NOT8r, X86::AL,
12194 X86::GR8RegisterClass);
12196 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12197 X86::OR8ri, X86::MOV8rm,
12199 X86::NOT8r, X86::AL,
12200 X86::GR8RegisterClass);
12201 case X86::ATOMXOR8:
12202 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12203 X86::XOR8ri, X86::MOV8rm,
12205 X86::NOT8r, X86::AL,
12206 X86::GR8RegisterClass);
12207 case X86::ATOMNAND8:
12208 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12209 X86::AND8ri, X86::MOV8rm,
12211 X86::NOT8r, X86::AL,
12212 X86::GR8RegisterClass, true);
12213 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12214 // This group is for 64-bit host.
12215 case X86::ATOMAND64:
12216 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12217 X86::AND64ri32, X86::MOV64rm,
12219 X86::NOT64r, X86::RAX,
12220 X86::GR64RegisterClass);
12221 case X86::ATOMOR64:
12222 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12223 X86::OR64ri32, X86::MOV64rm,
12225 X86::NOT64r, X86::RAX,
12226 X86::GR64RegisterClass);
12227 case X86::ATOMXOR64:
12228 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12229 X86::XOR64ri32, X86::MOV64rm,
12231 X86::NOT64r, X86::RAX,
12232 X86::GR64RegisterClass);
12233 case X86::ATOMNAND64:
12234 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12235 X86::AND64ri32, X86::MOV64rm,
12237 X86::NOT64r, X86::RAX,
12238 X86::GR64RegisterClass, true);
12239 case X86::ATOMMIN64:
12240 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12241 case X86::ATOMMAX64:
12242 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12243 case X86::ATOMUMIN64:
12244 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12245 case X86::ATOMUMAX64:
12246 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12248 // This group does 64-bit operations on a 32-bit host.
12249 case X86::ATOMAND6432:
12250 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12251 X86::AND32rr, X86::AND32rr,
12252 X86::AND32ri, X86::AND32ri,
12254 case X86::ATOMOR6432:
12255 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12256 X86::OR32rr, X86::OR32rr,
12257 X86::OR32ri, X86::OR32ri,
12259 case X86::ATOMXOR6432:
12260 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12261 X86::XOR32rr, X86::XOR32rr,
12262 X86::XOR32ri, X86::XOR32ri,
12264 case X86::ATOMNAND6432:
12265 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12266 X86::AND32rr, X86::AND32rr,
12267 X86::AND32ri, X86::AND32ri,
12269 case X86::ATOMADD6432:
12270 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12271 X86::ADD32rr, X86::ADC32rr,
12272 X86::ADD32ri, X86::ADC32ri,
12274 case X86::ATOMSUB6432:
12275 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12276 X86::SUB32rr, X86::SBB32rr,
12277 X86::SUB32ri, X86::SBB32ri,
12279 case X86::ATOMSWAP6432:
12280 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12281 X86::MOV32rr, X86::MOV32rr,
12282 X86::MOV32ri, X86::MOV32ri,
12284 case X86::VASTART_SAVE_XMM_REGS:
12285 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12287 case X86::VAARG_64:
12288 return EmitVAARG64WithCustomInserter(MI, BB);
12292 //===----------------------------------------------------------------------===//
12293 // X86 Optimization Hooks
12294 //===----------------------------------------------------------------------===//
12296 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12300 const SelectionDAG &DAG,
12301 unsigned Depth) const {
12302 unsigned Opc = Op.getOpcode();
12303 assert((Opc >= ISD::BUILTIN_OP_END ||
12304 Opc == ISD::INTRINSIC_WO_CHAIN ||
12305 Opc == ISD::INTRINSIC_W_CHAIN ||
12306 Opc == ISD::INTRINSIC_VOID) &&
12307 "Should use MaskedValueIsZero if you don't know whether Op"
12308 " is a target node!");
12310 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12324 // These nodes' second result is a boolean.
12325 if (Op.getResNo() == 0)
12328 case X86ISD::SETCC:
12329 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12330 Mask.getBitWidth() - 1);
12332 case ISD::INTRINSIC_WO_CHAIN: {
12333 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12334 unsigned NumLoBits = 0;
12337 case Intrinsic::x86_sse_movmsk_ps:
12338 case Intrinsic::x86_avx_movmsk_ps_256:
12339 case Intrinsic::x86_sse2_movmsk_pd:
12340 case Intrinsic::x86_avx_movmsk_pd_256:
12341 case Intrinsic::x86_mmx_pmovmskb:
12342 case Intrinsic::x86_sse2_pmovmskb_128: {
12343 // High bits of movmskp{s|d}, pmovmskb are known zero.
12345 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12346 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12347 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12348 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12349 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12350 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12352 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12353 Mask.getBitWidth() - NumLoBits);
12362 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12363 unsigned Depth) const {
12364 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12365 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12366 return Op.getValueType().getScalarType().getSizeInBits();
12372 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12373 /// node is a GlobalAddress + offset.
12374 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12375 const GlobalValue* &GA,
12376 int64_t &Offset) const {
12377 if (N->getOpcode() == X86ISD::Wrapper) {
12378 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12379 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12380 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12384 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12387 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12388 /// same as extracting the high 128-bit part of 256-bit vector and then
12389 /// inserting the result into the low part of a new 256-bit vector
12390 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12391 EVT VT = SVOp->getValueType(0);
12392 int NumElems = VT.getVectorNumElements();
12394 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12395 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12396 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12397 SVOp->getMaskElt(j) >= 0)
12403 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12404 /// same as extracting the low 128-bit part of 256-bit vector and then
12405 /// inserting the result into the high part of a new 256-bit vector
12406 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12407 EVT VT = SVOp->getValueType(0);
12408 int NumElems = VT.getVectorNumElements();
12410 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12411 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12412 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12413 SVOp->getMaskElt(j) >= 0)
12419 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12420 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12421 TargetLowering::DAGCombinerInfo &DCI) {
12422 DebugLoc dl = N->getDebugLoc();
12423 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12424 SDValue V1 = SVOp->getOperand(0);
12425 SDValue V2 = SVOp->getOperand(1);
12426 EVT VT = SVOp->getValueType(0);
12427 int NumElems = VT.getVectorNumElements();
12429 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12430 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12434 // V UNDEF BUILD_VECTOR UNDEF
12436 // CONCAT_VECTOR CONCAT_VECTOR
12439 // RESULT: V + zero extended
12441 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12442 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12443 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12446 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12449 // To match the shuffle mask, the first half of the mask should
12450 // be exactly the first vector, and all the rest a splat with the
12451 // first element of the second one.
12452 for (int i = 0; i < NumElems/2; ++i)
12453 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12454 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12457 // Emit a zeroed vector and insert the desired subvector on its
12459 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
12460 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12461 DAG.getConstant(0, MVT::i32), DAG, dl);
12462 return DCI.CombineTo(N, InsV);
12465 //===--------------------------------------------------------------------===//
12466 // Combine some shuffles into subvector extracts and inserts:
12469 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12470 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12471 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12473 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12474 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12475 return DCI.CombineTo(N, InsV);
12478 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12479 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12480 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12481 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12482 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12483 return DCI.CombineTo(N, InsV);
12489 /// PerformShuffleCombine - Performs several different shuffle combines.
12490 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12491 TargetLowering::DAGCombinerInfo &DCI,
12492 const X86Subtarget *Subtarget) {
12493 DebugLoc dl = N->getDebugLoc();
12494 EVT VT = N->getValueType(0);
12496 // Don't create instructions with illegal types after legalize types has run.
12497 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12498 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12501 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12502 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12503 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12504 return PerformShuffleCombine256(N, DAG, DCI);
12506 // Only handle 128 wide vector from here on.
12507 if (VT.getSizeInBits() != 128)
12510 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12511 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12512 // consecutive, non-overlapping, and in the right order.
12513 SmallVector<SDValue, 16> Elts;
12514 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12515 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12517 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12520 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12521 /// generation and convert it from being a bunch of shuffles and extracts
12522 /// to a simple store and scalar loads to extract the elements.
12523 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12524 const TargetLowering &TLI) {
12525 SDValue InputVector = N->getOperand(0);
12527 // Only operate on vectors of 4 elements, where the alternative shuffling
12528 // gets to be more expensive.
12529 if (InputVector.getValueType() != MVT::v4i32)
12532 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12533 // single use which is a sign-extend or zero-extend, and all elements are
12535 SmallVector<SDNode *, 4> Uses;
12536 unsigned ExtractedElements = 0;
12537 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12538 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12539 if (UI.getUse().getResNo() != InputVector.getResNo())
12542 SDNode *Extract = *UI;
12543 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12546 if (Extract->getValueType(0) != MVT::i32)
12548 if (!Extract->hasOneUse())
12550 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12551 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12553 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12556 // Record which element was extracted.
12557 ExtractedElements |=
12558 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12560 Uses.push_back(Extract);
12563 // If not all the elements were used, this may not be worthwhile.
12564 if (ExtractedElements != 15)
12567 // Ok, we've now decided to do the transformation.
12568 DebugLoc dl = InputVector.getDebugLoc();
12570 // Store the value to a temporary stack slot.
12571 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12572 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12573 MachinePointerInfo(), false, false, 0);
12575 // Replace each use (extract) with a load of the appropriate element.
12576 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12577 UE = Uses.end(); UI != UE; ++UI) {
12578 SDNode *Extract = *UI;
12580 // cOMpute the element's address.
12581 SDValue Idx = Extract->getOperand(1);
12583 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12584 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12585 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12587 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12588 StackPtr, OffsetVal);
12590 // Load the scalar.
12591 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12592 ScalarAddr, MachinePointerInfo(),
12595 // Replace the exact with the load.
12596 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12599 // The replacement was made in place; don't return anything.
12603 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12605 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12606 const X86Subtarget *Subtarget) {
12607 DebugLoc DL = N->getDebugLoc();
12608 SDValue Cond = N->getOperand(0);
12609 // Get the LHS/RHS of the select.
12610 SDValue LHS = N->getOperand(1);
12611 SDValue RHS = N->getOperand(2);
12612 EVT VT = LHS.getValueType();
12614 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12615 // instructions match the semantics of the common C idiom x<y?x:y but not
12616 // x<=y?x:y, because of how they handle negative zero (which can be
12617 // ignored in unsafe-math mode).
12618 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12619 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
12620 (Subtarget->hasXMMInt() ||
12621 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
12622 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12624 unsigned Opcode = 0;
12625 // Check for x CC y ? x : y.
12626 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12627 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12631 // Converting this to a min would handle NaNs incorrectly, and swapping
12632 // the operands would cause it to handle comparisons between positive
12633 // and negative zero incorrectly.
12634 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12635 if (!UnsafeFPMath &&
12636 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12638 std::swap(LHS, RHS);
12640 Opcode = X86ISD::FMIN;
12643 // Converting this to a min would handle comparisons between positive
12644 // and negative zero incorrectly.
12645 if (!UnsafeFPMath &&
12646 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12648 Opcode = X86ISD::FMIN;
12651 // Converting this to a min would handle both negative zeros and NaNs
12652 // incorrectly, but we can swap the operands to fix both.
12653 std::swap(LHS, RHS);
12657 Opcode = X86ISD::FMIN;
12661 // Converting this to a max would handle comparisons between positive
12662 // and negative zero incorrectly.
12663 if (!UnsafeFPMath &&
12664 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12666 Opcode = X86ISD::FMAX;
12669 // Converting this to a max would handle NaNs incorrectly, and swapping
12670 // the operands would cause it to handle comparisons between positive
12671 // and negative zero incorrectly.
12672 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12673 if (!UnsafeFPMath &&
12674 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12676 std::swap(LHS, RHS);
12678 Opcode = X86ISD::FMAX;
12681 // Converting this to a max would handle both negative zeros and NaNs
12682 // incorrectly, but we can swap the operands to fix both.
12683 std::swap(LHS, RHS);
12687 Opcode = X86ISD::FMAX;
12690 // Check for x CC y ? y : x -- a min/max with reversed arms.
12691 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12692 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12696 // Converting this to a min would handle comparisons between positive
12697 // and negative zero incorrectly, and swapping the operands would
12698 // cause it to handle NaNs incorrectly.
12699 if (!UnsafeFPMath &&
12700 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12701 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12703 std::swap(LHS, RHS);
12705 Opcode = X86ISD::FMIN;
12708 // Converting this to a min would handle NaNs incorrectly.
12709 if (!UnsafeFPMath &&
12710 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12712 Opcode = X86ISD::FMIN;
12715 // Converting this to a min would handle both negative zeros and NaNs
12716 // incorrectly, but we can swap the operands to fix both.
12717 std::swap(LHS, RHS);
12721 Opcode = X86ISD::FMIN;
12725 // Converting this to a max would handle NaNs incorrectly.
12726 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12728 Opcode = X86ISD::FMAX;
12731 // Converting this to a max would handle comparisons between positive
12732 // and negative zero incorrectly, and swapping the operands would
12733 // cause it to handle NaNs incorrectly.
12734 if (!UnsafeFPMath &&
12735 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12736 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12738 std::swap(LHS, RHS);
12740 Opcode = X86ISD::FMAX;
12743 // Converting this to a max would handle both negative zeros and NaNs
12744 // incorrectly, but we can swap the operands to fix both.
12745 std::swap(LHS, RHS);
12749 Opcode = X86ISD::FMAX;
12755 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12758 // If this is a select between two integer constants, try to do some
12760 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12761 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12762 // Don't do this for crazy integer types.
12763 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12764 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12765 // so that TrueC (the true value) is larger than FalseC.
12766 bool NeedsCondInvert = false;
12768 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12769 // Efficiently invertible.
12770 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12771 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12772 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12773 NeedsCondInvert = true;
12774 std::swap(TrueC, FalseC);
12777 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12778 if (FalseC->getAPIntValue() == 0 &&
12779 TrueC->getAPIntValue().isPowerOf2()) {
12780 if (NeedsCondInvert) // Invert the condition if needed.
12781 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12782 DAG.getConstant(1, Cond.getValueType()));
12784 // Zero extend the condition if needed.
12785 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12787 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12788 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12789 DAG.getConstant(ShAmt, MVT::i8));
12792 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12793 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12794 if (NeedsCondInvert) // Invert the condition if needed.
12795 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12796 DAG.getConstant(1, Cond.getValueType()));
12798 // Zero extend the condition if needed.
12799 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12800 FalseC->getValueType(0), Cond);
12801 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12802 SDValue(FalseC, 0));
12805 // Optimize cases that will turn into an LEA instruction. This requires
12806 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12807 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12808 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12809 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12811 bool isFastMultiplier = false;
12813 switch ((unsigned char)Diff) {
12815 case 1: // result = add base, cond
12816 case 2: // result = lea base( , cond*2)
12817 case 3: // result = lea base(cond, cond*2)
12818 case 4: // result = lea base( , cond*4)
12819 case 5: // result = lea base(cond, cond*4)
12820 case 8: // result = lea base( , cond*8)
12821 case 9: // result = lea base(cond, cond*8)
12822 isFastMultiplier = true;
12827 if (isFastMultiplier) {
12828 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12829 if (NeedsCondInvert) // Invert the condition if needed.
12830 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12831 DAG.getConstant(1, Cond.getValueType()));
12833 // Zero extend the condition if needed.
12834 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12836 // Scale the condition by the difference.
12838 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12839 DAG.getConstant(Diff, Cond.getValueType()));
12841 // Add the base if non-zero.
12842 if (FalseC->getAPIntValue() != 0)
12843 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12844 SDValue(FalseC, 0));
12854 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12855 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12856 TargetLowering::DAGCombinerInfo &DCI) {
12857 DebugLoc DL = N->getDebugLoc();
12859 // If the flag operand isn't dead, don't touch this CMOV.
12860 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12863 SDValue FalseOp = N->getOperand(0);
12864 SDValue TrueOp = N->getOperand(1);
12865 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12866 SDValue Cond = N->getOperand(3);
12867 if (CC == X86::COND_E || CC == X86::COND_NE) {
12868 switch (Cond.getOpcode()) {
12872 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12873 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12874 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12878 // If this is a select between two integer constants, try to do some
12879 // optimizations. Note that the operands are ordered the opposite of SELECT
12881 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12882 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12883 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12884 // larger than FalseC (the false value).
12885 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12886 CC = X86::GetOppositeBranchCondition(CC);
12887 std::swap(TrueC, FalseC);
12890 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12891 // This is efficient for any integer data type (including i8/i16) and
12893 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12894 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12895 DAG.getConstant(CC, MVT::i8), Cond);
12897 // Zero extend the condition if needed.
12898 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12900 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12901 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12902 DAG.getConstant(ShAmt, MVT::i8));
12903 if (N->getNumValues() == 2) // Dead flag value?
12904 return DCI.CombineTo(N, Cond, SDValue());
12908 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12909 // for any integer data type, including i8/i16.
12910 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12911 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12912 DAG.getConstant(CC, MVT::i8), Cond);
12914 // Zero extend the condition if needed.
12915 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12916 FalseC->getValueType(0), Cond);
12917 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12918 SDValue(FalseC, 0));
12920 if (N->getNumValues() == 2) // Dead flag value?
12921 return DCI.CombineTo(N, Cond, SDValue());
12925 // Optimize cases that will turn into an LEA instruction. This requires
12926 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12927 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12928 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12929 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12931 bool isFastMultiplier = false;
12933 switch ((unsigned char)Diff) {
12935 case 1: // result = add base, cond
12936 case 2: // result = lea base( , cond*2)
12937 case 3: // result = lea base(cond, cond*2)
12938 case 4: // result = lea base( , cond*4)
12939 case 5: // result = lea base(cond, cond*4)
12940 case 8: // result = lea base( , cond*8)
12941 case 9: // result = lea base(cond, cond*8)
12942 isFastMultiplier = true;
12947 if (isFastMultiplier) {
12948 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12949 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12950 DAG.getConstant(CC, MVT::i8), Cond);
12951 // Zero extend the condition if needed.
12952 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12954 // Scale the condition by the difference.
12956 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12957 DAG.getConstant(Diff, Cond.getValueType()));
12959 // Add the base if non-zero.
12960 if (FalseC->getAPIntValue() != 0)
12961 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12962 SDValue(FalseC, 0));
12963 if (N->getNumValues() == 2) // Dead flag value?
12964 return DCI.CombineTo(N, Cond, SDValue());
12974 /// PerformMulCombine - Optimize a single multiply with constant into two
12975 /// in order to implement it with two cheaper instructions, e.g.
12976 /// LEA + SHL, LEA + LEA.
12977 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12978 TargetLowering::DAGCombinerInfo &DCI) {
12979 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12982 EVT VT = N->getValueType(0);
12983 if (VT != MVT::i64)
12986 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12989 uint64_t MulAmt = C->getZExtValue();
12990 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12993 uint64_t MulAmt1 = 0;
12994 uint64_t MulAmt2 = 0;
12995 if ((MulAmt % 9) == 0) {
12997 MulAmt2 = MulAmt / 9;
12998 } else if ((MulAmt % 5) == 0) {
13000 MulAmt2 = MulAmt / 5;
13001 } else if ((MulAmt % 3) == 0) {
13003 MulAmt2 = MulAmt / 3;
13006 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13007 DebugLoc DL = N->getDebugLoc();
13009 if (isPowerOf2_64(MulAmt2) &&
13010 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13011 // If second multiplifer is pow2, issue it first. We want the multiply by
13012 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13014 std::swap(MulAmt1, MulAmt2);
13017 if (isPowerOf2_64(MulAmt1))
13018 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13019 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13021 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13022 DAG.getConstant(MulAmt1, VT));
13024 if (isPowerOf2_64(MulAmt2))
13025 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13026 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13028 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13029 DAG.getConstant(MulAmt2, VT));
13031 // Do not add new nodes to DAG combiner worklist.
13032 DCI.CombineTo(N, NewMul, false);
13037 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13038 SDValue N0 = N->getOperand(0);
13039 SDValue N1 = N->getOperand(1);
13040 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13041 EVT VT = N0.getValueType();
13043 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13044 // since the result of setcc_c is all zero's or all ones.
13045 if (N1C && N0.getOpcode() == ISD::AND &&
13046 N0.getOperand(1).getOpcode() == ISD::Constant) {
13047 SDValue N00 = N0.getOperand(0);
13048 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13049 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13050 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13051 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13052 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13053 APInt ShAmt = N1C->getAPIntValue();
13054 Mask = Mask.shl(ShAmt);
13056 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13057 N00, DAG.getConstant(Mask, VT));
13064 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13066 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13067 const X86Subtarget *Subtarget) {
13068 EVT VT = N->getValueType(0);
13069 if (!VT.isVector() && VT.isInteger() &&
13070 N->getOpcode() == ISD::SHL)
13071 return PerformSHLCombine(N, DAG);
13073 // On X86 with SSE2 support, we can transform this to a vector shift if
13074 // all elements are shifted by the same amount. We can't do this in legalize
13075 // because the a constant vector is typically transformed to a constant pool
13076 // so we have no knowledge of the shift amount.
13077 if (!Subtarget->hasXMMInt())
13080 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
13083 SDValue ShAmtOp = N->getOperand(1);
13084 EVT EltVT = VT.getVectorElementType();
13085 DebugLoc DL = N->getDebugLoc();
13086 SDValue BaseShAmt = SDValue();
13087 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13088 unsigned NumElts = VT.getVectorNumElements();
13090 for (; i != NumElts; ++i) {
13091 SDValue Arg = ShAmtOp.getOperand(i);
13092 if (Arg.getOpcode() == ISD::UNDEF) continue;
13096 for (; i != NumElts; ++i) {
13097 SDValue Arg = ShAmtOp.getOperand(i);
13098 if (Arg.getOpcode() == ISD::UNDEF) continue;
13099 if (Arg != BaseShAmt) {
13103 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13104 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13105 SDValue InVec = ShAmtOp.getOperand(0);
13106 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13107 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13109 for (; i != NumElts; ++i) {
13110 SDValue Arg = InVec.getOperand(i);
13111 if (Arg.getOpcode() == ISD::UNDEF) continue;
13115 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13117 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13118 if (C->getZExtValue() == SplatIdx)
13119 BaseShAmt = InVec.getOperand(1);
13122 if (BaseShAmt.getNode() == 0)
13123 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13124 DAG.getIntPtrConstant(0));
13128 // The shift amount is an i32.
13129 if (EltVT.bitsGT(MVT::i32))
13130 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13131 else if (EltVT.bitsLT(MVT::i32))
13132 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13134 // The shift amount is identical so we can do a vector shift.
13135 SDValue ValOp = N->getOperand(0);
13136 switch (N->getOpcode()) {
13138 llvm_unreachable("Unknown shift opcode!");
13141 if (VT == MVT::v2i64)
13142 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13143 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13145 if (VT == MVT::v4i32)
13146 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13147 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13149 if (VT == MVT::v8i16)
13150 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13151 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13155 if (VT == MVT::v4i32)
13156 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13157 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13159 if (VT == MVT::v8i16)
13160 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13161 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13165 if (VT == MVT::v2i64)
13166 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13167 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13169 if (VT == MVT::v4i32)
13170 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13171 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13173 if (VT == MVT::v8i16)
13174 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13175 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13183 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13184 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13185 // and friends. Likewise for OR -> CMPNEQSS.
13186 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13187 TargetLowering::DAGCombinerInfo &DCI,
13188 const X86Subtarget *Subtarget) {
13191 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13192 // we're requiring SSE2 for both.
13193 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13194 SDValue N0 = N->getOperand(0);
13195 SDValue N1 = N->getOperand(1);
13196 SDValue CMP0 = N0->getOperand(1);
13197 SDValue CMP1 = N1->getOperand(1);
13198 DebugLoc DL = N->getDebugLoc();
13200 // The SETCCs should both refer to the same CMP.
13201 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13204 SDValue CMP00 = CMP0->getOperand(0);
13205 SDValue CMP01 = CMP0->getOperand(1);
13206 EVT VT = CMP00.getValueType();
13208 if (VT == MVT::f32 || VT == MVT::f64) {
13209 bool ExpectingFlags = false;
13210 // Check for any users that want flags:
13211 for (SDNode::use_iterator UI = N->use_begin(),
13213 !ExpectingFlags && UI != UE; ++UI)
13214 switch (UI->getOpcode()) {
13219 ExpectingFlags = true;
13221 case ISD::CopyToReg:
13222 case ISD::SIGN_EXTEND:
13223 case ISD::ZERO_EXTEND:
13224 case ISD::ANY_EXTEND:
13228 if (!ExpectingFlags) {
13229 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13230 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13232 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13233 X86::CondCode tmp = cc0;
13238 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13239 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13240 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13241 X86ISD::NodeType NTOperator = is64BitFP ?
13242 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13243 // FIXME: need symbolic constants for these magic numbers.
13244 // See X86ATTInstPrinter.cpp:printSSECC().
13245 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13246 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13247 DAG.getConstant(x86cc, MVT::i8));
13248 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13250 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13251 DAG.getConstant(1, MVT::i32));
13252 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13253 return OneBitOfTruth;
13261 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13262 /// so it can be folded inside ANDNP.
13263 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13264 EVT VT = N->getValueType(0);
13266 // Match direct AllOnes for 128 and 256-bit vectors
13267 if (ISD::isBuildVectorAllOnes(N))
13270 // Look through a bit convert.
13271 if (N->getOpcode() == ISD::BITCAST)
13272 N = N->getOperand(0).getNode();
13274 // Sometimes the operand may come from a insert_subvector building a 256-bit
13276 if (VT.getSizeInBits() == 256 &&
13277 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13278 SDValue V1 = N->getOperand(0);
13279 SDValue V2 = N->getOperand(1);
13281 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13282 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13283 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13284 ISD::isBuildVectorAllOnes(V2.getNode()))
13291 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13292 TargetLowering::DAGCombinerInfo &DCI,
13293 const X86Subtarget *Subtarget) {
13294 if (DCI.isBeforeLegalizeOps())
13297 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13301 EVT VT = N->getValueType(0);
13303 // Create ANDN instructions
13304 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13305 SDValue N0 = N->getOperand(0);
13306 SDValue N1 = N->getOperand(1);
13307 DebugLoc DL = N->getDebugLoc();
13309 // Check LHS for not
13310 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13311 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13312 // Check RHS for not
13313 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13314 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13319 // Want to form ANDNP nodes:
13320 // 1) In the hopes of then easily combining them with OR and AND nodes
13321 // to form PBLEND/PSIGN.
13322 // 2) To match ANDN packed intrinsics
13323 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13326 SDValue N0 = N->getOperand(0);
13327 SDValue N1 = N->getOperand(1);
13328 DebugLoc DL = N->getDebugLoc();
13330 // Check LHS for vnot
13331 if (N0.getOpcode() == ISD::XOR &&
13332 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13333 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13334 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13336 // Check RHS for vnot
13337 if (N1.getOpcode() == ISD::XOR &&
13338 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13339 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13340 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13345 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13346 TargetLowering::DAGCombinerInfo &DCI,
13347 const X86Subtarget *Subtarget) {
13348 if (DCI.isBeforeLegalizeOps())
13351 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13355 EVT VT = N->getValueType(0);
13356 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
13359 SDValue N0 = N->getOperand(0);
13360 SDValue N1 = N->getOperand(1);
13362 // look for psign/blend
13363 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) {
13364 if (VT == MVT::v2i64) {
13365 // Canonicalize pandn to RHS
13366 if (N0.getOpcode() == X86ISD::ANDNP)
13368 // or (and (m, x), (pandn m, y))
13369 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13370 SDValue Mask = N1.getOperand(0);
13371 SDValue X = N1.getOperand(1);
13373 if (N0.getOperand(0) == Mask)
13374 Y = N0.getOperand(1);
13375 if (N0.getOperand(1) == Mask)
13376 Y = N0.getOperand(0);
13378 // Check to see if the mask appeared in both the AND and ANDNP and
13382 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13383 if (Mask.getOpcode() != ISD::BITCAST ||
13384 X.getOpcode() != ISD::BITCAST ||
13385 Y.getOpcode() != ISD::BITCAST)
13388 // Look through mask bitcast.
13389 Mask = Mask.getOperand(0);
13390 EVT MaskVT = Mask.getValueType();
13392 // Validate that the Mask operand is a vector sra node. The sra node
13393 // will be an intrinsic.
13394 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13397 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13398 // there is no psrai.b
13399 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13400 case Intrinsic::x86_sse2_psrai_w:
13401 case Intrinsic::x86_sse2_psrai_d:
13403 default: return SDValue();
13406 // Check that the SRA is all signbits.
13407 SDValue SraC = Mask.getOperand(2);
13408 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13409 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13410 if ((SraAmt + 1) != EltBits)
13413 DebugLoc DL = N->getDebugLoc();
13415 // Now we know we at least have a plendvb with the mask val. See if
13416 // we can form a psignb/w/d.
13417 // psign = x.type == y.type == mask.type && y = sub(0, x);
13418 X = X.getOperand(0);
13419 Y = Y.getOperand(0);
13420 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13421 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13422 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
13425 case 8: Opc = X86ISD::PSIGNB; break;
13426 case 16: Opc = X86ISD::PSIGNW; break;
13427 case 32: Opc = X86ISD::PSIGND; break;
13431 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
13432 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
13435 // PBLENDVB only available on SSE 4.1
13436 if (!(Subtarget->hasSSE41() || Subtarget->hasAVX()))
13439 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
13440 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
13441 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
13442 Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y);
13443 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
13448 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13449 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13451 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13453 if (!N0.hasOneUse() || !N1.hasOneUse())
13456 SDValue ShAmt0 = N0.getOperand(1);
13457 if (ShAmt0.getValueType() != MVT::i8)
13459 SDValue ShAmt1 = N1.getOperand(1);
13460 if (ShAmt1.getValueType() != MVT::i8)
13462 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13463 ShAmt0 = ShAmt0.getOperand(0);
13464 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13465 ShAmt1 = ShAmt1.getOperand(0);
13467 DebugLoc DL = N->getDebugLoc();
13468 unsigned Opc = X86ISD::SHLD;
13469 SDValue Op0 = N0.getOperand(0);
13470 SDValue Op1 = N1.getOperand(0);
13471 if (ShAmt0.getOpcode() == ISD::SUB) {
13472 Opc = X86ISD::SHRD;
13473 std::swap(Op0, Op1);
13474 std::swap(ShAmt0, ShAmt1);
13477 unsigned Bits = VT.getSizeInBits();
13478 if (ShAmt1.getOpcode() == ISD::SUB) {
13479 SDValue Sum = ShAmt1.getOperand(0);
13480 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13481 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13482 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13483 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13484 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13485 return DAG.getNode(Opc, DL, VT,
13487 DAG.getNode(ISD::TRUNCATE, DL,
13490 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13491 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13493 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13494 return DAG.getNode(Opc, DL, VT,
13495 N0.getOperand(0), N1.getOperand(0),
13496 DAG.getNode(ISD::TRUNCATE, DL,
13503 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13504 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13505 const X86Subtarget *Subtarget) {
13506 LoadSDNode *Ld = cast<LoadSDNode>(N);
13507 EVT RegVT = Ld->getValueType(0);
13508 EVT MemVT = Ld->getMemoryVT();
13509 DebugLoc dl = Ld->getDebugLoc();
13510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13512 ISD::LoadExtType Ext = Ld->getExtensionType();
13514 // If this is a vector EXT Load then attempt to optimize it using a
13515 // shuffle. We need SSE4 for the shuffles.
13516 // TODO: It is possible to support ZExt by zeroing the undef values
13517 // during the shuffle phase or after the shuffle.
13518 if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13519 assert(MemVT != RegVT && "Cannot extend to the same type");
13520 assert(MemVT.isVector() && "Must load a vector from memory");
13522 unsigned NumElems = RegVT.getVectorNumElements();
13523 unsigned RegSz = RegVT.getSizeInBits();
13524 unsigned MemSz = MemVT.getSizeInBits();
13525 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13526 // All sizes must be a power of two
13527 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13529 // Attempt to load the original value using a single load op.
13530 // Find a scalar type which is equal to the loaded word size.
13531 MVT SclrLoadTy = MVT::i8;
13532 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13533 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13534 MVT Tp = (MVT::SimpleValueType)tp;
13535 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13541 // Proceed if a load word is found.
13542 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13544 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13545 RegSz/SclrLoadTy.getSizeInBits());
13547 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13548 RegSz/MemVT.getScalarType().getSizeInBits());
13549 // Can't shuffle using an illegal type.
13550 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13552 // Perform a single load.
13553 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
13555 Ld->getPointerInfo(), Ld->isVolatile(),
13556 Ld->isNonTemporal(), Ld->getAlignment());
13558 // Insert the word loaded into a vector.
13559 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13560 LoadUnitVecVT, ScalarLoad);
13562 // Bitcast the loaded value to a vector of the original element type, in
13563 // the size of the target vector type.
13564 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector);
13565 unsigned SizeRatio = RegSz/MemSz;
13567 // Redistribute the loaded elements into the different locations.
13568 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13569 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
13571 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13572 DAG.getUNDEF(SlicedVec.getValueType()),
13573 ShuffleVec.data());
13575 // Bitcast to the requested type.
13576 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13577 // Replace the original load with the new sequence
13578 // and return the new chain.
13579 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
13580 return SDValue(ScalarLoad.getNode(), 1);
13586 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13587 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13588 const X86Subtarget *Subtarget) {
13589 StoreSDNode *St = cast<StoreSDNode>(N);
13590 EVT VT = St->getValue().getValueType();
13591 EVT StVT = St->getMemoryVT();
13592 DebugLoc dl = St->getDebugLoc();
13593 SDValue StoredVal = St->getOperand(1);
13594 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13596 // If we are saving a concatination of two XMM registers, perform two stores.
13597 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13598 // 128-bit ones. If in the future the cost becomes only one memory access the
13599 // first version would be better.
13600 if (VT.getSizeInBits() == 256 &&
13601 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13602 StoredVal.getNumOperands() == 2) {
13604 SDValue Value0 = StoredVal.getOperand(0);
13605 SDValue Value1 = StoredVal.getOperand(1);
13607 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13608 SDValue Ptr0 = St->getBasePtr();
13609 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13611 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13612 St->getPointerInfo(), St->isVolatile(),
13613 St->isNonTemporal(), St->getAlignment());
13614 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13615 St->getPointerInfo(), St->isVolatile(),
13616 St->isNonTemporal(), St->getAlignment());
13617 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13620 // Optimize trunc store (of multiple scalars) to shuffle and store.
13621 // First, pack all of the elements in one place. Next, store to memory
13622 // in fewer chunks.
13623 if (St->isTruncatingStore() && VT.isVector()) {
13624 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13625 unsigned NumElems = VT.getVectorNumElements();
13626 assert(StVT != VT && "Cannot truncate to the same type");
13627 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13628 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13630 // From, To sizes and ElemCount must be pow of two
13631 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13632 // We are going to use the original vector elt for storing.
13633 // Accumulated smaller vector elements must be a multiple of the store size.
13634 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
13636 unsigned SizeRatio = FromSz / ToSz;
13638 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13640 // Create a type on which we perform the shuffle
13641 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13642 StVT.getScalarType(), NumElems*SizeRatio);
13644 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13646 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13647 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13648 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13650 // Can't shuffle using an illegal type
13651 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13653 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13654 DAG.getUNDEF(WideVec.getValueType()),
13655 ShuffleVec.data());
13656 // At this point all of the data is stored at the bottom of the
13657 // register. We now need to save it to mem.
13659 // Find the largest store unit
13660 MVT StoreType = MVT::i8;
13661 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13662 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13663 MVT Tp = (MVT::SimpleValueType)tp;
13664 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
13668 // Bitcast the original vector into a vector of store-size units
13669 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
13670 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
13671 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
13672 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
13673 SmallVector<SDValue, 8> Chains;
13674 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
13675 TLI.getPointerTy());
13676 SDValue Ptr = St->getBasePtr();
13678 // Perform one or more big stores into memory.
13679 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
13680 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13681 StoreType, ShuffWide,
13682 DAG.getIntPtrConstant(i));
13683 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
13684 St->getPointerInfo(), St->isVolatile(),
13685 St->isNonTemporal(), St->getAlignment());
13686 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13687 Chains.push_back(Ch);
13690 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
13695 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
13696 // the FP state in cases where an emms may be missing.
13697 // A preferable solution to the general problem is to figure out the right
13698 // places to insert EMMS. This qualifies as a quick hack.
13700 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13701 if (VT.getSizeInBits() != 64)
13704 const Function *F = DAG.getMachineFunction().getFunction();
13705 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13706 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13707 && Subtarget->hasXMMInt();
13708 if ((VT.isVector() ||
13709 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13710 isa<LoadSDNode>(St->getValue()) &&
13711 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13712 St->getChain().hasOneUse() && !St->isVolatile()) {
13713 SDNode* LdVal = St->getValue().getNode();
13714 LoadSDNode *Ld = 0;
13715 int TokenFactorIndex = -1;
13716 SmallVector<SDValue, 8> Ops;
13717 SDNode* ChainVal = St->getChain().getNode();
13718 // Must be a store of a load. We currently handle two cases: the load
13719 // is a direct child, and it's under an intervening TokenFactor. It is
13720 // possible to dig deeper under nested TokenFactors.
13721 if (ChainVal == LdVal)
13722 Ld = cast<LoadSDNode>(St->getChain());
13723 else if (St->getValue().hasOneUse() &&
13724 ChainVal->getOpcode() == ISD::TokenFactor) {
13725 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13726 if (ChainVal->getOperand(i).getNode() == LdVal) {
13727 TokenFactorIndex = i;
13728 Ld = cast<LoadSDNode>(St->getValue());
13730 Ops.push_back(ChainVal->getOperand(i));
13734 if (!Ld || !ISD::isNormalLoad(Ld))
13737 // If this is not the MMX case, i.e. we are just turning i64 load/store
13738 // into f64 load/store, avoid the transformation if there are multiple
13739 // uses of the loaded value.
13740 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13743 DebugLoc LdDL = Ld->getDebugLoc();
13744 DebugLoc StDL = N->getDebugLoc();
13745 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13746 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13748 if (Subtarget->is64Bit() || F64IsLegal) {
13749 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13750 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13751 Ld->getPointerInfo(), Ld->isVolatile(),
13752 Ld->isNonTemporal(), Ld->getAlignment());
13753 SDValue NewChain = NewLd.getValue(1);
13754 if (TokenFactorIndex != -1) {
13755 Ops.push_back(NewChain);
13756 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13759 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13760 St->getPointerInfo(),
13761 St->isVolatile(), St->isNonTemporal(),
13762 St->getAlignment());
13765 // Otherwise, lower to two pairs of 32-bit loads / stores.
13766 SDValue LoAddr = Ld->getBasePtr();
13767 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13768 DAG.getConstant(4, MVT::i32));
13770 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13771 Ld->getPointerInfo(),
13772 Ld->isVolatile(), Ld->isNonTemporal(),
13773 Ld->getAlignment());
13774 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13775 Ld->getPointerInfo().getWithOffset(4),
13776 Ld->isVolatile(), Ld->isNonTemporal(),
13777 MinAlign(Ld->getAlignment(), 4));
13779 SDValue NewChain = LoLd.getValue(1);
13780 if (TokenFactorIndex != -1) {
13781 Ops.push_back(LoLd);
13782 Ops.push_back(HiLd);
13783 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13787 LoAddr = St->getBasePtr();
13788 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13789 DAG.getConstant(4, MVT::i32));
13791 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13792 St->getPointerInfo(),
13793 St->isVolatile(), St->isNonTemporal(),
13794 St->getAlignment());
13795 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13796 St->getPointerInfo().getWithOffset(4),
13798 St->isNonTemporal(),
13799 MinAlign(St->getAlignment(), 4));
13800 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13805 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
13806 /// and return the operands for the horizontal operation in LHS and RHS. A
13807 /// horizontal operation performs the binary operation on successive elements
13808 /// of its first operand, then on successive elements of its second operand,
13809 /// returning the resulting values in a vector. For example, if
13810 /// A = < float a0, float a1, float a2, float a3 >
13812 /// B = < float b0, float b1, float b2, float b3 >
13813 /// then the result of doing a horizontal operation on A and B is
13814 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
13815 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
13816 /// A horizontal-op B, for some already available A and B, and if so then LHS is
13817 /// set to A, RHS to B, and the routine returns 'true'.
13818 /// Note that the binary operation should have the property that if one of the
13819 /// operands is UNDEF then the result is UNDEF.
13820 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool isCommutative) {
13821 // Look for the following pattern: if
13822 // A = < float a0, float a1, float a2, float a3 >
13823 // B = < float b0, float b1, float b2, float b3 >
13825 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
13826 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
13827 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
13828 // which is A horizontal-op B.
13830 // At least one of the operands should be a vector shuffle.
13831 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
13832 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
13835 EVT VT = LHS.getValueType();
13836 unsigned N = VT.getVectorNumElements();
13838 // View LHS in the form
13839 // LHS = VECTOR_SHUFFLE A, B, LMask
13840 // If LHS is not a shuffle then pretend it is the shuffle
13841 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
13842 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
13845 SmallVector<int, 8> LMask(N);
13846 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
13847 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
13848 A = LHS.getOperand(0);
13849 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
13850 B = LHS.getOperand(1);
13851 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask);
13853 if (LHS.getOpcode() != ISD::UNDEF)
13855 for (unsigned i = 0; i != N; ++i)
13859 // Likewise, view RHS in the form
13860 // RHS = VECTOR_SHUFFLE C, D, RMask
13862 SmallVector<int, 8> RMask(N);
13863 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
13864 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
13865 C = RHS.getOperand(0);
13866 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
13867 D = RHS.getOperand(1);
13868 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask);
13870 if (RHS.getOpcode() != ISD::UNDEF)
13872 for (unsigned i = 0; i != N; ++i)
13876 // Check that the shuffles are both shuffling the same vectors.
13877 if (!(A == C && B == D) && !(A == D && B == C))
13880 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
13881 if (!A.getNode() && !B.getNode())
13884 // If A and B occur in reverse order in RHS, then "swap" them (which means
13885 // rewriting the mask).
13887 for (unsigned i = 0; i != N; ++i) {
13888 unsigned Idx = RMask[i];
13891 else if (Idx < 2*N)
13895 // At this point LHS and RHS are equivalent to
13896 // LHS = VECTOR_SHUFFLE A, B, LMask
13897 // RHS = VECTOR_SHUFFLE A, B, RMask
13898 // Check that the masks correspond to performing a horizontal operation.
13899 for (unsigned i = 0; i != N; ++i) {
13900 unsigned LIdx = LMask[i], RIdx = RMask[i];
13902 // Ignore any UNDEF components.
13903 if (LIdx >= 2*N || RIdx >= 2*N || (!A.getNode() && (LIdx < N || RIdx < N))
13904 || (!B.getNode() && (LIdx >= N || RIdx >= N)))
13907 // Check that successive elements are being operated on. If not, this is
13908 // not a horizontal operation.
13909 if (!(LIdx == 2*i && RIdx == 2*i + 1) &&
13910 !(isCommutative && LIdx == 2*i + 1 && RIdx == 2*i))
13914 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
13915 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
13919 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
13920 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
13921 const X86Subtarget *Subtarget) {
13922 EVT VT = N->getValueType(0);
13923 SDValue LHS = N->getOperand(0);
13924 SDValue RHS = N->getOperand(1);
13926 // Try to synthesize horizontal adds from adds of shuffles.
13927 if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) &&
13928 (VT == MVT::v4f32 || VT == MVT::v2f64) &&
13929 isHorizontalBinOp(LHS, RHS, true))
13930 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
13934 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
13935 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
13936 const X86Subtarget *Subtarget) {
13937 EVT VT = N->getValueType(0);
13938 SDValue LHS = N->getOperand(0);
13939 SDValue RHS = N->getOperand(1);
13941 // Try to synthesize horizontal subs from subs of shuffles.
13942 if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) &&
13943 (VT == MVT::v4f32 || VT == MVT::v2f64) &&
13944 isHorizontalBinOp(LHS, RHS, false))
13945 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
13949 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13950 /// X86ISD::FXOR nodes.
13951 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13952 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13953 // F[X]OR(0.0, x) -> x
13954 // F[X]OR(x, 0.0) -> x
13955 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13956 if (C->getValueAPF().isPosZero())
13957 return N->getOperand(1);
13958 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13959 if (C->getValueAPF().isPosZero())
13960 return N->getOperand(0);
13964 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13965 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13966 // FAND(0.0, x) -> 0.0
13967 // FAND(x, 0.0) -> 0.0
13968 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13969 if (C->getValueAPF().isPosZero())
13970 return N->getOperand(0);
13971 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13972 if (C->getValueAPF().isPosZero())
13973 return N->getOperand(1);
13977 static SDValue PerformBTCombine(SDNode *N,
13979 TargetLowering::DAGCombinerInfo &DCI) {
13980 // BT ignores high bits in the bit index operand.
13981 SDValue Op1 = N->getOperand(1);
13982 if (Op1.hasOneUse()) {
13983 unsigned BitWidth = Op1.getValueSizeInBits();
13984 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13985 APInt KnownZero, KnownOne;
13986 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13987 !DCI.isBeforeLegalizeOps());
13988 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13989 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13990 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13991 DCI.CommitTargetLoweringOpt(TLO);
13996 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13997 SDValue Op = N->getOperand(0);
13998 if (Op.getOpcode() == ISD::BITCAST)
13999 Op = Op.getOperand(0);
14000 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14001 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14002 VT.getVectorElementType().getSizeInBits() ==
14003 OpVT.getVectorElementType().getSizeInBits()) {
14004 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14009 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
14010 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14011 // (and (i32 x86isd::setcc_carry), 1)
14012 // This eliminates the zext. This transformation is necessary because
14013 // ISD::SETCC is always legalized to i8.
14014 DebugLoc dl = N->getDebugLoc();
14015 SDValue N0 = N->getOperand(0);
14016 EVT VT = N->getValueType(0);
14017 if (N0.getOpcode() == ISD::AND &&
14019 N0.getOperand(0).hasOneUse()) {
14020 SDValue N00 = N0.getOperand(0);
14021 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14023 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14024 if (!C || C->getZExtValue() != 1)
14026 return DAG.getNode(ISD::AND, dl, VT,
14027 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14028 N00.getOperand(0), N00.getOperand(1)),
14029 DAG.getConstant(1, VT));
14035 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14036 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14037 unsigned X86CC = N->getConstantOperandVal(0);
14038 SDValue EFLAG = N->getOperand(1);
14039 DebugLoc DL = N->getDebugLoc();
14041 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14042 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14044 if (X86CC == X86::COND_B)
14045 return DAG.getNode(ISD::AND, DL, MVT::i8,
14046 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14047 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14048 DAG.getConstant(1, MVT::i8));
14053 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14054 const X86TargetLowering *XTLI) {
14055 SDValue Op0 = N->getOperand(0);
14056 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14057 // a 32-bit target where SSE doesn't support i64->FP operations.
14058 if (Op0.getOpcode() == ISD::LOAD) {
14059 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14060 EVT VT = Ld->getValueType(0);
14061 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14062 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14063 !XTLI->getSubtarget()->is64Bit() &&
14064 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14065 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14066 Ld->getChain(), Op0, DAG);
14067 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14074 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14075 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14076 X86TargetLowering::DAGCombinerInfo &DCI) {
14077 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14078 // the result is either zero or one (depending on the input carry bit).
14079 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14080 if (X86::isZeroNode(N->getOperand(0)) &&
14081 X86::isZeroNode(N->getOperand(1)) &&
14082 // We don't have a good way to replace an EFLAGS use, so only do this when
14084 SDValue(N, 1).use_empty()) {
14085 DebugLoc DL = N->getDebugLoc();
14086 EVT VT = N->getValueType(0);
14087 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14088 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14089 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14090 DAG.getConstant(X86::COND_B,MVT::i8),
14092 DAG.getConstant(1, VT));
14093 return DCI.CombineTo(N, Res1, CarryOut);
14099 // fold (add Y, (sete X, 0)) -> adc 0, Y
14100 // (add Y, (setne X, 0)) -> sbb -1, Y
14101 // (sub (sete X, 0), Y) -> sbb 0, Y
14102 // (sub (setne X, 0), Y) -> adc -1, Y
14103 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14104 DebugLoc DL = N->getDebugLoc();
14106 // Look through ZExts.
14107 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14108 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14111 SDValue SetCC = Ext.getOperand(0);
14112 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14115 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14116 if (CC != X86::COND_E && CC != X86::COND_NE)
14119 SDValue Cmp = SetCC.getOperand(1);
14120 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14121 !X86::isZeroNode(Cmp.getOperand(1)) ||
14122 !Cmp.getOperand(0).getValueType().isInteger())
14125 SDValue CmpOp0 = Cmp.getOperand(0);
14126 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14127 DAG.getConstant(1, CmpOp0.getValueType()));
14129 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14130 if (CC == X86::COND_NE)
14131 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14132 DL, OtherVal.getValueType(), OtherVal,
14133 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14134 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14135 DL, OtherVal.getValueType(), OtherVal,
14136 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14139 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
14140 SDValue Op0 = N->getOperand(0);
14141 SDValue Op1 = N->getOperand(1);
14143 // X86 can't encode an immediate LHS of a sub. See if we can push the
14144 // negation into a preceding instruction.
14145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14146 // If the RHS of the sub is a XOR with one use and a constant, invert the
14147 // immediate. Then add one to the LHS of the sub so we can turn
14148 // X-Y -> X+~Y+1, saving one register.
14149 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14150 isa<ConstantSDNode>(Op1.getOperand(1))) {
14151 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14152 EVT VT = Op0.getValueType();
14153 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14155 DAG.getConstant(~XorC, VT));
14156 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14157 DAG.getConstant(C->getAPIntValue()+1, VT));
14161 return OptimizeConditionalInDecrement(N, DAG);
14164 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14165 DAGCombinerInfo &DCI) const {
14166 SelectionDAG &DAG = DCI.DAG;
14167 switch (N->getOpcode()) {
14169 case ISD::EXTRACT_VECTOR_ELT:
14170 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14172 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
14173 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14174 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
14175 case ISD::SUB: return PerformSubCombine(N, DAG);
14176 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14177 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14180 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14181 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14182 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14183 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14184 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14185 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14186 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14187 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14189 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14190 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14191 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14192 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14193 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
14194 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14195 case X86ISD::SHUFPS: // Handle all target specific shuffles
14196 case X86ISD::SHUFPD:
14197 case X86ISD::PALIGN:
14198 case X86ISD::PUNPCKHBW:
14199 case X86ISD::PUNPCKHWD:
14200 case X86ISD::PUNPCKHDQ:
14201 case X86ISD::PUNPCKHQDQ:
14202 case X86ISD::UNPCKHPS:
14203 case X86ISD::UNPCKHPD:
14204 case X86ISD::VUNPCKHPSY:
14205 case X86ISD::VUNPCKHPDY:
14206 case X86ISD::PUNPCKLBW:
14207 case X86ISD::PUNPCKLWD:
14208 case X86ISD::PUNPCKLDQ:
14209 case X86ISD::PUNPCKLQDQ:
14210 case X86ISD::UNPCKLPS:
14211 case X86ISD::UNPCKLPD:
14212 case X86ISD::VUNPCKLPSY:
14213 case X86ISD::VUNPCKLPDY:
14214 case X86ISD::MOVHLPS:
14215 case X86ISD::MOVLHPS:
14216 case X86ISD::PSHUFD:
14217 case X86ISD::PSHUFHW:
14218 case X86ISD::PSHUFLW:
14219 case X86ISD::MOVSS:
14220 case X86ISD::MOVSD:
14221 case X86ISD::VPERMILPS:
14222 case X86ISD::VPERMILPSY:
14223 case X86ISD::VPERMILPD:
14224 case X86ISD::VPERMILPDY:
14225 case X86ISD::VPERM2F128:
14226 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14232 /// isTypeDesirableForOp - Return true if the target has native support for
14233 /// the specified value type and it is 'desirable' to use the type for the
14234 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14235 /// instruction encodings are longer and some i16 instructions are slow.
14236 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14237 if (!isTypeLegal(VT))
14239 if (VT != MVT::i16)
14246 case ISD::SIGN_EXTEND:
14247 case ISD::ZERO_EXTEND:
14248 case ISD::ANY_EXTEND:
14261 /// IsDesirableToPromoteOp - This method query the target whether it is
14262 /// beneficial for dag combiner to promote the specified node. If true, it
14263 /// should return the desired promotion type by reference.
14264 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14265 EVT VT = Op.getValueType();
14266 if (VT != MVT::i16)
14269 bool Promote = false;
14270 bool Commute = false;
14271 switch (Op.getOpcode()) {
14274 LoadSDNode *LD = cast<LoadSDNode>(Op);
14275 // If the non-extending load has a single use and it's not live out, then it
14276 // might be folded.
14277 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14278 Op.hasOneUse()*/) {
14279 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14280 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14281 // The only case where we'd want to promote LOAD (rather then it being
14282 // promoted as an operand is when it's only use is liveout.
14283 if (UI->getOpcode() != ISD::CopyToReg)
14290 case ISD::SIGN_EXTEND:
14291 case ISD::ZERO_EXTEND:
14292 case ISD::ANY_EXTEND:
14297 SDValue N0 = Op.getOperand(0);
14298 // Look out for (store (shl (load), x)).
14299 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14312 SDValue N0 = Op.getOperand(0);
14313 SDValue N1 = Op.getOperand(1);
14314 if (!Commute && MayFoldLoad(N1))
14316 // Avoid disabling potential load folding opportunities.
14317 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14319 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14329 //===----------------------------------------------------------------------===//
14330 // X86 Inline Assembly Support
14331 //===----------------------------------------------------------------------===//
14333 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14334 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14336 std::string AsmStr = IA->getAsmString();
14338 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14339 SmallVector<StringRef, 4> AsmPieces;
14340 SplitString(AsmStr, AsmPieces, ";\n");
14342 switch (AsmPieces.size()) {
14343 default: return false;
14345 AsmStr = AsmPieces[0];
14347 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
14349 // FIXME: this should verify that we are targeting a 486 or better. If not,
14350 // we will turn this bswap into something that will be lowered to logical ops
14351 // instead of emitting the bswap asm. For now, we don't support 486 or lower
14352 // so don't worry about this.
14354 if (AsmPieces.size() == 2 &&
14355 (AsmPieces[0] == "bswap" ||
14356 AsmPieces[0] == "bswapq" ||
14357 AsmPieces[0] == "bswapl") &&
14358 (AsmPieces[1] == "$0" ||
14359 AsmPieces[1] == "${0:q}")) {
14360 // No need to check constraints, nothing other than the equivalent of
14361 // "=r,0" would be valid here.
14362 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14363 if (!Ty || Ty->getBitWidth() % 16 != 0)
14365 return IntrinsicLowering::LowerToByteSwap(CI);
14367 // rorw $$8, ${0:w} --> llvm.bswap.i16
14368 if (CI->getType()->isIntegerTy(16) &&
14369 AsmPieces.size() == 3 &&
14370 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
14371 AsmPieces[1] == "$$8," &&
14372 AsmPieces[2] == "${0:w}" &&
14373 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14375 const std::string &ConstraintsStr = IA->getConstraintString();
14376 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14377 std::sort(AsmPieces.begin(), AsmPieces.end());
14378 if (AsmPieces.size() == 4 &&
14379 AsmPieces[0] == "~{cc}" &&
14380 AsmPieces[1] == "~{dirflag}" &&
14381 AsmPieces[2] == "~{flags}" &&
14382 AsmPieces[3] == "~{fpsr}") {
14383 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14384 if (!Ty || Ty->getBitWidth() % 16 != 0)
14386 return IntrinsicLowering::LowerToByteSwap(CI);
14391 if (CI->getType()->isIntegerTy(32) &&
14392 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14393 SmallVector<StringRef, 4> Words;
14394 SplitString(AsmPieces[0], Words, " \t,");
14395 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14396 Words[2] == "${0:w}") {
14398 SplitString(AsmPieces[1], Words, " \t,");
14399 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
14400 Words[2] == "$0") {
14402 SplitString(AsmPieces[2], Words, " \t,");
14403 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14404 Words[2] == "${0:w}") {
14406 const std::string &ConstraintsStr = IA->getConstraintString();
14407 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14408 std::sort(AsmPieces.begin(), AsmPieces.end());
14409 if (AsmPieces.size() == 4 &&
14410 AsmPieces[0] == "~{cc}" &&
14411 AsmPieces[1] == "~{dirflag}" &&
14412 AsmPieces[2] == "~{flags}" &&
14413 AsmPieces[3] == "~{fpsr}") {
14414 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14415 if (!Ty || Ty->getBitWidth() % 16 != 0)
14417 return IntrinsicLowering::LowerToByteSwap(CI);
14424 if (CI->getType()->isIntegerTy(64)) {
14425 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14426 if (Constraints.size() >= 2 &&
14427 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14428 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14429 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14430 SmallVector<StringRef, 4> Words;
14431 SplitString(AsmPieces[0], Words, " \t");
14432 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
14434 SplitString(AsmPieces[1], Words, " \t");
14435 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
14437 SplitString(AsmPieces[2], Words, " \t,");
14438 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
14439 Words[2] == "%edx") {
14440 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14441 if (!Ty || Ty->getBitWidth() % 16 != 0)
14443 return IntrinsicLowering::LowerToByteSwap(CI);
14456 /// getConstraintType - Given a constraint letter, return the type of
14457 /// constraint it is for this target.
14458 X86TargetLowering::ConstraintType
14459 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14460 if (Constraint.size() == 1) {
14461 switch (Constraint[0]) {
14472 return C_RegisterClass;
14496 return TargetLowering::getConstraintType(Constraint);
14499 /// Examine constraint type and operand type and determine a weight value.
14500 /// This object must already have been set up with the operand type
14501 /// and the current alternative constraint selected.
14502 TargetLowering::ConstraintWeight
14503 X86TargetLowering::getSingleConstraintMatchWeight(
14504 AsmOperandInfo &info, const char *constraint) const {
14505 ConstraintWeight weight = CW_Invalid;
14506 Value *CallOperandVal = info.CallOperandVal;
14507 // If we don't have a value, we can't do a match,
14508 // but allow it at the lowest weight.
14509 if (CallOperandVal == NULL)
14511 Type *type = CallOperandVal->getType();
14512 // Look at the constraint type.
14513 switch (*constraint) {
14515 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14526 if (CallOperandVal->getType()->isIntegerTy())
14527 weight = CW_SpecificReg;
14532 if (type->isFloatingPointTy())
14533 weight = CW_SpecificReg;
14536 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14537 weight = CW_SpecificReg;
14541 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14542 weight = CW_Register;
14545 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14546 if (C->getZExtValue() <= 31)
14547 weight = CW_Constant;
14551 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14552 if (C->getZExtValue() <= 63)
14553 weight = CW_Constant;
14557 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14558 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14559 weight = CW_Constant;
14563 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14564 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14565 weight = CW_Constant;
14569 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14570 if (C->getZExtValue() <= 3)
14571 weight = CW_Constant;
14575 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14576 if (C->getZExtValue() <= 0xff)
14577 weight = CW_Constant;
14582 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14583 weight = CW_Constant;
14587 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14588 if ((C->getSExtValue() >= -0x80000000LL) &&
14589 (C->getSExtValue() <= 0x7fffffffLL))
14590 weight = CW_Constant;
14594 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14595 if (C->getZExtValue() <= 0xffffffff)
14596 weight = CW_Constant;
14603 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14604 /// with another that has more specific requirements based on the type of the
14605 /// corresponding operand.
14606 const char *X86TargetLowering::
14607 LowerXConstraint(EVT ConstraintVT) const {
14608 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14609 // 'f' like normal targets.
14610 if (ConstraintVT.isFloatingPoint()) {
14611 if (Subtarget->hasXMMInt())
14613 if (Subtarget->hasXMM())
14617 return TargetLowering::LowerXConstraint(ConstraintVT);
14620 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14621 /// vector. If it is invalid, don't add anything to Ops.
14622 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14623 std::string &Constraint,
14624 std::vector<SDValue>&Ops,
14625 SelectionDAG &DAG) const {
14626 SDValue Result(0, 0);
14628 // Only support length 1 constraints for now.
14629 if (Constraint.length() > 1) return;
14631 char ConstraintLetter = Constraint[0];
14632 switch (ConstraintLetter) {
14635 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14636 if (C->getZExtValue() <= 31) {
14637 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14643 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14644 if (C->getZExtValue() <= 63) {
14645 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14651 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14652 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
14653 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14659 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14660 if (C->getZExtValue() <= 255) {
14661 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14667 // 32-bit signed value
14668 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14669 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14670 C->getSExtValue())) {
14671 // Widen to 64 bits here to get it sign extended.
14672 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
14675 // FIXME gcc accepts some relocatable values here too, but only in certain
14676 // memory models; it's complicated.
14681 // 32-bit unsigned value
14682 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14683 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14684 C->getZExtValue())) {
14685 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14689 // FIXME gcc accepts some relocatable values here too, but only in certain
14690 // memory models; it's complicated.
14694 // Literal immediates are always ok.
14695 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
14696 // Widen to 64 bits here to get it sign extended.
14697 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
14701 // In any sort of PIC mode addresses need to be computed at runtime by
14702 // adding in a register or some sort of table lookup. These can't
14703 // be used as immediates.
14704 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
14707 // If we are in non-pic codegen mode, we allow the address of a global (with
14708 // an optional displacement) to be used with 'i'.
14709 GlobalAddressSDNode *GA = 0;
14710 int64_t Offset = 0;
14712 // Match either (GA), (GA+C), (GA+C1+C2), etc.
14714 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
14715 Offset += GA->getOffset();
14717 } else if (Op.getOpcode() == ISD::ADD) {
14718 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14719 Offset += C->getZExtValue();
14720 Op = Op.getOperand(0);
14723 } else if (Op.getOpcode() == ISD::SUB) {
14724 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14725 Offset += -C->getZExtValue();
14726 Op = Op.getOperand(0);
14731 // Otherwise, this isn't something we can handle, reject it.
14735 const GlobalValue *GV = GA->getGlobal();
14736 // If we require an extra load to get this address, as in PIC mode, we
14737 // can't accept it.
14738 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
14739 getTargetMachine())))
14742 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
14743 GA->getValueType(0), Offset);
14748 if (Result.getNode()) {
14749 Ops.push_back(Result);
14752 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14755 std::pair<unsigned, const TargetRegisterClass*>
14756 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
14758 // First, see if this is a constraint that directly corresponds to an LLVM
14760 if (Constraint.size() == 1) {
14761 // GCC Constraint Letters
14762 switch (Constraint[0]) {
14764 // TODO: Slight differences here in allocation order and leaving
14765 // RIP in the class. Do they matter any more here than they do
14766 // in the normal allocation?
14767 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
14768 if (Subtarget->is64Bit()) {
14769 if (VT == MVT::i32 || VT == MVT::f32)
14770 return std::make_pair(0U, X86::GR32RegisterClass);
14771 else if (VT == MVT::i16)
14772 return std::make_pair(0U, X86::GR16RegisterClass);
14773 else if (VT == MVT::i8 || VT == MVT::i1)
14774 return std::make_pair(0U, X86::GR8RegisterClass);
14775 else if (VT == MVT::i64 || VT == MVT::f64)
14776 return std::make_pair(0U, X86::GR64RegisterClass);
14779 // 32-bit fallthrough
14780 case 'Q': // Q_REGS
14781 if (VT == MVT::i32 || VT == MVT::f32)
14782 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
14783 else if (VT == MVT::i16)
14784 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
14785 else if (VT == MVT::i8 || VT == MVT::i1)
14786 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
14787 else if (VT == MVT::i64)
14788 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
14790 case 'r': // GENERAL_REGS
14791 case 'l': // INDEX_REGS
14792 if (VT == MVT::i8 || VT == MVT::i1)
14793 return std::make_pair(0U, X86::GR8RegisterClass);
14794 if (VT == MVT::i16)
14795 return std::make_pair(0U, X86::GR16RegisterClass);
14796 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
14797 return std::make_pair(0U, X86::GR32RegisterClass);
14798 return std::make_pair(0U, X86::GR64RegisterClass);
14799 case 'R': // LEGACY_REGS
14800 if (VT == MVT::i8 || VT == MVT::i1)
14801 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
14802 if (VT == MVT::i16)
14803 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
14804 if (VT == MVT::i32 || !Subtarget->is64Bit())
14805 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
14806 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
14807 case 'f': // FP Stack registers.
14808 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
14809 // value to the correct fpstack register class.
14810 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
14811 return std::make_pair(0U, X86::RFP32RegisterClass);
14812 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
14813 return std::make_pair(0U, X86::RFP64RegisterClass);
14814 return std::make_pair(0U, X86::RFP80RegisterClass);
14815 case 'y': // MMX_REGS if MMX allowed.
14816 if (!Subtarget->hasMMX()) break;
14817 return std::make_pair(0U, X86::VR64RegisterClass);
14818 case 'Y': // SSE_REGS if SSE2 allowed
14819 if (!Subtarget->hasXMMInt()) break;
14821 case 'x': // SSE_REGS if SSE1 allowed
14822 if (!Subtarget->hasXMM()) break;
14824 switch (VT.getSimpleVT().SimpleTy) {
14826 // Scalar SSE types.
14829 return std::make_pair(0U, X86::FR32RegisterClass);
14832 return std::make_pair(0U, X86::FR64RegisterClass);
14840 return std::make_pair(0U, X86::VR128RegisterClass);
14846 // Use the default implementation in TargetLowering to convert the register
14847 // constraint into a member of a register class.
14848 std::pair<unsigned, const TargetRegisterClass*> Res;
14849 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
14851 // Not found as a standard register?
14852 if (Res.second == 0) {
14853 // Map st(0) -> st(7) -> ST0
14854 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14855 tolower(Constraint[1]) == 's' &&
14856 tolower(Constraint[2]) == 't' &&
14857 Constraint[3] == '(' &&
14858 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14859 Constraint[5] == ')' &&
14860 Constraint[6] == '}') {
14862 Res.first = X86::ST0+Constraint[4]-'0';
14863 Res.second = X86::RFP80RegisterClass;
14867 // GCC allows "st(0)" to be called just plain "st".
14868 if (StringRef("{st}").equals_lower(Constraint)) {
14869 Res.first = X86::ST0;
14870 Res.second = X86::RFP80RegisterClass;
14875 if (StringRef("{flags}").equals_lower(Constraint)) {
14876 Res.first = X86::EFLAGS;
14877 Res.second = X86::CCRRegisterClass;
14881 // 'A' means EAX + EDX.
14882 if (Constraint == "A") {
14883 Res.first = X86::EAX;
14884 Res.second = X86::GR32_ADRegisterClass;
14890 // Otherwise, check to see if this is a register class of the wrong value
14891 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14892 // turn into {ax},{dx}.
14893 if (Res.second->hasType(VT))
14894 return Res; // Correct type already, nothing to do.
14896 // All of the single-register GCC register classes map their values onto
14897 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14898 // really want an 8-bit or 32-bit register, map to the appropriate register
14899 // class and return the appropriate register.
14900 if (Res.second == X86::GR16RegisterClass) {
14901 if (VT == MVT::i8) {
14902 unsigned DestReg = 0;
14903 switch (Res.first) {
14905 case X86::AX: DestReg = X86::AL; break;
14906 case X86::DX: DestReg = X86::DL; break;
14907 case X86::CX: DestReg = X86::CL; break;
14908 case X86::BX: DestReg = X86::BL; break;
14911 Res.first = DestReg;
14912 Res.second = X86::GR8RegisterClass;
14914 } else if (VT == MVT::i32) {
14915 unsigned DestReg = 0;
14916 switch (Res.first) {
14918 case X86::AX: DestReg = X86::EAX; break;
14919 case X86::DX: DestReg = X86::EDX; break;
14920 case X86::CX: DestReg = X86::ECX; break;
14921 case X86::BX: DestReg = X86::EBX; break;
14922 case X86::SI: DestReg = X86::ESI; break;
14923 case X86::DI: DestReg = X86::EDI; break;
14924 case X86::BP: DestReg = X86::EBP; break;
14925 case X86::SP: DestReg = X86::ESP; break;
14928 Res.first = DestReg;
14929 Res.second = X86::GR32RegisterClass;
14931 } else if (VT == MVT::i64) {
14932 unsigned DestReg = 0;
14933 switch (Res.first) {
14935 case X86::AX: DestReg = X86::RAX; break;
14936 case X86::DX: DestReg = X86::RDX; break;
14937 case X86::CX: DestReg = X86::RCX; break;
14938 case X86::BX: DestReg = X86::RBX; break;
14939 case X86::SI: DestReg = X86::RSI; break;
14940 case X86::DI: DestReg = X86::RDI; break;
14941 case X86::BP: DestReg = X86::RBP; break;
14942 case X86::SP: DestReg = X86::RSP; break;
14945 Res.first = DestReg;
14946 Res.second = X86::GR64RegisterClass;
14949 } else if (Res.second == X86::FR32RegisterClass ||
14950 Res.second == X86::FR64RegisterClass ||
14951 Res.second == X86::VR128RegisterClass) {
14952 // Handle references to XMM physical registers that got mapped into the
14953 // wrong class. This can happen with constraints like {xmm0} where the
14954 // target independent register mapper will just pick the first match it can
14955 // find, ignoring the required type.
14956 if (VT == MVT::f32)
14957 Res.second = X86::FR32RegisterClass;
14958 else if (VT == MVT::f64)
14959 Res.second = X86::FR64RegisterClass;
14960 else if (X86::VR128RegisterClass->hasType(VT))
14961 Res.second = X86::VR128RegisterClass;