1 //===- X86InstrVMX.td - VMX Instruction Set Extension ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the instructions that make up the Intel VMX instruction
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept {$src2, $src1|$src1, $src2}", []>, OpSize, T8;
21 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
22 "invept {$src2, $src1|$src1, $src2}", []>, OpSize, T8;
24 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
25 "invvpid {$src2, $src1|$src1, $src2}", []>, OpSize, T8;
26 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
27 "invvpid {$src2, $src1|$src1, $src2}", []>, OpSize, T8;
29 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
30 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
31 "vmclear\t$vmcs", []>, OpSize, TB;
33 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
35 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
36 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
37 "vmptrld\t$vmcs", []>, TB;
38 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
39 "vmptrst\t$vmcs", []>, TB;
40 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
41 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
42 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
43 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
44 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
45 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
46 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
47 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
48 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
49 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
50 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
51 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
52 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
53 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
54 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
55 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
57 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
58 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
59 "vmxon\t{$vmxon}", []>, XS;