2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
38 #include <machine/bus.h>
40 #include <dev/uart/uart.h>
41 #include <dev/uart/uart_cpu.h>
42 #include <dev/uart/uart_bus.h>
43 #include <arm/at91/at91rm92reg.h>
44 #include <arm/at91/at91_usartreg.h>
45 #include <arm/at91/at91_pdcreg.h>
46 #include <arm/at91/at91var.h>
50 #define DEFAULT_RCLK at91_master_clock
51 #define USART_BUFFER_SIZE 128
54 * High-level UART interface.
56 struct at91_usart_rx {
58 uint8_t buffer[USART_BUFFER_SIZE];
62 struct at91_usart_softc {
63 struct uart_softc base;
64 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
68 struct at91_usart_rx ping_pong[2];
69 struct at91_usart_rx *ping;
70 struct at91_usart_rx *pong;
73 #define RD4(bas, reg) \
74 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
75 #define WR4(bas, reg, value) \
76 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
78 #define SIGCHG(c, i, s, d) \
81 i |= (i & s) ? s : s | d; \
83 i = (i & s) ? (i & ~s) | d : i; \
87 #define BAUD2DIVISOR(b) \
88 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
91 * Low-level UART interface.
93 static int at91_usart_probe(struct uart_bas *bas);
94 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
95 static void at91_usart_term(struct uart_bas *bas);
96 static void at91_usart_putc(struct uart_bas *bas, int);
97 static int at91_usart_rxready(struct uart_bas *bas);
98 static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx);
100 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
103 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
104 int stopbits, int parity)
109 * Assume 3-write RS-232 configuration.
110 * XXX Not sure how uart will present the other modes to us, so
111 * XXX they are unimplemented. maybe ioctl?
113 mr = USART_MR_MODE_NORMAL;
114 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
117 * Or in the databits requested
120 mr &= ~USART_MR_MODE9;
123 mr |= USART_MR_CHRL_5BITS;
126 mr |= USART_MR_CHRL_6BITS;
129 mr |= USART_MR_CHRL_7BITS;
132 mr |= USART_MR_CHRL_8BITS;
135 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
145 case UART_PARITY_NONE:
146 mr |= USART_MR_PAR_NONE;
148 case UART_PARITY_ODD:
149 mr |= USART_MR_PAR_ODD;
151 case UART_PARITY_EVEN:
152 mr |= USART_MR_PAR_EVEN;
154 case UART_PARITY_MARK:
155 mr |= USART_MR_PAR_MARK;
157 case UART_PARITY_SPACE:
158 mr |= USART_MR_PAR_SPACE;
165 * Or in the stop bits. Note: The hardware supports 1.5 stop
166 * bits in async mode, but there's no way to specify that
167 * AFAICT. Instead, rely on the convention documented at
168 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
169 * states that 1.5 stop bits are used for 5 bit bytes and
170 * 2 stop bits only for longer bytes.
173 mr |= USART_MR_NBSTOP_1;
174 else if (databits > 5)
175 mr |= USART_MR_NBSTOP_2;
177 mr |= USART_MR_NBSTOP_1_5;
180 * We want normal plumbing mode too, none of this fancy
181 * loopback or echo mode.
183 mr |= USART_MR_CHMODE_NORMAL;
185 mr &= ~USART_MR_MSBF; /* lsb first */
186 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
188 WR4(bas, USART_MR, mr);
191 * Set the baud rate (only if we know our master clock rate)
193 if (DEFAULT_RCLK != 0)
194 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
196 /* XXX Need to take possible synchronous mode into account */
200 static struct uart_ops at91_usart_ops = {
201 .probe = at91_usart_probe,
202 .init = at91_usart_init,
203 .term = at91_usart_term,
204 .putc = at91_usart_putc,
205 .rxready = at91_usart_rxready,
206 .getc = at91_usart_getc,
210 at91_usart_probe(struct uart_bas *bas)
212 /* We know that this is always here */
217 * Initialize this device for use as a console.
220 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
224 at91_usart_param(bas, baudrate, databits, stopbits, parity);
226 /* Reset the rx and tx buffers and turn on rx and tx */
227 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
228 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
229 WR4(bas, USART_IDR, 0xffffffff);
233 * Free resources now that we're no longer the console. This appears to
234 * be never called, and I'm unsure quite what to do if I am called.
237 at91_usart_term(struct uart_bas *bas)
243 * Put a character of console output (so we do it here polling rather than
247 at91_usart_putc(struct uart_bas *bas, int c)
250 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
252 WR4(bas, USART_THR, c);
256 * Check for a character available.
259 at91_usart_rxready(struct uart_bas *bas)
262 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
266 * Block waiting for a character.
269 at91_usart_getc(struct uart_bas *bas, struct mtx *mtx)
273 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
275 c = RD4(bas, USART_RHR);
280 static int at91_usart_bus_probe(struct uart_softc *sc);
281 static int at91_usart_bus_attach(struct uart_softc *sc);
282 static int at91_usart_bus_flush(struct uart_softc *, int);
283 static int at91_usart_bus_getsig(struct uart_softc *);
284 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
285 static int at91_usart_bus_ipend(struct uart_softc *);
286 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
287 static int at91_usart_bus_receive(struct uart_softc *);
288 static int at91_usart_bus_setsig(struct uart_softc *, int);
289 static int at91_usart_bus_transmit(struct uart_softc *);
291 static kobj_method_t at91_usart_methods[] = {
292 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
293 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
294 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
295 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
296 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
297 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
298 KOBJMETHOD(uart_param, at91_usart_bus_param),
299 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
300 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
301 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
307 at91_usart_bus_probe(struct uart_softc *sc)
310 sc->sc_txfifosz = USART_BUFFER_SIZE;
311 sc->sc_rxfifosz = USART_BUFFER_SIZE;
317 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
321 *(bus_addr_t *)arg = segs[0].ds_addr;
325 at91_usart_bus_attach(struct uart_softc *sc)
330 struct at91_usart_softc *atsc;
332 atsc = (struct at91_usart_softc *)sc;
335 * See if we have a TIMEOUT bit. We disable all interrupts as
336 * a side effect. Boot loaders may have enabled them. Since
337 * a TIMEOUT interrupt can't happen without other setup, the
338 * apparent race here can't actually happen.
340 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
341 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
342 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
343 atsc->flags |= HAS_TIMEOUT;
344 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
347 * Allocate DMA tags and maps
349 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
350 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
351 USART_BUFFER_SIZE, 1, USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL,
352 NULL, &atsc->dmatag);
355 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map);
358 if (atsc->flags & HAS_TIMEOUT) {
359 for (i = 0; i < 2; i++) {
360 err = bus_dmamap_create(atsc->dmatag, 0,
361 &atsc->ping_pong[i].map);
364 err = bus_dmamap_load(atsc->dmatag,
365 atsc->ping_pong[i].map,
366 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
367 at91_getaddr, &atsc->ping_pong[i].pa, 0);
370 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map,
371 BUS_DMASYNC_PREREAD);
373 atsc->ping = &atsc->ping_pong[0];
374 atsc->pong = &atsc->ping_pong[1];
378 * Prime the pump with the RX buffer. We use two 64 byte bounce
379 * buffers here to avoid data overflow.
382 /* Turn on rx and tx */
383 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
384 WR4(&sc->sc_bas, USART_CR, cr);
385 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
388 * Setup the PDC to receive data. We use the ping-pong buffers
389 * so that we can more easily bounce between the two and so that
390 * we get an interrupt 1/2 way through the software 'fifo' we have
393 if (atsc->flags & HAS_TIMEOUT) {
394 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
395 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
396 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
397 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
398 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
400 /* Set the receive timeout to be 1.5 character times. */
401 WR4(&sc->sc_bas, USART_RTOR, 12);
402 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
403 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
404 USART_CSR_RXBUFF | USART_CSR_ENDRX);
406 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
408 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
415 at91_usart_bus_transmit(struct uart_softc *sc)
418 struct at91_usart_softc *atsc;
420 atsc = (struct at91_usart_softc *)sc;
421 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf,
422 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0)
424 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
426 uart_lock(sc->sc_hwmtx);
429 * Setup the PDC to transfer the data and interrupt us when it
430 * is done. We've already requested the interrupt.
432 WR4(&sc->sc_bas, PDC_TPR, addr);
433 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
434 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
435 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
436 uart_unlock(sc->sc_hwmtx);
440 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
442 uint32_t new, old, cr;
443 struct uart_bas *bas;
449 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
451 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
452 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
454 uart_lock(sc->sc_hwmtx);
457 cr |= USART_CR_DTREN;
459 cr |= USART_CR_DTRDIS;
461 cr |= USART_CR_RTSEN;
463 cr |= USART_CR_RTSDIS;
464 WR4(bas, USART_CR, cr);
465 uart_unlock(sc->sc_hwmtx);
469 at91_usart_bus_receive(struct uart_softc *sc)
475 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
476 int stopbits, int parity)
479 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
484 at91_rx_put(struct uart_softc *sc, int key)
488 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
489 kdb_alt_break(key, &sc->sc_altbrk);
491 uart_rx_put(sc, key);
495 at91_usart_bus_ipend(struct uart_softc *sc)
497 int csr = RD4(&sc->sc_bas, USART_CSR);
498 int ipend = 0, i, len;
499 struct at91_usart_softc *atsc;
500 struct at91_usart_rx *p;
502 atsc = (struct at91_usart_softc *)sc;
503 if (csr & USART_CSR_ENDTX) {
504 bus_dmamap_sync(atsc->dmatag, atsc->tx_map,
505 BUS_DMASYNC_POSTWRITE);
506 bus_dmamap_unload(atsc->dmatag, atsc->tx_map);
508 uart_lock(sc->sc_hwmtx);
509 if (csr & USART_CSR_TXRDY) {
511 ipend |= SER_INT_TXIDLE;
512 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY);
514 if (csr & USART_CSR_ENDTX) {
516 ipend |= SER_INT_TXIDLE;
517 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX);
521 * Due to the contraints of the DMA engine present in the
522 * atmel chip, I can't just say I have a rx interrupt pending
523 * and do all the work elsewhere. I need to look at the CSR
524 * bits right now and do things based on them to avoid races.
526 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) {
527 // Have a buffer overflow. Copy all data from both
528 // ping and pong. Insert overflow character. Reset
529 // ping and pong and re-enable the PDC to receive
531 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
532 BUS_DMASYNC_POSTREAD);
533 bus_dmamap_sync(atsc->dmatag, atsc->pong->map,
534 BUS_DMASYNC_POSTREAD);
535 for (i = 0; i < sc->sc_rxfifosz; i++)
536 at91_rx_put(sc, atsc->ping->buffer[i]);
537 for (i = 0; i < sc->sc_rxfifosz; i++)
538 at91_rx_put(sc, atsc->pong->buffer[i]);
539 uart_rx_put(sc, UART_STAT_OVERRUN);
540 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT);
541 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
542 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
543 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
544 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
545 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
546 ipend |= SER_INT_RXREADY;
548 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) {
549 // Shuffle data from 'ping' of ping pong buffer, but
550 // leave current 'pong' in place, as it has become the
551 // new 'ping'. We need to copy data and setup the old
552 // 'ping' as the new 'pong' when we're done.
553 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
554 BUS_DMASYNC_POSTREAD);
555 for (i = 0; i < sc->sc_rxfifosz; i++)
556 at91_rx_put(sc, atsc->ping->buffer[i]);
558 atsc->ping = atsc->pong;
560 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
561 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
562 ipend |= SER_INT_RXREADY;
564 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) {
565 // We have one partial buffer. We need to stop the
566 // PDC, get the number of characters left and from
567 // that compute number of valid characters. We then
568 // need to reset ping and pong and reenable the PDC.
569 // Not sure if there's a race here at fast baud rates
570 // we need to worry about.
571 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
572 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
573 BUS_DMASYNC_POSTREAD);
574 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
575 for (i = 0; i < len; i++)
576 at91_rx_put(sc, atsc->ping->buffer[i]);
577 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
578 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
579 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
580 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
581 ipend |= SER_INT_RXREADY;
583 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) {
584 // We have another charater in a device that doesn't support
585 // timeouts, so we do it one character at a time.
586 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
587 ipend |= SER_INT_RXREADY;
590 if (csr & USART_CSR_RXBRK) {
591 unsigned int cr = USART_CR_RSTSTA;
593 ipend |= SER_INT_BREAK;
594 WR4(&sc->sc_bas, USART_CR, cr);
596 uart_unlock(sc->sc_hwmtx);
600 at91_usart_bus_flush(struct uart_softc *sc, int what)
606 at91_usart_bus_getsig(struct uart_softc *sc)
611 uart_lock(sc->sc_hwmtx);
612 csr = RD4(&sc->sc_bas, USART_CSR);
614 if (csr & USART_CSR_CTS)
616 if (csr & USART_CSR_DCD)
618 if (csr & USART_CSR_DSR)
620 if (csr & USART_CSR_RI)
622 new = sig & ~SER_MASK_DELTA;
624 uart_unlock(sc->sc_hwmtx);
629 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
632 case UART_IOCTL_BREAK:
633 case UART_IOCTL_IFLOW:
634 case UART_IOCTL_OFLOW:
636 case UART_IOCTL_BAUD:
637 /* only if we know our master clock rate */
638 if (DEFAULT_RCLK != 0)
639 WR4(&sc->sc_bas, USART_BRGR,
640 BAUD2DIVISOR(*(int *)data));
646 struct uart_class at91_usart_class = {
649 sizeof(struct at91_usart_softc),
650 .uc_ops = &at91_usart_ops,