sys/dev/agp/agp_i810.c

   1 /*-
   2  * Copyright (c) 2000 Doug Rabson
   3  * Copyright (c) 2000 Ruslan Ermilov
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
  30  * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include "opt_bus.h"
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/malloc.h>
  41 #include <sys/kernel.h>
  42 #include <sys/module.h>
  43 #include <sys/bus.h>
  44 #include <sys/lock.h>
  45 #include <sys/mutex.h>
  46 #include <sys/proc.h>
  47
  48 #include <dev/agp/agppriv.h>
  49 #include <dev/agp/agpreg.h>
  50 #include <dev/pci/pcivar.h>
  51 #include <dev/pci/pcireg.h>
  52
  53 #include <vm/vm.h>
  54 #include <vm/vm_object.h>
  55 #include <vm/vm_page.h>
  56 #include <vm/vm_pageout.h>
  57 #include <vm/pmap.h>
  58
  59 #include <machine/bus.h>
  60 #include <machine/resource.h>
  61 #include <machine/md_var.h>
  62 #include <sys/rman.h>
  63
  64 MALLOC_DECLARE(M_AGP);
  65
  66 enum {
  67         CHIP_I810,      /* i810/i815 */
  68         CHIP_I830,      /* 830M/845G */
  69         CHIP_I855,      /* 852GM/855GM/865G */
  70         CHIP_I915,      /* 915G/915GM */
  71         CHIP_I965,      /* G965 */
  72         CHIP_G33,       /* G33/Q33/Q35 */
  73         CHIP_IGD,       /* Pineview */
  74         CHIP_G4X,       /* G45/Q45 */
  75 };
  76
  77 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
  78  * allocated by us.  The i915 has registers in BAR 0 and the GATT is at the
  79  * start of the stolen memory, and should only be accessed by the OS through
  80  * BAR 3.  The G965 has registers and GATT in the same BAR (0) -- first 512KB
  81  * is registers, second 512KB is GATT.
  82  */
  83 static struct resource_spec agp_i810_res_spec[] = {
  84         { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
  85         { -1, 0 }
  86 };
  87
  88 static struct resource_spec agp_i915_res_spec[] = {
  89         { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
  90         { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
  91         { -1, 0 }
  92 };
  93
  94 static struct resource_spec agp_i965_res_spec[] = {
  95         { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
  96         { -1, 0 }
  97 };
  98
  99 struct agp_i810_softc {
 100         struct agp_softc agp;
 101         u_int32_t initial_aperture;     /* aperture size at startup */
 102         struct agp_gatt *gatt;
 103         int chiptype;                   /* i810-like or i830 */
 104         u_int32_t dcache_size;          /* i810 only */
 105         u_int32_t stolen;               /* number of i830/845 gtt entries for stolen memory */
 106         device_t bdev;                  /* bridge device */
 107
 108         void *argb_cursor;              /* contigmalloc area for ARGB cursor */
 109
 110         struct resource_spec * sc_res_spec;
 111         struct resource *sc_res[2];
 112 };
 113
 114 /* For adding new devices, devid is the id of the graphics controller
 115  * (pci:0:2:0, for example).  The placeholder (usually at pci:0:2:1) for the
 116  * second head should never be added.  The bridge_offset is the offset to
 117  * subtract from devid to get the id of the hostb that the device is on.
 118  */
 119 static const struct agp_i810_match {
 120         int devid;
 121         int chiptype;
 122         int bridge_offset;
 123         char *name;
 124 } agp_i810_matches[] = {
 125         {0x71218086, CHIP_I810, 0x00010000,
 126             "Intel 82810 (i810 GMCH) SVGA controller"},
 127         {0x71238086, CHIP_I810, 0x00010000,
 128             "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
 129         {0x71258086, CHIP_I810, 0x00010000,
 130             "Intel 82810E (i810E GMCH) SVGA controller"},
 131         {0x11328086, CHIP_I810, 0x00020000,
 132             "Intel 82815 (i815 GMCH) SVGA controller"},
 133         {0x35778086, CHIP_I830, 0x00020000,
 134             "Intel 82830M (830M GMCH) SVGA controller"},
 135         {0x25628086, CHIP_I830, 0x00020000,
 136             "Intel 82845M (845M GMCH) SVGA controller"},
 137         {0x35828086, CHIP_I855, 0x00020000,
 138             "Intel 82852/855GM SVGA controller"},
 139         {0x25728086, CHIP_I855, 0x00020000,
 140             "Intel 82865G (865G GMCH) SVGA controller"},
 141         {0x25828086, CHIP_I915, 0x00020000,
 142             "Intel 82915G (915G GMCH) SVGA controller"},
 143         {0x258A8086, CHIP_I915, 0x00020000,
 144             "Intel E7221 SVGA controller"},
 145         {0x25928086, CHIP_I915, 0x00020000,
 146             "Intel 82915GM (915GM GMCH) SVGA controller"},
 147         {0x27728086, CHIP_I915, 0x00020000,
 148             "Intel 82945G (945G GMCH) SVGA controller"},
 149         {0x27A28086, CHIP_I915, 0x00020000,
 150             "Intel 82945GM (945GM GMCH) SVGA controller"},
 151         {0x27AE8086, CHIP_I915, 0x00020000,
 152             "Intel 945GME SVGA controller"},
 153         {0x29728086, CHIP_I965, 0x00020000,
 154             "Intel 946GZ SVGA controller"},
 155         {0x29828086, CHIP_I965, 0x00020000,
 156             "Intel G965 SVGA controller"},
 157         {0x29928086, CHIP_I965, 0x00020000,
 158             "Intel Q965 SVGA controller"},
 159         {0x29A28086, CHIP_I965, 0x00020000,
 160             "Intel G965 SVGA controller"},
 161         {0x29B28086, CHIP_G33, 0x00020000,
 162             "Intel Q35 SVGA controller"},
 163         {0x29C28086, CHIP_G33, 0x00020000,
 164             "Intel G33 SVGA controller"},
 165         {0x29D28086, CHIP_G33, 0x00020000,
 166             "Intel Q33 SVGA controller"},
 167         {0xA0018086, CHIP_IGD, 0x00010000,
 168             "Intel Pineview SVGA controller"},
 169         {0xA0118086, CHIP_IGD, 0x00010000,
 170             "Intel Pineview (M) SVGA controller"},
 171         {0x2A028086, CHIP_I965, 0x00020000,
 172             "Intel GM965 SVGA controller"},
 173         {0x2A128086, CHIP_I965, 0x00020000,
 174             "Intel GME965 SVGA controller"},
 175         {0x2A428086, CHIP_G4X, 0x00020000,
 176             "Intel GM45 SVGA controller"},
 177         {0x2E028086, CHIP_G4X, 0x00020000,
 178             "Intel Eaglelake SVGA controller"},
 179         {0x2E128086, CHIP_G4X, 0x00020000,
 180             "Intel Q45 SVGA controller"},
 181         {0x2E228086, CHIP_G4X, 0x00020000,
 182             "Intel G45 SVGA controller"},
 183         {0x2E328086, CHIP_G4X, 0x00020000,
 184             "Intel G41 SVGA controller"},
 185         {0x00428086, CHIP_G4X, 0x00020000,
 186             "Intel Ironlake (D) SVGA controller"},
 187         {0x00468086, CHIP_G4X, 0x00020000,
 188             "Intel Ironlake (M) SVGA controller"},
 189         {0, 0, 0, NULL}
 190 };
 191
 192 static const struct agp_i810_match*
 193 agp_i810_match(device_t dev)
 194 {
 195         int i, devid;
 196
 197         if (pci_get_class(dev) != PCIC_DISPLAY
 198             || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
 199                 return NULL;
 200
 201         devid = pci_get_devid(dev);
 202         for (i = 0; agp_i810_matches[i].devid != 0; i++) {
 203                 if (agp_i810_matches[i].devid == devid)
 204                     break;
 205         }
 206         if (agp_i810_matches[i].devid == 0)
 207                 return NULL;
 208         else
 209                 return &agp_i810_matches[i];
 210 }
 211
 212 /*
 213  * Find bridge device.
 214  */
 215 static device_t
 216 agp_i810_find_bridge(device_t dev)
 217 {
 218         device_t *children, child;
 219         int nchildren, i;
 220         u_int32_t devid;
 221         const struct agp_i810_match *match;
 222
 223         match = agp_i810_match(dev);
 224         devid = match->devid - match->bridge_offset;
 225
 226         if (device_get_children(device_get_parent(device_get_parent(dev)),
 227             &children, &nchildren))
 228                 return 0;
 229
 230         for (i = 0; i < nchildren; i++) {
 231                 child = children[i];
 232
 233                 if (pci_get_devid(child) == devid) {
 234                         free(children, M_TEMP);
 235                         return child;
 236                 }
 237         }
 238         free(children, M_TEMP);
 239         return 0;
 240 }
 241
 242 static void
 243 agp_i810_identify(driver_t *driver, device_t parent)
 244 {
 245
 246         if (device_find_child(parent, "agp", -1) == NULL &&
 247             agp_i810_match(parent))
 248                 device_add_child(parent, "agp", -1);
 249 }
 250
 251 static int
 252 agp_i810_probe(device_t dev)
 253 {
 254         device_t bdev;
 255         const struct agp_i810_match *match;
 256         u_int8_t smram;
 257         int gcc1, deven;
 258
 259         if (resource_disabled("agp", device_get_unit(dev)))
 260                 return (ENXIO);
 261         match = agp_i810_match(dev);
 262         if (match == NULL)
 263                 return ENXIO;
 264
 265         bdev = agp_i810_find_bridge(dev);
 266         if (!bdev) {
 267                 if (bootverbose)
 268                         printf("I810: can't find bridge device\n");
 269                 return ENXIO;
 270         }
 271
 272         /*
 273          * checking whether internal graphics device has been activated.
 274          */
 275         switch (match->chiptype) {
 276         case CHIP_I810:
 277                 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
 278                 if ((smram & AGP_I810_SMRAM_GMS) ==
 279                     AGP_I810_SMRAM_GMS_DISABLED) {
 280                         if (bootverbose)
 281                                 printf("I810: disabled, not probing\n");
 282                         return ENXIO;
 283                 }
 284                 break;
 285         case CHIP_I830:
 286         case CHIP_I855:
 287                 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
 288                 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
 289                     AGP_I830_GCC1_DEV2_DISABLED) {
 290                         if (bootverbose)
 291                                 printf("I830: disabled, not probing\n");
 292                         return ENXIO;
 293                 }
 294                 break;
 295         case CHIP_I915:
 296         case CHIP_I965:
 297         case CHIP_G33:
 298         case CHIP_IGD:
 299         case CHIP_G4X:
 300                 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
 301                 if ((deven & AGP_I915_DEVEN_D2F0) ==
 302                     AGP_I915_DEVEN_D2F0_DISABLED) {
 303                         if (bootverbose)
 304                                 printf("I915: disabled, not probing\n");
 305                         return ENXIO;
 306                 }
 307                 break;
 308         }
 309
 310         if (match->devid == 0x35828086) {
 311                 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
 312                 case AGP_I855_GME:
 313                         device_set_desc(dev,
 314                             "Intel 82855GME (855GME GMCH) SVGA controller");
 315                         break;
 316                 case AGP_I855_GM:
 317                         device_set_desc(dev,
 318                             "Intel 82855GM (855GM GMCH) SVGA controller");
 319                         break;
 320                 case AGP_I852_GME:
 321                         device_set_desc(dev,
 322                             "Intel 82852GME (852GME GMCH) SVGA controller");
 323                         break;
 324                 case AGP_I852_GM:
 325                         device_set_desc(dev,
 326                             "Intel 82852GM (852GM GMCH) SVGA controller");
 327                         break;
 328                 default:
 329                         device_set_desc(dev,
 330                             "Intel 8285xM (85xGM GMCH) SVGA controller");
 331                         break;
 332                 }
 333         } else {
 334                 device_set_desc(dev, match->name);
 335         }
 336
 337         return BUS_PROBE_DEFAULT;
 338 }
 339
 340 static void
 341 agp_i810_dump_regs(device_t dev)
 342 {
 343         struct agp_i810_softc *sc = device_get_softc(dev);
 344
 345         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
 346             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
 347
 348         switch (sc->chiptype) {
 349         case CHIP_I810:
 350                 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
 351                     pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
 352                 break;
 353         case CHIP_I830:
 354                 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
 355                     pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
 356                 break;
 357         case CHIP_I855:
 358                 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 359                     pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 360                 break;
 361         case CHIP_I915:
 362         case CHIP_I965:
 363         case CHIP_G33:
 364         case CHIP_IGD:
 365         case CHIP_G4X:
 366                 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 367                     pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 368                 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
 369                     pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
 370                 break;
 371         }
 372         device_printf(dev, "Aperture resource size: %d bytes\n",
 373             AGP_GET_APERTURE(dev));
 374 }
 375
 376 static int
 377 agp_i810_attach(device_t dev)
 378 {
 379         struct agp_i810_softc *sc = device_get_softc(dev);
 380         struct agp_gatt *gatt;
 381         const struct agp_i810_match *match;
 382         int error;
 383
 384         sc->bdev = agp_i810_find_bridge(dev);
 385         if (!sc->bdev)
 386                 return ENOENT;
 387
 388         match = agp_i810_match(dev);
 389         sc->chiptype = match->chiptype;
 390
 391         switch (sc->chiptype) {
 392         case CHIP_I810:
 393         case CHIP_I830:
 394         case CHIP_I855:
 395                 sc->sc_res_spec = agp_i810_res_spec;
 396                 agp_set_aperture_resource(dev, AGP_APBASE);
 397                 break;
 398         case CHIP_I915:
 399         case CHIP_G33:
 400         case CHIP_IGD:
 401                 sc->sc_res_spec = agp_i915_res_spec;
 402                 agp_set_aperture_resource(dev, AGP_I915_GMADR);
 403                 break;
 404         case CHIP_I965:
 405         case CHIP_G4X:
 406                 sc->sc_res_spec = agp_i965_res_spec;
 407                 agp_set_aperture_resource(dev, AGP_I915_GMADR);
 408                 break;
 409         }
 410
 411         error = agp_generic_attach(dev);
 412         if (error)
 413                 return error;
 414
 415         if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
 416             sc->chiptype != CHIP_IGD && sc->chiptype != CHIP_G4X &&
 417             ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
 418         {
 419                 device_printf(dev, "agp_i810.c does not support physical "
 420                     "memory above 4GB.\n");
 421                 return ENOENT;
 422         }
 423
 424         if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
 425                 agp_generic_detach(dev);
 426                 return ENODEV;
 427         }
 428
 429         sc->initial_aperture = AGP_GET_APERTURE(dev);
 430
 431         gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
 432         if (!gatt) {
 433                 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
 434                 agp_generic_detach(dev);
 435                 return ENOMEM;
 436         }
 437         sc->gatt = gatt;
 438
 439         gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
 440
 441         if ( sc->chiptype == CHIP_I810 ) {
 442                 /* Some i810s have on-chip memory called dcache */
 443                 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
 444                     AGP_I810_DRT_POPULATED)
 445                         sc->dcache_size = 4 * 1024 * 1024;
 446                 else
 447                         sc->dcache_size = 0;
 448
 449                 /* According to the specs the gatt on the i810 must be 64k */
 450                 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
 451                                         0, ~0, PAGE_SIZE, 0);
 452                 if (!gatt->ag_virtual) {
 453                         if (bootverbose)
 454                                 device_printf(dev, "contiguous allocation failed\n");
 455                         bus_release_resources(dev, sc->sc_res_spec,
 456                             sc->sc_res);
 457                         free(gatt, M_AGP);
 458                         agp_generic_detach(dev);
 459                         return ENOMEM;
 460                 }
 461                 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
 462
 463                 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
 464                 agp_flush_cache();
 465                 /* Install the GATT. */
 466                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
 467                     gatt->ag_physical | 1);
 468         } else if ( sc->chiptype == CHIP_I830 ) {
 469                 /* The i830 automatically initializes the 128k gatt on boot. */
 470                 unsigned int gcc1, pgtblctl;
 471
 472                 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
 473                 switch (gcc1 & AGP_I830_GCC1_GMS) {
 474                         case AGP_I830_GCC1_GMS_STOLEN_512:
 475                                 sc->stolen = (512 - 132) * 1024 / 4096;
 476                                 break;
 477                         case AGP_I830_GCC1_GMS_STOLEN_1024:
 478                                 sc->stolen = (1024 - 132) * 1024 / 4096;
 479                                 break;
 480                         case AGP_I830_GCC1_GMS_STOLEN_8192:
 481                                 sc->stolen = (8192 - 132) * 1024 / 4096;
 482                                 break;
 483                         default:
 484                                 sc->stolen = 0;
 485                                 device_printf(dev, "unknown memory configuration, disabling\n");
 486                                 bus_release_resources(dev, sc->sc_res_spec,
 487                                     sc->sc_res);
 488                                 free(gatt, M_AGP);
 489                                 agp_generic_detach(dev);
 490                                 return EINVAL;
 491                 }
 492
 493                 /* GATT address is already in there, make sure it's enabled */
 494                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 495                 pgtblctl |= 1;
 496                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 497
 498                 gatt->ag_physical = pgtblctl & ~1;
 499         } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
 500             sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
 501             sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
 502                 unsigned int gcc1, pgtblctl, stolen, gtt_size;
 503
 504                 /* Stolen memory is set up at the beginning of the aperture by
 505                  * the BIOS, consisting of the GATT followed by 4kb for the
 506                  * BIOS display.
 507                  */
 508                 switch (sc->chiptype) {
 509                 case CHIP_I855:
 510                         gtt_size = 128;
 511                         break;
 512                 case CHIP_I915:
 513                         gtt_size = 256;
 514                         break;
 515                 case CHIP_I965:
 516                         switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
 517                             AGP_I810_PGTBL_SIZE_MASK) {
 518                         case AGP_I810_PGTBL_SIZE_128KB:
 519                                 gtt_size = 128;
 520                                 break;
 521                         case AGP_I810_PGTBL_SIZE_256KB:
 522                                 gtt_size = 256;
 523                                 break;
 524                         case AGP_I810_PGTBL_SIZE_512KB:
 525                                 gtt_size = 512;
 526                                 break;
 527                         case AGP_I965_PGTBL_SIZE_1MB:
 528                                 gtt_size = 1024;
 529                                 break;
 530                         case AGP_I965_PGTBL_SIZE_2MB:
 531                                 gtt_size = 2048;
 532                                 break;
 533                         case AGP_I965_PGTBL_SIZE_1_5MB:
 534                                 gtt_size = 1024 + 512;
 535                                 break;
 536                         default:
 537                                 device_printf(dev, "Bad PGTBL size\n");
 538                                 bus_release_resources(dev, sc->sc_res_spec,
 539                                     sc->sc_res);
 540                                 free(gatt, M_AGP);
 541                                 agp_generic_detach(dev);
 542                                 return EINVAL;
 543                         }
 544                         break;
 545                 case CHIP_G33:
 546                         gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
 547                         switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
 548                         case AGP_G33_MGGC_GGMS_SIZE_1M:
 549                                 gtt_size = 1024;
 550                                 break;
 551                         case AGP_G33_MGGC_GGMS_SIZE_2M:
 552                                 gtt_size = 2048;
 553                                 break;
 554                         default:
 555                                 device_printf(dev, "Bad PGTBL size\n");
 556                                 bus_release_resources(dev, sc->sc_res_spec,
 557                                     sc->sc_res);
 558                                 free(gatt, M_AGP);
 559                                 agp_generic_detach(dev);
 560                                 return EINVAL;
 561                         }
 562                         break;
 563                 case CHIP_IGD:
 564                 case CHIP_G4X:
 565                         gtt_size = 0;
 566                         break;
 567                 default:
 568                         device_printf(dev, "Bad chiptype\n");
 569                         bus_release_resources(dev, sc->sc_res_spec,
 570                             sc->sc_res);
 571                         free(gatt, M_AGP);
 572                         agp_generic_detach(dev);
 573                         return EINVAL;
 574                 }
 575
 576                 /* GCC1 is called MGGC on i915+ */
 577                 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
 578                 switch (gcc1 & AGP_I855_GCC1_GMS) {
 579                 case AGP_I855_GCC1_GMS_STOLEN_1M:
 580                         stolen = 1024;
 581                         break;
 582                 case AGP_I855_GCC1_GMS_STOLEN_4M:
 583                         stolen = 4 * 1024;
 584                         break;
 585                 case AGP_I855_GCC1_GMS_STOLEN_8M:
 586                         stolen = 8 * 1024;
 587                         break;
 588                 case AGP_I855_GCC1_GMS_STOLEN_16M:
 589                         stolen = 16 * 1024;
 590                         break;
 591                 case AGP_I855_GCC1_GMS_STOLEN_32M:
 592                         stolen = 32 * 1024;
 593                         break;
 594                 case AGP_I915_GCC1_GMS_STOLEN_48M:
 595                         if (sc->chiptype == CHIP_I915 ||
 596                             sc->chiptype == CHIP_I965 ||
 597                             sc->chiptype == CHIP_G33 ||
 598                             sc->chiptype == CHIP_IGD ||
 599                             sc->chiptype == CHIP_G4X) {
 600                                 stolen = 48 * 1024;
 601                         } else {
 602                                 stolen = 0;
 603                         }
 604                         break;
 605                 case AGP_I915_GCC1_GMS_STOLEN_64M:
 606                         if (sc->chiptype == CHIP_I915 ||
 607                             sc->chiptype == CHIP_I965 ||
 608                             sc->chiptype == CHIP_G33 ||
 609                             sc->chiptype == CHIP_IGD ||
 610                             sc->chiptype == CHIP_G4X) {
 611                                 stolen = 64 * 1024;
 612                         } else {
 613                                 stolen = 0;
 614                         }
 615                         break;
 616                 case AGP_G33_GCC1_GMS_STOLEN_128M:
 617                         if (sc->chiptype == CHIP_I965 ||
 618                             sc->chiptype == CHIP_G33 ||
 619                             sc->chiptype == CHIP_IGD ||
 620                             sc->chiptype == CHIP_G4X) {
 621                                 stolen = 128 * 1024;
 622                         } else {
 623                                 stolen = 0;
 624                         }
 625                         break;
 626                 case AGP_G33_GCC1_GMS_STOLEN_256M:
 627                         if (sc->chiptype == CHIP_I965 ||
 628                             sc->chiptype == CHIP_G33 ||
 629                             sc->chiptype == CHIP_IGD ||
 630                             sc->chiptype == CHIP_G4X) {
 631                                 stolen = 256 * 1024;
 632                         } else {
 633                                 stolen = 0;
 634                         }
 635                         break;
 636                 case AGP_G4X_GCC1_GMS_STOLEN_96M:
 637                         if (sc->chiptype == CHIP_I965 ||
 638                             sc->chiptype == CHIP_G4X) {
 639                                 stolen = 96 * 1024;
 640                         } else {
 641                                 stolen = 0;
 642                         }
 643                         break;
 644                 case AGP_G4X_GCC1_GMS_STOLEN_160M:
 645                         if (sc->chiptype == CHIP_I965 ||
 646                             sc->chiptype == CHIP_G4X) {
 647                                 stolen = 160 * 1024;
 648                         } else {
 649                                 stolen = 0;
 650                         }
 651                         break;
 652                 case AGP_G4X_GCC1_GMS_STOLEN_224M:
 653                         if (sc->chiptype == CHIP_I965 ||
 654                             sc->chiptype == CHIP_G4X) {
 655                                 stolen = 224 * 1024;
 656                         } else {
 657                                 stolen = 0;
 658                         }
 659                         break;
 660                 case AGP_G4X_GCC1_GMS_STOLEN_352M:
 661                         if (sc->chiptype == CHIP_I965 ||
 662                             sc->chiptype == CHIP_G4X) {
 663                                 stolen = 352 * 1024;
 664                         } else {
 665                                 stolen = 0;
 666                         }
 667                         break;
 668                 default:
 669                         device_printf(dev, "unknown memory configuration, "
 670                             "disabling\n");
 671                         bus_release_resources(dev, sc->sc_res_spec,
 672                             sc->sc_res);
 673                         free(gatt, M_AGP);
 674                         agp_generic_detach(dev);
 675                         return EINVAL;
 676                 }
 677
 678                 gtt_size += 4;
 679
 680                 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
 681
 682                 /* GATT address is already in there, make sure it's enabled */
 683                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 684                 pgtblctl |= 1;
 685                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 686
 687                 gatt->ag_physical = pgtblctl & ~1;
 688         }
 689
 690         device_printf(dev, "aperture size is %dM",
 691             sc->initial_aperture / 1024 / 1024);
 692         if (sc->stolen > 0)
 693                 printf(", detected %dk stolen memory\n", sc->stolen * 4);
 694         else
 695                 printf("\n");
 696
 697         if (0)
 698                 agp_i810_dump_regs(dev);
 699
 700         return 0;
 701 }
 702
 703 static int
 704 agp_i810_detach(device_t dev)
 705 {
 706         struct agp_i810_softc *sc = device_get_softc(dev);
 707
 708         agp_free_cdev(dev);
 709
 710         /* Clear the GATT base. */
 711         if ( sc->chiptype == CHIP_I810 ) {
 712                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
 713         } else {
 714                 unsigned int pgtblctl;
 715                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 716                 pgtblctl &= ~1;
 717                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 718         }
 719
 720         /* Put the aperture back the way it started. */
 721         AGP_SET_APERTURE(dev, sc->initial_aperture);
 722
 723         if ( sc->chiptype == CHIP_I810 ) {
 724                 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
 725         }
 726         free(sc->gatt, M_AGP);
 727
 728         bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
 729         agp_free_res(dev);
 730
 731         return 0;
 732 }
 733
 734 static int
 735 agp_i810_resume(device_t dev)
 736 {
 737         struct agp_i810_softc *sc;
 738         sc = device_get_softc(dev);
 739
 740         AGP_SET_APERTURE(dev, sc->initial_aperture);
 741
 742         /* Install the GATT. */
 743         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
 744         sc->gatt->ag_physical | 1);
 745
 746         return (bus_generic_resume(dev));
 747 }
 748
 749 /**
 750  * Sets the PCI resource size of the aperture on i830-class and below chipsets,
 751  * while returning failure on later chipsets when an actual change is
 752  * requested.
 753  *
 754  * This whole function is likely bogus, as the kernel would probably need to
 755  * reconfigure the placement of the AGP aperture if a larger size is requested,
 756  * which doesn't happen currently.
 757  */
 758 static int
 759 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
 760 {
 761         struct agp_i810_softc *sc = device_get_softc(dev);
 762         u_int16_t miscc, gcc1;
 763
 764         switch (sc->chiptype) {
 765         case CHIP_I810:
 766                 /*
 767                  * Double check for sanity.
 768                  */
 769                 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
 770                         device_printf(dev, "bad aperture size %d\n", aperture);
 771                         return EINVAL;
 772                 }
 773
 774                 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
 775                 miscc &= ~AGP_I810_MISCC_WINSIZE;
 776                 if (aperture == 32 * 1024 * 1024)
 777                         miscc |= AGP_I810_MISCC_WINSIZE_32;
 778                 else
 779                         miscc |= AGP_I810_MISCC_WINSIZE_64;
 780
 781                 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
 782                 break;
 783         case CHIP_I830:
 784                 if (aperture != 64 * 1024 * 1024 &&
 785                     aperture != 128 * 1024 * 1024) {
 786                         device_printf(dev, "bad aperture size %d\n", aperture);
 787                         return EINVAL;
 788                 }
 789                 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
 790                 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
 791                 if (aperture == 64 * 1024 * 1024)
 792                         gcc1 |= AGP_I830_GCC1_GMASIZE_64;
 793                 else
 794                         gcc1 |= AGP_I830_GCC1_GMASIZE_128;
 795
 796                 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
 797                 break;
 798         case CHIP_I855:
 799         case CHIP_I915:
 800         case CHIP_I965:
 801         case CHIP_G33:
 802         case CHIP_IGD:
 803         case CHIP_G4X:
 804                 return agp_generic_set_aperture(dev, aperture);
 805         }
 806
 807         return 0;
 808 }
 809
 810 /**
 811  * Writes a GTT entry mapping the page at the given offset from the beginning
 812  * of the aperture to the given physical address.
 813  */
 814 static void
 815 agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
 816     int enabled)
 817 {
 818         struct agp_i810_softc *sc = device_get_softc(dev);
 819         u_int32_t pte;
 820
 821         pte = (u_int32_t)physical | 1;
 822         if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
 823             sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
 824                 pte |= (physical & 0x0000000f00000000ull) >> 28;
 825         } else {
 826                 /* If we do actually have memory above 4GB on an older system,
 827                  * crash cleanly rather than scribble on system memory,
 828                  * so we know we need to fix it.
 829                  */
 830                 KASSERT((pte & 0x0000000f00000000ull) == 0,
 831                     (">4GB physical address in agp"));
 832         }
 833
 834         switch (sc->chiptype) {
 835         case CHIP_I810:
 836         case CHIP_I830:
 837         case CHIP_I855:
 838                 bus_write_4(sc->sc_res[0],
 839                     AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
 840                 break;
 841         case CHIP_I915:
 842         case CHIP_G33:
 843         case CHIP_IGD:
 844                 bus_write_4(sc->sc_res[1],
 845                     (offset >> AGP_PAGE_SHIFT) * 4, pte);
 846                 break;
 847         case CHIP_I965:
 848                 bus_write_4(sc->sc_res[0],
 849                     (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
 850                 break;
 851         case CHIP_G4X:
 852                 bus_write_4(sc->sc_res[0],
 853                     (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
 854                 break;
 855         }
 856 }
 857
 858 static int
 859 agp_i810_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
 860 {
 861         struct agp_i810_softc *sc = device_get_softc(dev);
 862
 863         if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
 864                 device_printf(dev, "failed: offset is 0x%08jx, shift is %d, entries is %d\n", (intmax_t)offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
 865                 return EINVAL;
 866         }
 867
 868         if ( sc->chiptype != CHIP_I810 ) {
 869                 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
 870                         device_printf(dev, "trying to bind into stolen memory");
 871                         return EINVAL;
 872                 }
 873         }
 874
 875         agp_i810_write_gtt_entry(dev, offset, physical, 1);
 876
 877         return 0;
 878 }
 879
 880 static int
 881 agp_i810_unbind_page(device_t dev, vm_offset_t offset)
 882 {
 883         struct agp_i810_softc *sc = device_get_softc(dev);
 884
 885         if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
 886                 return EINVAL;
 887
 888         if ( sc->chiptype != CHIP_I810 ) {
 889                 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
 890                         device_printf(dev, "trying to unbind from stolen memory");
 891                         return EINVAL;
 892                 }
 893         }
 894
 895         agp_i810_write_gtt_entry(dev, offset, 0, 0);
 896
 897         return 0;
 898 }
 899
 900 /*
 901  * Writing via memory mapped registers already flushes all TLBs.
 902  */
 903 static void
 904 agp_i810_flush_tlb(device_t dev)
 905 {
 906 }
 907
 908 static int
 909 agp_i810_enable(device_t dev, u_int32_t mode)
 910 {
 911
 912         return 0;
 913 }
 914
 915 static struct agp_memory *
 916 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
 917 {
 918         struct agp_i810_softc *sc = device_get_softc(dev);
 919         struct agp_memory *mem;
 920
 921         if ((size & (AGP_PAGE_SIZE - 1)) != 0)
 922                 return 0;
 923
 924         if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
 925                 return 0;
 926
 927         if (type == 1) {
 928                 /*
 929                  * Mapping local DRAM into GATT.
 930                  */
 931                 if ( sc->chiptype != CHIP_I810 )
 932                         return 0;
 933                 if (size != sc->dcache_size)
 934                         return 0;
 935         } else if (type == 2) {
 936                 /*
 937                  * Type 2 is the contiguous physical memory type, that hands
 938                  * back a physical address.  This is used for cursors on i810.
 939                  * Hand back as many single pages with physical as the user
 940                  * wants, but only allow one larger allocation (ARGB cursor)
 941                  * for simplicity.
 942                  */
 943                 if (size != AGP_PAGE_SIZE) {
 944                         if (sc->argb_cursor != NULL)
 945                                 return 0;
 946
 947                         /* Allocate memory for ARGB cursor, if we can. */
 948                         sc->argb_cursor = contigmalloc(size, M_AGP,
 949                            0, 0, ~0, PAGE_SIZE, 0);
 950                         if (sc->argb_cursor == NULL)
 951                                 return 0;
 952                 }
 953         }
 954
 955         mem = malloc(sizeof *mem, M_AGP, M_WAITOK);
 956         mem->am_id = sc->agp.as_nextid++;
 957         mem->am_size = size;
 958         mem->am_type = type;
 959         if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
 960                 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
 961                                                  atop(round_page(size)));
 962         else
 963                 mem->am_obj = 0;
 964
 965         if (type == 2) {
 966                 if (size == AGP_PAGE_SIZE) {
 967                         /*
 968                          * Allocate and wire down the page now so that we can
 969                          * get its physical address.
 970                          */
 971                         vm_page_t m;
 972
 973                         VM_OBJECT_LOCK(mem->am_obj);
 974                         m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY |
 975                             VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY);
 976                         VM_OBJECT_UNLOCK(mem->am_obj);
 977                         mem->am_physical = VM_PAGE_TO_PHYS(m);
 978                 } else {
 979                         /* Our allocation is already nicely wired down for us.
 980                          * Just grab the physical address.
 981                          */
 982                         mem->am_physical = vtophys(sc->argb_cursor);
 983                 }
 984         } else {
 985                 mem->am_physical = 0;
 986         }
 987
 988         mem->am_offset = 0;
 989         mem->am_is_bound = 0;
 990         TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
 991         sc->agp.as_allocated += size;
 992
 993         return mem;
 994 }
 995
 996 static int
 997 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
 998 {
 999         struct agp_i810_softc *sc = device_get_softc(dev);
1000
1001         if (mem->am_is_bound)
1002                 return EBUSY;
1003
1004         if (mem->am_type == 2) {
1005                 if (mem->am_size == AGP_PAGE_SIZE) {
1006                         /*
1007                          * Unwire the page which we wired in alloc_memory.
1008                          */
1009                         vm_page_t m;
1010
1011                         VM_OBJECT_LOCK(mem->am_obj);
1012                         m = vm_page_lookup(mem->am_obj, 0);
1013                         vm_page_lock(m);
1014                         vm_page_unwire(m, 0);
1015                         vm_page_unlock(m);
1016                         VM_OBJECT_UNLOCK(mem->am_obj);
1017                 } else {
1018                         contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1019                         sc->argb_cursor = NULL;
1020                 }
1021         }
1022
1023         sc->agp.as_allocated -= mem->am_size;
1024         TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1025         if (mem->am_obj)
1026                 vm_object_deallocate(mem->am_obj);
1027         free(mem, M_AGP);
1028         return 0;
1029 }
1030
1031 static int
1032 agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1033                      vm_offset_t offset)
1034 {
1035         struct agp_i810_softc *sc = device_get_softc(dev);
1036         vm_offset_t i;
1037
1038         /* Do some sanity checks first. */
1039         if ((offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1040             offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1041                 device_printf(dev, "binding memory at bad offset %#x\n",
1042                     (int)offset);
1043                 return EINVAL;
1044         }
1045
1046         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1047                 mtx_lock(&sc->agp.as_lock);
1048                 if (mem->am_is_bound) {
1049                         mtx_unlock(&sc->agp.as_lock);
1050                         return EINVAL;
1051                 }
1052                 /* The memory's already wired down, just stick it in the GTT. */
1053                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1054                         agp_i810_write_gtt_entry(dev, offset + i,
1055                             mem->am_physical + i, 1);
1056                 }
1057                 agp_flush_cache();
1058                 mem->am_offset = offset;
1059                 mem->am_is_bound = 1;
1060                 mtx_unlock(&sc->agp.as_lock);
1061                 return 0;
1062         }
1063
1064         if (mem->am_type != 1)
1065                 return agp_generic_bind_memory(dev, mem, offset);
1066
1067         if ( sc->chiptype != CHIP_I810 )
1068                 return EINVAL;
1069
1070         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1071                 bus_write_4(sc->sc_res[0],
1072                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1073         }
1074
1075         return 0;
1076 }
1077
1078 static int
1079 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1080 {
1081         struct agp_i810_softc *sc = device_get_softc(dev);
1082         vm_offset_t i;
1083
1084         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1085                 mtx_lock(&sc->agp.as_lock);
1086                 if (!mem->am_is_bound) {
1087                         mtx_unlock(&sc->agp.as_lock);
1088                         return EINVAL;
1089                 }
1090
1091                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1092                         agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1093                             0, 0);
1094                 }
1095                 agp_flush_cache();
1096                 mem->am_is_bound = 0;
1097                 mtx_unlock(&sc->agp.as_lock);
1098                 return 0;
1099         }
1100
1101         if (mem->am_type != 1)
1102                 return agp_generic_unbind_memory(dev, mem);
1103
1104         if ( sc->chiptype != CHIP_I810 )
1105                 return EINVAL;
1106
1107         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1108                 bus_write_4(sc->sc_res[0],
1109                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1110         }
1111
1112         return 0;
1113 }
1114
1115 static device_method_t agp_i810_methods[] = {
1116         /* Device interface */
1117         DEVMETHOD(device_identify,      agp_i810_identify),
1118         DEVMETHOD(device_probe,         agp_i810_probe),
1119         DEVMETHOD(device_attach,        agp_i810_attach),
1120         DEVMETHOD(device_detach,        agp_i810_detach),
1121         DEVMETHOD(device_suspend,       bus_generic_suspend),
1122         DEVMETHOD(device_resume,        agp_i810_resume),
1123
1124         /* AGP interface */
1125         DEVMETHOD(agp_get_aperture,     agp_generic_get_aperture),
1126         DEVMETHOD(agp_set_aperture,     agp_i810_set_aperture),
1127         DEVMETHOD(agp_bind_page,        agp_i810_bind_page),
1128         DEVMETHOD(agp_unbind_page,      agp_i810_unbind_page),
1129         DEVMETHOD(agp_flush_tlb,        agp_i810_flush_tlb),
1130         DEVMETHOD(agp_enable,           agp_i810_enable),
1131         DEVMETHOD(agp_alloc_memory,     agp_i810_alloc_memory),
1132         DEVMETHOD(agp_free_memory,      agp_i810_free_memory),
1133         DEVMETHOD(agp_bind_memory,      agp_i810_bind_memory),
1134         DEVMETHOD(agp_unbind_memory,    agp_i810_unbind_memory),
1135
1136         { 0, 0 }
1137 };
1138
1139 static driver_t agp_i810_driver = {
1140         "agp",
1141         agp_i810_methods,
1142         sizeof(struct agp_i810_softc),
1143 };
1144
1145 static devclass_t agp_devclass;
1146
1147 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0);
1148 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1149 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);