sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } const bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5718 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5719 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 218         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57761 },
 219         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57765 },
 220         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 221         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57781 },
 222         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57785 },
 223         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 224         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 225         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57791 },
 226         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57795 },
 227
 228         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 229
 230         { TC_VENDORID,          TC_DEVICEID_3C996 },
 231
 232         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 233         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 234         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 235
 236         { 0, 0 }
 237 };
 238
 239 static const struct bge_vendor {
 240         uint16_t        v_id;
 241         const char      *v_name;
 242 } const bge_vendors[] = {
 243         { ALTEON_VENDORID,      "Alteon" },
 244         { ALTIMA_VENDORID,      "Altima" },
 245         { APPLE_VENDORID,       "Apple" },
 246         { BCOM_VENDORID,        "Broadcom" },
 247         { SK_VENDORID,          "SysKonnect" },
 248         { TC_VENDORID,          "3Com" },
 249         { FJTSU_VENDORID,       "Fujitsu" },
 250
 251         { 0, NULL }
 252 };
 253
 254 static const struct bge_revision {
 255         uint32_t        br_chipid;
 256         const char      *br_name;
 257 } const bge_revisions[] = {
 258         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 259         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 260         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 261         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 262         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 263         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 264         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 265         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 266         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 267         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 268         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 269         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 270         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 271         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 272         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 273         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 274         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 275         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 276         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 277         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 278         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 279         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 280         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 281         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 282         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 283         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 284         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 285         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 286         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 287         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 288         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 289         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 290         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 291         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 292         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 293         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 294         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 295         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 296         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 297         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 298         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 299         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 300         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 301         { BGE_CHIPID_BCM5717_A0,        "BCM5717 A0" },
 302         { BGE_CHIPID_BCM5717_B0,        "BCM5717 B0" },
 303         { BGE_CHIPID_BCM5719_A0,        "BCM5719 A0" },
 304         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 305         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 306         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 307         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 308         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 309         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 310         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 311         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 312         /* 5754 and 5787 share the same ASIC ID */
 313         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 314         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 315         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 316         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 317         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 318         { BGE_CHIPID_BCM57765_A0,       "BCM57765 A0" },
 319         { BGE_CHIPID_BCM57765_B0,       "BCM57765 B0" },
 320         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 321         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 322
 323         { 0, NULL }
 324 };
 325
 326 /*
 327  * Some defaults for major revisions, so that newer steppings
 328  * that we don't know about have a shot at working.
 329  */
 330 static const struct bge_revision const bge_majorrevs[] = {
 331         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 332         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 333         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 334         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 335         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 336         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 337         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 338         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 339         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 340         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 341         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 342         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 343         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 344         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 345         /* 5754 and 5787 share the same ASIC ID */
 346         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 347         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 348         { BGE_ASICREV_BCM57765,         "unknown BCM57765" },
 349         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 350         { BGE_ASICREV_BCM5717,          "unknown BCM5717" },
 351         { BGE_ASICREV_BCM5719,          "unknown BCM5719" },
 352
 353         { 0, NULL }
 354 };
 355
 356 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 357 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 358 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 359 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 360 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 361 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 362 #define BGE_IS_5717_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
 363
 364 const struct bge_revision * bge_lookup_rev(uint32_t);
 365 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 366
 367 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 368
 369 static int bge_probe(device_t);
 370 static int bge_attach(device_t);
 371 static int bge_detach(device_t);
 372 static int bge_suspend(device_t);
 373 static int bge_resume(device_t);
 374 static void bge_release_resources(struct bge_softc *);
 375 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 376 static int bge_dma_alloc(struct bge_softc *);
 377 static void bge_dma_free(struct bge_softc *);
 378 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
 379     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
 380
 381 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 382 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 383 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 384 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 385 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 386
 387 static void bge_txeof(struct bge_softc *, uint16_t);
 388 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
 389 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 390
 391 static void bge_asf_driver_up (struct bge_softc *);
 392 static void bge_tick(void *);
 393 static void bge_stats_clear_regs(struct bge_softc *);
 394 static void bge_stats_update(struct bge_softc *);
 395 static void bge_stats_update_regs(struct bge_softc *);
 396 static struct mbuf *bge_check_short_dma(struct mbuf *);
 397 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 398     uint16_t *, uint16_t *);
 399 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 400
 401 static void bge_intr(void *);
 402 static int bge_msi_intr(void *);
 403 static void bge_intr_task(void *, int);
 404 static void bge_start_locked(struct ifnet *);
 405 static void bge_start(struct ifnet *);
 406 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 407 static void bge_init_locked(struct bge_softc *);
 408 static void bge_init(void *);
 409 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 410 static void bge_stop(struct bge_softc *);
 411 static void bge_watchdog(struct bge_softc *);
 412 static int bge_shutdown(device_t);
 413 static int bge_ifmedia_upd_locked(struct ifnet *);
 414 static int bge_ifmedia_upd(struct ifnet *);
 415 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 416
 417 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 418 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 419
 420 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 421 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 422
 423 static void bge_setpromisc(struct bge_softc *);
 424 static void bge_setmulti(struct bge_softc *);
 425 static void bge_setvlan(struct bge_softc *);
 426
 427 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 428 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 429 static int bge_newbuf_std(struct bge_softc *, int);
 430 static int bge_newbuf_jumbo(struct bge_softc *, int);
 431 static int bge_init_rx_ring_std(struct bge_softc *);
 432 static void bge_free_rx_ring_std(struct bge_softc *);
 433 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 434 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 435 static void bge_free_tx_ring(struct bge_softc *);
 436 static int bge_init_tx_ring(struct bge_softc *);
 437
 438 static int bge_chipinit(struct bge_softc *);
 439 static int bge_blockinit(struct bge_softc *);
 440
 441 static int bge_has_eaddr(struct bge_softc *);
 442 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 443 static void bge_writemem_ind(struct bge_softc *, int, int);
 444 static void bge_writembx(struct bge_softc *, int, int);
 445 #ifdef notdef
 446 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 447 #endif
 448 static void bge_writemem_direct(struct bge_softc *, int, int);
 449 static void bge_writereg_ind(struct bge_softc *, int, int);
 450
 451 static int bge_miibus_readreg(device_t, int, int);
 452 static int bge_miibus_writereg(device_t, int, int, int);
 453 static void bge_miibus_statchg(device_t);
 454 #ifdef DEVICE_POLLING
 455 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 456 #endif
 457
 458 #define BGE_RESET_START 1
 459 #define BGE_RESET_STOP  2
 460 static void bge_sig_post_reset(struct bge_softc *, int);
 461 static void bge_sig_legacy(struct bge_softc *, int);
 462 static void bge_sig_pre_reset(struct bge_softc *, int);
 463 static void bge_stop_fw(struct bge_softc *);
 464 static int bge_reset(struct bge_softc *);
 465 static void bge_link_upd(struct bge_softc *);
 466
 467 /*
 468  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 469  * leak information to untrusted users.  It is also known to cause alignment
 470  * traps on certain architectures.
 471  */
 472 #ifdef BGE_REGISTER_DEBUG
 473 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 474 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 475 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 476 #endif
 477 static void bge_add_sysctls(struct bge_softc *);
 478 static void bge_add_sysctl_stats_regs(struct bge_softc *,
 479     struct sysctl_ctx_list *, struct sysctl_oid_list *);
 480 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
 481     struct sysctl_oid_list *);
 482 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 483
 484 static device_method_t bge_methods[] = {
 485         /* Device interface */
 486         DEVMETHOD(device_probe,         bge_probe),
 487         DEVMETHOD(device_attach,        bge_attach),
 488         DEVMETHOD(device_detach,        bge_detach),
 489         DEVMETHOD(device_shutdown,      bge_shutdown),
 490         DEVMETHOD(device_suspend,       bge_suspend),
 491         DEVMETHOD(device_resume,        bge_resume),
 492
 493         /* bus interface */
 494         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 495         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 496
 497         /* MII interface */
 498         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 499         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 500         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 501
 502         { 0, 0 }
 503 };
 504
 505 static driver_t bge_driver = {
 506         "bge",
 507         bge_methods,
 508         sizeof(struct bge_softc)
 509 };
 510
 511 static devclass_t bge_devclass;
 512
 513 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 514 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 515
 516 static int bge_allow_asf = 1;
 517
 518 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 519
 520 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 521 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 522         "Allow ASF mode if available");
 523
 524 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 525 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 526 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 527 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 528 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 529
 530 static int
 531 bge_has_eaddr(struct bge_softc *sc)
 532 {
 533 #ifdef __sparc64__
 534         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 535         device_t dev;
 536         uint32_t subvendor;
 537
 538         dev = sc->bge_dev;
 539
 540         /*
 541          * The on-board BGEs found in sun4u machines aren't fitted with
 542          * an EEPROM which means that we have to obtain the MAC address
 543          * via OFW and that some tests will always fail.  We distinguish
 544          * such BGEs by the subvendor ID, which also has to be obtained
 545          * from OFW instead of the PCI configuration space as the latter
 546          * indicates Broadcom as the subvendor of the netboot interface.
 547          * For early Blade 1500 and 2500 we even have to check the OFW
 548          * device path as the subvendor ID always defaults to Broadcom
 549          * there.
 550          */
 551         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 552             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 553             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 554                 return (0);
 555         memset(buf, 0, sizeof(buf));
 556         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 557                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 558                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 559                         return (0);
 560                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 561                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 562                         return (0);
 563         }
 564 #endif
 565         return (1);
 566 }
 567
 568 static uint32_t
 569 bge_readmem_ind(struct bge_softc *sc, int off)
 570 {
 571         device_t dev;
 572         uint32_t val;
 573
 574         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 575             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 576                 return (0);
 577
 578         dev = sc->bge_dev;
 579
 580         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 581         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 582         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 583         return (val);
 584 }
 585
 586 static void
 587 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 588 {
 589         device_t dev;
 590
 591         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 592             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 593                 return;
 594
 595         dev = sc->bge_dev;
 596
 597         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 598         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 599         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 600 }
 601
 602 #ifdef notdef
 603 static uint32_t
 604 bge_readreg_ind(struct bge_softc *sc, int off)
 605 {
 606         device_t dev;
 607
 608         dev = sc->bge_dev;
 609
 610         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 611         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 612 }
 613 #endif
 614
 615 static void
 616 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 617 {
 618         device_t dev;
 619
 620         dev = sc->bge_dev;
 621
 622         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 623         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 624 }
 625
 626 static void
 627 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 628 {
 629         CSR_WRITE_4(sc, off, val);
 630 }
 631
 632 static void
 633 bge_writembx(struct bge_softc *sc, int off, int val)
 634 {
 635         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 636                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 637
 638         CSR_WRITE_4(sc, off, val);
 639 }
 640
 641 /*
 642  * Map a single buffer address.
 643  */
 644
 645 static void
 646 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 647 {
 648         struct bge_dmamap_arg *ctx;
 649
 650         if (error)
 651                 return;
 652
 653         KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
 654
 655         ctx = arg;
 656         ctx->bge_busaddr = segs->ds_addr;
 657 }
 658
 659 static uint8_t
 660 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 661 {
 662         uint32_t access, byte = 0;
 663         int i;
 664
 665         /* Lock. */
 666         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 667         for (i = 0; i < 8000; i++) {
 668                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 669                         break;
 670                 DELAY(20);
 671         }
 672         if (i == 8000)
 673                 return (1);
 674
 675         /* Enable access. */
 676         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 677         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 678
 679         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 680         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 681         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 682                 DELAY(10);
 683                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 684                         DELAY(10);
 685                         break;
 686                 }
 687         }
 688
 689         if (i == BGE_TIMEOUT * 10) {
 690                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 691                 return (1);
 692         }
 693
 694         /* Get result. */
 695         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 696
 697         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 698
 699         /* Disable access. */
 700         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 701
 702         /* Unlock. */
 703         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 704         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 705
 706         return (0);
 707 }
 708
 709 /*
 710  * Read a sequence of bytes from NVRAM.
 711  */
 712 static int
 713 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 714 {
 715         int err = 0, i;
 716         uint8_t byte = 0;
 717
 718         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 719                 return (1);
 720
 721         for (i = 0; i < cnt; i++) {
 722                 err = bge_nvram_getbyte(sc, off + i, &byte);
 723                 if (err)
 724                         break;
 725                 *(dest + i) = byte;
 726         }
 727
 728         return (err ? 1 : 0);
 729 }
 730
 731 /*
 732  * Read a byte of data stored in the EEPROM at address 'addr.' The
 733  * BCM570x supports both the traditional bitbang interface and an
 734  * auto access interface for reading the EEPROM. We use the auto
 735  * access method.
 736  */
 737 static uint8_t
 738 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 739 {
 740         int i;
 741         uint32_t byte = 0;
 742
 743         /*
 744          * Enable use of auto EEPROM access so we can avoid
 745          * having to use the bitbang method.
 746          */
 747         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 748
 749         /* Reset the EEPROM, load the clock period. */
 750         CSR_WRITE_4(sc, BGE_EE_ADDR,
 751             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 752         DELAY(20);
 753
 754         /* Issue the read EEPROM command. */
 755         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 756
 757         /* Wait for completion */
 758         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 759                 DELAY(10);
 760                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 761                         break;
 762         }
 763
 764         if (i == BGE_TIMEOUT * 10) {
 765                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 766                 return (1);
 767         }
 768
 769         /* Get result. */
 770         byte = CSR_READ_4(sc, BGE_EE_DATA);
 771
 772         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 773
 774         return (0);
 775 }
 776
 777 /*
 778  * Read a sequence of bytes from the EEPROM.
 779  */
 780 static int
 781 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 782 {
 783         int i, error = 0;
 784         uint8_t byte = 0;
 785
 786         for (i = 0; i < cnt; i++) {
 787                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 788                 if (error)
 789                         break;
 790                 *(dest + i) = byte;
 791         }
 792
 793         return (error ? 1 : 0);
 794 }
 795
 796 static int
 797 bge_miibus_readreg(device_t dev, int phy, int reg)
 798 {
 799         struct bge_softc *sc;
 800         uint32_t val;
 801         int i;
 802
 803         sc = device_get_softc(dev);
 804
 805         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 806         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 807                 CSR_WRITE_4(sc, BGE_MI_MODE,
 808                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 809                 DELAY(80);
 810         }
 811
 812         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 813             BGE_MIPHY(phy) | BGE_MIREG(reg));
 814
 815         /* Poll for the PHY register access to complete. */
 816         for (i = 0; i < BGE_TIMEOUT; i++) {
 817                 DELAY(10);
 818                 val = CSR_READ_4(sc, BGE_MI_COMM);
 819                 if ((val & BGE_MICOMM_BUSY) == 0) {
 820                         DELAY(5);
 821                         val = CSR_READ_4(sc, BGE_MI_COMM);
 822                         break;
 823                 }
 824         }
 825
 826         if (i == BGE_TIMEOUT) {
 827                 device_printf(sc->bge_dev,
 828                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 829                     phy, reg, val);
 830                 val = 0;
 831         }
 832
 833         /* Restore the autopoll bit if necessary. */
 834         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 835                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 836                 DELAY(80);
 837         }
 838
 839         if (val & BGE_MICOMM_READFAIL)
 840                 return (0);
 841
 842         return (val & 0xFFFF);
 843 }
 844
 845 static int
 846 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 847 {
 848         struct bge_softc *sc;
 849         int i;
 850
 851         sc = device_get_softc(dev);
 852
 853         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 854             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 855                 return (0);
 856
 857         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 858         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 859                 CSR_WRITE_4(sc, BGE_MI_MODE,
 860                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 861                 DELAY(80);
 862         }
 863
 864         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 865             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 866
 867         for (i = 0; i < BGE_TIMEOUT; i++) {
 868                 DELAY(10);
 869                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 870                         DELAY(5);
 871                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 872                         break;
 873                 }
 874         }
 875
 876         /* Restore the autopoll bit if necessary. */
 877         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 878                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 879                 DELAY(80);
 880         }
 881
 882         if (i == BGE_TIMEOUT)
 883                 device_printf(sc->bge_dev,
 884                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 885                     phy, reg, val);
 886
 887         return (0);
 888 }
 889
 890 static void
 891 bge_miibus_statchg(device_t dev)
 892 {
 893         struct bge_softc *sc;
 894         struct mii_data *mii;
 895         sc = device_get_softc(dev);
 896         mii = device_get_softc(sc->bge_miibus);
 897
 898         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 899             (IFM_ACTIVE | IFM_AVALID)) {
 900                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 901                 case IFM_10_T:
 902                 case IFM_100_TX:
 903                         sc->bge_link = 1;
 904                         break;
 905                 case IFM_1000_T:
 906                 case IFM_1000_SX:
 907                 case IFM_2500_SX:
 908                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 909                                 sc->bge_link = 1;
 910                         else
 911                                 sc->bge_link = 0;
 912                         break;
 913                 default:
 914                         sc->bge_link = 0;
 915                         break;
 916                 }
 917         } else
 918                 sc->bge_link = 0;
 919         if (sc->bge_link == 0)
 920                 return;
 921         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 922         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 923             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 924                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 925         else
 926                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 927
 928         if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) {
 929                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 930                 if ((IFM_OPTIONS(mii->mii_media_active) &
 931                     IFM_ETH_TXPAUSE) != 0)
 932                         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
 933                 else
 934                         BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
 935                 if ((IFM_OPTIONS(mii->mii_media_active) &
 936                     IFM_ETH_RXPAUSE) != 0)
 937                         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
 938                 else
 939                         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
 940         } else {
 941                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 942                 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
 943                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
 944         }
 945 }
 946
 947 /*
 948  * Intialize a standard receive ring descriptor.
 949  */
 950 static int
 951 bge_newbuf_std(struct bge_softc *sc, int i)
 952 {
 953         struct mbuf *m;
 954         struct bge_rx_bd *r;
 955         bus_dma_segment_t segs[1];
 956         bus_dmamap_t map;
 957         int error, nsegs;
 958
 959         if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
 960             (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
 961             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
 962                 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
 963                 if (m == NULL)
 964                         return (ENOBUFS);
 965                 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 966         } else {
 967                 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 968                 if (m == NULL)
 969                         return (ENOBUFS);
 970                 m->m_len = m->m_pkthdr.len = MCLBYTES;
 971         }
 972         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 973                 m_adj(m, ETHER_ALIGN);
 974
 975         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 976             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 977         if (error != 0) {
 978                 m_freem(m);
 979                 return (error);
 980         }
 981         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 982                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 983                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 984                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 985                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 986         }
 987         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 988         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 989         sc->bge_cdata.bge_rx_std_sparemap = map;
 990         sc->bge_cdata.bge_rx_std_chain[i] = m;
 991         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
 992         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 993         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 994         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 995         r->bge_flags = BGE_RXBDFLAG_END;
 996         r->bge_len = segs[0].ds_len;
 997         r->bge_idx = i;
 998
 999         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1000             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1001
1002         return (0);
1003 }
1004
1005 /*
1006  * Initialize a jumbo receive ring descriptor. This allocates
1007  * a jumbo buffer from the pool managed internally by the driver.
1008  */
1009 static int
1010 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1011 {
1012         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1013         bus_dmamap_t map;
1014         struct bge_extrx_bd *r;
1015         struct mbuf *m;
1016         int error, nsegs;
1017
1018         MGETHDR(m, M_DONTWAIT, MT_DATA);
1019         if (m == NULL)
1020                 return (ENOBUFS);
1021
1022         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
1023         if (!(m->m_flags & M_EXT)) {
1024                 m_freem(m);
1025                 return (ENOBUFS);
1026         }
1027         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1028         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1029                 m_adj(m, ETHER_ALIGN);
1030
1031         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1032             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1033         if (error != 0) {
1034                 m_freem(m);
1035                 return (error);
1036         }
1037
1038         if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1039                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1040                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1041                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1042                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1043         }
1044         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1045         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1046             sc->bge_cdata.bge_rx_jumbo_sparemap;
1047         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1048         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1049         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1050         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1051         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1052         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1053
1054         /*
1055          * Fill in the extended RX buffer descriptor.
1056          */
1057         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1058         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1059         r->bge_idx = i;
1060         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1061         switch (nsegs) {
1062         case 4:
1063                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1064                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1065                 r->bge_len3 = segs[3].ds_len;
1066                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1067         case 3:
1068                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1069                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1070                 r->bge_len2 = segs[2].ds_len;
1071                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1072         case 2:
1073                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1074                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1075                 r->bge_len1 = segs[1].ds_len;
1076                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1077         case 1:
1078                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1079                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1080                 r->bge_len0 = segs[0].ds_len;
1081                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1082                 break;
1083         default:
1084                 panic("%s: %d segments\n", __func__, nsegs);
1085         }
1086
1087         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1088             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1089
1090         return (0);
1091 }
1092
1093 static int
1094 bge_init_rx_ring_std(struct bge_softc *sc)
1095 {
1096         int error, i;
1097
1098         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1099         sc->bge_std = 0;
1100         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1101                 if ((error = bge_newbuf_std(sc, i)) != 0)
1102                         return (error);
1103                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1104         }
1105
1106         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1107             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1108
1109         sc->bge_std = 0;
1110         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1111
1112         return (0);
1113 }
1114
1115 static void
1116 bge_free_rx_ring_std(struct bge_softc *sc)
1117 {
1118         int i;
1119
1120         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1121                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1122                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1123                             sc->bge_cdata.bge_rx_std_dmamap[i],
1124                             BUS_DMASYNC_POSTREAD);
1125                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1126                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1127                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1128                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1129                 }
1130                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1131                     sizeof(struct bge_rx_bd));
1132         }
1133 }
1134
1135 static int
1136 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1137 {
1138         struct bge_rcb *rcb;
1139         int error, i;
1140
1141         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1142         sc->bge_jumbo = 0;
1143         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1144                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1145                         return (error);
1146                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1147         }
1148
1149         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1150             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1151
1152         sc->bge_jumbo = 0;
1153
1154         /* Enable the jumbo receive producer ring. */
1155         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1156         rcb->bge_maxlen_flags =
1157             BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1158         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1159
1160         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1161
1162         return (0);
1163 }
1164
1165 static void
1166 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1167 {
1168         int i;
1169
1170         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1171                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1172                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1173                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1174                             BUS_DMASYNC_POSTREAD);
1175                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1176                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1177                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1178                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1179                 }
1180                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1181                     sizeof(struct bge_extrx_bd));
1182         }
1183 }
1184
1185 static void
1186 bge_free_tx_ring(struct bge_softc *sc)
1187 {
1188         int i;
1189
1190         if (sc->bge_ldata.bge_tx_ring == NULL)
1191                 return;
1192
1193         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1194                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1195                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1196                             sc->bge_cdata.bge_tx_dmamap[i],
1197                             BUS_DMASYNC_POSTWRITE);
1198                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1199                             sc->bge_cdata.bge_tx_dmamap[i]);
1200                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1201                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1202                 }
1203                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1204                     sizeof(struct bge_tx_bd));
1205         }
1206 }
1207
1208 static int
1209 bge_init_tx_ring(struct bge_softc *sc)
1210 {
1211         sc->bge_txcnt = 0;
1212         sc->bge_tx_saved_considx = 0;
1213
1214         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1215         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1216             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1217
1218         /* Initialize transmit producer index for host-memory send ring. */
1219         sc->bge_tx_prodidx = 0;
1220         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1221
1222         /* 5700 b2 errata */
1223         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1224                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1225
1226         /* NIC-memory send ring not used; initialize to zero. */
1227         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1228         /* 5700 b2 errata */
1229         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1230                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1231
1232         return (0);
1233 }
1234
1235 static void
1236 bge_setpromisc(struct bge_softc *sc)
1237 {
1238         struct ifnet *ifp;
1239
1240         BGE_LOCK_ASSERT(sc);
1241
1242         ifp = sc->bge_ifp;
1243
1244         /* Enable or disable promiscuous mode as needed. */
1245         if (ifp->if_flags & IFF_PROMISC)
1246                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1247         else
1248                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1249 }
1250
1251 static void
1252 bge_setmulti(struct bge_softc *sc)
1253 {
1254         struct ifnet *ifp;
1255         struct ifmultiaddr *ifma;
1256         uint32_t hashes[4] = { 0, 0, 0, 0 };
1257         int h, i;
1258
1259         BGE_LOCK_ASSERT(sc);
1260
1261         ifp = sc->bge_ifp;
1262
1263         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1264                 for (i = 0; i < 4; i++)
1265                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1266                 return;
1267         }
1268
1269         /* First, zot all the existing filters. */
1270         for (i = 0; i < 4; i++)
1271                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1272
1273         /* Now program new ones. */
1274         if_maddr_rlock(ifp);
1275         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1276                 if (ifma->ifma_addr->sa_family != AF_LINK)
1277                         continue;
1278                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1279                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1280                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1281         }
1282         if_maddr_runlock(ifp);
1283
1284         for (i = 0; i < 4; i++)
1285                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1286 }
1287
1288 static void
1289 bge_setvlan(struct bge_softc *sc)
1290 {
1291         struct ifnet *ifp;
1292
1293         BGE_LOCK_ASSERT(sc);
1294
1295         ifp = sc->bge_ifp;
1296
1297         /* Enable or disable VLAN tag stripping as needed. */
1298         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1299                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1300         else
1301                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1302 }
1303
1304 static void
1305 bge_sig_pre_reset(struct bge_softc *sc, int type)
1306 {
1307
1308         /*
1309          * Some chips don't like this so only do this if ASF is enabled
1310          */
1311         if (sc->bge_asf_mode)
1312                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1313
1314         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1315                 switch (type) {
1316                 case BGE_RESET_START:
1317                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1318                         break;
1319                 case BGE_RESET_STOP:
1320                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1321                         break;
1322                 }
1323         }
1324 }
1325
1326 static void
1327 bge_sig_post_reset(struct bge_softc *sc, int type)
1328 {
1329
1330         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1331                 switch (type) {
1332                 case BGE_RESET_START:
1333                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1334                         /* START DONE */
1335                         break;
1336                 case BGE_RESET_STOP:
1337                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1338                         break;
1339                 }
1340         }
1341 }
1342
1343 static void
1344 bge_sig_legacy(struct bge_softc *sc, int type)
1345 {
1346
1347         if (sc->bge_asf_mode) {
1348                 switch (type) {
1349                 case BGE_RESET_START:
1350                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1351                         break;
1352                 case BGE_RESET_STOP:
1353                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1354                         break;
1355                 }
1356         }
1357 }
1358
1359 static void
1360 bge_stop_fw(struct bge_softc *sc)
1361 {
1362         int i;
1363
1364         if (sc->bge_asf_mode) {
1365                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1366                 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1367                     CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1368
1369                 for (i = 0; i < 100; i++ ) {
1370                         if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1371                                 break;
1372                         DELAY(10);
1373                 }
1374         }
1375 }
1376
1377 /*
1378  * Do endian, PCI and DMA initialization.
1379  */
1380 static int
1381 bge_chipinit(struct bge_softc *sc)
1382 {
1383         uint32_t dma_rw_ctl, misc_ctl;
1384         uint16_t val;
1385         int i;
1386
1387         /* Set endianness before we access any non-PCI registers. */
1388         misc_ctl = BGE_INIT;
1389         if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1390                 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1391         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1392
1393         /* Clear the MAC control register */
1394         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1395
1396         /*
1397          * Clear the MAC statistics block in the NIC's
1398          * internal memory.
1399          */
1400         for (i = BGE_STATS_BLOCK;
1401             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1402                 BGE_MEMWIN_WRITE(sc, i, 0);
1403
1404         for (i = BGE_STATUS_BLOCK;
1405             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1406                 BGE_MEMWIN_WRITE(sc, i, 0);
1407
1408         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1409                 /*
1410                  *  Fix data corruption caused by non-qword write with WB.
1411                  *  Fix master abort in PCI mode.
1412                  *  Fix PCI latency timer.
1413                  */
1414                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1415                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1416                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1417         }
1418
1419         /*
1420          * Set up the PCI DMA control register.
1421          */
1422         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1423             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1424         if (sc->bge_flags & BGE_FLAG_PCIE) {
1425                 /* Read watermark not used, 128 bytes for write. */
1426                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1427         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1428                 if (BGE_IS_5714_FAMILY(sc)) {
1429                         /* 256 bytes for read and write. */
1430                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1431                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1432                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1433                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1434                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1435                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1436                         /*
1437                          * In the BCM5703, the DMA read watermark should
1438                          * be set to less than or equal to the maximum
1439                          * memory read byte count of the PCI-X command
1440                          * register.
1441                          */
1442                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1443                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1444                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1445                         /* 1536 bytes for read, 384 bytes for write. */
1446                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1447                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1448                 } else {
1449                         /* 384 bytes for read and write. */
1450                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1451                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1452                             0x0F;
1453                 }
1454                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1455                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1456                         uint32_t tmp;
1457
1458                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1459                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1460                         if (tmp == 6 || tmp == 7)
1461                                 dma_rw_ctl |=
1462                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1463
1464                         /* Set PCI-X DMA write workaround. */
1465                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1466                 }
1467         } else {
1468                 /* Conventional PCI bus: 256 bytes for read and write. */
1469                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1470                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1471
1472                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1473                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1474                         dma_rw_ctl |= 0x0F;
1475         }
1476         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1477             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1478                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1479                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1480         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1481             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1482                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1483         if (BGE_IS_5717_PLUS(sc)) {
1484                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1485                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1486                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1487                 /*
1488                  * Enable HW workaround for controllers that misinterpret
1489                  * a status tag update and leave interrupts permanently
1490                  * disabled.
1491                  */
1492                 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1493                     sc->bge_asicrev != BGE_ASICREV_BCM57765)
1494                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1495         }
1496         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1497
1498         /*
1499          * Set up general mode register.
1500          */
1501         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1502             BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1503             BGE_MODECTL_TX_NO_PHDR_CSUM);
1504
1505         /*
1506          * BCM5701 B5 have a bug causing data corruption when using
1507          * 64-bit DMA reads, which can be terminated early and then
1508          * completed later as 32-bit accesses, in combination with
1509          * certain bridges.
1510          */
1511         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1512             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1513                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1514
1515         /*
1516          * Tell the firmware the driver is running
1517          */
1518         if (sc->bge_asf_mode & ASF_STACKUP)
1519                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1520
1521         /*
1522          * Disable memory write invalidate.  Apparently it is not supported
1523          * properly by these devices.  Also ensure that INTx isn't disabled,
1524          * as these chips need it even when using MSI.
1525          */
1526         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1527             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1528
1529         /* Set the timer prescaler (always 66Mhz) */
1530         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1531
1532         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1533         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1534                 DELAY(40);      /* XXX */
1535
1536                 /* Put PHY into ready state */
1537                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1538                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1539                 DELAY(40);
1540         }
1541
1542         return (0);
1543 }
1544
1545 static int
1546 bge_blockinit(struct bge_softc *sc)
1547 {
1548         struct bge_rcb *rcb;
1549         bus_size_t vrcb;
1550         bge_hostaddr taddr;
1551         uint32_t dmactl, val;
1552         int i, limit;
1553
1554         /*
1555          * Initialize the memory window pointer register so that
1556          * we can access the first 32K of internal NIC RAM. This will
1557          * allow us to set up the TX send ring RCBs and the RX return
1558          * ring RCBs, plus other things which live in NIC memory.
1559          */
1560         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1561
1562         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1563
1564         if (!(BGE_IS_5705_PLUS(sc))) {
1565                 /* Configure mbuf memory pool */
1566                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1567                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1568                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1569                 else
1570                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1571
1572                 /* Configure DMA resource pool */
1573                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1574                     BGE_DMA_DESCRIPTORS);
1575                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1576         }
1577
1578         /* Configure mbuf pool watermarks */
1579         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1580             sc->bge_asicrev == BGE_ASICREV_BCM57765) {
1581                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1582                 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1583                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1584                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1585                 } else {
1586                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1587                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1588                 }
1589         } else if (!BGE_IS_5705_PLUS(sc)) {
1590                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1591                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1592                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1593         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1594                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1595                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1596                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1597         } else {
1598                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1599                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1600                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1601         }
1602
1603         /* Configure DMA resource watermarks */
1604         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1605         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1606
1607         /* Enable buffer manager */
1608         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1609         /*
1610          * Change the arbitration algorithm of TXMBUF read request to
1611          * round-robin instead of priority based for BCM5719.  When
1612          * TXFIFO is almost empty, RDMA will hold its request until
1613          * TXFIFO is not almost empty.
1614          */
1615         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1616                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1617         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1618
1619         /* Poll for buffer manager start indication */
1620         for (i = 0; i < BGE_TIMEOUT; i++) {
1621                 DELAY(10);
1622                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1623                         break;
1624         }
1625
1626         if (i == BGE_TIMEOUT) {
1627                 device_printf(sc->bge_dev, "buffer manager failed to start\n");
1628                 return (ENXIO);
1629         }
1630
1631         /* Enable flow-through queues */
1632         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1633         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1634
1635         /* Wait until queue initialization is complete */
1636         for (i = 0; i < BGE_TIMEOUT; i++) {
1637                 DELAY(10);
1638                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1639                         break;
1640         }
1641
1642         if (i == BGE_TIMEOUT) {
1643                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1644                 return (ENXIO);
1645         }
1646
1647         /*
1648          * Summary of rings supported by the controller:
1649          *
1650          * Standard Receive Producer Ring
1651          * - This ring is used to feed receive buffers for "standard"
1652          *   sized frames (typically 1536 bytes) to the controller.
1653          *
1654          * Jumbo Receive Producer Ring
1655          * - This ring is used to feed receive buffers for jumbo sized
1656          *   frames (i.e. anything bigger than the "standard" frames)
1657          *   to the controller.
1658          *
1659          * Mini Receive Producer Ring
1660          * - This ring is used to feed receive buffers for "mini"
1661          *   sized frames to the controller.
1662          * - This feature required external memory for the controller
1663          *   but was never used in a production system.  Should always
1664          *   be disabled.
1665          *
1666          * Receive Return Ring
1667          * - After the controller has placed an incoming frame into a
1668          *   receive buffer that buffer is moved into a receive return
1669          *   ring.  The driver is then responsible to passing the
1670          *   buffer up to the stack.  Many versions of the controller
1671          *   support multiple RR rings.
1672          *
1673          * Send Ring
1674          * - This ring is used for outgoing frames.  Many versions of
1675          *   the controller support multiple send rings.
1676          */
1677
1678         /* Initialize the standard receive producer ring control block. */
1679         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1680         rcb->bge_hostaddr.bge_addr_lo =
1681             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1682         rcb->bge_hostaddr.bge_addr_hi =
1683             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1684         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1685             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1686         if (BGE_IS_5717_PLUS(sc)) {
1687                 /*
1688                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1689                  * Bits 15-2 : Maximum RX frame size
1690                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1691                  * Bit 0     : Reserved
1692                  */
1693                 rcb->bge_maxlen_flags =
1694                     BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
1695         } else if (BGE_IS_5705_PLUS(sc)) {
1696                 /*
1697                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1698                  * Bits 15-2 : Reserved (should be 0)
1699                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1700                  * Bit 0     : Reserved
1701                  */
1702                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1703         } else {
1704                 /*
1705                  * Ring size is always XXX entries
1706                  * Bits 31-16: Maximum RX frame size
1707                  * Bits 15-2 : Reserved (should be 0)
1708                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1709                  * Bit 0     : Reserved
1710                  */
1711                 rcb->bge_maxlen_flags =
1712                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1713         }
1714         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1715             sc->bge_asicrev == BGE_ASICREV_BCM5719)
1716                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1717         else
1718                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1719         /* Write the standard receive producer ring control block. */
1720         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1721         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1722         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1723         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1724
1725         /* Reset the standard receive producer ring producer index. */
1726         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1727
1728         /*
1729          * Initialize the jumbo RX producer ring control
1730          * block.  We set the 'ring disabled' bit in the
1731          * flags field until we're actually ready to start
1732          * using this ring (i.e. once we set the MTU
1733          * high enough to require it).
1734          */
1735         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1736                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1737                 /* Get the jumbo receive producer ring RCB parameters. */
1738                 rcb->bge_hostaddr.bge_addr_lo =
1739                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1740                 rcb->bge_hostaddr.bge_addr_hi =
1741                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1742                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1743                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1744                     BUS_DMASYNC_PREREAD);
1745                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1746                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1747                 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1748                     sc->bge_asicrev == BGE_ASICREV_BCM5719)
1749                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1750                 else
1751                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1752                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1753                     rcb->bge_hostaddr.bge_addr_hi);
1754                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1755                     rcb->bge_hostaddr.bge_addr_lo);
1756                 /* Program the jumbo receive producer ring RCB parameters. */
1757                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1758                     rcb->bge_maxlen_flags);
1759                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1760                 /* Reset the jumbo receive producer ring producer index. */
1761                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1762         }
1763
1764         /* Disable the mini receive producer ring RCB. */
1765         if (BGE_IS_5700_FAMILY(sc)) {
1766                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1767                 rcb->bge_maxlen_flags =
1768                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1769                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1770                     rcb->bge_maxlen_flags);
1771                 /* Reset the mini receive producer ring producer index. */
1772                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1773         }
1774
1775         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1776         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1777                 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1778                     sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1779                     sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
1780                         CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1781                             (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1782         }
1783         /*
1784          * The BD ring replenish thresholds control how often the
1785          * hardware fetches new BD's from the producer rings in host
1786          * memory.  Setting the value too low on a busy system can
1787          * starve the hardware and recue the throughpout.
1788          *
1789          * Set the BD ring replentish thresholds. The recommended
1790          * values are 1/8th the number of descriptors allocated to
1791          * each ring.
1792          * XXX The 5754 requires a lower threshold, so it might be a
1793          * requirement of all 575x family chips.  The Linux driver sets
1794          * the lower threshold for all 5705 family chips as well, but there
1795          * are reports that it might not need to be so strict.
1796          *
1797          * XXX Linux does some extra fiddling here for the 5906 parts as
1798          * well.
1799          */
1800         if (BGE_IS_5705_PLUS(sc))
1801                 val = 8;
1802         else
1803                 val = BGE_STD_RX_RING_CNT / 8;
1804         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1805         if (BGE_IS_JUMBO_CAPABLE(sc))
1806                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1807                     BGE_JUMBO_RX_RING_CNT/8);
1808         if (BGE_IS_5717_PLUS(sc)) {
1809                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1810                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1811         }
1812
1813         /*
1814          * Disable all send rings by setting the 'ring disabled' bit
1815          * in the flags field of all the TX send ring control blocks,
1816          * located in NIC memory.
1817          */
1818         if (!BGE_IS_5705_PLUS(sc))
1819                 /* 5700 to 5704 had 16 send rings. */
1820                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1821         else
1822                 limit = 1;
1823         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1824         for (i = 0; i < limit; i++) {
1825                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1826                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1827                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1828                 vrcb += sizeof(struct bge_rcb);
1829         }
1830
1831         /* Configure send ring RCB 0 (we use only the first ring) */
1832         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1833         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1834         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1835         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1836         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1837             sc->bge_asicrev == BGE_ASICREV_BCM5719)
1838                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1839         else
1840                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1841                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1842         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1843             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1844
1845         /*
1846          * Disable all receive return rings by setting the
1847          * 'ring diabled' bit in the flags field of all the receive
1848          * return ring control blocks, located in NIC memory.
1849          */
1850         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1851             sc->bge_asicrev == BGE_ASICREV_BCM5719) {
1852                 /* Should be 17, use 16 until we get an SRAM map. */
1853                 limit = 16;
1854         } else if (!BGE_IS_5705_PLUS(sc))
1855                 limit = BGE_RX_RINGS_MAX;
1856         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1857             sc->bge_asicrev == BGE_ASICREV_BCM57765)
1858                 limit = 4;
1859         else
1860                 limit = 1;
1861         /* Disable all receive return rings. */
1862         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1863         for (i = 0; i < limit; i++) {
1864                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1865                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1866                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1867                     BGE_RCB_FLAG_RING_DISABLED);
1868                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1869                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1870                     (i * (sizeof(uint64_t))), 0);
1871                 vrcb += sizeof(struct bge_rcb);
1872         }
1873
1874         /*
1875          * Set up receive return ring 0.  Note that the NIC address
1876          * for RX return rings is 0x0.  The return rings live entirely
1877          * within the host, so the nicaddr field in the RCB isn't used.
1878          */
1879         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1880         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1881         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1882         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1883         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1884         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1885             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1886
1887         /* Set random backoff seed for TX */
1888         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1889             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1890             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1891             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1892             BGE_TX_BACKOFF_SEED_MASK);
1893
1894         /* Set inter-packet gap */
1895         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1896
1897         /*
1898          * Specify which ring to use for packets that don't match
1899          * any RX rules.
1900          */
1901         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1902
1903         /*
1904          * Configure number of RX lists. One interrupt distribution
1905          * list, sixteen active lists, one bad frames class.
1906          */
1907         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1908
1909         /* Inialize RX list placement stats mask. */
1910         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1911         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1912
1913         /* Disable host coalescing until we get it set up */
1914         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1915
1916         /* Poll to make sure it's shut down. */
1917         for (i = 0; i < BGE_TIMEOUT; i++) {
1918                 DELAY(10);
1919                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1920                         break;
1921         }
1922
1923         if (i == BGE_TIMEOUT) {
1924                 device_printf(sc->bge_dev,
1925                     "host coalescing engine failed to idle\n");
1926                 return (ENXIO);
1927         }
1928
1929         /* Set up host coalescing defaults */
1930         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1931         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1932         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1933         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1934         if (!(BGE_IS_5705_PLUS(sc))) {
1935                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1936                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1937         }
1938         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1939         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1940
1941         /* Set up address of statistics block */
1942         if (!(BGE_IS_5705_PLUS(sc))) {
1943                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1944                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1945                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1946                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1947                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1948                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1949                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1950         }
1951
1952         /* Set up address of status block */
1953         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1954             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1955         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1956             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1957
1958         /* Set up status block size. */
1959         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1960             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1961                 val = BGE_STATBLKSZ_FULL;
1962                 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1963         } else {
1964                 val = BGE_STATBLKSZ_32BYTE;
1965                 bzero(sc->bge_ldata.bge_status_block, 32);
1966         }
1967         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
1968             sc->bge_cdata.bge_status_map,
1969             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1970
1971         /* Turn on host coalescing state machine */
1972         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1973
1974         /* Turn on RX BD completion state machine and enable attentions */
1975         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1976             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1977
1978         /* Turn on RX list placement state machine */
1979         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1980
1981         /* Turn on RX list selector state machine. */
1982         if (!(BGE_IS_5705_PLUS(sc)))
1983                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1984
1985         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1986             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1987             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1988             BGE_MACMODE_FRMHDR_DMA_ENB;
1989
1990         if (sc->bge_flags & BGE_FLAG_TBI)
1991                 val |= BGE_PORTMODE_TBI;
1992         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1993                 val |= BGE_PORTMODE_GMII;
1994         else
1995                 val |= BGE_PORTMODE_MII;
1996
1997         /* Turn on DMA, clear stats */
1998         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1999
2000         /* Set misc. local control, enable interrupts on attentions */
2001         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2002
2003 #ifdef notdef
2004         /* Assert GPIO pins for PHY reset */
2005         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2006             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2007         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2008             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2009 #endif
2010
2011         /* Turn on DMA completion state machine */
2012         if (!(BGE_IS_5705_PLUS(sc)))
2013                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2014
2015         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2016
2017         /* Enable host coalescing bug fix. */
2018         if (BGE_IS_5755_PLUS(sc))
2019                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2020
2021         /* Request larger DMA burst size to get better performance. */
2022         if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2023                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2024
2025         /* Turn on write DMA state machine */
2026         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2027         DELAY(40);
2028
2029         /* Turn on read DMA state machine */
2030         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2031
2032         if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2033                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2034
2035         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2036             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2037             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2038                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2039                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2040                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2041         if (sc->bge_flags & BGE_FLAG_PCIE)
2042                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2043         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2044                 val |= BGE_RDMAMODE_TSO4_ENABLE;
2045                 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2046                     sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2047                     sc->bge_asicrev == BGE_ASICREV_BCM57780)
2048                         val |= BGE_RDMAMODE_TSO6_ENABLE;
2049         }
2050         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2051             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2052             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2053             sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2054             BGE_IS_5717_PLUS(sc)) {
2055                 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
2056                 /*
2057                  * Adjust tx margin to prevent TX data corruption and
2058                  * fix internal FIFO overflow.
2059                  */
2060                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2061                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2062                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2063                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2064                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2065                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2066                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2067                 }
2068                 /*
2069                  * Enable fix for read DMA FIFO overruns.
2070                  * The fix is to limit the number of RX BDs
2071                  * the hardware would fetch at a fime.
2072                  */
2073                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
2074                     BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2075         }
2076
2077         if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2078                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2079                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2080                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2081                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2082         }
2083
2084         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2085         DELAY(40);
2086
2087         /* Turn on RX data completion state machine */
2088         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2089
2090         /* Turn on RX BD initiator state machine */
2091         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2092
2093         /* Turn on RX data and RX BD initiator state machine */
2094         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2095
2096         /* Turn on Mbuf cluster free state machine */
2097         if (!(BGE_IS_5705_PLUS(sc)))
2098                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2099
2100         /* Turn on send BD completion state machine */
2101         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2102
2103         /* Turn on send data completion state machine */
2104         val = BGE_SDCMODE_ENABLE;
2105         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2106                 val |= BGE_SDCMODE_CDELAY;
2107         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2108
2109         /* Turn on send data initiator state machine */
2110         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2111                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2112                     BGE_SDIMODE_HW_LSO_PRE_DMA);
2113         else
2114                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2115
2116         /* Turn on send BD initiator state machine */
2117         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2118
2119         /* Turn on send BD selector state machine */
2120         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2121
2122         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2123         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2124             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2125
2126         /* ack/clear link change events */
2127         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2128             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2129             BGE_MACSTAT_LINK_CHANGED);
2130         CSR_WRITE_4(sc, BGE_MI_STS, 0);
2131
2132         /*
2133          * Enable attention when the link has changed state for
2134          * devices that use auto polling.
2135          */
2136         if (sc->bge_flags & BGE_FLAG_TBI) {
2137                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2138         } else {
2139                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2140                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2141                         DELAY(80);
2142                 }
2143                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2144                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2145                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2146                             BGE_EVTENB_MI_INTERRUPT);
2147         }
2148
2149         /*
2150          * Clear any pending link state attention.
2151          * Otherwise some link state change events may be lost until attention
2152          * is cleared by bge_intr() -> bge_link_upd() sequence.
2153          * It's not necessary on newer BCM chips - perhaps enabling link
2154          * state change attentions implies clearing pending attention.
2155          */
2156         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2157             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2158             BGE_MACSTAT_LINK_CHANGED);
2159
2160         /* Enable link state change attentions. */
2161         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2162
2163         return (0);
2164 }
2165
2166 const struct bge_revision *
2167 bge_lookup_rev(uint32_t chipid)
2168 {
2169         const struct bge_revision *br;
2170
2171         for (br = bge_revisions; br->br_name != NULL; br++) {
2172                 if (br->br_chipid == chipid)
2173                         return (br);
2174         }
2175
2176         for (br = bge_majorrevs; br->br_name != NULL; br++) {
2177                 if (br->br_chipid == BGE_ASICREV(chipid))
2178                         return (br);
2179         }
2180
2181         return (NULL);
2182 }
2183
2184 const struct bge_vendor *
2185 bge_lookup_vendor(uint16_t vid)
2186 {
2187         const struct bge_vendor *v;
2188
2189         for (v = bge_vendors; v->v_name != NULL; v++)
2190                 if (v->v_id == vid)
2191                         return (v);
2192
2193         panic("%s: unknown vendor %d", __func__, vid);
2194         return (NULL);
2195 }
2196
2197 /*
2198  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2199  * against our list and return its name if we find a match.
2200  *
2201  * Note that since the Broadcom controller contains VPD support, we
2202  * try to get the device name string from the controller itself instead
2203  * of the compiled-in string. It guarantees we'll always announce the
2204  * right product name. We fall back to the compiled-in string when
2205  * VPD is unavailable or corrupt.
2206  */
2207 static int
2208 bge_probe(device_t dev)
2209 {
2210         char buf[96];
2211         char model[64];
2212         const struct bge_revision *br;
2213         const char *pname;
2214         struct bge_softc *sc = device_get_softc(dev);
2215         const struct bge_type *t = bge_devs;
2216         const struct bge_vendor *v;
2217         uint32_t id;
2218         uint16_t did, vid;
2219
2220         sc->bge_dev = dev;
2221         vid = pci_get_vendor(dev);
2222         did = pci_get_device(dev);
2223         while(t->bge_vid != 0) {
2224                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2225                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2226                             BGE_PCIMISCCTL_ASICREV_SHIFT;
2227                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2228                                 /*
2229                                  * Find the ASCI revision.  Different chips
2230                                  * use different registers.
2231                                  */
2232                                 switch (pci_get_device(dev)) {
2233                                 case BCOM_DEVICEID_BCM5717:
2234                                 case BCOM_DEVICEID_BCM5718:
2235                                 case BCOM_DEVICEID_BCM5719:
2236                                         id = pci_read_config(dev,
2237                                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2238                                         break;
2239                                 case BCOM_DEVICEID_BCM57761:
2240                                 case BCOM_DEVICEID_BCM57765:
2241                                 case BCOM_DEVICEID_BCM57781:
2242                                 case BCOM_DEVICEID_BCM57785:
2243                                 case BCOM_DEVICEID_BCM57791:
2244                                 case BCOM_DEVICEID_BCM57795:
2245                                         id = pci_read_config(dev,
2246                                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2247                                         break;
2248                                 default:
2249                                         id = pci_read_config(dev,
2250                                             BGE_PCI_PRODID_ASICREV, 4);
2251                                 }
2252                         }
2253                         br = bge_lookup_rev(id);
2254                         v = bge_lookup_vendor(vid);
2255                         if (bge_has_eaddr(sc) &&
2256                             pci_get_vpd_ident(dev, &pname) == 0)
2257                                 snprintf(model, 64, "%s", pname);
2258                         else
2259                                 snprintf(model, 64, "%s %s", v->v_name,
2260                                     br != NULL ? br->br_name :
2261                                     "NetXtreme Ethernet Controller");
2262                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
2263                             br != NULL ? "" : "unknown ", id);
2264                         device_set_desc_copy(dev, buf);
2265                         return (0);
2266                 }
2267                 t++;
2268         }
2269
2270         return (ENXIO);
2271 }
2272
2273 static void
2274 bge_dma_free(struct bge_softc *sc)
2275 {
2276         int i;
2277
2278         /* Destroy DMA maps for RX buffers. */
2279         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2280                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2281                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2282                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2283         }
2284         if (sc->bge_cdata.bge_rx_std_sparemap)
2285                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2286                     sc->bge_cdata.bge_rx_std_sparemap);
2287
2288         /* Destroy DMA maps for jumbo RX buffers. */
2289         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2290                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2291                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2292                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2293         }
2294         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2295                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2296                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2297
2298         /* Destroy DMA maps for TX buffers. */
2299         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2300                 if (sc->bge_cdata.bge_tx_dmamap[i])
2301                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2302                             sc->bge_cdata.bge_tx_dmamap[i]);
2303         }
2304
2305         if (sc->bge_cdata.bge_rx_mtag)
2306                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2307         if (sc->bge_cdata.bge_tx_mtag)
2308                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2309
2310
2311         /* Destroy standard RX ring. */
2312         if (sc->bge_cdata.bge_rx_std_ring_map)
2313                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2314                     sc->bge_cdata.bge_rx_std_ring_map);
2315         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2316                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2317                     sc->bge_ldata.bge_rx_std_ring,
2318                     sc->bge_cdata.bge_rx_std_ring_map);
2319
2320         if (sc->bge_cdata.bge_rx_std_ring_tag)
2321                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2322
2323         /* Destroy jumbo RX ring. */
2324         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2325                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2326                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2327
2328         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2329             sc->bge_ldata.bge_rx_jumbo_ring)
2330                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2331                     sc->bge_ldata.bge_rx_jumbo_ring,
2332                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2333
2334         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2335                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2336
2337         /* Destroy RX return ring. */
2338         if (sc->bge_cdata.bge_rx_return_ring_map)
2339                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2340                     sc->bge_cdata.bge_rx_return_ring_map);
2341
2342         if (sc->bge_cdata.bge_rx_return_ring_map &&
2343             sc->bge_ldata.bge_rx_return_ring)
2344                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2345                     sc->bge_ldata.bge_rx_return_ring,
2346                     sc->bge_cdata.bge_rx_return_ring_map);
2347
2348         if (sc->bge_cdata.bge_rx_return_ring_tag)
2349                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2350
2351         /* Destroy TX ring. */
2352         if (sc->bge_cdata.bge_tx_ring_map)
2353                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2354                     sc->bge_cdata.bge_tx_ring_map);
2355
2356         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2357                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2358                     sc->bge_ldata.bge_tx_ring,
2359                     sc->bge_cdata.bge_tx_ring_map);
2360
2361         if (sc->bge_cdata.bge_tx_ring_tag)
2362                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2363
2364         /* Destroy status block. */
2365         if (sc->bge_cdata.bge_status_map)
2366                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2367                     sc->bge_cdata.bge_status_map);
2368
2369         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2370                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2371                     sc->bge_ldata.bge_status_block,
2372                     sc->bge_cdata.bge_status_map);
2373
2374         if (sc->bge_cdata.bge_status_tag)
2375                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2376
2377         /* Destroy statistics block. */
2378         if (sc->bge_cdata.bge_stats_map)
2379                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2380                     sc->bge_cdata.bge_stats_map);
2381
2382         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2383                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2384                     sc->bge_ldata.bge_stats,
2385                     sc->bge_cdata.bge_stats_map);
2386
2387         if (sc->bge_cdata.bge_stats_tag)
2388                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2389
2390         if (sc->bge_cdata.bge_buffer_tag)
2391                 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2392
2393         /* Destroy the parent tag. */
2394         if (sc->bge_cdata.bge_parent_tag)
2395                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2396 }
2397
2398 static int
2399 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2400     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2401     bus_addr_t *paddr, const char *msg)
2402 {
2403         struct bge_dmamap_arg ctx;
2404         bus_addr_t lowaddr;
2405         bus_size_t ring_end;
2406         int error;
2407
2408         lowaddr = BUS_SPACE_MAXADDR;
2409 again:
2410         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2411             alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2412             NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2413         if (error != 0) {
2414                 device_printf(sc->bge_dev,
2415                     "could not create %s dma tag\n", msg);
2416                 return (ENOMEM);
2417         }
2418         /* Allocate DMA'able memory for ring. */
2419         error = bus_dmamem_alloc(*tag, (void **)ring,
2420             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2421         if (error != 0) {
2422                 device_printf(sc->bge_dev,
2423                     "could not allocate DMA'able memory for %s\n", msg);
2424                 return (ENOMEM);
2425         }
2426         /* Load the address of the ring. */
2427         ctx.bge_busaddr = 0;
2428         error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2429             &ctx, BUS_DMA_NOWAIT);
2430         if (error != 0) {
2431                 device_printf(sc->bge_dev,
2432                     "could not load DMA'able memory for %s\n", msg);
2433                 return (ENOMEM);
2434         }
2435         *paddr = ctx.bge_busaddr;
2436         ring_end = *paddr + maxsize;
2437         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2438             BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) {
2439                 /*
2440                  * 4GB boundary crossed.  Limit maximum allowable DMA
2441                  * address space to 32bit and try again.
2442                  */
2443                 bus_dmamap_unload(*tag, *map);
2444                 bus_dmamem_free(*tag, *ring, *map);
2445                 bus_dma_tag_destroy(*tag);
2446                 if (bootverbose)
2447                         device_printf(sc->bge_dev, "4GB boundary crossed, "
2448                             "limit DMA address space to 32bit for %s\n", msg);
2449                 *ring = NULL;
2450                 *tag = NULL;
2451                 *map = NULL;
2452                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2453                 goto again;
2454         }
2455         return (0);
2456 }
2457
2458 static int
2459 bge_dma_alloc(struct bge_softc *sc)
2460 {
2461         bus_addr_t lowaddr;
2462         bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz;
2463         int i, error;
2464
2465         lowaddr = BUS_SPACE_MAXADDR;
2466         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2467                 lowaddr = BGE_DMA_MAXADDR;
2468         /*
2469          * Allocate the parent bus DMA tag appropriate for PCI.
2470          */
2471         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2472             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2473             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2474             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2475         if (error != 0) {
2476                 device_printf(sc->bge_dev,
2477                     "could not allocate parent dma tag\n");
2478                 return (ENOMEM);
2479         }
2480
2481         /* Create tag for standard RX ring. */
2482         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2483             &sc->bge_cdata.bge_rx_std_ring_tag,
2484             (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2485             &sc->bge_cdata.bge_rx_std_ring_map,
2486             &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2487         if (error)
2488                 return (error);
2489
2490         /* Create tag for RX return ring. */
2491         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2492             &sc->bge_cdata.bge_rx_return_ring_tag,
2493             (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2494             &sc->bge_cdata.bge_rx_return_ring_map,
2495             &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2496         if (error)
2497                 return (error);
2498
2499         /* Create tag for TX ring. */
2500         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2501             &sc->bge_cdata.bge_tx_ring_tag,
2502             (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2503             &sc->bge_cdata.bge_tx_ring_map,
2504             &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2505         if (error)
2506                 return (error);
2507
2508         /*
2509          * Create tag for status block.
2510          * Because we only use single Tx/Rx/Rx return ring, use
2511          * minimum status block size except BCM5700 AX/BX which
2512          * seems to want to see full status block size regardless
2513          * of configured number of ring.
2514          */
2515         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2516             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2517                 sbsz = BGE_STATUS_BLK_SZ;
2518         else
2519                 sbsz = 32;
2520         error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2521             &sc->bge_cdata.bge_status_tag,
2522             (uint8_t **)&sc->bge_ldata.bge_status_block,
2523             &sc->bge_cdata.bge_status_map,
2524             &sc->bge_ldata.bge_status_block_paddr, "status block");
2525         if (error)
2526                 return (error);
2527
2528         /* Create tag for statistics block. */
2529         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2530             &sc->bge_cdata.bge_stats_tag,
2531             (uint8_t **)&sc->bge_ldata.bge_stats,
2532             &sc->bge_cdata.bge_stats_map,
2533             &sc->bge_ldata.bge_stats_paddr, "statistics block");
2534         if (error)
2535                 return (error);
2536
2537         /* Create tag for jumbo RX ring. */
2538         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2539                 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
2540                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
2541                     (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
2542                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
2543                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
2544                 if (error)
2545                         return (error);
2546         }
2547
2548         /* Create parent tag for buffers. */
2549         boundary = 0;
2550         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
2551                 boundary = BGE_DMA_BNDRY;
2552                 /*
2553                  * XXX
2554                  * watchdog timeout issue was observed on BCM5704 which
2555                  * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
2556                  * Limiting DMA address space to 32bits seems to address
2557                  * it.
2558                  */
2559                 if (sc->bge_flags & BGE_FLAG_PCIX)
2560                         lowaddr = BUS_SPACE_MAXADDR_32BIT;
2561         }
2562         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2563             1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL,
2564             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2565             0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
2566         if (error != 0) {
2567                 device_printf(sc->bge_dev,
2568                     "could not allocate buffer dma tag\n");
2569                 return (ENOMEM);
2570         }
2571         /* Create tag for Tx mbufs. */
2572         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2573                 txsegsz = BGE_TSOSEG_SZ;
2574                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2575         } else {
2576                 txsegsz = MCLBYTES;
2577                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2578         }
2579         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
2580             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2581             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2582             &sc->bge_cdata.bge_tx_mtag);
2583
2584         if (error) {
2585                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2586                 return (ENOMEM);
2587         }
2588
2589         /* Create tag for Rx mbufs. */
2590         if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
2591                 rxmaxsegsz = MJUM9BYTES;
2592         else
2593                 rxmaxsegsz = MCLBYTES;
2594         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
2595             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
2596             rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2597
2598         if (error) {
2599                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2600                 return (ENOMEM);
2601         }
2602
2603         /* Create DMA maps for RX buffers. */
2604         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2605             &sc->bge_cdata.bge_rx_std_sparemap);
2606         if (error) {
2607                 device_printf(sc->bge_dev,
2608                     "can't create spare DMA map for RX\n");
2609                 return (ENOMEM);
2610         }
2611         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2612                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2613                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2614                 if (error) {
2615                         device_printf(sc->bge_dev,
2616                             "can't create DMA map for RX\n");
2617                         return (ENOMEM);
2618                 }
2619         }
2620
2621         /* Create DMA maps for TX buffers. */
2622         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2623                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2624                             &sc->bge_cdata.bge_tx_dmamap[i]);
2625                 if (error) {
2626                         device_printf(sc->bge_dev,
2627                             "can't create DMA map for TX\n");
2628                         return (ENOMEM);
2629                 }
2630         }
2631
2632         /* Create tags for jumbo RX buffers. */
2633         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2634                 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
2635                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2636                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2637                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2638                 if (error) {
2639                         device_printf(sc->bge_dev,
2640                             "could not allocate jumbo dma tag\n");
2641                         return (ENOMEM);
2642                 }
2643                 /* Create DMA maps for jumbo RX buffers. */
2644                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2645                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2646                 if (error) {
2647                         device_printf(sc->bge_dev,
2648                             "can't create spare DMA map for jumbo RX\n");
2649                         return (ENOMEM);
2650                 }
2651                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2652                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2653                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2654                         if (error) {
2655                                 device_printf(sc->bge_dev,
2656                                     "can't create DMA map for jumbo RX\n");
2657                                 return (ENOMEM);
2658                         }
2659                 }
2660         }
2661
2662         return (0);
2663 }
2664
2665 /*
2666  * Return true if this device has more than one port.
2667  */
2668 static int
2669 bge_has_multiple_ports(struct bge_softc *sc)
2670 {
2671         device_t dev = sc->bge_dev;
2672         u_int b, d, f, fscan, s;
2673
2674         d = pci_get_domain(dev);
2675         b = pci_get_bus(dev);
2676         s = pci_get_slot(dev);
2677         f = pci_get_function(dev);
2678         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2679                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2680                         return (1);
2681         return (0);
2682 }
2683
2684 /*
2685  * Return true if MSI can be used with this device.
2686  */
2687 static int
2688 bge_can_use_msi(struct bge_softc *sc)
2689 {
2690         int can_use_msi = 0;
2691
2692         /* Disable MSI for polling(4). */
2693 #ifdef DEVICE_POLLING
2694         return (0);
2695 #endif
2696         switch (sc->bge_asicrev) {
2697         case BGE_ASICREV_BCM5714_A0:
2698         case BGE_ASICREV_BCM5714:
2699                 /*
2700                  * Apparently, MSI doesn't work when these chips are
2701                  * configured in single-port mode.
2702                  */
2703                 if (bge_has_multiple_ports(sc))
2704                         can_use_msi = 1;
2705                 break;
2706         case BGE_ASICREV_BCM5750:
2707                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2708                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2709                         can_use_msi = 1;
2710                 break;
2711         default:
2712                 if (BGE_IS_575X_PLUS(sc))
2713                         can_use_msi = 1;
2714         }
2715         return (can_use_msi);
2716 }
2717
2718 static int
2719 bge_attach(device_t dev)
2720 {
2721         struct ifnet *ifp;
2722         struct bge_softc *sc;
2723         uint32_t hwcfg = 0, misccfg;
2724         u_char eaddr[ETHER_ADDR_LEN];
2725         int capmask, error, f, msicount, phy_addr, reg, rid, trys;
2726
2727         sc = device_get_softc(dev);
2728         sc->bge_dev = dev;
2729
2730         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2731
2732         /*
2733          * Map control/status registers.
2734          */
2735         pci_enable_busmaster(dev);
2736
2737         rid = PCIR_BAR(0);
2738         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2739             RF_ACTIVE);
2740
2741         if (sc->bge_res == NULL) {
2742                 device_printf (sc->bge_dev, "couldn't map memory\n");
2743                 error = ENXIO;
2744                 goto fail;
2745         }
2746
2747         /* Save various chip information. */
2748         sc->bge_chipid =
2749             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2750             BGE_PCIMISCCTL_ASICREV_SHIFT;
2751         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2752                 /*
2753                  * Find the ASCI revision.  Different chips use different
2754                  * registers.
2755                  */
2756                 switch (pci_get_device(dev)) {
2757                 case BCOM_DEVICEID_BCM5717:
2758                 case BCOM_DEVICEID_BCM5718:
2759                 case BCOM_DEVICEID_BCM5719:
2760                         sc->bge_chipid = pci_read_config(dev,
2761                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2762                         break;
2763                 case BCOM_DEVICEID_BCM57761:
2764                 case BCOM_DEVICEID_BCM57765:
2765                 case BCOM_DEVICEID_BCM57781:
2766                 case BCOM_DEVICEID_BCM57785:
2767                 case BCOM_DEVICEID_BCM57791:
2768                 case BCOM_DEVICEID_BCM57795:
2769                         sc->bge_chipid = pci_read_config(dev,
2770                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2771                         break;
2772                 default:
2773                         sc->bge_chipid = pci_read_config(dev,
2774                             BGE_PCI_PRODID_ASICREV, 4);
2775                 }
2776         }
2777         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2778         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2779
2780         /* Set default PHY address. */
2781         phy_addr = 1;
2782          /*
2783           * PHY address mapping for various devices.
2784           *
2785           *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2786           * ---------+-------+-------+-------+-------+
2787           * BCM57XX  |   1   |   X   |   X   |   X   |
2788           * BCM5704  |   1   |   X   |   1   |   X   |
2789           * BCM5717  |   1   |   8   |   2   |   9   |
2790           * BCM5719  |   1   |   8   |   2   |   9   |
2791           *
2792           * Other addresses may respond but they are not
2793           * IEEE compliant PHYs and should be ignored.
2794           */
2795         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2796             sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2797                 f = pci_get_function(dev);
2798                 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2799                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2800                             BGE_SGDIGSTS_IS_SERDES)
2801                                 phy_addr = f + 8;
2802                         else
2803                                 phy_addr = f + 1;
2804                 } else {
2805                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2806                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2807                                 phy_addr = f + 8;
2808                         else
2809                                 phy_addr = f + 1;
2810                 }
2811         }
2812
2813         /*
2814          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2815          * 5705 A0 and A1 chips.
2816          */
2817         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2818             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2819             (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2820             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2821             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2822                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
2823
2824         if (bge_has_eaddr(sc))
2825                 sc->bge_flags |= BGE_FLAG_EADDR;
2826
2827         /* Save chipset family. */
2828         switch (sc->bge_asicrev) {
2829         case BGE_ASICREV_BCM5717:
2830         case BGE_ASICREV_BCM5719:
2831                 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
2832         case BGE_ASICREV_BCM57765:
2833                 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
2834                     BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
2835                     BGE_FLAG_JUMBO_FRAME;
2836                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2837                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2838                         /* Jumbo frame on BCM5719 A0 does not work. */
2839                         sc->bge_flags &= ~BGE_FLAG_JUMBO;
2840                 }
2841                 break;
2842         case BGE_ASICREV_BCM5755:
2843         case BGE_ASICREV_BCM5761:
2844         case BGE_ASICREV_BCM5784:
2845         case BGE_ASICREV_BCM5785:
2846         case BGE_ASICREV_BCM5787:
2847         case BGE_ASICREV_BCM57780:
2848                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2849                     BGE_FLAG_5705_PLUS;
2850                 break;
2851         case BGE_ASICREV_BCM5700:
2852         case BGE_ASICREV_BCM5701:
2853         case BGE_ASICREV_BCM5703:
2854         case BGE_ASICREV_BCM5704:
2855                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2856                 break;
2857         case BGE_ASICREV_BCM5714_A0:
2858         case BGE_ASICREV_BCM5780:
2859         case BGE_ASICREV_BCM5714:
2860                 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
2861                 /* FALLTHROUGH */
2862         case BGE_ASICREV_BCM5750:
2863         case BGE_ASICREV_BCM5752:
2864         case BGE_ASICREV_BCM5906:
2865                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2866                 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2867                         sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
2868                 /* FALLTHROUGH */
2869         case BGE_ASICREV_BCM5705:
2870                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2871                 break;
2872         }
2873
2874         /* Set various PHY bug flags. */
2875         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2876             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2877                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
2878         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2879             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2880                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2881         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2882                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2883         if (pci_get_subvendor(dev) == DELL_VENDORID)
2884                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2885         if ((BGE_IS_5705_PLUS(sc)) &&
2886             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2887             sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
2888             sc->bge_asicrev != BGE_ASICREV_BCM5719 &&
2889             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2890             sc->bge_asicrev != BGE_ASICREV_BCM57765 &&
2891             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2892                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2893                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2894                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2895                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2896                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2897                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2898                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2899                         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2900                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2901                 } else
2902                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2903         }
2904
2905         /* Identify the chips that use an CPMU. */
2906         if (BGE_IS_5717_PLUS(sc) ||
2907             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2908             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2909             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2910             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2911                 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
2912         if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
2913                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2914         else
2915                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2916         /* Enable auto polling for BCM570[0-5]. */
2917         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
2918                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2919
2920         /*
2921          * All controllers that are not 5755 or higher have 4GB
2922          * boundary DMA bug.
2923          * Whenever an address crosses a multiple of the 4GB boundary
2924          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2925          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2926          * state machine will lockup and cause the device to hang.
2927          */
2928         if (BGE_IS_5755_PLUS(sc) == 0)
2929                 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2930
2931         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2932         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2933                 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2934                     misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2935                         sc->bge_flags |= BGE_FLAG_5788;
2936         }
2937
2938         capmask = BMSR_DEFCAPMASK;
2939         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2940             (misccfg == 0x4000 || misccfg == 0x8000)) ||
2941             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2942             pci_get_vendor(dev) == BCOM_VENDORID &&
2943             (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
2944             pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
2945             pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
2946             (pci_get_vendor(dev) == BCOM_VENDORID &&
2947             (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
2948             pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
2949             pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
2950             pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
2951             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2952                 /* These chips are 10/100 only. */
2953                 capmask &= ~BMSR_EXTSTAT;
2954         }
2955
2956         /*
2957          * Some controllers seem to require a special firmware to use
2958          * TSO. But the firmware is not available to FreeBSD and Linux
2959          * claims that the TSO performed by the firmware is slower than
2960          * hardware based TSO. Moreover the firmware based TSO has one
2961          * known bug which can't handle TSO if ethernet header + IP/TCP
2962          * header is greater than 80 bytes. The workaround for the TSO
2963          * bug exist but it seems it's too expensive than not using
2964          * TSO at all. Some hardwares also have the TSO bug so limit
2965          * the TSO to the controllers that are not affected TSO issues
2966          * (e.g. 5755 or higher).
2967          */
2968         if (BGE_IS_5717_PLUS(sc)) {
2969                 /* BCM5717 requires different TSO configuration. */
2970                 sc->bge_flags |= BGE_FLAG_TSO3;
2971                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2972                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2973                         /* TSO on BCM5719 A0 does not work. */
2974                         sc->bge_flags &= ~BGE_FLAG_TSO3;
2975                 }
2976         } else if (BGE_IS_5755_PLUS(sc)) {
2977                 /*
2978                  * BCM5754 and BCM5787 shares the same ASIC id so
2979                  * explicit device id check is required.
2980                  * Due to unknown reason TSO does not work on BCM5755M.
2981                  */
2982                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2983                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2984                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
2985                         sc->bge_flags |= BGE_FLAG_TSO;
2986         }
2987
2988         /*
2989          * Check if this is a PCI-X or PCI Express device.
2990          */
2991         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
2992                 /*
2993                  * Found a PCI Express capabilities register, this
2994                  * must be a PCI Express device.
2995                  */
2996                 sc->bge_flags |= BGE_FLAG_PCIE;
2997                 sc->bge_expcap = reg;
2998                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2999                         pci_set_max_read_req(dev, 2048);
3000                 else if (pci_get_max_read_req(dev) != 4096)
3001                         pci_set_max_read_req(dev, 4096);
3002         } else {
3003                 /*
3004                  * Check if the device is in PCI-X Mode.
3005                  * (This bit is not valid on PCI Express controllers.)
3006                  */
3007                 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3008                         sc->bge_pcixcap = reg;
3009                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3010                     BGE_PCISTATE_PCI_BUSMODE) == 0)
3011                         sc->bge_flags |= BGE_FLAG_PCIX;
3012         }
3013
3014         /*
3015          * The 40bit DMA bug applies to the 5714/5715 controllers and is
3016          * not actually a MAC controller bug but an issue with the embedded
3017          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3018          */
3019         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3020                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3021         /*
3022          * Allocate the interrupt, using MSI if possible.  These devices
3023          * support 8 MSI messages, but only the first one is used in
3024          * normal operation.
3025          */
3026         rid = 0;
3027         if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3028                 sc->bge_msicap = reg;
3029                 if (bge_can_use_msi(sc)) {
3030                         msicount = pci_msi_count(dev);
3031                         if (msicount > 1)
3032                                 msicount = 1;
3033                 } else
3034                         msicount = 0;
3035                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
3036                         rid = 1;
3037                         sc->bge_flags |= BGE_FLAG_MSI;
3038                 }
3039         }
3040
3041         /*
3042          * All controllers except BCM5700 supports tagged status but
3043          * we use tagged status only for MSI case on BCM5717. Otherwise
3044          * MSI on BCM5717 does not work.
3045          */
3046 #ifndef DEVICE_POLLING
3047         if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3048                 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3049 #endif
3050
3051         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3052             RF_SHAREABLE | RF_ACTIVE);
3053
3054         if (sc->bge_irq == NULL) {
3055                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3056                 error = ENXIO;
3057                 goto fail;
3058         }
3059
3060         device_printf(dev,
3061             "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
3062             sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
3063             (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
3064             ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
3065
3066         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3067
3068         /* Try to reset the chip. */
3069         if (bge_reset(sc)) {
3070                 device_printf(sc->bge_dev, "chip reset failed\n");
3071                 error = ENXIO;
3072                 goto fail;
3073         }
3074
3075         sc->bge_asf_mode = 0;
3076         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
3077             == BGE_MAGIC_NUMBER)) {
3078                 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
3079                     & BGE_HWCFG_ASF) {
3080                         sc->bge_asf_mode |= ASF_ENABLE;
3081                         sc->bge_asf_mode |= ASF_STACKUP;
3082                         if (BGE_IS_575X_PLUS(sc))
3083                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3084                 }
3085         }
3086
3087         /* Try to reset the chip again the nice way. */
3088         bge_stop_fw(sc);
3089         bge_sig_pre_reset(sc, BGE_RESET_STOP);
3090         if (bge_reset(sc)) {
3091                 device_printf(sc->bge_dev, "chip reset failed\n");
3092                 error = ENXIO;
3093                 goto fail;
3094         }
3095
3096         bge_sig_legacy(sc, BGE_RESET_STOP);
3097         bge_sig_post_reset(sc, BGE_RESET_STOP);
3098
3099         if (bge_chipinit(sc)) {
3100                 device_printf(sc->bge_dev, "chip initialization failed\n");
3101                 error = ENXIO;
3102                 goto fail;
3103         }
3104
3105         error = bge_get_eaddr(sc, eaddr);
3106         if (error) {
3107                 device_printf(sc->bge_dev,
3108                     "failed to read station address\n");
3109                 error = ENXIO;
3110                 goto fail;
3111         }
3112
3113         /* 5705 limits RX return ring to 512 entries. */
3114         if (BGE_IS_5717_PLUS(sc))
3115                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3116         else if (BGE_IS_5705_PLUS(sc))
3117                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3118         else
3119                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3120
3121         if (bge_dma_alloc(sc)) {
3122                 device_printf(sc->bge_dev,
3123                     "failed to allocate DMA resources\n");
3124                 error = ENXIO;
3125                 goto fail;
3126         }
3127
3128         bge_add_sysctls(sc);
3129
3130         /* Set default tuneable values. */
3131         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3132         sc->bge_rx_coal_ticks = 150;
3133         sc->bge_tx_coal_ticks = 150;
3134         sc->bge_rx_max_coal_bds = 10;
3135         sc->bge_tx_max_coal_bds = 10;
3136
3137         /* Initialize checksum features to use. */
3138         sc->bge_csum_features = BGE_CSUM_FEATURES;
3139         if (sc->bge_forced_udpcsum != 0)
3140                 sc->bge_csum_features |= CSUM_UDP;
3141
3142         /* Set up ifnet structure */
3143         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3144         if (ifp == NULL) {
3145                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3146                 error = ENXIO;
3147                 goto fail;
3148         }
3149         ifp->if_softc = sc;
3150         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3151         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3152         ifp->if_ioctl = bge_ioctl;
3153         ifp->if_start = bge_start;
3154         ifp->if_init = bge_init;
3155         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3156         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3157         IFQ_SET_READY(&ifp->if_snd);
3158         ifp->if_hwassist = sc->bge_csum_features;
3159         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3160             IFCAP_VLAN_MTU;
3161         if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3162                 ifp->if_hwassist |= CSUM_TSO;
3163                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3164         }
3165 #ifdef IFCAP_VLAN_HWCSUM
3166         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3167 #endif
3168         ifp->if_capenable = ifp->if_capabilities;
3169 #ifdef DEVICE_POLLING
3170         ifp->if_capabilities |= IFCAP_POLLING;
3171 #endif
3172
3173         /*
3174          * 5700 B0 chips do not support checksumming correctly due
3175          * to hardware bugs.
3176          */
3177         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3178                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
3179                 ifp->if_capenable &= ~IFCAP_HWCSUM;
3180                 ifp->if_hwassist = 0;
3181         }
3182
3183         /*
3184          * Figure out what sort of media we have by checking the
3185          * hardware config word in the first 32k of NIC internal memory,
3186          * or fall back to examining the EEPROM if necessary.
3187          * Note: on some BCM5700 cards, this value appears to be unset.
3188          * If that's the case, we have to rely on identifying the NIC
3189          * by its PCI subsystem ID, as we do below for the SysKonnect
3190          * SK-9D41.
3191          */
3192         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
3193                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
3194         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3195             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3196                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3197                     sizeof(hwcfg))) {
3198                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
3199                         error = ENXIO;
3200                         goto fail;
3201                 }
3202                 hwcfg = ntohl(hwcfg);
3203         }
3204
3205         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3206         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3207             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3208                 if (BGE_IS_5714_FAMILY(sc))
3209                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
3210                 else
3211                         sc->bge_flags |= BGE_FLAG_TBI;
3212         }
3213
3214         if (sc->bge_flags & BGE_FLAG_TBI) {
3215                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3216                     bge_ifmedia_sts);
3217                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3218                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3219                     0, NULL);
3220                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3221                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3222                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3223         } else {
3224                 /*
3225                  * Do transceiver setup and tell the firmware the
3226                  * driver is down so we can try to get access the
3227                  * probe if ASF is running.  Retry a couple of times
3228                  * if we get a conflict with the ASF firmware accessing
3229                  * the PHY.
3230                  */
3231                 trys = 0;
3232                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3233 again:
3234                 bge_asf_driver_up(sc);
3235
3236                 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3237                     bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY,
3238                     MIIF_DOPAUSE);
3239                 if (error != 0) {
3240                         if (trys++ < 4) {
3241                                 device_printf(sc->bge_dev, "Try again\n");
3242                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
3243                                     BMCR_RESET);
3244                                 goto again;
3245                         }
3246                         device_printf(sc->bge_dev, "attaching PHYs failed\n");
3247                         goto fail;
3248                 }
3249
3250                 /*
3251                  * Now tell the firmware we are going up after probing the PHY
3252                  */
3253                 if (sc->bge_asf_mode & ASF_STACKUP)
3254                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3255         }
3256
3257         /*
3258          * When using the BCM5701 in PCI-X mode, data corruption has
3259          * been observed in the first few bytes of some received packets.
3260          * Aligning the packet buffer in memory eliminates the corruption.
3261          * Unfortunately, this misaligns the packet payloads.  On platforms
3262          * which do not support unaligned accesses, we will realign the
3263          * payloads by copying the received packets.
3264          */
3265         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3266             sc->bge_flags & BGE_FLAG_PCIX)
3267                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3268
3269         /*
3270          * Call MI attach routine.
3271          */
3272         ether_ifattach(ifp, eaddr);
3273         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3274
3275         /* Tell upper layer we support long frames. */
3276         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3277
3278         /*
3279          * Hookup IRQ last.
3280          */
3281         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3282                 /* Take advantage of single-shot MSI. */
3283                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3284                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3285                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3286                     taskqueue_thread_enqueue, &sc->bge_tq);
3287                 if (sc->bge_tq == NULL) {
3288                         device_printf(dev, "could not create taskqueue.\n");
3289                         ether_ifdetach(ifp);
3290                         error = ENXIO;
3291                         goto fail;
3292                 }
3293                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
3294                     device_get_nameunit(sc->bge_dev));
3295                 error = bus_setup_intr(dev, sc->bge_irq,
3296                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3297                     &sc->bge_intrhand);
3298                 if (error)
3299                         ether_ifdetach(ifp);
3300         } else
3301                 error = bus_setup_intr(dev, sc->bge_irq,
3302                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3303                     &sc->bge_intrhand);
3304
3305         if (error) {
3306                 bge_detach(dev);
3307                 device_printf(sc->bge_dev, "couldn't set up irq\n");
3308         }
3309
3310         return (0);
3311
3312 fail:
3313         bge_release_resources(sc);
3314
3315         return (error);
3316 }
3317
3318 static int
3319 bge_detach(device_t dev)
3320 {
3321         struct bge_softc *sc;
3322         struct ifnet *ifp;
3323
3324         sc = device_get_softc(dev);
3325         ifp = sc->bge_ifp;
3326
3327 #ifdef DEVICE_POLLING
3328         if (ifp->if_capenable & IFCAP_POLLING)
3329                 ether_poll_deregister(ifp);
3330 #endif
3331
3332         BGE_LOCK(sc);
3333         bge_stop(sc);
3334         bge_reset(sc);
3335         BGE_UNLOCK(sc);
3336
3337         callout_drain(&sc->bge_stat_ch);
3338
3339         if (sc->bge_tq)
3340                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3341         ether_ifdetach(ifp);
3342
3343         if (sc->bge_flags & BGE_FLAG_TBI) {
3344                 ifmedia_removeall(&sc->bge_ifmedia);
3345         } else {
3346                 bus_generic_detach(dev);
3347                 device_delete_child(dev, sc->bge_miibus);
3348         }
3349
3350         bge_release_resources(sc);
3351
3352         return (0);
3353 }
3354
3355 static void
3356 bge_release_resources(struct bge_softc *sc)
3357 {
3358         device_t dev;
3359
3360         dev = sc->bge_dev;
3361
3362         if (sc->bge_tq != NULL)
3363                 taskqueue_free(sc->bge_tq);
3364
3365         if (sc->bge_intrhand != NULL)
3366                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3367
3368         if (sc->bge_irq != NULL)
3369                 bus_release_resource(dev, SYS_RES_IRQ,
3370                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3371
3372         if (sc->bge_flags & BGE_FLAG_MSI)
3373                 pci_release_msi(dev);
3374
3375         if (sc->bge_res != NULL)
3376                 bus_release_resource(dev, SYS_RES_MEMORY,
3377                     PCIR_BAR(0), sc->bge_res);
3378
3379         if (sc->bge_ifp != NULL)
3380                 if_free(sc->bge_ifp);
3381
3382         bge_dma_free(sc);
3383
3384         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3385                 BGE_LOCK_DESTROY(sc);
3386 }
3387
3388 static int
3389 bge_reset(struct bge_softc *sc)
3390 {
3391         device_t dev;
3392         uint32_t cachesize, command, pcistate, reset, val;
3393         void (*write_op)(struct bge_softc *, int, int);
3394         uint16_t devctl;
3395         int i;
3396
3397         dev = sc->bge_dev;
3398
3399         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3400             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3401                 if (sc->bge_flags & BGE_FLAG_PCIE)
3402                         write_op = bge_writemem_direct;
3403                 else
3404                         write_op = bge_writemem_ind;
3405         } else
3406                 write_op = bge_writereg_ind;
3407
3408         /* Save some important PCI state. */
3409         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3410         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3411         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3412
3413         pci_write_config(dev, BGE_PCI_MISC_CTL,
3414             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3415             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3416
3417         /* Disable fastboot on controllers that support it. */
3418         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3419             BGE_IS_5755_PLUS(sc)) {
3420                 if (bootverbose)
3421                         device_printf(dev, "Disabling fastboot\n");
3422                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3423         }
3424
3425         /*
3426          * Write the magic number to SRAM at offset 0xB50.
3427          * When firmware finishes its initialization it will
3428          * write ~BGE_MAGIC_NUMBER to the same location.
3429          */
3430         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3431
3432         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3433
3434         /* XXX: Broadcom Linux driver. */
3435         if (sc->bge_flags & BGE_FLAG_PCIE) {
3436                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3437                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3438                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3439                         /* Prevent PCIE link training during global reset */
3440                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3441                         reset |= 1 << 29;
3442                 }
3443         }
3444
3445         /*
3446          * Set GPHY Power Down Override to leave GPHY
3447          * powered up in D0 uninitialized.
3448          */
3449         if (BGE_IS_5705_PLUS(sc))
3450                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
3451
3452         /* Issue global reset */
3453         write_op(sc, BGE_MISC_CFG, reset);
3454
3455         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3456                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3457                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3458                     val | BGE_VCPU_STATUS_DRV_RESET);
3459                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3460                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3461                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3462         }
3463
3464         DELAY(1000);
3465
3466         /* XXX: Broadcom Linux driver. */
3467         if (sc->bge_flags & BGE_FLAG_PCIE) {
3468                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3469                         DELAY(500000); /* wait for link training to complete */
3470                         val = pci_read_config(dev, 0xC4, 4);
3471                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3472                 }
3473                 devctl = pci_read_config(dev,
3474                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3475                 /* Clear enable no snoop and disable relaxed ordering. */
3476                 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3477                     PCIM_EXP_CTL_NOSNOOP_ENABLE);
3478                 /* Set PCIE max payload size to 128. */
3479                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3480                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3481                     devctl, 2);
3482                 /* Clear error status. */
3483                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3484                     PCIM_EXP_STA_CORRECTABLE_ERROR |
3485                     PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3486                     PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3487         }
3488
3489         /* Reset some of the PCI state that got zapped by reset. */
3490         pci_write_config(dev, BGE_PCI_MISC_CTL,
3491             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3492             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3493         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3494         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3495         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3496         /*
3497          * Disable PCI-X relaxed ordering to ensure status block update
3498          * comes first then packet buffer DMA. Otherwise driver may
3499          * read stale status block.
3500          */
3501         if (sc->bge_flags & BGE_FLAG_PCIX) {
3502                 devctl = pci_read_config(dev,
3503                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
3504                 devctl &= ~PCIXM_COMMAND_ERO;
3505                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
3506                         devctl &= ~PCIXM_COMMAND_MAX_READ;
3507                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3508                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3509                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
3510                             PCIXM_COMMAND_MAX_READ);
3511                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3512                 }
3513                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
3514                     devctl, 2);
3515         }
3516         /* Re-enable MSI, if necessary, and enable the memory arbiter. */
3517         if (BGE_IS_5714_FAMILY(sc)) {
3518                 /* This chip disables MSI on reset. */
3519                 if (sc->bge_flags & BGE_FLAG_MSI) {
3520                         val = pci_read_config(dev,
3521                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3522                         pci_write_config(dev,
3523                             sc->bge_msicap + PCIR_MSI_CTRL,
3524                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3525                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3526                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3527                             val | BGE_MSIMODE_ENABLE);
3528                 }
3529                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3530                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3531         } else
3532                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3533
3534         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3535                 for (i = 0; i < BGE_TIMEOUT; i++) {
3536                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3537                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3538                                 break;
3539                         DELAY(100);
3540                 }
3541                 if (i == BGE_TIMEOUT) {
3542                         device_printf(dev, "reset timed out\n");
3543                         return (1);
3544                 }
3545         } else {
3546                 /*
3547                  * Poll until we see the 1's complement of the magic number.
3548                  * This indicates that the firmware initialization is complete.
3549                  * We expect this to fail if no chip containing the Ethernet
3550                  * address is fitted though.
3551                  */
3552                 for (i = 0; i < BGE_TIMEOUT; i++) {
3553                         DELAY(10);
3554                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3555                         if (val == ~BGE_MAGIC_NUMBER)
3556                                 break;
3557                 }
3558
3559                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3560                         device_printf(dev,
3561                             "firmware handshake timed out, found 0x%08x\n",
3562                             val);
3563                 /* BCM57765 A0 needs additional time before accessing. */
3564                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
3565                         DELAY(10 * 1000);       /* XXX */
3566         }
3567
3568         /*
3569          * XXX Wait for the value of the PCISTATE register to
3570          * return to its original pre-reset state. This is a
3571          * fairly good indicator of reset completion. If we don't
3572          * wait for the reset to fully complete, trying to read
3573          * from the device's non-PCI registers may yield garbage
3574          * results.
3575          */
3576         for (i = 0; i < BGE_TIMEOUT; i++) {
3577                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3578                         break;
3579                 DELAY(10);
3580         }
3581
3582         /* Fix up byte swapping. */
3583         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3584             BGE_MODECTL_BYTESWAP_DATA);
3585
3586         /* Tell the ASF firmware we are up */
3587         if (sc->bge_asf_mode & ASF_STACKUP)
3588                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3589
3590         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3591
3592         /*
3593          * The 5704 in TBI mode apparently needs some special
3594          * adjustment to insure the SERDES drive level is set
3595          * to 1.2V.
3596          */
3597         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3598             sc->bge_flags & BGE_FLAG_TBI) {
3599                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3600                 val = (val & ~0xFFF) | 0x880;
3601                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3602         }
3603
3604         /* XXX: Broadcom Linux driver. */
3605         if (sc->bge_flags & BGE_FLAG_PCIE &&
3606             !BGE_IS_5717_PLUS(sc) &&
3607             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3608             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3609                 /* Enable Data FIFO protection. */
3610                 val = CSR_READ_4(sc, 0x7C00);
3611                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3612         }
3613         DELAY(10000);
3614
3615         return (0);
3616 }
3617
3618 static __inline void
3619 bge_rxreuse_std(struct bge_softc *sc, int i)
3620 {
3621         struct bge_rx_bd *r;
3622
3623         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
3624         r->bge_flags = BGE_RXBDFLAG_END;
3625         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
3626         r->bge_idx = i;
3627         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3628 }
3629
3630 static __inline void
3631 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
3632 {
3633         struct bge_extrx_bd *r;
3634
3635         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
3636         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
3637         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
3638         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
3639         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
3640         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
3641         r->bge_idx = i;
3642         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3643 }
3644
3645 /*
3646  * Frame reception handling. This is called if there's a frame
3647  * on the receive return list.
3648  *
3649  * Note: we have to be able to handle two possibilities here:
3650  * 1) the frame is from the jumbo receive ring
3651  * 2) the frame is from the standard receive ring
3652  */
3653
3654 static int
3655 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3656 {
3657         struct ifnet *ifp;
3658         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3659         uint16_t rx_cons;
3660
3661         rx_cons = sc->bge_rx_saved_considx;
3662
3663         /* Nothing to do. */
3664         if (rx_cons == rx_prod)
3665                 return (rx_npkts);
3666
3667         ifp = sc->bge_ifp;
3668
3669         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3670             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3671         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3672             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3673         if (BGE_IS_JUMBO_CAPABLE(sc) &&
3674             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3675             (MCLBYTES - ETHER_ALIGN))
3676                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3677                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3678
3679         while (rx_cons != rx_prod) {
3680                 struct bge_rx_bd        *cur_rx;
3681                 uint32_t                rxidx;
3682                 struct mbuf             *m = NULL;
3683                 uint16_t                vlan_tag = 0;
3684                 int                     have_tag = 0;
3685
3686 #ifdef DEVICE_POLLING
3687                 if (ifp->if_capenable & IFCAP_POLLING) {
3688                         if (sc->rxcycles <= 0)
3689                                 break;
3690                         sc->rxcycles--;
3691                 }
3692 #endif
3693
3694                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3695
3696                 rxidx = cur_rx->bge_idx;
3697                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3698
3699                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3700                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3701                         have_tag = 1;
3702                         vlan_tag = cur_rx->bge_vlan_tag;
3703                 }
3704
3705                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3706                         jumbocnt++;
3707                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3708                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3709                                 bge_rxreuse_jumbo(sc, rxidx);
3710                                 continue;
3711                         }
3712                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3713                                 bge_rxreuse_jumbo(sc, rxidx);
3714                                 ifp->if_iqdrops++;
3715                                 continue;
3716                         }
3717                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3718                 } else {
3719                         stdcnt++;
3720                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3721                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3722                                 bge_rxreuse_std(sc, rxidx);
3723                                 continue;
3724                         }
3725                         if (bge_newbuf_std(sc, rxidx) != 0) {
3726                                 bge_rxreuse_std(sc, rxidx);
3727                                 ifp->if_iqdrops++;
3728                                 continue;
3729                         }
3730                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3731                 }
3732
3733                 ifp->if_ipackets++;
3734 #ifndef __NO_STRICT_ALIGNMENT
3735                 /*
3736                  * For architectures with strict alignment we must make sure
3737                  * the payload is aligned.
3738                  */
3739                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3740                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3741                             cur_rx->bge_len);
3742                         m->m_data += ETHER_ALIGN;
3743                 }
3744 #endif
3745                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3746                 m->m_pkthdr.rcvif = ifp;
3747
3748                 if (ifp->if_capenable & IFCAP_RXCSUM)
3749                         bge_rxcsum(sc, cur_rx, m);
3750
3751                 /*
3752                  * If we received a packet with a vlan tag,
3753                  * attach that information to the packet.
3754                  */
3755                 if (have_tag) {
3756                         m->m_pkthdr.ether_vtag = vlan_tag;
3757                         m->m_flags |= M_VLANTAG;
3758                 }
3759
3760                 if (holdlck != 0) {
3761                         BGE_UNLOCK(sc);
3762                         (*ifp->if_input)(ifp, m);
3763                         BGE_LOCK(sc);
3764                 } else
3765                         (*ifp->if_input)(ifp, m);
3766                 rx_npkts++;
3767
3768                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3769                         return (rx_npkts);
3770         }
3771
3772         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3773             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3774         if (stdcnt > 0)
3775                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3776                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3777
3778         if (jumbocnt > 0)
3779                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3780                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3781
3782         sc->bge_rx_saved_considx = rx_cons;
3783         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3784         if (stdcnt)
3785                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
3786                     BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
3787         if (jumbocnt)
3788                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
3789                     BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
3790 #ifdef notyet
3791         /*
3792          * This register wraps very quickly under heavy packet drops.
3793          * If you need correct statistics, you can enable this check.
3794          */
3795         if (BGE_IS_5705_PLUS(sc))
3796                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3797 #endif
3798         return (rx_npkts);
3799 }
3800
3801 static void
3802 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
3803 {
3804
3805         if (BGE_IS_5717_PLUS(sc)) {
3806                 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
3807                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3808                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3809                                 if ((cur_rx->bge_error_flag &
3810                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
3811                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3812                         }
3813                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
3814                                 m->m_pkthdr.csum_data =
3815                                     cur_rx->bge_tcp_udp_csum;
3816                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3817                                     CSUM_PSEUDO_HDR;
3818                         }
3819                 }
3820         } else {
3821                 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3822                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3823                         if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3824                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3825                 }
3826                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3827                     m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3828                         m->m_pkthdr.csum_data =
3829                             cur_rx->bge_tcp_udp_csum;
3830                         m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3831                             CSUM_PSEUDO_HDR;
3832                 }
3833         }
3834 }
3835
3836 static void
3837 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3838 {
3839         struct bge_tx_bd *cur_tx;
3840         struct ifnet *ifp;
3841
3842         BGE_LOCK_ASSERT(sc);
3843
3844         /* Nothing to do. */
3845         if (sc->bge_tx_saved_considx == tx_cons)
3846                 return;
3847
3848         ifp = sc->bge_ifp;
3849
3850         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3851             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3852         /*
3853          * Go through our tx ring and free mbufs for those
3854          * frames that have been sent.
3855          */
3856         while (sc->bge_tx_saved_considx != tx_cons) {
3857                 uint32_t                idx;
3858
3859                 idx = sc->bge_tx_saved_considx;
3860                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3861                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3862                         ifp->if_opackets++;
3863                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3864                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3865                             sc->bge_cdata.bge_tx_dmamap[idx],
3866                             BUS_DMASYNC_POSTWRITE);
3867                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3868                             sc->bge_cdata.bge_tx_dmamap[idx]);
3869                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3870                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3871                 }
3872                 sc->bge_txcnt--;
3873                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3874         }
3875
3876         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3877         if (sc->bge_txcnt == 0)
3878                 sc->bge_timer = 0;
3879 }
3880
3881 #ifdef DEVICE_POLLING
3882 static int
3883 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3884 {
3885         struct bge_softc *sc = ifp->if_softc;
3886         uint16_t rx_prod, tx_cons;
3887         uint32_t statusword;
3888         int rx_npkts = 0;
3889
3890         BGE_LOCK(sc);
3891         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3892                 BGE_UNLOCK(sc);
3893                 return (rx_npkts);
3894         }
3895
3896         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3897             sc->bge_cdata.bge_status_map,
3898             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3899         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3900         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3901
3902         statusword = sc->bge_ldata.bge_status_block->bge_status;
3903         sc->bge_ldata.bge_status_block->bge_status = 0;
3904
3905         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3906             sc->bge_cdata.bge_status_map,
3907             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3908
3909         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3910         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3911                 sc->bge_link_evt++;
3912
3913         if (cmd == POLL_AND_CHECK_STATUS)
3914                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3915                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3916                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3917                         bge_link_upd(sc);
3918
3919         sc->rxcycles = count;
3920         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3921         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3922                 BGE_UNLOCK(sc);
3923                 return (rx_npkts);
3924         }
3925         bge_txeof(sc, tx_cons);
3926         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3927                 bge_start_locked(ifp);
3928
3929         BGE_UNLOCK(sc);
3930         return (rx_npkts);
3931 }
3932 #endif /* DEVICE_POLLING */
3933
3934 static int
3935 bge_msi_intr(void *arg)
3936 {
3937         struct bge_softc *sc;
3938
3939         sc = (struct bge_softc *)arg;
3940         /*
3941          * This interrupt is not shared and controller already
3942          * disabled further interrupt.
3943          */
3944         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3945         return (FILTER_HANDLED);
3946 }
3947
3948 static void
3949 bge_intr_task(void *arg, int pending)
3950 {
3951         struct bge_softc *sc;
3952         struct ifnet *ifp;
3953         uint32_t status, status_tag;
3954         uint16_t rx_prod, tx_cons;
3955
3956         sc = (struct bge_softc *)arg;
3957         ifp = sc->bge_ifp;
3958
3959         BGE_LOCK(sc);
3960         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3961                 BGE_UNLOCK(sc);
3962                 return;
3963         }
3964
3965         /* Get updated status block. */
3966         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3967             sc->bge_cdata.bge_status_map,
3968             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3969
3970         /* Save producer/consumer indexess. */
3971         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3972         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3973         status = sc->bge_ldata.bge_status_block->bge_status;
3974         status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
3975         sc->bge_ldata.bge_status_block->bge_status = 0;
3976         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3977             sc->bge_cdata.bge_status_map,
3978             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3979         if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
3980                 status_tag = 0;
3981
3982         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
3983                 bge_link_upd(sc);
3984
3985         /* Let controller work. */
3986         bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
3987
3988         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3989             sc->bge_rx_saved_considx != rx_prod) {
3990                 /* Check RX return ring producer/consumer. */
3991                 BGE_UNLOCK(sc);
3992                 bge_rxeof(sc, rx_prod, 0);
3993                 BGE_LOCK(sc);
3994         }
3995         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3996                 /* Check TX ring producer/consumer. */
3997                 bge_txeof(sc, tx_cons);
3998                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3999                         bge_start_locked(ifp);
4000         }
4001         BGE_UNLOCK(sc);
4002 }
4003
4004 static void
4005 bge_intr(void *xsc)
4006 {
4007         struct bge_softc *sc;
4008         struct ifnet *ifp;
4009         uint32_t statusword;
4010         uint16_t rx_prod, tx_cons;
4011
4012         sc = xsc;
4013
4014         BGE_LOCK(sc);
4015
4016         ifp = sc->bge_ifp;
4017
4018 #ifdef DEVICE_POLLING
4019         if (ifp->if_capenable & IFCAP_POLLING) {
4020                 BGE_UNLOCK(sc);
4021                 return;
4022         }
4023 #endif
4024
4025         /*
4026          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4027          * disable interrupts by writing nonzero like we used to, since with
4028          * our current organization this just gives complications and
4029          * pessimizations for re-enabling interrupts.  We used to have races
4030          * instead of the necessary complications.  Disabling interrupts
4031          * would just reduce the chance of a status update while we are
4032          * running (by switching to the interrupt-mode coalescence
4033          * parameters), but this chance is already very low so it is more
4034          * efficient to get another interrupt than prevent it.
4035          *
4036          * We do the ack first to ensure another interrupt if there is a
4037          * status update after the ack.  We don't check for the status
4038          * changing later because it is more efficient to get another
4039          * interrupt than prevent it, not quite as above (not checking is
4040          * a smaller optimization than not toggling the interrupt enable,
4041          * since checking doesn't involve PCI accesses and toggling require
4042          * the status check).  So toggling would probably be a pessimization
4043          * even with MSI.  It would only be needed for using a task queue.
4044          */
4045         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4046
4047         /*
4048          * Do the mandatory PCI flush as well as get the link status.
4049          */
4050         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4051
4052         /* Make sure the descriptor ring indexes are coherent. */
4053         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4054             sc->bge_cdata.bge_status_map,
4055             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4056         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4057         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4058         sc->bge_ldata.bge_status_block->bge_status = 0;
4059         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4060             sc->bge_cdata.bge_status_map,
4061             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4062
4063         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4064             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4065             statusword || sc->bge_link_evt)
4066                 bge_link_upd(sc);
4067
4068         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4069                 /* Check RX return ring producer/consumer. */
4070                 bge_rxeof(sc, rx_prod, 1);
4071         }
4072
4073         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4074                 /* Check TX ring producer/consumer. */
4075                 bge_txeof(sc, tx_cons);
4076         }
4077
4078         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4079             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4080                 bge_start_locked(ifp);
4081
4082         BGE_UNLOCK(sc);
4083 }
4084
4085 static void
4086 bge_asf_driver_up(struct bge_softc *sc)
4087 {
4088         if (sc->bge_asf_mode & ASF_STACKUP) {
4089                 /* Send ASF heartbeat aprox. every 2s */
4090                 if (sc->bge_asf_count)
4091                         sc->bge_asf_count --;
4092                 else {
4093                         sc->bge_asf_count = 2;
4094                         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
4095                             BGE_FW_DRV_ALIVE);
4096                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
4097                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
4098                         CSR_WRITE_4(sc, BGE_CPU_EVENT,
4099                             CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
4100                 }
4101         }
4102 }
4103
4104 static void
4105 bge_tick(void *xsc)
4106 {
4107         struct bge_softc *sc = xsc;
4108         struct mii_data *mii = NULL;
4109
4110         BGE_LOCK_ASSERT(sc);
4111
4112         /* Synchronize with possible callout reset/stop. */
4113         if (callout_pending(&sc->bge_stat_ch) ||
4114             !callout_active(&sc->bge_stat_ch))
4115                 return;
4116
4117         if (BGE_IS_5705_PLUS(sc))
4118                 bge_stats_update_regs(sc);
4119         else
4120                 bge_stats_update(sc);
4121
4122         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4123                 mii = device_get_softc(sc->bge_miibus);
4124                 /*
4125                  * Do not touch PHY if we have link up. This could break
4126                  * IPMI/ASF mode or produce extra input errors
4127                  * (extra errors was reported for bcm5701 & bcm5704).
4128                  */
4129                 if (!sc->bge_link)
4130                         mii_tick(mii);
4131         } else {
4132                 /*
4133                  * Since in TBI mode auto-polling can't be used we should poll
4134                  * link status manually. Here we register pending link event
4135                  * and trigger interrupt.
4136                  */
4137 #ifdef DEVICE_POLLING
4138                 /* In polling mode we poll link state in bge_poll(). */
4139                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4140 #endif
4141                 {
4142                 sc->bge_link_evt++;
4143                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4144                     sc->bge_flags & BGE_FLAG_5788)
4145                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4146                 else
4147                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4148                 }
4149         }
4150
4151         bge_asf_driver_up(sc);
4152         bge_watchdog(sc);
4153
4154         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4155 }
4156
4157 static void
4158 bge_stats_update_regs(struct bge_softc *sc)
4159 {
4160         struct ifnet *ifp;
4161         struct bge_mac_stats *stats;
4162
4163         ifp = sc->bge_ifp;
4164         stats = &sc->bge_mac_stats;
4165
4166         stats->ifHCOutOctets +=
4167             CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4168         stats->etherStatsCollisions +=
4169             CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4170         stats->outXonSent +=
4171             CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4172         stats->outXoffSent +=
4173             CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4174         stats->dot3StatsInternalMacTransmitErrors +=
4175             CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4176         stats->dot3StatsSingleCollisionFrames +=
4177             CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4178         stats->dot3StatsMultipleCollisionFrames +=
4179             CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4180         stats->dot3StatsDeferredTransmissions +=
4181             CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4182         stats->dot3StatsExcessiveCollisions +=
4183             CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4184         stats->dot3StatsLateCollisions +=
4185             CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4186         stats->ifHCOutUcastPkts +=
4187             CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4188         stats->ifHCOutMulticastPkts +=
4189             CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4190         stats->ifHCOutBroadcastPkts +=
4191             CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4192
4193         stats->ifHCInOctets +=
4194             CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4195         stats->etherStatsFragments +=
4196             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4197         stats->ifHCInUcastPkts +=
4198             CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4199         stats->ifHCInMulticastPkts +=
4200             CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4201         stats->ifHCInBroadcastPkts +=
4202             CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4203         stats->dot3StatsFCSErrors +=
4204             CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4205         stats->dot3StatsAlignmentErrors +=
4206             CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4207         stats->xonPauseFramesReceived +=
4208             CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4209         stats->xoffPauseFramesReceived +=
4210             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4211         stats->macControlFramesReceived +=
4212             CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4213         stats->xoffStateEntered +=
4214             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4215         stats->dot3StatsFramesTooLong +=
4216             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4217         stats->etherStatsJabbers +=
4218             CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4219         stats->etherStatsUndersizePkts +=
4220             CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4221
4222         stats->FramesDroppedDueToFilters +=
4223             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4224         stats->DmaWriteQueueFull +=
4225             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4226         stats->DmaWriteHighPriQueueFull +=
4227             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4228         stats->NoMoreRxBDs +=
4229             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4230         stats->InputDiscards +=
4231             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4232         stats->InputErrors +=
4233             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4234         stats->RecvThresholdHit +=
4235             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4236
4237         ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4238         ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4239             stats->InputErrors);
4240 }
4241
4242 static void
4243 bge_stats_clear_regs(struct bge_softc *sc)
4244 {
4245
4246         CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4247         CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4248         CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4249         CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4250         CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4251         CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4252         CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4253         CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4254         CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4255         CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4256         CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4257         CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4258         CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4259
4260         CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4261         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4262         CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4263         CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4264         CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4265         CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4266         CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4267         CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4268         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4269         CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4270         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4271         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4272         CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4273         CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4274
4275         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4276         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4277         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4278         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4279         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4280         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4281         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4282 }
4283
4284 static void
4285 bge_stats_update(struct bge_softc *sc)
4286 {
4287         struct ifnet *ifp;
4288         bus_size_t stats;
4289         uint32_t cnt;   /* current register value */
4290
4291         ifp = sc->bge_ifp;
4292
4293         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4294
4295 #define READ_STAT(sc, stats, stat) \
4296         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4297
4298         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4299         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
4300         sc->bge_tx_collisions = cnt;
4301
4302         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4303         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
4304         sc->bge_rx_discards = cnt;
4305
4306         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4307         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
4308         sc->bge_tx_discards = cnt;
4309
4310 #undef  READ_STAT
4311 }
4312
4313 /*
4314  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
4315  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
4316  * but when such padded frames employ the bge IP/TCP checksum offload,
4317  * the hardware checksum assist gives incorrect results (possibly
4318  * from incorporating its own padding into the UDP/TCP checksum; who knows).
4319  * If we pad such runts with zeros, the onboard checksum comes out correct.
4320  */
4321 static __inline int
4322 bge_cksum_pad(struct mbuf *m)
4323 {
4324         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
4325         struct mbuf *last;
4326
4327         /* If there's only the packet-header and we can pad there, use it. */
4328         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
4329             M_TRAILINGSPACE(m) >= padlen) {
4330                 last = m;
4331         } else {
4332                 /*
4333                  * Walk packet chain to find last mbuf. We will either
4334                  * pad there, or append a new mbuf and pad it.
4335                  */
4336                 for (last = m; last->m_next != NULL; last = last->m_next);
4337                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
4338                         /* Allocate new empty mbuf, pad it. Compact later. */
4339                         struct mbuf *n;
4340
4341                         MGET(n, M_DONTWAIT, MT_DATA);
4342                         if (n == NULL)
4343                                 return (ENOBUFS);
4344                         n->m_len = 0;
4345                         last->m_next = n;
4346                         last = n;
4347                 }
4348         }
4349
4350         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
4351         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
4352         last->m_len += padlen;
4353         m->m_pkthdr.len += padlen;
4354
4355         return (0);
4356 }
4357
4358 static struct mbuf *
4359 bge_check_short_dma(struct mbuf *m)
4360 {
4361         struct mbuf *n;
4362         int found;
4363
4364         /*
4365          * If device receive two back-to-back send BDs with less than
4366          * or equal to 8 total bytes then the device may hang.  The two
4367          * back-to-back send BDs must in the same frame for this failure
4368          * to occur.  Scan mbuf chains and see whether two back-to-back
4369          * send BDs are there. If this is the case, allocate new mbuf
4370          * and copy the frame to workaround the silicon bug.
4371          */
4372         for (n = m, found = 0; n != NULL; n = n->m_next) {
4373                 if (n->m_len < 8) {
4374                         found++;
4375                         if (found > 1)
4376                                 break;
4377                         continue;
4378                 }
4379                 found = 0;
4380         }
4381
4382         if (found > 1) {
4383                 n = m_defrag(m, M_DONTWAIT);
4384                 if (n == NULL)
4385                         m_freem(m);
4386         } else
4387                 n = m;
4388         return (n);
4389 }
4390
4391 static struct mbuf *
4392 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
4393     uint16_t *flags)
4394 {
4395         struct ip *ip;
4396         struct tcphdr *tcp;
4397         struct mbuf *n;
4398         uint16_t hlen;
4399         uint32_t poff;
4400
4401         if (M_WRITABLE(m) == 0) {
4402                 /* Get a writable copy. */
4403                 n = m_dup(m, M_DONTWAIT);
4404                 m_freem(m);
4405                 if (n == NULL)
4406                         return (NULL);
4407                 m = n;
4408         }
4409         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
4410         if (m == NULL)
4411                 return (NULL);
4412         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
4413         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
4414         m = m_pullup(m, poff + sizeof(struct tcphdr));
4415         if (m == NULL)
4416                 return (NULL);
4417         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4418         m = m_pullup(m, poff + (tcp->th_off << 2));
4419         if (m == NULL)
4420                 return (NULL);
4421         /*
4422          * It seems controller doesn't modify IP length and TCP pseudo
4423          * checksum. These checksum computed by upper stack should be 0.
4424          */
4425         *mss = m->m_pkthdr.tso_segsz;
4426         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
4427         ip->ip_sum = 0;
4428         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
4429         /* Clear pseudo checksum computed by TCP stack. */
4430         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4431         tcp->th_sum = 0;
4432         /*
4433          * Broadcom controllers uses different descriptor format for
4434          * TSO depending on ASIC revision. Due to TSO-capable firmware
4435          * license issue and lower performance of firmware based TSO
4436          * we only support hardware based TSO.
4437          */
4438         /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
4439         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
4440         if (sc->bge_flags & BGE_FLAG_TSO3) {
4441                 /*
4442                  * For BCM5717 and newer controllers, hardware based TSO
4443                  * uses the 14 lower bits of the bge_mss field to store the
4444                  * MSS and the upper 2 bits to store the lowest 2 bits of
4445                  * the IP/TCP header length.  The upper 6 bits of the header
4446                  * length are stored in the bge_flags[14:10,4] field.  Jumbo
4447                  * frames are supported.
4448                  */
4449                 *mss |= ((hlen & 0x3) << 14);
4450                 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
4451         } else {
4452                 /*
4453                  * For BCM5755 and newer controllers, hardware based TSO uses
4454                  * the lower 11 bits to store the MSS and the upper 5 bits to
4455                  * store the IP/TCP header length. Jumbo frames are not
4456                  * supported.
4457                  */
4458                 *mss |= (hlen << 11);
4459         }
4460         return (m);
4461 }
4462
4463 /*
4464  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
4465  * pointers to descriptors.
4466  */
4467 static int
4468 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
4469 {
4470         bus_dma_segment_t       segs[BGE_NSEG_NEW];
4471         bus_dmamap_t            map;
4472         struct bge_tx_bd        *d;
4473         struct mbuf             *m = *m_head;
4474         uint32_t                idx = *txidx;
4475         uint16_t                csum_flags, mss, vlan_tag;
4476         int                     nsegs, i, error;
4477
4478         csum_flags = 0;
4479         mss = 0;
4480         vlan_tag = 0;
4481         if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
4482             m->m_next != NULL) {
4483                 *m_head = bge_check_short_dma(m);
4484                 if (*m_head == NULL)
4485                         return (ENOBUFS);
4486                 m = *m_head;
4487         }
4488         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
4489                 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
4490                 if (*m_head == NULL)
4491                         return (ENOBUFS);
4492                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
4493                     BGE_TXBDFLAG_CPU_POST_DMA;
4494         } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
4495                 if (m->m_pkthdr.csum_flags & CSUM_IP)
4496                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
4497                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
4498                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
4499                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
4500                             (error = bge_cksum_pad(m)) != 0) {
4501                                 m_freem(m);
4502                                 *m_head = NULL;
4503                                 return (error);
4504                         }
4505                 }
4506                 if (m->m_flags & M_LASTFRAG)
4507                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
4508                 else if (m->m_flags & M_FRAG)
4509                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
4510         }
4511
4512         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
4513                 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
4514                     m->m_pkthdr.len > ETHER_MAX_LEN)
4515                         csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
4516                 if (sc->bge_forced_collapse > 0 &&
4517                     (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
4518                         /*
4519                          * Forcedly collapse mbuf chains to overcome hardware
4520                          * limitation which only support a single outstanding
4521                          * DMA read operation.
4522                          */
4523                         if (sc->bge_forced_collapse == 1)
4524                                 m = m_defrag(m, M_DONTWAIT);
4525                         else
4526                                 m = m_collapse(m, M_DONTWAIT,
4527                                     sc->bge_forced_collapse);
4528                         if (m == NULL)
4529                                 m = *m_head;
4530                         *m_head = m;
4531                 }
4532         }
4533
4534         map = sc->bge_cdata.bge_tx_dmamap[idx];
4535         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
4536             &nsegs, BUS_DMA_NOWAIT);
4537         if (error == EFBIG) {
4538                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
4539                 if (m == NULL) {
4540                         m_freem(*m_head);
4541                         *m_head = NULL;
4542                         return (ENOBUFS);
4543                 }
4544                 *m_head = m;
4545                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
4546                     m, segs, &nsegs, BUS_DMA_NOWAIT);
4547                 if (error) {
4548                         m_freem(m);
4549                         *m_head = NULL;
4550                         return (error);
4551                 }
4552         } else if (error != 0)
4553                 return (error);
4554
4555         /* Check if we have enough free send BDs. */
4556         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
4557                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
4558                 return (ENOBUFS);
4559         }
4560
4561         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
4562
4563         if (m->m_flags & M_VLANTAG) {
4564                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4565                 vlan_tag = m->m_pkthdr.ether_vtag;
4566         }
4567         for (i = 0; ; i++) {
4568                 d = &sc->bge_ldata.bge_tx_ring[idx];
4569                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4570                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4571                 d->bge_len = segs[i].ds_len;
4572                 d->bge_flags = csum_flags;
4573                 d->bge_vlan_tag = vlan_tag;
4574                 d->bge_mss = mss;
4575                 if (i == nsegs - 1)
4576                         break;
4577                 BGE_INC(idx, BGE_TX_RING_CNT);
4578         }
4579
4580         /* Mark the last segment as end of packet... */
4581         d->bge_flags |= BGE_TXBDFLAG_END;
4582
4583         /*
4584          * Insure that the map for this transmission
4585          * is placed at the array index of the last descriptor
4586          * in this chain.
4587          */
4588         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4589         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4590         sc->bge_cdata.bge_tx_chain[idx] = m;
4591         sc->bge_txcnt += nsegs;
4592
4593         BGE_INC(idx, BGE_TX_RING_CNT);
4594         *txidx = idx;
4595
4596         return (0);
4597 }
4598
4599 /*
4600  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4601  * to the mbuf data regions directly in the transmit descriptors.
4602  */
4603 static void
4604 bge_start_locked(struct ifnet *ifp)
4605 {
4606         struct bge_softc *sc;
4607         struct mbuf *m_head;
4608         uint32_t prodidx;
4609         int count;
4610
4611         sc = ifp->if_softc;
4612         BGE_LOCK_ASSERT(sc);
4613
4614         if (!sc->bge_link ||
4615             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4616             IFF_DRV_RUNNING)
4617                 return;
4618
4619         prodidx = sc->bge_tx_prodidx;
4620
4621         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4622                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4623                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4624                         break;
4625                 }
4626                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4627                 if (m_head == NULL)
4628                         break;
4629
4630                 /*
4631                  * XXX
4632                  * The code inside the if() block is never reached since we
4633                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4634                  * requests to checksum TCP/UDP in a fragmented packet.
4635                  *
4636                  * XXX
4637                  * safety overkill.  If this is a fragmented packet chain
4638                  * with delayed TCP/UDP checksums, then only encapsulate
4639                  * it if we have enough descriptors to handle the entire
4640                  * chain at once.
4641                  * (paranoia -- may not actually be needed)
4642                  */
4643                 if (m_head->m_flags & M_FIRSTFRAG &&
4644                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4645                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4646                             m_head->m_pkthdr.csum_data + 16) {
4647                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4648                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4649                                 break;
4650                         }
4651                 }
4652
4653                 /*
4654                  * Pack the data into the transmit ring. If we
4655                  * don't have room, set the OACTIVE flag and wait
4656                  * for the NIC to drain the ring.
4657                  */
4658                 if (bge_encap(sc, &m_head, &prodidx)) {
4659                         if (m_head == NULL)
4660                                 break;
4661                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4662                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4663                         break;
4664                 }
4665                 ++count;
4666
4667                 /*
4668                  * If there's a BPF listener, bounce a copy of this frame
4669                  * to him.
4670                  */
4671 #ifdef ETHER_BPF_MTAP
4672                 ETHER_BPF_MTAP(ifp, m_head);
4673 #else
4674                 BPF_MTAP(ifp, m_head);
4675 #endif
4676         }
4677
4678         if (count > 0) {
4679                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4680                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4681                 /* Transmit. */
4682                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4683                 /* 5700 b2 errata */
4684                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4685                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4686
4687                 sc->bge_tx_prodidx = prodidx;
4688
4689                 /*
4690                  * Set a timeout in case the chip goes out to lunch.
4691                  */
4692                 sc->bge_timer = 5;
4693         }
4694 }
4695
4696 /*
4697  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4698  * to the mbuf data regions directly in the transmit descriptors.
4699  */
4700 static void
4701 bge_start(struct ifnet *ifp)
4702 {
4703         struct bge_softc *sc;
4704
4705         sc = ifp->if_softc;
4706         BGE_LOCK(sc);
4707         bge_start_locked(ifp);
4708         BGE_UNLOCK(sc);
4709 }
4710
4711 static void
4712 bge_init_locked(struct bge_softc *sc)
4713 {
4714         struct ifnet *ifp;
4715         uint16_t *m;
4716         uint32_t mode;
4717
4718         BGE_LOCK_ASSERT(sc);
4719
4720         ifp = sc->bge_ifp;
4721
4722         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4723                 return;
4724
4725         /* Cancel pending I/O and flush buffers. */
4726         bge_stop(sc);
4727
4728         bge_stop_fw(sc);
4729         bge_sig_pre_reset(sc, BGE_RESET_START);
4730         bge_reset(sc);
4731         bge_sig_legacy(sc, BGE_RESET_START);
4732         bge_sig_post_reset(sc, BGE_RESET_START);
4733
4734         bge_chipinit(sc);
4735
4736         /*
4737          * Init the various state machines, ring
4738          * control blocks and firmware.
4739          */
4740         if (bge_blockinit(sc)) {
4741                 device_printf(sc->bge_dev, "initialization failure\n");
4742                 return;
4743         }
4744
4745         ifp = sc->bge_ifp;
4746
4747         /* Specify MTU. */
4748         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4749             ETHER_HDR_LEN + ETHER_CRC_LEN +
4750             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4751
4752         /* Load our MAC address. */
4753         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4754         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4755         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4756
4757         /* Program promiscuous mode. */
4758         bge_setpromisc(sc);
4759
4760         /* Program multicast filter. */
4761         bge_setmulti(sc);
4762
4763         /* Program VLAN tag stripping. */
4764         bge_setvlan(sc);
4765
4766         /* Override UDP checksum offloading. */
4767         if (sc->bge_forced_udpcsum == 0)
4768                 sc->bge_csum_features &= ~CSUM_UDP;
4769         else
4770                 sc->bge_csum_features |= CSUM_UDP;
4771         if (ifp->if_capabilities & IFCAP_TXCSUM &&
4772             ifp->if_capenable & IFCAP_TXCSUM) {
4773                 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
4774                 ifp->if_hwassist |= sc->bge_csum_features;
4775         }
4776
4777         /* Init RX ring. */
4778         if (bge_init_rx_ring_std(sc) != 0) {
4779                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4780                 bge_stop(sc);
4781                 return;
4782         }
4783
4784         /*
4785          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4786          * memory to insure that the chip has in fact read the first
4787          * entry of the ring.
4788          */
4789         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4790                 uint32_t                v, i;
4791                 for (i = 0; i < 10; i++) {
4792                         DELAY(20);
4793                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4794                         if (v == (MCLBYTES - ETHER_ALIGN))
4795                                 break;
4796                 }
4797                 if (i == 10)
4798                         device_printf (sc->bge_dev,
4799                             "5705 A0 chip failed to load RX ring\n");
4800         }
4801
4802         /* Init jumbo RX ring. */
4803         if (BGE_IS_JUMBO_CAPABLE(sc) &&
4804             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4805             (MCLBYTES - ETHER_ALIGN)) {
4806                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4807                         device_printf(sc->bge_dev,
4808                             "no memory for jumbo Rx buffers.\n");
4809                         bge_stop(sc);
4810                         return;
4811                 }
4812         }
4813
4814         /* Init our RX return ring index. */
4815         sc->bge_rx_saved_considx = 0;
4816
4817         /* Init our RX/TX stat counters. */
4818         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4819
4820         /* Init TX ring. */
4821         bge_init_tx_ring(sc);
4822
4823         /* Enable TX MAC state machine lockup fix. */
4824         mode = CSR_READ_4(sc, BGE_TX_MODE);
4825         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
4826                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
4827         /* Turn on transmitter. */
4828         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
4829
4830         /* Turn on receiver. */
4831         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4832
4833         /*
4834          * Set the number of good frames to receive after RX MBUF
4835          * Low Watermark has been reached. After the RX MAC receives
4836          * this number of frames, it will drop subsequent incoming
4837          * frames until the MBUF High Watermark is reached.
4838          */
4839         if (sc->bge_asicrev == BGE_ASICREV_BCM57765)
4840                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
4841         else
4842                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
4843
4844         /* Clear MAC statistics. */
4845         if (BGE_IS_5705_PLUS(sc))
4846                 bge_stats_clear_regs(sc);
4847
4848         /* Tell firmware we're alive. */
4849         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4850
4851 #ifdef DEVICE_POLLING
4852         /* Disable interrupts if we are polling. */
4853         if (ifp->if_capenable & IFCAP_POLLING) {
4854                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4855                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4856                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4857         } else
4858 #endif
4859
4860         /* Enable host interrupts. */
4861         {
4862         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4863         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4864         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4865         }
4866
4867         bge_ifmedia_upd_locked(ifp);
4868
4869         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4870         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4871
4872         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4873 }
4874
4875 static void
4876 bge_init(void *xsc)
4877 {
4878         struct bge_softc *sc = xsc;
4879
4880         BGE_LOCK(sc);
4881         bge_init_locked(sc);
4882         BGE_UNLOCK(sc);
4883 }
4884
4885 /*
4886  * Set media options.
4887  */
4888 static int
4889 bge_ifmedia_upd(struct ifnet *ifp)
4890 {
4891         struct bge_softc *sc = ifp->if_softc;
4892         int res;
4893
4894         BGE_LOCK(sc);
4895         res = bge_ifmedia_upd_locked(ifp);
4896         BGE_UNLOCK(sc);
4897
4898         return (res);
4899 }
4900
4901 static int
4902 bge_ifmedia_upd_locked(struct ifnet *ifp)
4903 {
4904         struct bge_softc *sc = ifp->if_softc;
4905         struct mii_data *mii;
4906         struct mii_softc *miisc;
4907         struct ifmedia *ifm;
4908
4909         BGE_LOCK_ASSERT(sc);
4910
4911         ifm = &sc->bge_ifmedia;
4912
4913         /* If this is a 1000baseX NIC, enable the TBI port. */
4914         if (sc->bge_flags & BGE_FLAG_TBI) {
4915                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4916                         return (EINVAL);
4917                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4918                 case IFM_AUTO:
4919                         /*
4920                          * The BCM5704 ASIC appears to have a special
4921                          * mechanism for programming the autoneg
4922                          * advertisement registers in TBI mode.
4923                          */
4924                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4925                                 uint32_t sgdig;
4926                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4927                                 if (sgdig & BGE_SGDIGSTS_DONE) {
4928                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4929                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4930                                         sgdig |= BGE_SGDIGCFG_AUTO |
4931                                             BGE_SGDIGCFG_PAUSE_CAP |
4932                                             BGE_SGDIGCFG_ASYM_PAUSE;
4933                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4934                                             sgdig | BGE_SGDIGCFG_SEND);
4935                                         DELAY(5);
4936                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4937                                 }
4938                         }
4939                         break;
4940                 case IFM_1000_SX:
4941                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4942                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4943                                     BGE_MACMODE_HALF_DUPLEX);
4944                         } else {
4945                                 BGE_SETBIT(sc, BGE_MAC_MODE,
4946                                     BGE_MACMODE_HALF_DUPLEX);
4947                         }
4948                         break;
4949                 default:
4950                         return (EINVAL);
4951                 }
4952                 return (0);
4953         }
4954
4955         sc->bge_link_evt++;
4956         mii = device_get_softc(sc->bge_miibus);
4957         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4958                 PHY_RESET(miisc);
4959         mii_mediachg(mii);
4960
4961         /*
4962          * Force an interrupt so that we will call bge_link_upd
4963          * if needed and clear any pending link state attention.
4964          * Without this we are not getting any further interrupts
4965          * for link state changes and thus will not UP the link and
4966          * not be able to send in bge_start_locked. The only
4967          * way to get things working was to receive a packet and
4968          * get an RX intr.
4969          * bge_tick should help for fiber cards and we might not
4970          * need to do this here if BGE_FLAG_TBI is set but as
4971          * we poll for fiber anyway it should not harm.
4972          */
4973         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4974             sc->bge_flags & BGE_FLAG_5788)
4975                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4976         else
4977                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4978
4979         return (0);
4980 }
4981
4982 /*
4983  * Report current media status.
4984  */
4985 static void
4986 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4987 {
4988         struct bge_softc *sc = ifp->if_softc;
4989         struct mii_data *mii;
4990
4991         BGE_LOCK(sc);
4992
4993         if (sc->bge_flags & BGE_FLAG_TBI) {
4994                 ifmr->ifm_status = IFM_AVALID;
4995                 ifmr->ifm_active = IFM_ETHER;
4996                 if (CSR_READ_4(sc, BGE_MAC_STS) &
4997                     BGE_MACSTAT_TBI_PCS_SYNCHED)
4998                         ifmr->ifm_status |= IFM_ACTIVE;
4999                 else {
5000                         ifmr->ifm_active |= IFM_NONE;
5001                         BGE_UNLOCK(sc);
5002                         return;
5003                 }
5004                 ifmr->ifm_active |= IFM_1000_SX;
5005                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5006                         ifmr->ifm_active |= IFM_HDX;
5007                 else
5008                         ifmr->ifm_active |= IFM_FDX;
5009                 BGE_UNLOCK(sc);
5010                 return;
5011         }
5012
5013         mii = device_get_softc(sc->bge_miibus);
5014         mii_pollstat(mii);
5015         ifmr->ifm_active = mii->mii_media_active;
5016         ifmr->ifm_status = mii->mii_media_status;
5017
5018         BGE_UNLOCK(sc);
5019 }
5020
5021 static int
5022 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5023 {
5024         struct bge_softc *sc = ifp->if_softc;
5025         struct ifreq *ifr = (struct ifreq *) data;
5026         struct mii_data *mii;
5027         int flags, mask, error = 0;
5028
5029         switch (command) {
5030         case SIOCSIFMTU:
5031                 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5032                     (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5033                         if (ifr->ifr_mtu < ETHERMIN ||
5034                             ifr->ifr_mtu > BGE_JUMBO_MTU) {
5035                                 error = EINVAL;
5036                                 break;
5037                         }
5038                 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5039                         error = EINVAL;
5040                         break;
5041                 }
5042                 BGE_LOCK(sc);
5043                 if (ifp->if_mtu != ifr->ifr_mtu) {
5044                         ifp->if_mtu = ifr->ifr_mtu;
5045                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5046                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5047                                 bge_init_locked(sc);
5048                         }
5049                 }
5050                 BGE_UNLOCK(sc);
5051                 break;
5052         case SIOCSIFFLAGS:
5053                 BGE_LOCK(sc);
5054                 if (ifp->if_flags & IFF_UP) {
5055                         /*
5056                          * If only the state of the PROMISC flag changed,
5057                          * then just use the 'set promisc mode' command
5058                          * instead of reinitializing the entire NIC. Doing
5059                          * a full re-init means reloading the firmware and
5060                          * waiting for it to start up, which may take a
5061                          * second or two.  Similarly for ALLMULTI.
5062                          */
5063                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5064                                 flags = ifp->if_flags ^ sc->bge_if_flags;
5065                                 if (flags & IFF_PROMISC)
5066                                         bge_setpromisc(sc);
5067                                 if (flags & IFF_ALLMULTI)
5068                                         bge_setmulti(sc);
5069                         } else
5070                                 bge_init_locked(sc);
5071                 } else {
5072                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5073                                 bge_stop(sc);
5074                         }
5075                 }
5076                 sc->bge_if_flags = ifp->if_flags;
5077                 BGE_UNLOCK(sc);
5078                 error = 0;
5079                 break;
5080         case SIOCADDMULTI:
5081         case SIOCDELMULTI:
5082                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5083                         BGE_LOCK(sc);
5084                         bge_setmulti(sc);
5085                         BGE_UNLOCK(sc);
5086                         error = 0;
5087                 }
5088                 break;
5089         case SIOCSIFMEDIA:
5090         case SIOCGIFMEDIA:
5091                 if (sc->bge_flags & BGE_FLAG_TBI) {
5092                         error = ifmedia_ioctl(ifp, ifr,
5093                             &sc->bge_ifmedia, command);
5094                 } else {
5095                         mii = device_get_softc(sc->bge_miibus);
5096                         error = ifmedia_ioctl(ifp, ifr,
5097                             &mii->mii_media, command);
5098                 }
5099                 break;
5100         case SIOCSIFCAP:
5101                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5102 #ifdef DEVICE_POLLING
5103                 if (mask & IFCAP_POLLING) {
5104                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
5105                                 error = ether_poll_register(bge_poll, ifp);
5106                                 if (error)
5107                                         return (error);
5108                                 BGE_LOCK(sc);
5109                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5110                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5111                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5112                                 ifp->if_capenable |= IFCAP_POLLING;
5113                                 BGE_UNLOCK(sc);
5114                         } else {
5115                                 error = ether_poll_deregister(ifp);
5116                                 /* Enable interrupt even in error case */
5117                                 BGE_LOCK(sc);
5118                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5119                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5120                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5121                                 ifp->if_capenable &= ~IFCAP_POLLING;
5122                                 BGE_UNLOCK(sc);
5123                         }
5124                 }
5125 #endif
5126                 if ((mask & IFCAP_TXCSUM) != 0 &&
5127                     (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5128                         ifp->if_capenable ^= IFCAP_TXCSUM;
5129                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5130                                 ifp->if_hwassist |= sc->bge_csum_features;
5131                         else
5132                                 ifp->if_hwassist &= ~sc->bge_csum_features;
5133                 }
5134
5135                 if ((mask & IFCAP_RXCSUM) != 0 &&
5136                     (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5137                         ifp->if_capenable ^= IFCAP_RXCSUM;
5138
5139                 if ((mask & IFCAP_TSO4) != 0 &&
5140                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5141                         ifp->if_capenable ^= IFCAP_TSO4;
5142                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5143                                 ifp->if_hwassist |= CSUM_TSO;
5144                         else
5145                                 ifp->if_hwassist &= ~CSUM_TSO;
5146                 }
5147
5148                 if (mask & IFCAP_VLAN_MTU) {
5149                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
5150                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5151                         bge_init(sc);
5152                 }
5153
5154                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5155                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5156                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5157                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5158                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5159                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5160                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5161                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5162                         BGE_LOCK(sc);
5163                         bge_setvlan(sc);
5164                         BGE_UNLOCK(sc);
5165                 }
5166 #ifdef VLAN_CAPABILITIES
5167                 VLAN_CAPABILITIES(ifp);
5168 #endif
5169                 break;
5170         default:
5171                 error = ether_ioctl(ifp, command, data);
5172                 break;
5173         }
5174
5175         return (error);
5176 }
5177
5178 static void
5179 bge_watchdog(struct bge_softc *sc)
5180 {
5181         struct ifnet *ifp;
5182
5183         BGE_LOCK_ASSERT(sc);
5184
5185         if (sc->bge_timer == 0 || --sc->bge_timer)
5186                 return;
5187
5188         ifp = sc->bge_ifp;
5189
5190         if_printf(ifp, "watchdog timeout -- resetting\n");
5191
5192         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5193         bge_init_locked(sc);
5194
5195         ifp->if_oerrors++;
5196 }
5197
5198 static void
5199 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5200 {
5201         int i;
5202
5203         BGE_CLRBIT(sc, reg, bit);
5204
5205         for (i = 0; i < BGE_TIMEOUT; i++) {
5206                 if ((CSR_READ_4(sc, reg) & bit) == 0)
5207                         return;
5208                 DELAY(100);
5209         }
5210 }
5211
5212 /*
5213  * Stop the adapter and free any mbufs allocated to the
5214  * RX and TX lists.
5215  */
5216 static void
5217 bge_stop(struct bge_softc *sc)
5218 {
5219         struct ifnet *ifp;
5220
5221         BGE_LOCK_ASSERT(sc);
5222
5223         ifp = sc->bge_ifp;
5224
5225         callout_stop(&sc->bge_stat_ch);
5226
5227         /* Disable host interrupts. */
5228         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5229         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5230
5231         /*
5232          * Tell firmware we're shutting down.
5233          */
5234         bge_stop_fw(sc);
5235         bge_sig_pre_reset(sc, BGE_RESET_STOP);
5236
5237         /*
5238          * Disable all of the receiver blocks.
5239          */
5240         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5241         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5242         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5243         if (BGE_IS_5700_FAMILY(sc))
5244                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5245         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5246         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5247         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5248
5249         /*
5250          * Disable all of the transmit blocks.
5251          */
5252         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5253         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5254         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5255         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5256         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5257         if (BGE_IS_5700_FAMILY(sc))
5258                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
5259         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
5260
5261         /*
5262          * Shut down all of the memory managers and related
5263          * state machines.
5264          */
5265         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
5266         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
5267         if (BGE_IS_5700_FAMILY(sc))
5268                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
5269
5270         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
5271         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
5272         if (!(BGE_IS_5705_PLUS(sc))) {
5273                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
5274                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
5275         }
5276         /* Update MAC statistics. */
5277         if (BGE_IS_5705_PLUS(sc))
5278                 bge_stats_update_regs(sc);
5279
5280         bge_reset(sc);
5281         bge_sig_legacy(sc, BGE_RESET_STOP);
5282         bge_sig_post_reset(sc, BGE_RESET_STOP);
5283
5284         /*
5285          * Keep the ASF firmware running if up.
5286          */
5287         if (sc->bge_asf_mode & ASF_STACKUP)
5288                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5289         else
5290                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5291
5292         /* Free the RX lists. */
5293         bge_free_rx_ring_std(sc);
5294
5295         /* Free jumbo RX list. */
5296         if (BGE_IS_JUMBO_CAPABLE(sc))
5297                 bge_free_rx_ring_jumbo(sc);
5298
5299         /* Free TX buffers. */
5300         bge_free_tx_ring(sc);
5301
5302         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
5303
5304         /* Clear MAC's link state (PHY may still have link UP). */
5305         if (bootverbose && sc->bge_link)
5306                 if_printf(sc->bge_ifp, "link DOWN\n");
5307         sc->bge_link = 0;
5308
5309         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
5310 }
5311
5312 /*
5313  * Stop all chip I/O so that the kernel's probe routines don't
5314  * get confused by errant DMAs when rebooting.
5315  */
5316 static int
5317 bge_shutdown(device_t dev)
5318 {
5319         struct bge_softc *sc;
5320
5321         sc = device_get_softc(dev);
5322         BGE_LOCK(sc);
5323         bge_stop(sc);
5324         bge_reset(sc);
5325         BGE_UNLOCK(sc);
5326
5327         return (0);
5328 }
5329
5330 static int
5331 bge_suspend(device_t dev)
5332 {
5333         struct bge_softc *sc;
5334
5335         sc = device_get_softc(dev);
5336         BGE_LOCK(sc);
5337         bge_stop(sc);
5338         BGE_UNLOCK(sc);
5339
5340         return (0);
5341 }
5342
5343 static int
5344 bge_resume(device_t dev)
5345 {
5346         struct bge_softc *sc;
5347         struct ifnet *ifp;
5348
5349         sc = device_get_softc(dev);
5350         BGE_LOCK(sc);
5351         ifp = sc->bge_ifp;
5352         if (ifp->if_flags & IFF_UP) {
5353                 bge_init_locked(sc);
5354                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5355                         bge_start_locked(ifp);
5356         }
5357         BGE_UNLOCK(sc);
5358
5359         return (0);
5360 }
5361
5362 static void
5363 bge_link_upd(struct bge_softc *sc)
5364 {
5365         struct mii_data *mii;
5366         uint32_t link, status;
5367
5368         BGE_LOCK_ASSERT(sc);
5369
5370         /* Clear 'pending link event' flag. */
5371         sc->bge_link_evt = 0;
5372
5373         /*
5374          * Process link state changes.
5375          * Grrr. The link status word in the status block does
5376          * not work correctly on the BCM5700 rev AX and BX chips,
5377          * according to all available information. Hence, we have
5378          * to enable MII interrupts in order to properly obtain
5379          * async link changes. Unfortunately, this also means that
5380          * we have to read the MAC status register to detect link
5381          * changes, thereby adding an additional register access to
5382          * the interrupt handler.
5383          *
5384          * XXX: perhaps link state detection procedure used for
5385          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
5386          */
5387
5388         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
5389             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
5390                 status = CSR_READ_4(sc, BGE_MAC_STS);
5391                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
5392                         mii = device_get_softc(sc->bge_miibus);
5393                         mii_pollstat(mii);
5394                         if (!sc->bge_link &&
5395                             mii->mii_media_status & IFM_ACTIVE &&
5396                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5397                                 sc->bge_link++;
5398                                 if (bootverbose)
5399                                         if_printf(sc->bge_ifp, "link UP\n");
5400                         } else if (sc->bge_link &&
5401                             (!(mii->mii_media_status & IFM_ACTIVE) ||
5402                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
5403                                 sc->bge_link = 0;
5404                                 if (bootverbose)
5405                                         if_printf(sc->bge_ifp, "link DOWN\n");
5406                         }
5407
5408                         /* Clear the interrupt. */
5409                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
5410                             BGE_EVTENB_MI_INTERRUPT);
5411                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
5412                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
5413                             BRGPHY_INTRS);
5414                 }
5415                 return;
5416         }
5417
5418         if (sc->bge_flags & BGE_FLAG_TBI) {
5419                 status = CSR_READ_4(sc, BGE_MAC_STS);
5420                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
5421                         if (!sc->bge_link) {
5422                                 sc->bge_link++;
5423                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
5424                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
5425                                             BGE_MACMODE_TBI_SEND_CFGS);
5426                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
5427                                 if (bootverbose)
5428                                         if_printf(sc->bge_ifp, "link UP\n");
5429                                 if_link_state_change(sc->bge_ifp,
5430                                     LINK_STATE_UP);
5431                         }
5432                 } else if (sc->bge_link) {
5433                         sc->bge_link = 0;
5434                         if (bootverbose)
5435                                 if_printf(sc->bge_ifp, "link DOWN\n");
5436                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
5437                 }
5438         } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
5439                 /*
5440                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
5441                  * in status word always set. Workaround this bug by reading
5442                  * PHY link status directly.
5443                  */
5444                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
5445
5446                 if (link != sc->bge_link ||
5447                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
5448                         mii = device_get_softc(sc->bge_miibus);
5449                         mii_pollstat(mii);
5450                         if (!sc->bge_link &&
5451                             mii->mii_media_status & IFM_ACTIVE &&
5452                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5453                                 sc->bge_link++;
5454                                 if (bootverbose)
5455                                         if_printf(sc->bge_ifp, "link UP\n");
5456                         } else if (sc->bge_link &&
5457                             (!(mii->mii_media_status & IFM_ACTIVE) ||
5458                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
5459                                 sc->bge_link = 0;
5460                                 if (bootverbose)
5461                                         if_printf(sc->bge_ifp, "link DOWN\n");
5462                         }
5463                 }
5464         } else {
5465                 /*
5466                  * For controllers that call mii_tick, we have to poll
5467                  * link status.
5468                  */
5469                 mii = device_get_softc(sc->bge_miibus);
5470                 mii_pollstat(mii);
5471                 bge_miibus_statchg(sc->bge_dev);
5472         }
5473
5474         /* Clear the attention. */
5475         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
5476             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
5477             BGE_MACSTAT_LINK_CHANGED);
5478 }
5479
5480 static void
5481 bge_add_sysctls(struct bge_softc *sc)
5482 {
5483         struct sysctl_ctx_list *ctx;
5484         struct sysctl_oid_list *children;
5485         char tn[32];
5486         int unit;
5487
5488         ctx = device_get_sysctl_ctx(sc->bge_dev);
5489         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
5490
5491 #ifdef BGE_REGISTER_DEBUG
5492         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
5493             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
5494             "Debug Information");
5495
5496         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
5497             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
5498             "Register Read");
5499
5500         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
5501             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
5502             "Memory Read");
5503
5504 #endif
5505
5506         unit = device_get_unit(sc->bge_dev);
5507         /*
5508          * A common design characteristic for many Broadcom client controllers
5509          * is that they only support a single outstanding DMA read operation
5510          * on the PCIe bus. This means that it will take twice as long to fetch
5511          * a TX frame that is split into header and payload buffers as it does
5512          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
5513          * these controllers, coalescing buffers to reduce the number of memory
5514          * reads is effective way to get maximum performance(about 940Mbps).
5515          * Without collapsing TX buffers the maximum TCP bulk transfer
5516          * performance is about 850Mbps. However forcing coalescing mbufs
5517          * consumes a lot of CPU cycles, so leave it off by default.
5518          */
5519         sc->bge_forced_collapse = 0;
5520         snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
5521         TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
5522         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
5523             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
5524             "Number of fragmented TX buffers of a frame allowed before "
5525             "forced collapsing");
5526
5527         /*
5528          * It seems all Broadcom controllers have a bug that can generate UDP
5529          * datagrams with checksum value 0 when TX UDP checksum offloading is
5530          * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
5531          * Even though the probability of generating such UDP datagrams is
5532          * low, I don't want to see FreeBSD boxes to inject such datagrams
5533          * into network so disable UDP checksum offloading by default.  Users
5534          * still override this behavior by setting a sysctl variable,
5535          * dev.bge.0.forced_udpcsum.
5536          */
5537         sc->bge_forced_udpcsum = 0;
5538         snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
5539         TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
5540         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
5541             CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
5542             "Enable UDP checksum offloading even if controller can "
5543             "generate UDP checksum value 0");
5544
5545         if (BGE_IS_5705_PLUS(sc))
5546                 bge_add_sysctl_stats_regs(sc, ctx, children);
5547         else
5548                 bge_add_sysctl_stats(sc, ctx, children);
5549 }
5550
5551 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
5552         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
5553             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
5554             desc)
5555
5556 static void
5557 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5558     struct sysctl_oid_list *parent)
5559 {
5560         struct sysctl_oid *tree;
5561         struct sysctl_oid_list *children, *schildren;
5562
5563         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
5564             NULL, "BGE Statistics");
5565         schildren = children = SYSCTL_CHILDREN(tree);
5566         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
5567             children, COSFramesDroppedDueToFilters,
5568             "FramesDroppedDueToFilters");
5569         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
5570             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
5571         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
5572             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
5573         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
5574             children, nicNoMoreRxBDs, "NoMoreRxBDs");
5575         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
5576             children, ifInDiscards, "InputDiscards");
5577         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
5578             children, ifInErrors, "InputErrors");
5579         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
5580             children, nicRecvThresholdHit, "RecvThresholdHit");
5581         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
5582             children, nicDmaReadQueueFull, "DmaReadQueueFull");
5583         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
5584             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
5585         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
5586             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
5587         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
5588             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
5589         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
5590             children, nicRingStatusUpdate, "RingStatusUpdate");
5591         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
5592             children, nicInterrupts, "Interrupts");
5593         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
5594             children, nicAvoidedInterrupts, "AvoidedInterrupts");
5595         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
5596             children, nicSendThresholdHit, "SendThresholdHit");
5597
5598         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
5599             NULL, "BGE RX Statistics");
5600         children = SYSCTL_CHILDREN(tree);
5601         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
5602             children, rxstats.ifHCInOctets, "ifHCInOctets");
5603         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
5604             children, rxstats.etherStatsFragments, "Fragments");
5605         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
5606             children, rxstats.ifHCInUcastPkts, "UnicastPkts");
5607         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
5608             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
5609         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
5610             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
5611         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
5612             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
5613         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
5614             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
5615         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
5616             children, rxstats.xoffPauseFramesReceived,
5617             "xoffPauseFramesReceived");
5618         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
5619             children, rxstats.macControlFramesReceived,
5620             "ControlFramesReceived");
5621         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
5622             children, rxstats.xoffStateEntered, "xoffStateEntered");
5623         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
5624             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
5625         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
5626             children, rxstats.etherStatsJabbers, "Jabbers");
5627         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
5628             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
5629         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
5630             children, rxstats.inRangeLengthError, "inRangeLengthError");
5631         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
5632             children, rxstats.outRangeLengthError, "outRangeLengthError");
5633
5634         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
5635             NULL, "BGE TX Statistics");
5636         children = SYSCTL_CHILDREN(tree);
5637         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
5638             children, txstats.ifHCOutOctets, "ifHCOutOctets");
5639         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
5640             children, txstats.etherStatsCollisions, "Collisions");
5641         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
5642             children, txstats.outXonSent, "XonSent");
5643         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
5644             children, txstats.outXoffSent, "XoffSent");
5645         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
5646             children, txstats.flowControlDone, "flowControlDone");
5647         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
5648             children, txstats.dot3StatsInternalMacTransmitErrors,
5649             "InternalMacTransmitErrors");
5650         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
5651             children, txstats.dot3StatsSingleCollisionFrames,
5652             "SingleCollisionFrames");
5653         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
5654             children, txstats.dot3StatsMultipleCollisionFrames,
5655             "MultipleCollisionFrames");
5656         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
5657             children, txstats.dot3StatsDeferredTransmissions,
5658             "DeferredTransmissions");
5659         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5660             children, txstats.dot3StatsExcessiveCollisions,
5661             "ExcessiveCollisions");
5662         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5663             children, txstats.dot3StatsLateCollisions,
5664             "LateCollisions");
5665         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5666             children, txstats.ifHCOutUcastPkts, "UnicastPkts");
5667         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5668             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5669         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5670             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5671         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5672             children, txstats.dot3StatsCarrierSenseErrors,
5673             "CarrierSenseErrors");
5674         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5675             children, txstats.ifOutDiscards, "Discards");
5676         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5677             children, txstats.ifOutErrors, "Errors");
5678 }
5679
5680 #undef BGE_SYSCTL_STAT
5681
5682 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
5683             SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
5684
5685 static void
5686 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5687     struct sysctl_oid_list *parent)
5688 {
5689         struct sysctl_oid *tree;
5690         struct sysctl_oid_list *child, *schild;
5691         struct bge_mac_stats *stats;
5692
5693         stats = &sc->bge_mac_stats;
5694         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
5695             NULL, "BGE Statistics");
5696         schild = child = SYSCTL_CHILDREN(tree);
5697         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
5698             &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
5699         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
5700             &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
5701         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
5702             &stats->DmaWriteHighPriQueueFull,
5703             "NIC DMA Write High Priority Queue Full");
5704         BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
5705             &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
5706         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
5707             &stats->InputDiscards, "Discarded Input Frames");
5708         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
5709             &stats->InputErrors, "Input Errors");
5710         BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
5711             &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
5712
5713         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
5714             NULL, "BGE RX Statistics");
5715         child = SYSCTL_CHILDREN(tree);
5716         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
5717             &stats->ifHCInOctets, "Inbound Octets");
5718         BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
5719             &stats->etherStatsFragments, "Fragments");
5720         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
5721             &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
5722         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
5723             &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
5724         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
5725             &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
5726         BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
5727             &stats->dot3StatsFCSErrors, "FCS Errors");
5728         BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
5729             &stats->dot3StatsAlignmentErrors, "Alignment Errors");
5730         BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
5731             &stats->xonPauseFramesReceived, "XON Pause Frames Received");
5732         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
5733             &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
5734         BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
5735             &stats->macControlFramesReceived, "MAC Control Frames Received");
5736         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
5737             &stats->xoffStateEntered, "XOFF State Entered");
5738         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
5739             &stats->dot3StatsFramesTooLong, "Frames Too Long");
5740         BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
5741             &stats->etherStatsJabbers, "Jabbers");
5742         BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
5743             &stats->etherStatsUndersizePkts, "Undersized Packets");
5744
5745         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
5746             NULL, "BGE TX Statistics");
5747         child = SYSCTL_CHILDREN(tree);
5748         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
5749             &stats->ifHCOutOctets, "Outbound Octets");
5750         BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
5751             &stats->etherStatsCollisions, "TX Collisions");
5752         BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
5753             &stats->outXonSent, "XON Sent");
5754         BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
5755             &stats->outXoffSent, "XOFF Sent");
5756         BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
5757             &stats->dot3StatsInternalMacTransmitErrors,
5758             "Internal MAC TX Errors");
5759         BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
5760             &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
5761         BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
5762             &stats->dot3StatsMultipleCollisionFrames,
5763             "Multiple Collision Frames");
5764         BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
5765             &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
5766         BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
5767             &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
5768         BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
5769             &stats->dot3StatsLateCollisions, "Late Collisions");
5770         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
5771             &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
5772         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
5773             &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
5774         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
5775             &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
5776 }
5777
5778 #undef  BGE_SYSCTL_STAT_ADD64
5779
5780 static int
5781 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5782 {
5783         struct bge_softc *sc;
5784         uint32_t result;
5785         int offset;
5786
5787         sc = (struct bge_softc *)arg1;
5788         offset = arg2;
5789         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5790             offsetof(bge_hostaddr, bge_addr_lo));
5791         return (sysctl_handle_int(oidp, &result, 0, req));
5792 }
5793
5794 #ifdef BGE_REGISTER_DEBUG
5795 static int
5796 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5797 {
5798         struct bge_softc *sc;
5799         uint16_t *sbdata;
5800         int error;
5801         int result;
5802         int i, j;
5803
5804         result = -1;
5805         error = sysctl_handle_int(oidp, &result, 0, req);
5806         if (error || (req->newptr == NULL))
5807                 return (error);
5808
5809         if (result == 1) {
5810                 sc = (struct bge_softc *)arg1;
5811
5812                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5813                 printf("Status Block:\n");
5814                 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5815                         printf("%06x:", i);
5816                         for (j = 0; j < 8; j++) {
5817                                 printf(" %04x", sbdata[i]);
5818                                 i += 4;
5819                         }
5820                         printf("\n");
5821                 }
5822
5823                 printf("Registers:\n");
5824                 for (i = 0x800; i < 0xA00; ) {
5825                         printf("%06x:", i);
5826                         for (j = 0; j < 8; j++) {
5827                                 printf(" %08x", CSR_READ_4(sc, i));
5828                                 i += 4;
5829                         }
5830                         printf("\n");
5831                 }
5832
5833                 printf("Hardware Flags:\n");
5834                 if (BGE_IS_5755_PLUS(sc))
5835                         printf(" - 5755 Plus\n");
5836                 if (BGE_IS_575X_PLUS(sc))
5837                         printf(" - 575X Plus\n");
5838                 if (BGE_IS_5705_PLUS(sc))
5839                         printf(" - 5705 Plus\n");
5840                 if (BGE_IS_5714_FAMILY(sc))
5841                         printf(" - 5714 Family\n");
5842                 if (BGE_IS_5700_FAMILY(sc))
5843                         printf(" - 5700 Family\n");
5844                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5845                         printf(" - Supports Jumbo Frames\n");
5846                 if (sc->bge_flags & BGE_FLAG_PCIX)
5847                         printf(" - PCI-X Bus\n");
5848                 if (sc->bge_flags & BGE_FLAG_PCIE)
5849                         printf(" - PCI Express Bus\n");
5850                 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
5851                         printf(" - No 3 LEDs\n");
5852                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5853                         printf(" - RX Alignment Bug\n");
5854         }
5855
5856         return (error);
5857 }
5858
5859 static int
5860 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5861 {
5862         struct bge_softc *sc;
5863         int error;
5864         uint16_t result;
5865         uint32_t val;
5866
5867         result = -1;
5868         error = sysctl_handle_int(oidp, &result, 0, req);
5869         if (error || (req->newptr == NULL))
5870                 return (error);
5871
5872         if (result < 0x8000) {
5873                 sc = (struct bge_softc *)arg1;
5874                 val = CSR_READ_4(sc, result);
5875                 printf("reg 0x%06X = 0x%08X\n", result, val);
5876         }
5877
5878         return (error);
5879 }
5880
5881 static int
5882 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5883 {
5884         struct bge_softc *sc;
5885         int error;
5886         uint16_t result;
5887         uint32_t val;
5888
5889         result = -1;
5890         error = sysctl_handle_int(oidp, &result, 0, req);
5891         if (error || (req->newptr == NULL))
5892                 return (error);
5893
5894         if (result < 0x8000) {
5895                 sc = (struct bge_softc *)arg1;
5896                 val = bge_readmem_ind(sc, result);
5897                 printf("mem 0x%06X = 0x%08X\n", result, val);
5898         }
5899
5900         return (error);
5901 }
5902 #endif
5903
5904 static int
5905 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5906 {
5907
5908         if (sc->bge_flags & BGE_FLAG_EADDR)
5909                 return (1);
5910
5911 #ifdef __sparc64__
5912         OF_getetheraddr(sc->bge_dev, ether_addr);
5913         return (0);
5914 #endif
5915         return (1);
5916 }
5917
5918 static int
5919 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5920 {
5921         uint32_t mac_addr;
5922
5923         mac_addr = bge_readmem_ind(sc, 0x0c14);
5924         if ((mac_addr >> 16) == 0x484b) {
5925                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5926                 ether_addr[1] = (uint8_t)mac_addr;
5927                 mac_addr = bge_readmem_ind(sc, 0x0c18);
5928                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5929                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5930                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5931                 ether_addr[5] = (uint8_t)mac_addr;
5932                 return (0);
5933         }
5934         return (1);
5935 }
5936
5937 static int
5938 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5939 {
5940         int mac_offset = BGE_EE_MAC_OFFSET;
5941
5942         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5943                 mac_offset = BGE_EE_MAC_OFFSET_5906;
5944
5945         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5946             ETHER_ADDR_LEN));
5947 }
5948
5949 static int
5950 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5951 {
5952
5953         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5954                 return (1);
5955
5956         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5957            ETHER_ADDR_LEN));
5958 }
5959
5960 static int
5961 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5962 {
5963         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5964                 /* NOTE: Order is critical */
5965                 bge_get_eaddr_fw,
5966                 bge_get_eaddr_mem,
5967                 bge_get_eaddr_nvram,
5968                 bge_get_eaddr_eeprom,
5969                 NULL
5970         };
5971         const bge_eaddr_fcn_t *func;
5972
5973         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5974                 if ((*func)(sc, eaddr) == 0)
5975                         break;
5976         }
5977         return (*func == NULL ? ENXIO : 0);
5978 }