2 * Copyright 2008 Nathan Whitehorn. All rights reserved.
3 * Copyright 2003 by Peter Grehan. All rights reserved.
4 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp
34 * BMAC/BMAC+ Macio cell 10/100 ethernet driver
35 * The low-cost, low-feature Apple variant of the Sun HME
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
44 #include <sys/endian.h>
46 #include <sys/module.h>
47 #include <sys/malloc.h>
48 #include <sys/kernel.h>
49 #include <sys/socket.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
59 #include <machine/pio.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
65 #include <dev/mii/mii.h>
66 #include <dev/mii/mii_bitbang.h>
67 #include <dev/mii/miivar.h>
69 #include <dev/ofw/ofw_bus.h>
70 #include <dev/ofw/openfirm.h>
71 #include <machine/dbdma.h>
73 MODULE_DEPEND(bm, ether, 1, 1, 1);
74 MODULE_DEPEND(bm, miibus, 1, 1, 1);
76 /* "controller miibus0" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
82 static int bm_probe (device_t);
83 static int bm_attach (device_t);
84 static int bm_detach (device_t);
85 static int bm_shutdown (device_t);
87 static void bm_start (struct ifnet *);
88 static void bm_start_locked (struct ifnet *);
89 static int bm_encap (struct bm_softc *sc, struct mbuf **m_head);
90 static int bm_ioctl (struct ifnet *, u_long, caddr_t);
91 static void bm_init (void *);
92 static void bm_init_locked (struct bm_softc *sc);
93 static void bm_chip_setup (struct bm_softc *sc);
94 static void bm_stop (struct bm_softc *sc);
95 static void bm_setladrf (struct bm_softc *sc);
96 static void bm_dummypacket (struct bm_softc *sc);
97 static void bm_txintr (void *xsc);
98 static void bm_rxintr (void *xsc);
100 static int bm_add_rxbuf (struct bm_softc *sc, int i);
101 static int bm_add_rxbuf_dma (struct bm_softc *sc, int i);
102 static void bm_enable_interrupts (struct bm_softc *sc);
103 static void bm_disable_interrupts (struct bm_softc *sc);
104 static void bm_tick (void *xsc);
106 static int bm_ifmedia_upd (struct ifnet *);
107 static void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *);
109 static int bm_miibus_readreg (device_t, int, int);
110 static int bm_miibus_writereg (device_t, int, int, int);
111 static void bm_miibus_statchg (device_t);
116 static uint32_t bm_mii_bitbang_read(device_t);
117 static void bm_mii_bitbang_write(device_t, uint32_t);
119 static const struct mii_bitbang_ops bm_mii_bitbang_ops = {
121 bm_mii_bitbang_write,
123 BM_MII_DATAOUT, /* MII_BIT_MDO */
124 BM_MII_DATAIN, /* MII_BIT_MDI */
125 BM_MII_CLK, /* MII_BIT_MDC */
126 BM_MII_OENABLE, /* MII_BIT_DIR_HOST_PHY */
127 0, /* MII_BIT_DIR_PHY_HOST */
131 static device_method_t bm_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, bm_probe),
134 DEVMETHOD(device_attach, bm_attach),
135 DEVMETHOD(device_detach, bm_detach),
136 DEVMETHOD(device_shutdown, bm_shutdown),
138 /* bus interface, for miibus */
139 DEVMETHOD(bus_print_child, bus_generic_print_child),
140 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
143 DEVMETHOD(miibus_readreg, bm_miibus_readreg),
144 DEVMETHOD(miibus_writereg, bm_miibus_writereg),
145 DEVMETHOD(miibus_statchg, bm_miibus_statchg),
149 static driver_t bm_macio_driver = {
152 sizeof(struct bm_softc)
155 static devclass_t bm_devclass;
157 DRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0);
158 DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0);
161 * MII internal routines
165 * Write the MII serial port for the MII bit-bang module.
168 bm_mii_bitbang_write(device_t dev, uint32_t val)
172 sc = device_get_softc(dev);
174 CSR_WRITE_2(sc, BM_MII_CSR, val);
175 CSR_BARRIER(sc, BM_MII_CSR, 2,
176 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
180 * Read the MII serial port for the MII bit-bang module.
183 bm_mii_bitbang_read(device_t dev)
188 sc = device_get_softc(dev);
190 reg = CSR_READ_2(sc, BM_MII_CSR);
191 CSR_BARRIER(sc, BM_MII_CSR, 2,
192 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
201 bm_miibus_readreg(device_t dev, int phy, int reg)
204 return (mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg));
208 bm_miibus_writereg(device_t dev, int phy, int reg, int data)
211 mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg);
217 bm_miibus_statchg(device_t dev)
219 struct bm_softc *sc = device_get_softc(dev);
223 reg = CSR_READ_2(sc, BM_TX_CONFIG);
224 new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX;
226 if (new_duplex != sc->sc_duplex) {
227 /* Turn off TX MAC while we fiddle its settings */
230 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
231 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE)
235 if (new_duplex && !sc->sc_duplex)
236 reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX;
237 else if (!new_duplex && sc->sc_duplex)
238 reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX);
240 if (new_duplex != sc->sc_duplex) {
241 /* Turn TX MAC back on */
244 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
245 sc->sc_duplex = new_duplex;
250 * ifmedia/mii callbacks
253 bm_ifmedia_upd(struct ifnet *ifp)
255 struct bm_softc *sc = ifp->if_softc;
259 error = mii_mediachg(sc->sc_mii);
265 bm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm)
267 struct bm_softc *sc = ifp->if_softc;
270 mii_pollstat(sc->sc_mii);
271 ifm->ifm_active = sc->sc_mii->mii_media_active;
272 ifm->ifm_status = sc->sc_mii->mii_media_status;
280 bm_probe(device_t dev)
282 const char *dname = ofw_bus_get_name(dev);
283 const char *dcompat = ofw_bus_get_compat(dev);
286 * BMAC+ cells have a name of "ethernet" and
287 * a compatible property of "bmac+"
289 if (strcmp(dname, "bmac") == 0) {
290 device_set_desc(dev, "Apple BMAC Ethernet Adaptor");
291 } else if (strcmp(dcompat, "bmac+") == 0) {
292 device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor");
300 bm_attach(device_t dev)
305 int error, cellid, i;
306 struct bm_txsoft *txs;
307 struct bm_softc *sc = device_get_softc(dev);
309 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
312 sc->sc_duplex = ~IFM_FDX;
315 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
317 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
319 /* Check for an improved version of Paddington */
320 sc->sc_streaming = 0;
322 node = ofw_bus_get_node(dev);
324 OF_getprop(node, "cell-id", &cellid, sizeof(cellid));
326 sc->sc_streaming = 1;
329 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
330 &sc->sc_memrid, RF_ACTIVE);
331 if (sc->sc_memr == NULL) {
332 device_printf(dev, "Could not alloc chip registers!\n");
336 sc->sc_txdmarid = BM_TXDMA_REGISTERS;
337 sc->sc_rxdmarid = BM_RXDMA_REGISTERS;
339 sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
340 &sc->sc_txdmarid, RF_ACTIVE);
341 sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
342 &sc->sc_rxdmarid, RF_ACTIVE);
344 if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) {
345 device_printf(dev, "Could not map DBDMA registers!\n");
349 error = dbdma_allocate_channel(sc->sc_txdmar, 0, bus_get_dma_tag(dev),
350 BM_MAX_DMA_COMMANDS, &sc->sc_txdma);
351 error += dbdma_allocate_channel(sc->sc_rxdmar, 0, bus_get_dma_tag(dev),
352 BM_MAX_DMA_COMMANDS, &sc->sc_rxdma);
355 device_printf(dev,"Could not allocate DBDMA channel!\n");
359 /* alloc DMA tags and buffers */
360 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
361 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
362 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
363 NULL, &sc->sc_pdma_tag);
366 device_printf(dev,"Could not allocate DMA tag!\n");
370 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
371 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES,
372 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag);
375 device_printf(dev,"Could not allocate RX DMA channel!\n");
379 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
380 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS,
381 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag);
384 device_printf(dev,"Could not allocate TX DMA tag!\n");
388 /* init transmit descriptors */
389 STAILQ_INIT(&sc->sc_txfreeq);
390 STAILQ_INIT(&sc->sc_txdirtyq);
392 /* create TX DMA maps */
394 for (i = 0; i < BM_MAX_TX_PACKETS; i++) {
395 txs = &sc->sc_txsoft[i];
396 txs->txs_mbuf = NULL;
397 error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap);
399 device_printf(sc->sc_dev,
400 "unable to create TX DMA map %d, error = %d\n",
403 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
406 /* Create the receive buffer DMA maps. */
407 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
408 error = bus_dmamap_create(sc->sc_rdma_tag, 0,
409 &sc->sc_rxsoft[i].rxs_dmamap);
411 device_printf(sc->sc_dev,
412 "unable to create RX DMA map %d, error = %d\n",
415 sc->sc_rxsoft[i].rxs_mbuf = NULL;
418 /* alloc interrupt */
419 bm_disable_interrupts(sc);
421 sc->sc_txdmairqid = BM_TXDMA_INTERRUPT;
422 sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
423 &sc->sc_txdmairqid, RF_ACTIVE);
426 device_printf(dev,"Could not allocate TX interrupt!\n");
430 bus_setup_intr(dev,sc->sc_txdmairq,
431 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc,
434 sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT;
435 sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
436 &sc->sc_rxdmairqid, RF_ACTIVE);
439 device_printf(dev,"Could not allocate RX interrupt!\n");
443 bus_setup_intr(dev,sc->sc_rxdmairq,
444 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc,
448 * Get the ethernet address from OpenFirmware
450 eaddr = sc->sc_enaddr;
451 OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN);
455 * On Apple BMAC controllers, we end up in a weird state of
456 * partially-completed autonegotiation on boot. So we force
457 * autonegotation to try again.
459 error = mii_attach(dev, &sc->sc_miibus, ifp, bm_ifmedia_upd,
460 bm_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
463 device_printf(dev, "attaching PHYs failed\n");
467 /* reset the adapter */
470 sc->sc_mii = device_get_softc(sc->sc_miibus);
472 if_initname(ifp, device_get_name(sc->sc_dev),
473 device_get_unit(sc->sc_dev));
474 ifp->if_mtu = ETHERMTU;
475 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
476 ifp->if_start = bm_start;
477 ifp->if_ioctl = bm_ioctl;
478 ifp->if_init = bm_init;
479 IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS);
480 ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS;
481 IFQ_SET_READY(&ifp->if_snd);
483 /* Attach the interface. */
484 ether_ifattach(ifp, sc->sc_enaddr);
485 ifp->if_hwassist = 0;
491 bm_detach(device_t dev)
493 struct bm_softc *sc = device_get_softc(dev);
499 callout_drain(&sc->sc_tick_ch);
500 ether_ifdetach(sc->sc_ifp);
501 bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx);
502 bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih);
504 dbdma_free_channel(sc->sc_txdma);
505 dbdma_free_channel(sc->sc_rxdma);
507 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
508 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid,
510 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid,
513 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid,
515 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid,
518 mtx_destroy(&sc->sc_mtx);
525 bm_shutdown(device_t dev)
529 sc = device_get_softc(dev);
539 bm_dummypacket(struct bm_softc *sc)
546 MGETHDR(m, M_DONTWAIT, MT_DATA);
552 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
554 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
555 mtod(m, struct ether_header *)->ether_type = htons(3);
556 mtod(m, unsigned char *)[14] = 0;
557 mtod(m, unsigned char *)[15] = 0;
558 mtod(m, unsigned char *)[16] = 0xE3;
559 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
560 IF_ENQUEUE(&ifp->if_snd, m);
561 bm_start_locked(ifp);
567 struct bm_softc *sc = xsc;
568 struct ifnet *ifp = sc->sc_ifp;
570 int i, prev_stop, new_stop;
575 status = dbdma_get_chan_status(sc->sc_rxdma);
576 if (status & DBDMA_STATUS_DEAD) {
577 dbdma_reset(sc->sc_rxdma);
581 if (!(status & DBDMA_STATUS_RUN)) {
582 device_printf(sc->sc_dev,"Bad RX Interrupt!\n");
587 prev_stop = sc->next_rxdma_slot - 1;
589 prev_stop = sc->rxdma_loop_slot - 1;
597 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD);
599 for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) {
600 if (i == sc->rxdma_loop_slot)
606 status = dbdma_get_cmd_status(sc->sc_rxdma, i);
611 m = sc->sc_rxsoft[i].rxs_mbuf;
613 if (bm_add_rxbuf(sc, i)) {
623 m->m_pkthdr.rcvif = ifp;
624 m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2);
625 m->m_pkthdr.len = m->m_len;
627 /* Send up the stack */
629 (*ifp->if_input)(ifp, m);
632 /* Clear all fields on this command */
633 bm_add_rxbuf_dma(sc, i);
638 /* Change the last packet we processed to the ring buffer terminator,
639 * and restore a receive buffer to the old terminator */
641 dbdma_insert_stop(sc->sc_rxdma, new_stop);
642 bm_add_rxbuf_dma(sc, prev_stop);
643 if (i < sc->rxdma_loop_slot)
644 sc->next_rxdma_slot = i;
646 sc->next_rxdma_slot = 0;
648 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
650 dbdma_wake(sc->sc_rxdma);
658 struct bm_softc *sc = xsc;
659 struct ifnet *ifp = sc->sc_ifp;
660 struct bm_txsoft *txs;
665 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
666 if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc))
669 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
670 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
672 if (txs->txs_mbuf != NULL) {
673 m_freem(txs->txs_mbuf);
674 txs->txs_mbuf = NULL;
677 /* Set the first used TXDMA slot to the location of the
678 * STOP/NOP command associated with this packet. */
680 sc->first_used_txdma_slot = txs->txs_stopdesc;
682 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
690 * We freed some descriptors, so reset IFF_DRV_OACTIVE
693 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
694 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
696 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) &&
697 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
698 bm_start_locked(ifp);
705 bm_start(struct ifnet *ifp)
707 struct bm_softc *sc = ifp->if_softc;
710 bm_start_locked(ifp);
715 bm_start_locked(struct ifnet *ifp)
717 struct bm_softc *sc = ifp->if_softc;
718 struct mbuf *mb_head;
723 * We lay out our DBDMA program in the following manner:
726 * OUTPUT_LAST (+ Interrupt)
729 * To extend the channel, we append a new program,
730 * then replace STOP with NOP and wake the channel.
731 * If we stalled on the STOP already, the program proceeds,
732 * if not it will sail through the NOP.
735 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
736 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
741 prev_stop = sc->next_txdma_slot - 1;
743 if (bm_encap(sc, &mb_head)) {
744 /* Put the packet back and stop */
745 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
746 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
750 dbdma_insert_nop(sc->sc_txdma, prev_stop);
754 BPF_MTAP(ifp, mb_head);
757 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
760 dbdma_wake(sc->sc_txdma);
761 sc->sc_wdog_timer = 5;
766 bm_encap(struct bm_softc *sc, struct mbuf **m_head)
768 bus_dma_segment_t segs[BM_NTXSEGS];
769 struct bm_txsoft *txs;
771 int nsegs = BM_NTXSEGS;
776 /* Limit the command size to the number of free DBDMA slots */
778 if (sc->next_txdma_slot >= sc->first_used_txdma_slot)
779 nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot +
780 sc->first_used_txdma_slot; /* -2 for branch and indexing */
782 nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot;
784 /* Remove one slot for the STOP/NOP terminator */
787 if (nsegs > BM_NTXSEGS)
790 /* Get a work queue entry. */
791 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
792 /* Ran out of descriptors. */
796 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap,
797 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
799 if (error == EFBIG) {
800 m = m_collapse(*m_head, M_DONTWAIT, nsegs);
808 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag,
809 txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
815 } else if (error != 0)
824 txs->txs_ndescs = nsegs;
825 txs->txs_firstdesc = sc->next_txdma_slot;
827 for (i = 0; i < nsegs; i++) {
828 /* Loop back to the beginning if this is our last slot */
829 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1))
830 branch_type = DBDMA_ALWAYS;
832 branch_type = DBDMA_NEVER;
835 txs->txs_lastdesc = sc->next_txdma_slot;
837 dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++,
838 (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST,
839 0, segs[i].ds_addr, segs[i].ds_len,
840 (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS,
841 branch_type, DBDMA_NEVER, 0);
843 if (branch_type == DBDMA_ALWAYS)
844 sc->next_txdma_slot = 0;
847 /* We have a corner case where the STOP command is the last slot,
848 * but you can't branch in STOP commands. So add a NOP branch here
849 * and the STOP in slot 0. */
851 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) {
852 dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0);
853 sc->next_txdma_slot = 0;
856 txs->txs_stopdesc = sc->next_txdma_slot;
857 dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++);
859 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
860 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
861 txs->txs_mbuf = *m_head;
867 bm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
869 struct bm_softc *sc = ifp->if_softc;
870 struct ifreq *ifr = (struct ifreq *)data;
878 if ((ifp->if_flags & IFF_UP) != 0) {
879 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
880 ((ifp->if_flags ^ sc->sc_ifpflags) &
881 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
885 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
887 sc->sc_ifpflags = ifp->if_flags;
897 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
900 error = ether_ioctl(ifp, cmd, data);
908 bm_setladrf(struct bm_softc *sc)
910 struct ifnet *ifp = sc->sc_ifp;
911 struct ifmultiaddr *inm;
916 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS;
918 /* Turn off RX MAC while we fiddle its settings */
919 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
920 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE)
923 if ((ifp->if_flags & IFF_PROMISC) != 0) {
926 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
930 reg = CSR_READ_2(sc, BM_RX_CONFIG);
932 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
936 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
937 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
939 /* Clear the hash table. */
940 memset(hash, 0, sizeof(hash));
943 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
944 if (inm->ifma_addr->sa_family != AF_LINK)
946 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
947 inm->ifma_addr), ETHER_ADDR_LEN);
949 /* We just want the 6 most significant bits */
952 /* Set the corresponding bit in the filter. */
953 hash[crc >> 4] |= 1 << (crc & 0xf);
955 if_maddr_runlock(ifp);
958 /* Write out new hash table */
959 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]);
960 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]);
961 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]);
962 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]);
964 /* And turn the RX MAC back on, this time with the hash bit set */
965 reg |= BM_HASH_FILTER_ENABLE;
966 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
968 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE))
971 reg = CSR_READ_2(sc, BM_RX_CONFIG);
973 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
979 struct bm_softc *sc = xsc;
987 bm_chip_setup(struct bm_softc *sc)
990 uint16_t *eaddr_sect;
992 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
993 dbdma_stop(sc->sc_txdma);
994 dbdma_stop(sc->sc_rxdma);
997 CSR_WRITE_2(sc, BM_RX_RESET, 0x0000);
998 CSR_WRITE_2(sc, BM_TX_RESET, 0x0001);
1001 reg = CSR_READ_2(sc, BM_TX_RESET);
1002 } while (reg & 0x0001);
1004 /* Some random junk. OS X uses the system time. We use
1005 * the low 16 bits of the MAC address. */
1006 CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]);
1008 /* Enable transmit */
1009 reg = CSR_READ_2(sc, BM_TX_IFC);
1011 CSR_WRITE_2(sc, BM_TX_IFC, reg);
1013 CSR_READ_2(sc, BM_TX_PEAKCNT);
1017 bm_stop(struct bm_softc *sc)
1019 struct bm_txsoft *txs;
1022 /* Disable TX and RX MACs */
1023 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1025 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1027 reg = CSR_READ_2(sc, BM_RX_CONFIG);
1029 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1033 /* Stop DMA engine */
1034 dbdma_stop(sc->sc_rxdma);
1035 dbdma_stop(sc->sc_txdma);
1036 sc->next_rxdma_slot = 0;
1037 sc->rxdma_loop_slot = 0;
1039 /* Disable interrupts */
1040 bm_disable_interrupts(sc);
1042 /* Don't worry about pending transmits anymore */
1043 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1044 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1045 if (txs->txs_ndescs != 0) {
1046 bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap,
1047 BUS_DMASYNC_POSTWRITE);
1048 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
1049 if (txs->txs_mbuf != NULL) {
1050 m_freem(txs->txs_mbuf);
1051 txs->txs_mbuf = NULL;
1054 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1057 /* And we're down */
1058 sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1059 sc->sc_wdog_timer = 0;
1060 callout_stop(&sc->sc_tick_ch);
1064 bm_init_locked(struct bm_softc *sc)
1067 uint16_t *eaddr_sect;
1068 struct bm_rxsoft *rxs;
1071 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
1073 /* Zero RX slot info and stop DMA */
1074 dbdma_stop(sc->sc_rxdma);
1075 dbdma_stop(sc->sc_txdma);
1076 sc->next_rxdma_slot = 0;
1077 sc->rxdma_loop_slot = 0;
1079 /* Initialize TX/RX DBDMA programs */
1080 dbdma_insert_stop(sc->sc_rxdma, 0);
1081 dbdma_insert_stop(sc->sc_txdma, 0);
1082 dbdma_set_current_cmd(sc->sc_rxdma, 0);
1083 dbdma_set_current_cmd(sc->sc_txdma, 0);
1085 sc->next_rxdma_slot = 0;
1086 sc->next_txdma_slot = 1;
1087 sc->first_used_txdma_slot = 0;
1089 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
1090 rxs = &sc->sc_rxsoft[i];
1091 rxs->dbdma_slot = i;
1093 if (rxs->rxs_mbuf == NULL) {
1094 bm_add_rxbuf(sc, i);
1096 if (rxs->rxs_mbuf == NULL) {
1097 /* If we can't add anymore, mark the problem */
1098 rxs->dbdma_slot = -1;
1104 bm_add_rxbuf_dma(sc, i);
1108 * Now terminate the RX ring buffer, and follow with the loop to
1111 dbdma_insert_stop(sc->sc_rxdma, i - 1);
1112 dbdma_insert_branch(sc->sc_rxdma, i, 0);
1113 sc->rxdma_loop_slot = i;
1115 /* Now add in the first element of the RX DMA chain */
1116 bm_add_rxbuf_dma(sc, 0);
1118 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
1119 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
1121 /* Zero collision counters */
1122 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1123 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1124 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1125 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1127 /* Zero receive counters */
1128 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1129 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1130 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1131 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1132 CSR_WRITE_2(sc, BM_RXCV, 0);
1134 /* Prime transmit */
1135 CSR_WRITE_2(sc, BM_TX_THRESH, 0xff);
1137 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0);
1138 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001);
1141 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0);
1142 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001);
1144 /* Clear status reg */
1145 CSR_READ_2(sc, BM_STATUS);
1147 /* Zero hash filters */
1148 CSR_WRITE_2(sc, BM_HASHTAB0, 0);
1149 CSR_WRITE_2(sc, BM_HASHTAB1, 0);
1150 CSR_WRITE_2(sc, BM_HASHTAB2, 0);
1151 CSR_WRITE_2(sc, BM_HASHTAB3, 0);
1153 /* Write MAC address to chip */
1154 CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]);
1155 CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]);
1156 CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]);
1158 /* Final receive engine setup */
1159 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE;
1160 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1162 /* Now turn it all on! */
1163 dbdma_reset(sc->sc_rxdma);
1164 dbdma_reset(sc->sc_txdma);
1166 /* Enable RX and TX MACs. Setting the address filter has
1167 * the side effect of enabling the RX MAC. */
1170 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1172 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1175 * Enable interrupts, unwedge the controller with a dummy packet,
1176 * and nudge the DMA queue.
1178 bm_enable_interrupts(sc);
1180 dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */
1182 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING;
1183 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1184 sc->sc_ifpflags = sc->sc_ifp->if_flags;
1186 /* Resync PHY and MAC states */
1187 sc->sc_mii = device_get_softc(sc->sc_miibus);
1188 sc->sc_duplex = ~IFM_FDX;
1189 mii_mediachg(sc->sc_mii);
1191 /* Start the one second timer. */
1192 sc->sc_wdog_timer = 0;
1193 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1199 struct bm_softc *sc = arg;
1201 /* Read error counters */
1202 sc->sc_ifp->if_collisions += CSR_READ_2(sc, BM_TX_NCCNT) +
1203 CSR_READ_2(sc, BM_TX_FCCNT) + CSR_READ_2(sc, BM_TX_EXCNT) +
1204 CSR_READ_2(sc, BM_TX_LTCNT);
1206 sc->sc_ifp->if_ierrors += CSR_READ_2(sc, BM_RX_LECNT) +
1207 CSR_READ_2(sc, BM_RX_AECNT) + CSR_READ_2(sc, BM_RX_FECNT);
1209 /* Zero collision counters */
1210 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1211 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1212 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1213 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1215 /* Zero receive counters */
1216 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1217 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1218 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1219 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1220 CSR_WRITE_2(sc, BM_RXCV, 0);
1222 /* Check for link changes and run watchdog */
1223 mii_tick(sc->sc_mii);
1224 bm_miibus_statchg(sc->sc_dev);
1226 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) {
1227 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1232 device_printf(sc->sc_dev, "device timeout\n");
1238 bm_add_rxbuf(struct bm_softc *sc, int idx)
1240 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1242 bus_dma_segment_t segs[1];
1245 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1248 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1250 if (rxs->rxs_mbuf != NULL) {
1251 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap,
1252 BUS_DMASYNC_POSTREAD);
1253 bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap);
1256 error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m,
1257 segs, &nsegs, BUS_DMA_NOWAIT);
1259 device_printf(sc->sc_dev,
1260 "cannot load RS DMA map %d, error = %d\n", idx, error);
1264 /* If nsegs is wrong then the stack is corrupt. */
1266 ("%s: too many DMA segments (%d)", __func__, nsegs));
1268 rxs->segment = segs[0];
1270 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1276 bm_add_rxbuf_dma(struct bm_softc *sc, int idx)
1278 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1280 dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0,
1281 rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS,
1282 DBDMA_NEVER, DBDMA_NEVER, 0);
1288 bm_enable_interrupts(struct bm_softc *sc)
1290 CSR_WRITE_2(sc, BM_INTR_DISABLE,
1291 (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL);
1295 bm_disable_interrupts(struct bm_softc *sc)
1297 CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE);