2 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 CPL_PASS_OPEN_REQ = 0x1,
35 CPL_PASS_ACCEPT_RPL = 0x2,
36 CPL_ACT_OPEN_REQ = 0x3,
38 CPL_SET_TCB_FIELD = 0x5,
41 CPL_CLOSE_CON_REQ = 0x8,
42 CPL_CLOSE_LISTSRV_REQ = 0x9,
46 CPL_RX_DATA_ACK = 0xD,
48 CPL_RTE_DELETE_REQ = 0xF,
49 CPL_RTE_WRITE_REQ = 0x10,
50 CPL_RTE_READ_REQ = 0x11,
51 CPL_L2T_WRITE_REQ = 0x12,
52 CPL_L2T_READ_REQ = 0x13,
53 CPL_SMT_WRITE_REQ = 0x14,
54 CPL_SMT_READ_REQ = 0x15,
56 CPL_TID_RELEASE = 0x1A,
57 CPL_RX_MPS_PKT = 0x1B,
59 CPL_CLOSE_LISTSRV_RPL = 0x20,
61 CPL_GET_TCB_RPL = 0x22,
62 CPL_L2T_WRITE_RPL = 0x23,
63 CPL_PASS_OPEN_RPL = 0x24,
64 CPL_ACT_OPEN_RPL = 0x25,
65 CPL_PEER_CLOSE = 0x26,
66 CPL_RTE_DELETE_RPL = 0x27,
67 CPL_RTE_WRITE_RPL = 0x28,
68 CPL_RX_URG_PKT = 0x29,
69 CPL_ABORT_REQ_RSS = 0x2B,
70 CPL_RX_URG_NOTIFY = 0x2C,
71 CPL_ABORT_RPL_RSS = 0x2D,
72 CPL_SMT_WRITE_RPL = 0x2E,
73 CPL_TX_DATA_ACK = 0x2F,
75 CPL_RX_PHYS_ADDR = 0x30,
76 CPL_PCMD_READ_RPL = 0x31,
77 CPL_CLOSE_CON_RPL = 0x32,
79 CPL_L2T_READ_RPL = 0x34,
81 CPL_RDMA_CQE_READ_RSP = 0x36,
82 CPL_RDMA_CQE_ERR = 0x37,
83 CPL_RTE_READ_RPL = 0x38,
85 CPL_SET_TCB_RPL = 0x3A,
88 CPL_HIT_NOTIFY = 0x3D,
89 CPL_PKT_NOTIFY = 0x3E,
90 CPL_RX_DDP_COMPLETE = 0x3F,
92 CPL_ACT_ESTABLISH = 0x40,
93 CPL_PASS_ESTABLISH = 0x41,
94 CPL_RX_DATA_DDP = 0x42,
95 CPL_SMT_READ_RPL = 0x43,
96 CPL_PASS_ACCEPT_REQ = 0x44,
98 CPL_RX_FCOE_DDP = 0x46,
101 CPL_RDMA_READ_REQ = 0x60,
103 CPL_SET_LE_REQ = 0x80,
104 CPL_PASS_OPEN_REQ6 = 0x81,
105 CPL_ACT_OPEN_REQ6 = 0x83,
107 CPL_TX_DMA_ACK = 0xA0,
108 CPL_RDMA_TERMINATE = 0xA2,
109 CPL_RDMA_WRITE = 0xA4,
110 CPL_SGE_EGR_UPDATE = 0xA5,
111 CPL_SET_LE_RPL = 0xA6,
115 CPL_TRACE_PKT = 0xB0,
116 CPL_RX2TX_DATA = 0xB1,
124 CPL_TX_PKT_LSO = 0xED,
125 CPL_TX_PKT_XT = 0xEE,
127 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
132 CPL_ERR_TCAM_PARITY = 1,
133 CPL_ERR_TCAM_FULL = 3,
134 CPL_ERR_BAD_LENGTH = 15,
135 CPL_ERR_BAD_ROUTE = 18,
136 CPL_ERR_CONN_RESET = 20,
137 CPL_ERR_CONN_EXIST_SYNRECV = 21,
138 CPL_ERR_CONN_EXIST = 22,
139 CPL_ERR_ARP_MISS = 23,
140 CPL_ERR_BAD_SYN = 24,
141 CPL_ERR_CONN_TIMEDOUT = 30,
142 CPL_ERR_XMIT_TIMEDOUT = 31,
143 CPL_ERR_PERSIST_TIMEDOUT = 32,
144 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
145 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
146 CPL_ERR_RTX_NEG_ADVICE = 35,
147 CPL_ERR_PERSIST_NEG_ADVICE = 36,
148 CPL_ERR_ABORT_FAILED = 42,
149 CPL_ERR_IWARP_FLM = 50,
153 CPL_CONN_POLICY_AUTO = 0,
154 CPL_CONN_POLICY_ASK = 1,
155 CPL_CONN_POLICY_FILTER = 2,
156 CPL_CONN_POLICY_DENY = 3
168 ULP_CRC_HEADER = 1 << 0,
169 ULP_CRC_DATA = 1 << 1
173 CPL_PASS_OPEN_ACCEPT,
174 CPL_PASS_OPEN_REJECT,
175 CPL_PASS_OPEN_ACCEPT_TNL
179 CPL_ABORT_SEND_RST = 0,
183 enum { /* TX_PKT_XT checksum types */
197 enum { /* packet type in CPL_RX_PKT */
198 PKTYPE_XACT_UCAST = 0,
199 PKTYPE_HASH_UCAST = 1,
200 PKTYPE_XACT_MCAST = 2,
201 PKTYPE_HASH_MCAST = 3,
207 enum { /* DMAC type in CPL_RX_PKT */
213 enum { /* TCP congestion control algorithms */
220 enum { /* RSS hash type */
221 RSS_HASH_NONE = 0, /* no hash computed */
222 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */
223 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */
224 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */
227 enum { /* LE commands */
232 enum { /* LE request size */
246 #define S_CPL_OPCODE 24
247 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
248 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF)
249 #define G_TID(x) ((x) & 0xFFFFFF)
251 /* tid is assumed to be 24-bits */
252 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid))
254 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
256 /* extract the TID from a CPL command */
257 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
259 /* partitioning of TID fields that also carry a queue id */
261 #define M_TID_TID 0x3fff
262 #define V_TID_TID(x) ((x) << S_TID_TID)
263 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
266 #define M_TID_QID 0x3ff
267 #define V_TID_QID(x) ((x) << S_TID_QID)
268 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID)
278 #if defined(__LITTLE_ENDIAN_BITFIELD)
295 #if defined(__LITTLE_ENDIAN_BITFIELD)
314 #define S_HASHTYPE 20
315 #define M_HASHTYPE 0x3
316 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
319 #define M_QNUM 0xFFFF
320 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
323 struct work_request_hdr {
331 #define M_WR_LEN16 0xFF
332 #define V_WR_LEN16(x) ((x) << S_WR_LEN16)
333 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16)
338 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
339 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
341 # define WR_HDR struct work_request_hdr wr
342 # define WR_HDR_SIZE sizeof(struct work_request_hdr)
346 # define WR_HDR_SIZE 0
347 # define RSS_HDR struct rss_header rss_hdr;
350 /* option 0 fields */
351 #define S_ACCEPT_MODE 0
352 #define M_ACCEPT_MODE 0x3
353 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE)
354 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE)
357 #define M_TX_CHAN 0x3
358 #define V_TX_CHAN(x) ((x) << S_TX_CHAN)
359 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN)
362 #define V_NO_CONG(x) ((x) << S_NO_CONG)
363 #define F_NO_CONG V_NO_CONG(1U)
366 #define V_DELACK(x) ((x) << S_DELACK)
367 #define F_DELACK V_DELACK(1U)
369 #define S_INJECT_TIMER 6
370 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
371 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
373 #define S_NON_OFFLOAD 7
374 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
375 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
378 #define M_ULP_MODE 0xF
379 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
380 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
382 #define S_RCV_BUFSIZ 12
383 #define M_RCV_BUFSIZ 0x3FFU
384 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
385 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
389 #define V_DSCP(x) ((x) << S_DSCP)
390 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP)
392 #define S_SMAC_SEL 28
393 #define M_SMAC_SEL 0xFF
394 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
395 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL)
398 #define M_L2T_IDX 0xFFF
399 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX)
400 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
402 #define S_TCAM_BYPASS 48
403 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
404 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
407 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE)
408 #define F_NAGLE V_NAGLE(1ULL)
410 #define S_WND_SCALE 50
411 #define M_WND_SCALE 0xF
412 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE)
413 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
415 #define S_KEEP_ALIVE 54
416 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE)
417 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL)
421 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT)
422 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT)
424 #define S_MAX_RT_OVERRIDE 59
425 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE)
426 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL)
429 #define M_MSS_IDX 0xF
430 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
431 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
433 /* option 1 fields */
434 #define S_SYN_RSS_ENABLE 0
435 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE)
436 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U)
438 #define S_SYN_RSS_USE_HASH 1
439 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH)
440 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U)
442 #define S_SYN_RSS_QUEUE 2
443 #define M_SYN_RSS_QUEUE 0x3FF
444 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE)
445 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE)
447 #define S_LISTEN_INTF 12
448 #define M_LISTEN_INTF 0xFF
449 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF)
450 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF)
452 #define S_LISTEN_FILTER 20
453 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER)
454 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U)
456 #define S_SYN_DEFENSE 21
457 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
458 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
460 #define S_CONN_POLICY 22
461 #define M_CONN_POLICY 0x3
462 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
463 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
465 /* option 2 fields */
466 #define S_RSS_QUEUE 0
467 #define M_RSS_QUEUE 0x3FF
468 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
469 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
471 #define S_RSS_QUEUE_VALID 10
472 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
473 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
475 #define S_RX_COALESCE_VALID 11
476 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
477 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
479 #define S_RX_COALESCE 12
480 #define M_RX_COALESCE 0x3
481 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
482 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
484 #define S_CONG_CNTRL 14
485 #define M_CONG_CNTRL 0x3
486 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
487 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL)
491 #define V_PACE(x) ((x) << S_PACE)
492 #define G_PACE(x) (((x) >> S_PACE) & M_PACE)
494 #define S_CONG_CNTRL_VALID 18
495 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID)
496 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U)
498 #define S_PACE_VALID 19
499 #define V_PACE_VALID(x) ((x) << S_PACE_VALID)
500 #define F_PACE_VALID V_PACE_VALID(1U)
502 #define S_RX_FC_DISABLE 20
503 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
504 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
506 #define S_RX_FC_DDP 21
507 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP)
508 #define F_RX_FC_DDP V_RX_FC_DDP(1U)
510 #define S_RX_FC_VALID 22
511 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
512 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
514 #define S_TX_QUEUE 23
515 #define M_TX_QUEUE 0x7
516 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE)
517 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE)
519 #define S_RX_CHANNEL 26
520 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
521 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
523 #define S_CCTRL_ECN 27
524 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN)
525 #define F_CCTRL_ECN V_CCTRL_ECN(1U)
527 #define S_WND_SCALE_EN 28
528 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN)
529 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U)
531 #define S_TSTAMPS_EN 29
532 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN)
533 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U)
536 #define V_SACK_EN(x) ((x) << S_SACK_EN)
537 #define F_SACK_EN V_SACK_EN(1U)
539 struct cpl_pass_open_req {
550 struct cpl_pass_open_req6 {
563 struct cpl_pass_open_rpl {
570 struct cpl_pass_establish {
581 /* cpl_pass_establish.tos_stid fields */
582 #define S_PASS_OPEN_TID 0
583 #define M_PASS_OPEN_TID 0xFFFFFF
584 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
585 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
587 #define S_PASS_OPEN_TOS 24
588 #define M_PASS_OPEN_TOS 0xFF
589 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
590 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
592 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
593 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
594 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
595 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
596 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
597 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
599 struct cpl_pass_accept_req {
608 struct tcp_options tcpopt;
611 /* cpl_pass_accept_req.hdr_len fields */
612 #define S_SYN_RX_CHAN 0
613 #define M_SYN_RX_CHAN 0xF
614 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN)
615 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN)
617 #define S_TCP_HDR_LEN 10
618 #define M_TCP_HDR_LEN 0x3F
619 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
620 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN)
622 #define S_IP_HDR_LEN 16
623 #define M_IP_HDR_LEN 0x3FF
624 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
625 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN)
627 #define S_ETH_HDR_LEN 26
628 #define M_ETH_HDR_LEN 0x1F
629 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
630 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN)
632 /* cpl_pass_accept_req.l2info fields */
633 #define S_SYN_MAC_IDX 0
634 #define M_SYN_MAC_IDX 0x1FF
635 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX)
636 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX)
638 #define S_SYN_XACT_MATCH 9
639 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH)
640 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U)
642 #define S_SYN_INTF 12
643 #define M_SYN_INTF 0xF
644 #define V_SYN_INTF(x) ((x) << S_SYN_INTF)
645 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF)
647 struct cpl_pass_accept_rpl {
654 struct cpl_act_open_req {
666 /* cpl_act_open_req.params fields XXX */
667 #define S_AOPEN_VLAN_PRI 9
668 #define M_AOPEN_VLAN_PRI 0x3
669 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
670 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
672 #define S_AOPEN_VLAN_PRI_VALID 11
673 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
674 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U)
676 #define S_AOPEN_PKT_TYPE 12
677 #define M_AOPEN_PKT_TYPE 0x3
678 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
679 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
681 #define S_AOPEN_MAC_MATCH 14
682 #define M_AOPEN_MAC_MATCH 0x1F
683 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
684 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
686 #define S_AOPEN_MAC_MATCH_VALID 19
687 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
688 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U)
690 #define S_AOPEN_IFF_VLAN 20
691 #define M_AOPEN_IFF_VLAN 0xFFF
692 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
693 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
695 struct cpl_act_open_req6 {
709 struct cpl_act_open_rpl {
715 /* cpl_act_open_rpl.atid_status fields */
716 #define S_AOPEN_STATUS 0
717 #define M_AOPEN_STATUS 0xFF
718 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS)
719 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
721 #define S_AOPEN_ATID 8
722 #define M_AOPEN_ATID 0xFFFFFF
723 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID)
724 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
726 struct cpl_act_establish {
744 /* cpl_get_tcb.reply_ctrl fields */
746 #define M_QUEUENO 0x3FF
747 #define V_QUEUENO(x) ((x) << S_QUEUENO)
748 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO)
750 #define S_REPLY_CHAN 14
751 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
752 #define F_REPLY_CHAN V_REPLY_CHAN(1U)
754 #define S_NO_REPLY 15
755 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
756 #define F_NO_REPLY V_NO_REPLY(1U)
758 struct cpl_get_tcb_rpl {
773 struct cpl_set_tcb_field {
782 /* cpl_set_tcb_field.word_cookie fields */
785 #define V_WORD(x) ((x) << S_WORD)
786 #define G_WORD(x) (((x) >> S_WORD) & M_WORD)
790 #define V_COOKIE(x) ((x) << S_COOKIE)
791 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
793 struct cpl_set_tcb_rpl {
802 struct cpl_close_con_req {
808 struct cpl_close_con_rpl {
817 struct cpl_close_listsvr_req {
824 /* additional cpl_close_listsvr_req.reply_ctrl field */
825 #define S_LISTSVR_IPV6 14
826 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6)
827 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U)
829 struct cpl_close_listsvr_rpl {
836 struct cpl_abort_req_rss {
843 struct cpl_abort_req {
852 struct cpl_abort_rpl_rss {
859 struct cpl_abort_rpl {
868 struct cpl_peer_close {
874 struct cpl_tid_release {
889 /* tx_data_wr.flags fields */
890 #define S_TX_ACK_PAGES 21
891 #define M_TX_ACK_PAGES 0x7
892 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
893 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
895 /* tx_data_wr.param fields */
897 #define M_TX_PORT 0x7
898 #define V_TX_PORT(x) ((x) << S_TX_PORT)
899 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
903 #define V_TX_MSS(x) ((x) << S_TX_MSS)
904 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
907 #define M_TX_QOS 0xFF
908 #define V_TX_QOS(x) ((x) << S_TX_QOS)
909 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
911 #define S_TX_SNDBUF 16
912 #define M_TX_SNDBUF 0xFFFF
913 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
914 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
923 /* cpl_tx_data.flags fields */
925 #define V_TX_PROXY(x) ((x) << S_TX_PROXY)
926 #define F_TX_PROXY V_TX_PROXY(1U)
928 #define S_TX_ULP_SUBMODE 6
929 #define M_TX_ULP_SUBMODE 0xF
930 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
931 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
933 #define S_TX_ULP_MODE 10
934 #define M_TX_ULP_MODE 0xF
935 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
936 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
938 #define S_TX_SHOVE 14
939 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
940 #define F_TX_SHOVE V_TX_SHOVE(1U)
943 #define V_TX_MORE(x) ((x) << S_TX_MORE)
944 #define F_TX_MORE V_TX_MORE(1U)
947 #define V_TX_URG(x) ((x) << S_TX_URG)
948 #define F_TX_URG V_TX_URG(1U)
950 #define S_TX_FLUSH 17
951 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH)
952 #define F_TX_FLUSH V_TX_FLUSH(1U)
955 #define V_TX_SAVE(x) ((x) << S_TX_SAVE)
956 #define F_TX_SAVE V_TX_SAVE(1U)
959 #define V_TX_TNL(x) ((x) << S_TX_TNL)
960 #define F_TX_TNL V_TX_TNL(1U)
962 /* additional tx_data_wr.flags fields */
963 #define S_TX_CPU_IDX 0
964 #define M_TX_CPU_IDX 0x3F
965 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
966 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
968 #define S_TX_CLOSE 17
969 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
970 #define F_TX_CLOSE V_TX_CLOSE(1U)
973 #define V_TX_INIT(x) ((x) << S_TX_INIT)
974 #define F_TX_INIT V_TX_INIT(1U)
976 #define S_TX_IMM_ACK 19
977 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
978 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
980 #define S_TX_IMM_DMA 20
981 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
982 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
984 struct cpl_tx_data_ack {
990 struct cpl_wr_ack { /* XXX */
999 struct cpl_tx_pkt_core {
1008 struct cpl_tx_pkt_core c;
1011 #define cpl_tx_pkt_xt cpl_tx_pkt
1013 /* cpl_tx_pkt_core.ctrl0 fields */
1014 #define S_TXPKT_VF 0
1015 #define M_TXPKT_VF 0xFF
1016 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF)
1017 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF)
1019 #define S_TXPKT_PF 8
1020 #define M_TXPKT_PF 0x7
1021 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
1022 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
1024 #define S_TXPKT_VF_VLD 11
1025 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD)
1026 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U)
1028 #define S_TXPKT_OVLAN_IDX 12
1029 #define M_TXPKT_OVLAN_IDX 0xF
1030 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
1031 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX)
1033 #define S_TXPKT_INTF 16
1034 #define M_TXPKT_INTF 0xF
1035 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1036 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1038 #define S_TXPKT_SPECIAL_STAT 20
1039 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
1040 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U)
1042 #define S_TXPKT_INS_OVLAN 21
1043 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
1044 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U)
1046 #define S_TXPKT_STAT_DIS 22
1047 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
1048 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U)
1050 #define S_TXPKT_LOOPBACK 23
1051 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1052 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1054 #define S_TXPKT_OPCODE 24
1055 #define M_TXPKT_OPCODE 0xFF
1056 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1057 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1059 /* cpl_tx_pkt_core.ctrl1 fields */
1060 #define S_TXPKT_SA_IDX 0
1061 #define M_TXPKT_SA_IDX 0xFFF
1062 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX)
1063 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX)
1065 #define S_TXPKT_CSUM_END 12
1066 #define M_TXPKT_CSUM_END 0xFF
1067 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END)
1068 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END)
1070 #define S_TXPKT_CSUM_START 20
1071 #define M_TXPKT_CSUM_START 0x3FF
1072 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START)
1073 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START)
1075 #define S_TXPKT_IPHDR_LEN 20
1076 #define M_TXPKT_IPHDR_LEN 0x3FFF
1077 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
1078 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
1080 #define S_TXPKT_CSUM_LOC 30
1081 #define M_TXPKT_CSUM_LOC 0x3FF
1082 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC)
1083 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC)
1085 #define S_TXPKT_ETHHDR_LEN 34
1086 #define M_TXPKT_ETHHDR_LEN 0x3F
1087 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
1088 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
1090 #define S_TXPKT_CSUM_TYPE 40
1091 #define M_TXPKT_CSUM_TYPE 0xF
1092 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
1093 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
1095 #define S_TXPKT_VLAN 44
1096 #define M_TXPKT_VLAN 0xFFFF
1097 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
1098 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1100 #define S_TXPKT_VLAN_VLD 60
1101 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
1102 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
1104 #define S_TXPKT_IPSEC 61
1105 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC)
1106 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL)
1108 #define S_TXPKT_IPCSUM_DIS 62
1109 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
1110 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
1112 #define S_TXPKT_L4CSUM_DIS 63
1113 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
1114 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
1116 struct cpl_tx_pkt_lso {
1120 __be32 seqno_offset;
1122 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1125 /* cpl_tx_pkt_lso.lso_ctrl fields */
1126 #define S_LSO_TCPHDR_LEN 0
1127 #define M_LSO_TCPHDR_LEN 0xF
1128 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
1129 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
1131 #define S_LSO_IPHDR_LEN 4
1132 #define M_LSO_IPHDR_LEN 0xFFF
1133 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
1134 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
1136 #define S_LSO_ETHHDR_LEN 16
1137 #define M_LSO_ETHHDR_LEN 0xF
1138 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
1139 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
1141 #define S_LSO_IPV6 20
1142 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1143 #define F_LSO_IPV6 V_LSO_IPV6(1U)
1145 #define S_LSO_OFLD_ENCAP 21
1146 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP)
1147 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U)
1149 #define S_LSO_LAST_SLICE 22
1150 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
1151 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
1153 #define S_LSO_FIRST_SLICE 23
1154 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
1155 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
1157 #define S_LSO_OPCODE 24
1158 #define M_LSO_OPCODE 0xFF
1159 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
1160 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
1162 /* cpl_tx_pkt_lso.mss fields */
1164 #define M_LSO_MSS 0x3FFF
1165 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1166 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1168 #define S_LSO_IPID_SPLIT 15
1169 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT)
1170 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U)
1172 struct cpl_tx_pkt_coalesce {
1178 struct tx_pkt_coalesce_wr {
1180 #if !(defined C99_NOT_SUPPORTED)
1181 struct cpl_tx_pkt_coalesce cpl[0];
1185 struct mngt_pktsched_wr {
1198 struct cpl_iscsi_hdr_no_rss {
1199 union opcode_tid ot;
1208 struct cpl_iscsi_hdr {
1210 union opcode_tid ot;
1219 /* cpl_iscsi_hdr.pdu_len_ddp fields */
1220 #define S_ISCSI_PDU_LEN 0
1221 #define M_ISCSI_PDU_LEN 0x7FFF
1222 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
1223 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
1225 #define S_ISCSI_DDP 15
1226 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
1227 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
1229 struct cpl_rx_data {
1231 union opcode_tid ot;
1236 #if defined(__LITTLE_ENDIAN_BITFIELD)
1252 struct cpl_fcoe_hdr {
1254 union opcode_tid ot;
1268 struct cpl_rx_urg_notify {
1270 union opcode_tid ot;
1274 struct cpl_rx_urg_pkt {
1276 union opcode_tid ot;
1281 struct cpl_rx_data_ack {
1283 union opcode_tid ot;
1287 /* cpl_rx_data_ack.ack_seq fields */
1288 #define S_RX_CREDITS 0
1289 #define M_RX_CREDITS 0x3FFFFFF
1290 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1291 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1293 #define S_RX_MODULATE_TX 26
1294 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX)
1295 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U)
1297 #define S_RX_MODULATE_RX 27
1298 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX)
1299 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U)
1301 #define S_RX_FORCE_ACK 28
1302 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1303 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
1305 #define S_RX_DACK_MODE 29
1306 #define M_RX_DACK_MODE 0x3
1307 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1308 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1310 #define S_RX_DACK_CHANGE 31
1311 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1312 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
1314 struct cpl_rx_ddp_complete {
1316 union opcode_tid ot;
1322 struct cpl_rx_data_ddp {
1324 union opcode_tid ot;
1336 struct cpl_rx_fcoe_ddp {
1338 union opcode_tid ot;
1347 /* cpl_rx_{data,fcoe}_ddp.ddpvld fields */
1348 #define S_DDP_VALID 15
1349 #define M_DDP_VALID 0x1FFFF
1350 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1351 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1353 #define S_DDP_PPOD_MISMATCH 15
1354 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1355 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1357 #define S_DDP_PDU 16
1358 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1359 #define F_DDP_PDU V_DDP_PDU(1U)
1361 #define S_DDP_LLIMIT_ERR 17
1362 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1363 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1365 #define S_DDP_PPOD_PARITY_ERR 18
1366 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1367 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1369 #define S_DDP_PADDING_ERR 19
1370 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1371 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1373 #define S_DDP_HDRCRC_ERR 20
1374 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1375 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1377 #define S_DDP_DATACRC_ERR 21
1378 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1379 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1381 #define S_DDP_INVALID_TAG 22
1382 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1383 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1385 #define S_DDP_ULIMIT_ERR 23
1386 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1387 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1389 #define S_DDP_OFFSET_ERR 24
1390 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1391 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1393 #define S_DDP_COLOR_ERR 25
1394 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1395 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1397 #define S_DDP_TID_MISMATCH 26
1398 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1399 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1401 #define S_DDP_INVALID_PPOD 27
1402 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1403 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1405 #define S_DDP_ULP_MODE 28
1406 #define M_DDP_ULP_MODE 0xF
1407 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1408 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1410 /* cpl_rx_{data,fcoe}_ddp.ddp_report fields */
1411 #define S_DDP_OFFSET 0
1412 #define M_DDP_OFFSET 0xFFFFFF
1413 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1414 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1416 #define S_DDP_DACK_MODE 24
1417 #define M_DDP_DACK_MODE 0x3
1418 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1419 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1421 #define S_DDP_BUF_IDX 26
1422 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1423 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1425 #define S_DDP_URG 27
1426 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1427 #define F_DDP_URG V_DDP_URG(1U)
1429 #define S_DDP_PSH 28
1430 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1431 #define F_DDP_PSH V_DDP_PSH(1U)
1433 #define S_DDP_BUF_COMPLETE 29
1434 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1435 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1437 #define S_DDP_BUF_TIMED_OUT 30
1438 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1439 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1441 #define S_DDP_INV 31
1442 #define V_DDP_INV(x) ((x) << S_DDP_INV)
1443 #define F_DDP_INV V_DDP_INV(1U)
1448 #if defined(__LITTLE_ENDIAN_BITFIELD)
1469 /* rx_pkt.l2info fields */
1470 #define S_RX_ETHHDR_LEN 0
1471 #define M_RX_ETHHDR_LEN 0x1F
1472 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
1473 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
1475 #define S_RX_PKTYPE 5
1476 #define M_RX_PKTYPE 0x7
1477 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE)
1478 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE)
1480 #define S_RX_MACIDX 8
1481 #define M_RX_MACIDX 0x1FF
1482 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
1483 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
1485 #define S_RX_DATYPE 18
1486 #define M_RX_DATYPE 0x3
1487 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE)
1488 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE)
1490 #define S_RXF_PSH 20
1491 #define V_RXF_PSH(x) ((x) << S_RXF_PSH)
1492 #define F_RXF_PSH V_RXF_PSH(1U)
1494 #define S_RXF_SYN 21
1495 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
1496 #define F_RXF_SYN V_RXF_SYN(1U)
1498 #define S_RXF_UDP 22
1499 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
1500 #define F_RXF_UDP V_RXF_UDP(1U)
1502 #define S_RXF_TCP 23
1503 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
1504 #define F_RXF_TCP V_RXF_TCP(1U)
1507 #define V_RXF_IP(x) ((x) << S_RXF_IP)
1508 #define F_RXF_IP V_RXF_IP(1U)
1510 #define S_RXF_IP6 25
1511 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
1512 #define F_RXF_IP6 V_RXF_IP6(1U)
1514 #define S_RXF_SYN_COOKIE 26
1515 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE)
1516 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U)
1518 #define S_RXF_FCOE 26
1519 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE)
1520 #define F_RXF_FCOE V_RXF_FCOE(1U)
1522 #define S_RXF_LRO 27
1523 #define V_RXF_LRO(x) ((x) << S_RXF_LRO)
1524 #define F_RXF_LRO V_RXF_LRO(1U)
1526 #define S_RX_CHAN 28
1527 #define M_RX_CHAN 0xF
1528 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
1529 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
1531 /* rx_pkt.hdr_len fields */
1532 #define S_RX_TCPHDR_LEN 0
1533 #define M_RX_TCPHDR_LEN 0x3F
1534 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
1535 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
1537 #define S_RX_IPHDR_LEN 6
1538 #define M_RX_IPHDR_LEN 0x3FF
1539 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
1540 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
1542 /* rx_pkt.err_vec fields */
1543 #define S_RXERR_OR 0
1544 #define V_RXERR_OR(x) ((x) << S_RXERR_OR)
1545 #define F_RXERR_OR V_RXERR_OR(1U)
1547 #define S_RXERR_MAC 1
1548 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC)
1549 #define F_RXERR_MAC V_RXERR_MAC(1U)
1551 #define S_RXERR_IPVERS 2
1552 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS)
1553 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U)
1555 #define S_RXERR_FRAG 3
1556 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG)
1557 #define F_RXERR_FRAG V_RXERR_FRAG(1U)
1559 #define S_RXERR_ATTACK 4
1560 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK)
1561 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U)
1563 #define S_RXERR_ETHHDR_LEN 5
1564 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN)
1565 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U)
1567 #define S_RXERR_IPHDR_LEN 6
1568 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN)
1569 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U)
1571 #define S_RXERR_TCPHDR_LEN 7
1572 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN)
1573 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U)
1575 #define S_RXERR_PKT_LEN 8
1576 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN)
1577 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U)
1579 #define S_RXERR_TCP_OPT 9
1580 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT)
1581 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U)
1583 #define S_RXERR_IPCSUM 12
1584 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM)
1585 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U)
1587 #define S_RXERR_CSUM 13
1588 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM)
1589 #define F_RXERR_CSUM V_RXERR_CSUM(1U)
1591 #define S_RXERR_PING 14
1592 #define V_RXERR_PING(x) ((x) << S_RXERR_PING)
1593 #define F_RXERR_PING V_RXERR_PING(1U)
1595 struct cpl_trace_pkt {
1599 #if defined(__LITTLE_ENDIAN_BITFIELD)
1617 struct cpl_rte_delete_req {
1619 union opcode_tid ot;
1623 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */
1624 #define S_RTE_REQ_LUT_IX 8
1625 #define M_RTE_REQ_LUT_IX 0x7FF
1626 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1627 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1629 #define S_RTE_REQ_LUT_BASE 19
1630 #define M_RTE_REQ_LUT_BASE 0x7FF
1631 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1632 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1634 #define S_RTE_READ_REQ_SELECT 31
1635 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1636 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1638 struct cpl_rte_delete_rpl {
1640 union opcode_tid ot;
1645 struct cpl_rte_write_req {
1647 union opcode_tid ot;
1655 /* cpl_rte_write_req.write_sel fields */
1656 #define S_RTE_WR_L2TIDX 31
1657 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX)
1658 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U)
1660 #define S_RTE_WR_FADDR 30
1661 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR)
1662 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U)
1664 /* cpl_rte_write_req.lut_params fields */
1665 #define S_RTE_WR_LUT_IX 10
1666 #define M_RTE_WR_LUT_IX 0x7FF
1667 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX)
1668 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX)
1670 #define S_RTE_WR_LUT_BASE 21
1671 #define M_RTE_WR_LUT_BASE 0x7FF
1672 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE)
1673 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE)
1675 struct cpl_rte_write_rpl {
1677 union opcode_tid ot;
1682 struct cpl_rte_read_req {
1684 union opcode_tid ot;
1688 struct cpl_rte_read_rpl {
1690 union opcode_tid ot;
1694 #if defined(__LITTLE_ENDIAN_BITFIELD)
1704 struct cpl_l2t_write_req {
1706 union opcode_tid ot;
1713 /* cpl_l2t_write_req.params fields */
1714 #define S_L2T_W_INFO 2
1715 #define M_L2T_W_INFO 0x3F
1716 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO)
1717 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO)
1719 #define S_L2T_W_PORT 8
1720 #define M_L2T_W_PORT 0xF
1721 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
1722 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT)
1724 #define S_L2T_W_NOREPLY 15
1725 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
1726 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U)
1728 struct cpl_l2t_write_rpl {
1730 union opcode_tid ot;
1735 struct cpl_l2t_read_req {
1737 union opcode_tid ot;
1741 struct cpl_l2t_read_rpl {
1743 union opcode_tid ot;
1745 #if defined(__LITTLE_ENDIAN_BITFIELD)
1757 struct cpl_smt_write_req {
1759 union opcode_tid ot;
1767 /* cpl_smt_{read,write}_req.params fields */
1768 #define S_SMTW_OVLAN_IDX 16
1769 #define M_SMTW_OVLAN_IDX 0xF
1770 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX)
1771 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX)
1773 #define S_SMTW_IDX 20
1774 #define M_SMTW_IDX 0x7F
1775 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX)
1776 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX)
1778 #define S_SMTW_NORPL 31
1779 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL)
1780 #define F_SMTW_NORPL V_SMTW_NORPL(1U)
1782 /* cpl_smt_{read,write}_req.pfvf? fields */
1784 #define M_SMTW_VF 0xFF
1785 #define V_SMTW_VF(x) ((x) << S_SMTW_VF)
1786 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF)
1789 #define M_SMTW_PF 0x7
1790 #define V_SMTW_PF(x) ((x) << S_SMTW_PF)
1791 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF)
1793 #define S_SMTW_VF_VLD 11
1794 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD)
1795 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U)
1797 struct cpl_smt_write_rpl {
1799 union opcode_tid ot;
1804 struct cpl_smt_read_req {
1806 union opcode_tid ot;
1810 struct cpl_smt_read_rpl {
1812 union opcode_tid ot;
1822 struct cpl_barrier {
1830 /* cpl_barrier.chan_map fields */
1831 #define S_CHAN_MAP 4
1832 #define M_CHAN_MAP 0xF
1833 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP)
1834 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP)
1838 union opcode_tid ot;
1842 struct cpl_hit_notify {
1844 union opcode_tid ot;
1850 struct cpl_pkt_notify {
1852 union opcode_tid ot;
1859 /* cpl_{hit,pkt}_notify.info fields */
1860 #define S_NTFY_MAC_IDX 0
1861 #define M_NTFY_MAC_IDX 0x1FF
1862 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX)
1863 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX)
1865 #define S_NTFY_INTF 10
1866 #define M_NTFY_INTF 0xF
1867 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF)
1868 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF)
1870 #define S_NTFY_TCPHDR_LEN 14
1871 #define M_NTFY_TCPHDR_LEN 0xF
1872 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN)
1873 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN)
1875 #define S_NTFY_IPHDR_LEN 18
1876 #define M_NTFY_IPHDR_LEN 0x1FF
1877 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN)
1878 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN)
1880 #define S_NTFY_ETHHDR_LEN 27
1881 #define M_NTFY_ETHHDR_LEN 0x1F
1882 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN)
1883 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN)
1885 struct cpl_rdma_terminate {
1887 union opcode_tid ot;
1892 struct cpl_set_le_req {
1894 union opcode_tid ot;
1903 /* cpl_set_le_req.reply_ctrl additional fields */
1904 #define S_LE_REQ_IP6 13
1905 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6)
1906 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U)
1908 /* cpl_set_le_req.params fields */
1910 #define M_LE_CHAN 0x3
1911 #define V_LE_CHAN(x) ((x) << S_LE_CHAN)
1912 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN)
1914 #define S_LE_OFFSET 5
1915 #define M_LE_OFFSET 0x7
1916 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET)
1917 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET)
1920 #define V_LE_MORE(x) ((x) << S_LE_MORE)
1921 #define F_LE_MORE V_LE_MORE(1U)
1923 #define S_LE_REQSIZE 9
1924 #define M_LE_REQSIZE 0x7
1925 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE)
1926 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE)
1928 #define S_LE_REQCMD 12
1929 #define M_LE_REQCMD 0xF
1930 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD)
1931 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD)
1933 struct cpl_set_le_rpl {
1935 union opcode_tid ot;
1941 /* cpl_set_le_rpl.info fields */
1942 #define S_LE_RSPCMD 0
1943 #define M_LE_RSPCMD 0xF
1944 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD)
1945 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD)
1947 #define S_LE_RSPSIZE 4
1948 #define M_LE_RSPSIZE 0x7
1949 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE)
1950 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE)
1952 #define S_LE_RSPTYPE 7
1953 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE)
1954 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U)
1956 struct cpl_sge_egr_update {
1963 /* cpl_sge_egr_update.ot fields */
1965 #define M_EGR_QID 0x1FFFF
1966 #define V_EGR_QID(x) ((x) << S_EGR_QID)
1967 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID)
1969 struct cpl_fw2_pld {
1976 struct cpl_fw4_pld {
1987 struct cpl_fw6_pld {
1995 struct cpl_fw2_msg {
1997 union opcode_info oi;
2000 struct cpl_fw4_msg {
2009 struct cpl_fw4_ack {
2011 union opcode_tid ot;
2020 struct cpl_fw6_msg {
2029 /* cpl_fw6_msg.type values */
2031 FW6_TYPE_CMD_RPL = 0,
2034 /* ULP_TX opcodes */
2036 ULP_TX_MEM_READ = 2,
2037 ULP_TX_MEM_WRITE = 3,
2042 ULP_TX_SC_NOOP = 0x80,
2043 ULP_TX_SC_IMM = 0x81,
2044 ULP_TX_SC_DSGL = 0x82,
2045 ULP_TX_SC_ISGL = 0x83
2048 #define S_ULPTX_CMD 24
2049 #define M_ULPTX_CMD 0xFF
2050 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
2052 #define S_ULPTX_LEN16 0
2053 #define M_ULPTX_LEN16 0xFF
2054 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16)
2056 #define S_ULP_TX_SC_MORE 23
2057 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
2058 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
2060 struct ulptx_sge_pair {
2069 #if !(defined C99_NOT_SUPPORTED)
2070 struct ulptx_sge_pair sge[0];
2083 #if !(defined C99_NOT_SUPPORTED)
2084 struct ulptx_isge sge[0];
2088 struct ulptx_idata {
2093 #define S_ULPTX_NSGE 0
2094 #define M_ULPTX_NSGE 0xFFFF
2095 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
2100 __be32 len16; /* command length */
2101 __be32 dlen; /* data length in 32-byte units */
2105 /* additional ulp_mem_io.cmd fields */
2106 #define S_ULP_MEMIO_ORDER 23
2107 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
2108 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U)
2110 /* ulp_mem_io.lock_addr fields */
2111 #define S_ULP_MEMIO_ADDR 0
2112 #define M_ULP_MEMIO_ADDR 0x7FFFFFF
2113 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
2115 #define S_ULP_MEMIO_LOCK 31
2116 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
2117 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
2119 /* ulp_mem_io.dlen fields */
2120 #define S_ULP_MEMIO_DATA_LEN 0
2121 #define M_ULP_MEMIO_DATA_LEN 0x1F
2122 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
2129 /* ulp_txpkt.cmd_dest fields */
2130 #define S_ULP_TXPKT_DEST 16
2131 #define M_ULP_TXPKT_DEST 0x3
2132 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
2134 #define S_ULP_TXPKT_FID 4
2135 #define M_ULP_TXPKT_FID 0x7ff
2136 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
2138 #endif /* T4_MSG_H */