2 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 /* This file is automatically generated --- changes will be lost */
32 #define MYPF_BASE 0x1b000
33 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
35 #define PF0_BASE 0x1e000
36 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
38 #define PF1_BASE 0x1e400
39 #define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))
41 #define PF2_BASE 0x1e800
42 #define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))
44 #define PF3_BASE 0x1ec00
45 #define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))
47 #define PF4_BASE 0x1f000
48 #define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))
50 #define PF5_BASE 0x1f400
51 #define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))
53 #define PF6_BASE 0x1f800
54 #define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))
56 #define PF7_BASE 0x1fc00
57 #define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))
59 #define PF_STRIDE 0x400
60 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
61 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
63 #define MYPORT_BASE 0x1c000
64 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
66 #define PORT0_BASE 0x20000
67 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
69 #define PORT1_BASE 0x22000
70 #define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))
72 #define PORT2_BASE 0x24000
73 #define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))
75 #define PORT3_BASE 0x26000
76 #define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))
78 #define PORT_STRIDE 0x2000
79 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
80 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
82 #define VF_SGE_BASE 0x0
83 #define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
85 #define VF_MPS_BASE 0x100
86 #define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
88 #define VF_PL_BASE 0x200
89 #define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
91 #define VF_MBDATA_BASE 0x240
92 #define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
94 #define VF_CIM_BASE 0x300
95 #define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
97 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
98 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
100 #define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
101 #define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136
103 #define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8)
104 #define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136
106 #define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
107 #define NUM_PCIE_DMA_INSTANCES 4
109 #define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
110 #define NUM_PCIE_CMD_INSTANCES 2
112 #define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
113 #define NUM_PCIE_HMA_INSTANCES 1
115 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
116 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8
118 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
119 #define NUM_PCIE_MAILBOX_INSTANCES 1
121 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
122 #define NUM_PCIE_FW_INSTANCES 8
124 #define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
125 #define NUM_PCIE_FUNC_INSTANCES 256
127 #define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4)
128 #define NUM_PCIE_FID_INSTANCES 2048
130 #define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
131 #define NUM_PCIE_DMA_BUF_INSTANCES 4
133 #define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
134 #define NUM_MC_DDR3PHYDATX8_INSTANCES 9
136 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
137 #define NUM_MC_BIST_STATUS_INSTANCES 18
139 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
140 #define NUM_EDC_BIST_STATUS_INSTANCES 18
142 #define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4)
143 #define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16
145 #define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
146 #define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4
148 #define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
149 #define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4
151 #define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
152 #define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4
154 #define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4)
155 #define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4
157 #define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4)
158 #define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28
160 #define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4)
161 #define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28
163 #define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4)
164 #define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28
166 #define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4)
167 #define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28
169 #define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4)
170 #define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28
172 #define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4)
173 #define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28
175 #define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4)
176 #define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28
178 #define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4)
179 #define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28
181 #define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4)
182 #define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65
184 #define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4)
185 #define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9
187 #define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8)
188 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
190 #define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8)
191 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
193 #define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16)
194 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
196 #define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16)
197 #define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512
199 #define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16)
200 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
202 #define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16)
203 #define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512
205 #define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4)
206 #define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8
208 #define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8)
209 #define NUM_PL_VF_SLICE_L_INSTANCES 8
211 #define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8)
212 #define NUM_PL_VF_SLICE_H_INSTANCES 8
214 #define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4)
215 #define NUM_PL_FLR_VF_STATUS_INSTANCES 4
217 #define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4)
218 #define NUM_PL_VFID_MAP_INSTANCES 256
220 #define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4)
221 #define NUM_LE_DB_MASK_IPV4_INSTANCES 17
223 #define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4)
224 #define NUM_LE_DB_MASK_IPV6_INSTANCES 17
226 #define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
227 #define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
229 #define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
230 #define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17
232 #define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
233 #define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
235 #define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
236 #define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17
238 #define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
239 #define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17
241 #define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4)
242 #define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4
244 #define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4)
245 #define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12
247 #define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4)
248 #define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4
250 #define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4)
251 #define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12
253 #define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
254 #define NUM_UP_TSCH_CHANNEL_INSTANCES 4
256 #define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
257 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4
259 #define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16)
260 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128
262 #define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)
263 #define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
265 #define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
266 #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
268 /* registers for module SGE */
269 #define SGE_BASE_ADDR 0x1000
271 #define A_SGE_PF_KDOORBELL 0x0
274 #define M_QID 0x1ffffU
275 #define V_QID(x) ((x) << S_QID)
276 #define G_QID(x) (((x) >> S_QID) & M_QID)
279 #define V_DBPRIO(x) ((x) << S_DBPRIO)
280 #define F_DBPRIO V_DBPRIO(1U)
283 #define M_PIDX 0x3fffU
284 #define V_PIDX(x) ((x) << S_PIDX)
285 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
287 #define A_SGE_VF_KDOORBELL 0x0
288 #define A_SGE_PF_GTS 0x4
290 #define S_INGRESSQID 16
291 #define M_INGRESSQID 0xffffU
292 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
293 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
295 #define S_TIMERREG 13
296 #define M_TIMERREG 0x7U
297 #define V_TIMERREG(x) ((x) << S_TIMERREG)
298 #define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)
300 #define S_SEINTARM 12
301 #define V_SEINTARM(x) ((x) << S_SEINTARM)
302 #define F_SEINTARM V_SEINTARM(1U)
305 #define M_CIDXINC 0xfffU
306 #define V_CIDXINC(x) ((x) << S_CIDXINC)
307 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
309 #define A_SGE_VF_GTS 0x4
310 #define A_SGE_CONTROL 0x1008
312 #define S_IGRALLCPLTOFL 31
313 #define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
314 #define F_IGRALLCPLTOFL V_IGRALLCPLTOFL(1U)
316 #define S_FLSPLITMIN 22
317 #define M_FLSPLITMIN 0x1ffU
318 #define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
319 #define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)
321 #define S_FLSPLITMODE 20
322 #define M_FLSPLITMODE 0x3U
323 #define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
324 #define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)
326 #define S_DCASYSTYPE 19
327 #define V_DCASYSTYPE(x) ((x) << S_DCASYSTYPE)
328 #define F_DCASYSTYPE V_DCASYSTYPE(1U)
330 #define S_RXPKTCPLMODE 18
331 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
332 #define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U)
334 #define S_EGRSTATUSPAGESIZE 17
335 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
336 #define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U)
338 #define S_INGHINTENABLE1 15
339 #define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
340 #define F_INGHINTENABLE1 V_INGHINTENABLE1(1U)
342 #define S_INGHINTENABLE0 14
343 #define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
344 #define F_INGHINTENABLE0 V_INGHINTENABLE0(1U)
346 #define S_INGINTCOMPAREIDX 13
347 #define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
348 #define F_INGINTCOMPAREIDX V_INGINTCOMPAREIDX(1U)
350 #define S_PKTSHIFT 10
351 #define M_PKTSHIFT 0x7U
352 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
353 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
355 #define S_INGPCIEBOUNDARY 7
356 #define M_INGPCIEBOUNDARY 0x7U
357 #define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
358 #define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)
360 #define S_INGPADBOUNDARY 4
361 #define M_INGPADBOUNDARY 0x7U
362 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
363 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
365 #define S_EGRPCIEBOUNDARY 1
366 #define M_EGRPCIEBOUNDARY 0x7U
367 #define V_EGRPCIEBOUNDARY(x) ((x) << S_EGRPCIEBOUNDARY)
368 #define G_EGRPCIEBOUNDARY(x) (((x) >> S_EGRPCIEBOUNDARY) & M_EGRPCIEBOUNDARY)
370 #define S_GLOBALENABLE 0
371 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
372 #define F_GLOBALENABLE V_GLOBALENABLE(1U)
374 #define A_SGE_HOST_PAGE_SIZE 0x100c
376 #define S_HOSTPAGESIZEPF7 28
377 #define M_HOSTPAGESIZEPF7 0xfU
378 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
379 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
381 #define S_HOSTPAGESIZEPF6 24
382 #define M_HOSTPAGESIZEPF6 0xfU
383 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
384 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
386 #define S_HOSTPAGESIZEPF5 20
387 #define M_HOSTPAGESIZEPF5 0xfU
388 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
389 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
391 #define S_HOSTPAGESIZEPF4 16
392 #define M_HOSTPAGESIZEPF4 0xfU
393 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
394 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
396 #define S_HOSTPAGESIZEPF3 12
397 #define M_HOSTPAGESIZEPF3 0xfU
398 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
399 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
401 #define S_HOSTPAGESIZEPF2 8
402 #define M_HOSTPAGESIZEPF2 0xfU
403 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
404 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
406 #define S_HOSTPAGESIZEPF1 4
407 #define M_HOSTPAGESIZEPF1 0xfU
408 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
409 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
411 #define S_HOSTPAGESIZEPF0 0
412 #define M_HOSTPAGESIZEPF0 0xfU
413 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
414 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
416 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
418 #define S_QUEUESPERPAGEPF7 28
419 #define M_QUEUESPERPAGEPF7 0xfU
420 #define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
421 #define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)
423 #define S_QUEUESPERPAGEPF6 24
424 #define M_QUEUESPERPAGEPF6 0xfU
425 #define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
426 #define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)
428 #define S_QUEUESPERPAGEPF5 20
429 #define M_QUEUESPERPAGEPF5 0xfU
430 #define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
431 #define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)
433 #define S_QUEUESPERPAGEPF4 16
434 #define M_QUEUESPERPAGEPF4 0xfU
435 #define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
436 #define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)
438 #define S_QUEUESPERPAGEPF3 12
439 #define M_QUEUESPERPAGEPF3 0xfU
440 #define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
441 #define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)
443 #define S_QUEUESPERPAGEPF2 8
444 #define M_QUEUESPERPAGEPF2 0xfU
445 #define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
446 #define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)
448 #define S_QUEUESPERPAGEPF1 4
449 #define M_QUEUESPERPAGEPF1 0xfU
450 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
451 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
453 #define S_QUEUESPERPAGEPF0 0
454 #define M_QUEUESPERPAGEPF0 0xfU
455 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
456 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
458 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
460 #define S_QUEUESPERPAGEVFPF7 28
461 #define M_QUEUESPERPAGEVFPF7 0xfU
462 #define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
463 #define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
465 #define S_QUEUESPERPAGEVFPF6 24
466 #define M_QUEUESPERPAGEVFPF6 0xfU
467 #define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
468 #define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
470 #define S_QUEUESPERPAGEVFPF5 20
471 #define M_QUEUESPERPAGEVFPF5 0xfU
472 #define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
473 #define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
475 #define S_QUEUESPERPAGEVFPF4 16
476 #define M_QUEUESPERPAGEVFPF4 0xfU
477 #define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
478 #define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
480 #define S_QUEUESPERPAGEVFPF3 12
481 #define M_QUEUESPERPAGEVFPF3 0xfU
482 #define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
483 #define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
485 #define S_QUEUESPERPAGEVFPF2 8
486 #define M_QUEUESPERPAGEVFPF2 0xfU
487 #define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
488 #define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
490 #define S_QUEUESPERPAGEVFPF1 4
491 #define M_QUEUESPERPAGEVFPF1 0xfU
492 #define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
493 #define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
495 #define S_QUEUESPERPAGEVFPF0 0
496 #define M_QUEUESPERPAGEVFPF0 0xfU
497 #define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
498 #define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
500 #define A_SGE_USER_MODE_LIMITS 0x1018
502 #define S_OPCODE_MIN 24
503 #define M_OPCODE_MIN 0xffU
504 #define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
505 #define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)
507 #define S_OPCODE_MAX 16
508 #define M_OPCODE_MAX 0xffU
509 #define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
510 #define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)
512 #define S_LENGTH_MIN 8
513 #define M_LENGTH_MIN 0xffU
514 #define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
515 #define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)
517 #define S_LENGTH_MAX 0
518 #define M_LENGTH_MAX 0xffU
519 #define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
520 #define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)
522 #define A_SGE_WR_ERROR 0x101c
524 #define S_WR_ERROR_OPCODE 0
525 #define M_WR_ERROR_OPCODE 0xffU
526 #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
527 #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
529 #define A_SGE_PERR_INJECT 0x1020
532 #define M_MEMSEL 0x1fU
533 #define V_MEMSEL(x) ((x) << S_MEMSEL)
534 #define G_MEMSEL(x) (((x) >> S_MEMSEL) & M_MEMSEL)
536 #define S_INJECTDATAERR 0
537 #define V_INJECTDATAERR(x) ((x) << S_INJECTDATAERR)
538 #define F_INJECTDATAERR V_INJECTDATAERR(1U)
540 #define A_SGE_INT_CAUSE1 0x1024
542 #define S_PERR_FLM_CREDITFIFO 30
543 #define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
544 #define F_PERR_FLM_CREDITFIFO V_PERR_FLM_CREDITFIFO(1U)
546 #define S_PERR_IMSG_HINT_FIFO 29
547 #define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
548 #define F_PERR_IMSG_HINT_FIFO V_PERR_IMSG_HINT_FIFO(1U)
550 #define S_PERR_MC_PC 28
551 #define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
552 #define F_PERR_MC_PC V_PERR_MC_PC(1U)
554 #define S_PERR_MC_IGR_CTXT 27
555 #define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
556 #define F_PERR_MC_IGR_CTXT V_PERR_MC_IGR_CTXT(1U)
558 #define S_PERR_MC_EGR_CTXT 26
559 #define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
560 #define F_PERR_MC_EGR_CTXT V_PERR_MC_EGR_CTXT(1U)
562 #define S_PERR_MC_FLM 25
563 #define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
564 #define F_PERR_MC_FLM V_PERR_MC_FLM(1U)
566 #define S_PERR_PC_MCTAG 24
567 #define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
568 #define F_PERR_PC_MCTAG V_PERR_PC_MCTAG(1U)
570 #define S_PERR_PC_CHPI_RSP1 23
571 #define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
572 #define F_PERR_PC_CHPI_RSP1 V_PERR_PC_CHPI_RSP1(1U)
574 #define S_PERR_PC_CHPI_RSP0 22
575 #define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
576 #define F_PERR_PC_CHPI_RSP0 V_PERR_PC_CHPI_RSP0(1U)
578 #define S_PERR_DBP_PC_RSP_FIFO3 21
579 #define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
580 #define F_PERR_DBP_PC_RSP_FIFO3 V_PERR_DBP_PC_RSP_FIFO3(1U)
582 #define S_PERR_DBP_PC_RSP_FIFO2 20
583 #define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
584 #define F_PERR_DBP_PC_RSP_FIFO2 V_PERR_DBP_PC_RSP_FIFO2(1U)
586 #define S_PERR_DBP_PC_RSP_FIFO1 19
587 #define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
588 #define F_PERR_DBP_PC_RSP_FIFO1 V_PERR_DBP_PC_RSP_FIFO1(1U)
590 #define S_PERR_DBP_PC_RSP_FIFO0 18
591 #define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
592 #define F_PERR_DBP_PC_RSP_FIFO0 V_PERR_DBP_PC_RSP_FIFO0(1U)
594 #define S_PERR_DMARBT 17
595 #define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
596 #define F_PERR_DMARBT V_PERR_DMARBT(1U)
598 #define S_PERR_FLM_DBPFIFO 16
599 #define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
600 #define F_PERR_FLM_DBPFIFO V_PERR_FLM_DBPFIFO(1U)
602 #define S_PERR_FLM_MCREQ_FIFO 15
603 #define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
604 #define F_PERR_FLM_MCREQ_FIFO V_PERR_FLM_MCREQ_FIFO(1U)
606 #define S_PERR_FLM_HINTFIFO 14
607 #define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
608 #define F_PERR_FLM_HINTFIFO V_PERR_FLM_HINTFIFO(1U)
610 #define S_PERR_ALIGN_CTL_FIFO3 13
611 #define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
612 #define F_PERR_ALIGN_CTL_FIFO3 V_PERR_ALIGN_CTL_FIFO3(1U)
614 #define S_PERR_ALIGN_CTL_FIFO2 12
615 #define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
616 #define F_PERR_ALIGN_CTL_FIFO2 V_PERR_ALIGN_CTL_FIFO2(1U)
618 #define S_PERR_ALIGN_CTL_FIFO1 11
619 #define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
620 #define F_PERR_ALIGN_CTL_FIFO1 V_PERR_ALIGN_CTL_FIFO1(1U)
622 #define S_PERR_ALIGN_CTL_FIFO0 10
623 #define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
624 #define F_PERR_ALIGN_CTL_FIFO0 V_PERR_ALIGN_CTL_FIFO0(1U)
626 #define S_PERR_EDMA_FIFO3 9
627 #define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
628 #define F_PERR_EDMA_FIFO3 V_PERR_EDMA_FIFO3(1U)
630 #define S_PERR_EDMA_FIFO2 8
631 #define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
632 #define F_PERR_EDMA_FIFO2 V_PERR_EDMA_FIFO2(1U)
634 #define S_PERR_EDMA_FIFO1 7
635 #define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
636 #define F_PERR_EDMA_FIFO1 V_PERR_EDMA_FIFO1(1U)
638 #define S_PERR_EDMA_FIFO0 6
639 #define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
640 #define F_PERR_EDMA_FIFO0 V_PERR_EDMA_FIFO0(1U)
642 #define S_PERR_PD_FIFO3 5
643 #define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
644 #define F_PERR_PD_FIFO3 V_PERR_PD_FIFO3(1U)
646 #define S_PERR_PD_FIFO2 4
647 #define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
648 #define F_PERR_PD_FIFO2 V_PERR_PD_FIFO2(1U)
650 #define S_PERR_PD_FIFO1 3
651 #define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
652 #define F_PERR_PD_FIFO1 V_PERR_PD_FIFO1(1U)
654 #define S_PERR_PD_FIFO0 2
655 #define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
656 #define F_PERR_PD_FIFO0 V_PERR_PD_FIFO0(1U)
658 #define S_PERR_ING_CTXT_MIFRSP 1
659 #define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
660 #define F_PERR_ING_CTXT_MIFRSP V_PERR_ING_CTXT_MIFRSP(1U)
662 #define S_PERR_EGR_CTXT_MIFRSP 0
663 #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
664 #define F_PERR_EGR_CTXT_MIFRSP V_PERR_EGR_CTXT_MIFRSP(1U)
666 #define A_SGE_INT_ENABLE1 0x1028
667 #define A_SGE_PERR_ENABLE1 0x102c
668 #define A_SGE_INT_CAUSE2 0x1030
670 #define S_PERR_HINT_DELAY_FIFO1 30
671 #define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
672 #define F_PERR_HINT_DELAY_FIFO1 V_PERR_HINT_DELAY_FIFO1(1U)
674 #define S_PERR_HINT_DELAY_FIFO0 29
675 #define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
676 #define F_PERR_HINT_DELAY_FIFO0 V_PERR_HINT_DELAY_FIFO0(1U)
678 #define S_PERR_IMSG_PD_FIFO 28
679 #define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
680 #define F_PERR_IMSG_PD_FIFO V_PERR_IMSG_PD_FIFO(1U)
682 #define S_PERR_ULPTX_FIFO1 27
683 #define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
684 #define F_PERR_ULPTX_FIFO1 V_PERR_ULPTX_FIFO1(1U)
686 #define S_PERR_ULPTX_FIFO0 26
687 #define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
688 #define F_PERR_ULPTX_FIFO0 V_PERR_ULPTX_FIFO0(1U)
690 #define S_PERR_IDMA2IMSG_FIFO1 25
691 #define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
692 #define F_PERR_IDMA2IMSG_FIFO1 V_PERR_IDMA2IMSG_FIFO1(1U)
694 #define S_PERR_IDMA2IMSG_FIFO0 24
695 #define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
696 #define F_PERR_IDMA2IMSG_FIFO0 V_PERR_IDMA2IMSG_FIFO0(1U)
698 #define S_PERR_HEADERSPLIT_FIFO1 23
699 #define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
700 #define F_PERR_HEADERSPLIT_FIFO1 V_PERR_HEADERSPLIT_FIFO1(1U)
702 #define S_PERR_HEADERSPLIT_FIFO0 22
703 #define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
704 #define F_PERR_HEADERSPLIT_FIFO0 V_PERR_HEADERSPLIT_FIFO0(1U)
706 #define S_PERR_ESWITCH_FIFO3 21
707 #define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
708 #define F_PERR_ESWITCH_FIFO3 V_PERR_ESWITCH_FIFO3(1U)
710 #define S_PERR_ESWITCH_FIFO2 20
711 #define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
712 #define F_PERR_ESWITCH_FIFO2 V_PERR_ESWITCH_FIFO2(1U)
714 #define S_PERR_ESWITCH_FIFO1 19
715 #define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
716 #define F_PERR_ESWITCH_FIFO1 V_PERR_ESWITCH_FIFO1(1U)
718 #define S_PERR_ESWITCH_FIFO0 18
719 #define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
720 #define F_PERR_ESWITCH_FIFO0 V_PERR_ESWITCH_FIFO0(1U)
722 #define S_PERR_PC_DBP1 17
723 #define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
724 #define F_PERR_PC_DBP1 V_PERR_PC_DBP1(1U)
726 #define S_PERR_PC_DBP0 16
727 #define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
728 #define F_PERR_PC_DBP0 V_PERR_PC_DBP0(1U)
730 #define S_PERR_IMSG_OB_FIFO 15
731 #define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
732 #define F_PERR_IMSG_OB_FIFO V_PERR_IMSG_OB_FIFO(1U)
734 #define S_PERR_CONM_SRAM 14
735 #define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
736 #define F_PERR_CONM_SRAM V_PERR_CONM_SRAM(1U)
738 #define S_PERR_PC_MC_RSP 13
739 #define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
740 #define F_PERR_PC_MC_RSP V_PERR_PC_MC_RSP(1U)
742 #define S_PERR_ISW_IDMA0_FIFO 12
743 #define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
744 #define F_PERR_ISW_IDMA0_FIFO V_PERR_ISW_IDMA0_FIFO(1U)
746 #define S_PERR_ISW_IDMA1_FIFO 11
747 #define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
748 #define F_PERR_ISW_IDMA1_FIFO V_PERR_ISW_IDMA1_FIFO(1U)
750 #define S_PERR_ISW_DBP_FIFO 10
751 #define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
752 #define F_PERR_ISW_DBP_FIFO V_PERR_ISW_DBP_FIFO(1U)
754 #define S_PERR_ISW_GTS_FIFO 9
755 #define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
756 #define F_PERR_ISW_GTS_FIFO V_PERR_ISW_GTS_FIFO(1U)
758 #define S_PERR_ITP_EVR 8
759 #define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
760 #define F_PERR_ITP_EVR V_PERR_ITP_EVR(1U)
762 #define S_PERR_FLM_CNTXMEM 7
763 #define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
764 #define F_PERR_FLM_CNTXMEM V_PERR_FLM_CNTXMEM(1U)
766 #define S_PERR_FLM_L1CACHE 6
767 #define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
768 #define F_PERR_FLM_L1CACHE V_PERR_FLM_L1CACHE(1U)
770 #define S_PERR_DBP_HINT_FIFO 5
771 #define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
772 #define F_PERR_DBP_HINT_FIFO V_PERR_DBP_HINT_FIFO(1U)
774 #define S_PERR_DBP_HP_FIFO 4
775 #define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
776 #define F_PERR_DBP_HP_FIFO V_PERR_DBP_HP_FIFO(1U)
778 #define S_PERR_DBP_LP_FIFO 3
779 #define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
780 #define F_PERR_DBP_LP_FIFO V_PERR_DBP_LP_FIFO(1U)
782 #define S_PERR_ING_CTXT_CACHE 2
783 #define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
784 #define F_PERR_ING_CTXT_CACHE V_PERR_ING_CTXT_CACHE(1U)
786 #define S_PERR_EGR_CTXT_CACHE 1
787 #define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
788 #define F_PERR_EGR_CTXT_CACHE V_PERR_EGR_CTXT_CACHE(1U)
790 #define S_PERR_BASE_SIZE 0
791 #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
792 #define F_PERR_BASE_SIZE V_PERR_BASE_SIZE(1U)
794 #define A_SGE_INT_ENABLE2 0x1034
795 #define A_SGE_PERR_ENABLE2 0x1038
796 #define A_SGE_INT_CAUSE3 0x103c
798 #define S_ERR_FLM_DBP 31
799 #define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
800 #define F_ERR_FLM_DBP V_ERR_FLM_DBP(1U)
802 #define S_ERR_FLM_IDMA1 30
803 #define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
804 #define F_ERR_FLM_IDMA1 V_ERR_FLM_IDMA1(1U)
806 #define S_ERR_FLM_IDMA0 29
807 #define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
808 #define F_ERR_FLM_IDMA0 V_ERR_FLM_IDMA0(1U)
810 #define S_ERR_FLM_HINT 28
811 #define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
812 #define F_ERR_FLM_HINT V_ERR_FLM_HINT(1U)
814 #define S_ERR_PCIE_ERROR3 27
815 #define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
816 #define F_ERR_PCIE_ERROR3 V_ERR_PCIE_ERROR3(1U)
818 #define S_ERR_PCIE_ERROR2 26
819 #define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
820 #define F_ERR_PCIE_ERROR2 V_ERR_PCIE_ERROR2(1U)
822 #define S_ERR_PCIE_ERROR1 25
823 #define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
824 #define F_ERR_PCIE_ERROR1 V_ERR_PCIE_ERROR1(1U)
826 #define S_ERR_PCIE_ERROR0 24
827 #define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
828 #define F_ERR_PCIE_ERROR0 V_ERR_PCIE_ERROR0(1U)
830 #define S_ERR_TIMER_ABOVE_MAX_QID 23
831 #define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
832 #define F_ERR_TIMER_ABOVE_MAX_QID V_ERR_TIMER_ABOVE_MAX_QID(1U)
834 #define S_ERR_CPL_EXCEED_IQE_SIZE 22
835 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
836 #define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U)
838 #define S_ERR_INVALID_CIDX_INC 21
839 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
840 #define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U)
842 #define S_ERR_ITP_TIME_PAUSED 20
843 #define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
844 #define F_ERR_ITP_TIME_PAUSED V_ERR_ITP_TIME_PAUSED(1U)
846 #define S_ERR_CPL_OPCODE_0 19
847 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
848 #define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U)
850 #define S_ERR_DROPPED_DB 18
851 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
852 #define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)
854 #define S_ERR_DATA_CPL_ON_HIGH_QID1 17
855 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
856 #define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
858 #define S_ERR_DATA_CPL_ON_HIGH_QID0 16
859 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
860 #define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
862 #define S_ERR_BAD_DB_PIDX3 15
863 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
864 #define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U)
866 #define S_ERR_BAD_DB_PIDX2 14
867 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
868 #define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U)
870 #define S_ERR_BAD_DB_PIDX1 13
871 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
872 #define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U)
874 #define S_ERR_BAD_DB_PIDX0 12
875 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
876 #define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U)
878 #define S_ERR_ING_PCIE_CHAN 11
879 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
880 #define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U)
882 #define S_ERR_ING_CTXT_PRIO 10
883 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
884 #define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U)
886 #define S_ERR_EGR_CTXT_PRIO 9
887 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
888 #define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U)
890 #define S_DBFIFO_HP_INT 8
891 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
892 #define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)
894 #define S_DBFIFO_LP_INT 7
895 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
896 #define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)
898 #define S_REG_ADDRESS_ERR 6
899 #define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
900 #define F_REG_ADDRESS_ERR V_REG_ADDRESS_ERR(1U)
902 #define S_INGRESS_SIZE_ERR 5
903 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
904 #define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U)
906 #define S_EGRESS_SIZE_ERR 4
907 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
908 #define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U)
910 #define S_ERR_INV_CTXT3 3
911 #define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
912 #define F_ERR_INV_CTXT3 V_ERR_INV_CTXT3(1U)
914 #define S_ERR_INV_CTXT2 2
915 #define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
916 #define F_ERR_INV_CTXT2 V_ERR_INV_CTXT2(1U)
918 #define S_ERR_INV_CTXT1 1
919 #define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
920 #define F_ERR_INV_CTXT1 V_ERR_INV_CTXT1(1U)
922 #define S_ERR_INV_CTXT0 0
923 #define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
924 #define F_ERR_INV_CTXT0 V_ERR_INV_CTXT0(1U)
926 #define A_SGE_INT_ENABLE3 0x1040
927 #define A_SGE_FL_BUFFER_SIZE0 0x1044
930 #define M_SIZE 0xfffffffU
931 #define V_SIZE(x) ((x) << S_SIZE)
932 #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
934 #define A_SGE_FL_BUFFER_SIZE1 0x1048
935 #define A_SGE_FL_BUFFER_SIZE2 0x104c
936 #define A_SGE_FL_BUFFER_SIZE3 0x1050
937 #define A_SGE_FL_BUFFER_SIZE4 0x1054
938 #define A_SGE_FL_BUFFER_SIZE5 0x1058
939 #define A_SGE_FL_BUFFER_SIZE6 0x105c
940 #define A_SGE_FL_BUFFER_SIZE7 0x1060
941 #define A_SGE_FL_BUFFER_SIZE8 0x1064
942 #define A_SGE_FL_BUFFER_SIZE9 0x1068
943 #define A_SGE_FL_BUFFER_SIZE10 0x106c
944 #define A_SGE_FL_BUFFER_SIZE11 0x1070
945 #define A_SGE_FL_BUFFER_SIZE12 0x1074
946 #define A_SGE_FL_BUFFER_SIZE13 0x1078
947 #define A_SGE_FL_BUFFER_SIZE14 0x107c
948 #define A_SGE_FL_BUFFER_SIZE15 0x1080
949 #define A_SGE_DBQ_CTXT_BADDR 0x1084
952 #define M_BASEADDR 0x1fffffffU
953 #define V_BASEADDR(x) ((x) << S_BASEADDR)
954 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
956 #define A_SGE_IMSG_CTXT_BADDR 0x1088
957 #define A_SGE_FLM_CACHE_BADDR 0x108c
958 #define A_SGE_FLM_CFG 0x1090
961 #define M_OPMODE 0x3fU
962 #define V_OPMODE(x) ((x) << S_OPMODE)
963 #define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)
966 #define V_NOHDR(x) ((x) << S_NOHDR)
967 #define F_NOHDR V_NOHDR(1U)
969 #define S_CACHEPTRCNT 16
970 #define M_CACHEPTRCNT 0x3U
971 #define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
972 #define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)
974 #define S_EDRAMPTRCNT 14
975 #define M_EDRAMPTRCNT 0x3U
976 #define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
977 #define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)
979 #define S_HDRSTARTFLQ 11
980 #define M_HDRSTARTFLQ 0x7U
981 #define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
982 #define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)
984 #define S_FETCHTHRESH 6
985 #define M_FETCHTHRESH 0x1fU
986 #define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
987 #define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)
989 #define S_CREDITCNT 4
990 #define M_CREDITCNT 0x3U
991 #define V_CREDITCNT(x) ((x) << S_CREDITCNT)
992 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
995 #define V_NOEDRAM(x) ((x) << S_NOEDRAM)
996 #define F_NOEDRAM V_NOEDRAM(1U)
998 #define A_SGE_CONM_CTRL 0x1094
1000 #define S_EGRTHRESHOLD 8
1001 #define M_EGRTHRESHOLD 0x3fU
1002 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
1003 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
1005 #define S_INGTHRESHOLD 2
1006 #define M_INGTHRESHOLD 0x3fU
1007 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
1008 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
1010 #define S_MPS_ENABLE 1
1011 #define V_MPS_ENABLE(x) ((x) << S_MPS_ENABLE)
1012 #define F_MPS_ENABLE V_MPS_ENABLE(1U)
1014 #define S_TP_ENABLE 0
1015 #define V_TP_ENABLE(x) ((x) << S_TP_ENABLE)
1016 #define F_TP_ENABLE V_TP_ENABLE(1U)
1018 #define A_SGE_TIMESTAMP_LO 0x1098
1019 #define A_SGE_TIMESTAMP_HI 0x109c
1023 #define V_TSOP(x) ((x) << S_TSOP)
1024 #define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)
1027 #define M_TSVAL 0xfffffffU
1028 #define V_TSVAL(x) ((x) << S_TSVAL)
1029 #define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
1031 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
1033 #define S_THRESHOLD_0 24
1034 #define M_THRESHOLD_0 0x3fU
1035 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
1036 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
1038 #define S_THRESHOLD_1 16
1039 #define M_THRESHOLD_1 0x3fU
1040 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
1041 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
1043 #define S_THRESHOLD_2 8
1044 #define M_THRESHOLD_2 0x3fU
1045 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
1046 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
1048 #define S_THRESHOLD_3 0
1049 #define M_THRESHOLD_3 0x3fU
1050 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
1051 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
1053 #define A_SGE_DBFIFO_STATUS 0x10a4
1055 #define S_HP_INT_THRESH 28
1056 #define M_HP_INT_THRESH 0xfU
1057 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
1058 #define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)
1060 #define S_HP_COUNT 16
1061 #define M_HP_COUNT 0x7ffU
1062 #define V_HP_COUNT(x) ((x) << S_HP_COUNT)
1063 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
1065 #define S_LP_INT_THRESH 12
1066 #define M_LP_INT_THRESH 0xfU
1067 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
1068 #define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)
1070 #define S_LP_COUNT 0
1071 #define M_LP_COUNT 0x7ffU
1072 #define V_LP_COUNT(x) ((x) << S_LP_COUNT)
1073 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
1075 #define A_SGE_DOORBELL_CONTROL 0x10a8
1077 #define S_HINTDEPTHCTL 27
1078 #define M_HINTDEPTHCTL 0x1fU
1079 #define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
1080 #define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)
1082 #define S_NOCOALESCE 26
1083 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
1084 #define F_NOCOALESCE V_NOCOALESCE(1U)
1086 #define S_HP_WEIGHT 24
1087 #define M_HP_WEIGHT 0x3U
1088 #define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
1089 #define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)
1091 #define S_HP_DISABLE 23
1092 #define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
1093 #define F_HP_DISABLE V_HP_DISABLE(1U)
1095 #define S_FORCEUSERDBTOLP 22
1096 #define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
1097 #define F_FORCEUSERDBTOLP V_FORCEUSERDBTOLP(1U)
1099 #define S_FORCEVFPF0DBTOLP 21
1100 #define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
1101 #define F_FORCEVFPF0DBTOLP V_FORCEVFPF0DBTOLP(1U)
1103 #define S_FORCEVFPF1DBTOLP 20
1104 #define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
1105 #define F_FORCEVFPF1DBTOLP V_FORCEVFPF1DBTOLP(1U)
1107 #define S_FORCEVFPF2DBTOLP 19
1108 #define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
1109 #define F_FORCEVFPF2DBTOLP V_FORCEVFPF2DBTOLP(1U)
1111 #define S_FORCEVFPF3DBTOLP 18
1112 #define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
1113 #define F_FORCEVFPF3DBTOLP V_FORCEVFPF3DBTOLP(1U)
1115 #define S_FORCEVFPF4DBTOLP 17
1116 #define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
1117 #define F_FORCEVFPF4DBTOLP V_FORCEVFPF4DBTOLP(1U)
1119 #define S_FORCEVFPF5DBTOLP 16
1120 #define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
1121 #define F_FORCEVFPF5DBTOLP V_FORCEVFPF5DBTOLP(1U)
1123 #define S_FORCEVFPF6DBTOLP 15
1124 #define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
1125 #define F_FORCEVFPF6DBTOLP V_FORCEVFPF6DBTOLP(1U)
1127 #define S_FORCEVFPF7DBTOLP 14
1128 #define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
1129 #define F_FORCEVFPF7DBTOLP V_FORCEVFPF7DBTOLP(1U)
1131 #define S_ENABLE_DROP 13
1132 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
1133 #define F_ENABLE_DROP V_ENABLE_DROP(1U)
1135 #define S_DROP_TIMEOUT 1
1136 #define M_DROP_TIMEOUT 0xfffU
1137 #define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
1138 #define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)
1140 #define S_DROPPED_DB 0
1141 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
1142 #define F_DROPPED_DB V_DROPPED_DB(1U)
1144 #define A_SGE_DROPPED_DOORBELL 0x10ac
1145 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
1147 #define S_THROTTLE_COUNT 1
1148 #define M_THROTTLE_COUNT 0xfffU
1149 #define V_THROTTLE_COUNT(x) ((x) << S_THROTTLE_COUNT)
1150 #define G_THROTTLE_COUNT(x) (((x) >> S_THROTTLE_COUNT) & M_THROTTLE_COUNT)
1152 #define S_THROTTLE_ENABLE 0
1153 #define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE)
1154 #define F_THROTTLE_ENABLE V_THROTTLE_ENABLE(1U)
1156 #define A_SGE_ITP_CONTROL 0x10b4
1158 #define S_CRITICAL_TIME 10
1159 #define M_CRITICAL_TIME 0x7fffU
1160 #define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
1161 #define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)
1163 #define S_LL_EMPTY 4
1164 #define M_LL_EMPTY 0x3fU
1165 #define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
1166 #define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)
1168 #define S_LL_READ_WAIT_DISABLE 0
1169 #define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
1170 #define F_LL_READ_WAIT_DISABLE V_LL_READ_WAIT_DISABLE(1U)
1172 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
1174 #define S_TIMERVALUE0 16
1175 #define M_TIMERVALUE0 0xffffU
1176 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
1177 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
1179 #define S_TIMERVALUE1 0
1180 #define M_TIMERVALUE1 0xffffU
1181 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
1182 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
1184 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
1186 #define S_TIMERVALUE2 16
1187 #define M_TIMERVALUE2 0xffffU
1188 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
1189 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
1191 #define S_TIMERVALUE3 0
1192 #define M_TIMERVALUE3 0xffffU
1193 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
1194 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
1196 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
1198 #define S_TIMERVALUE4 16
1199 #define M_TIMERVALUE4 0xffffU
1200 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
1201 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
1203 #define S_TIMERVALUE5 0
1204 #define M_TIMERVALUE5 0xffffU
1205 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
1206 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
1208 #define A_SGE_PD_RSP_CREDIT01 0x10c4
1210 #define S_RSPCREDITEN0 31
1211 #define V_RSPCREDITEN0(x) ((x) << S_RSPCREDITEN0)
1212 #define F_RSPCREDITEN0 V_RSPCREDITEN0(1U)
1214 #define S_MAXTAG0 24
1215 #define M_MAXTAG0 0x7fU
1216 #define V_MAXTAG0(x) ((x) << S_MAXTAG0)
1217 #define G_MAXTAG0(x) (((x) >> S_MAXTAG0) & M_MAXTAG0)
1219 #define S_MAXRSPCNT0 16
1220 #define M_MAXRSPCNT0 0xffU
1221 #define V_MAXRSPCNT0(x) ((x) << S_MAXRSPCNT0)
1222 #define G_MAXRSPCNT0(x) (((x) >> S_MAXRSPCNT0) & M_MAXRSPCNT0)
1224 #define S_RSPCREDITEN1 15
1225 #define V_RSPCREDITEN1(x) ((x) << S_RSPCREDITEN1)
1226 #define F_RSPCREDITEN1 V_RSPCREDITEN1(1U)
1229 #define M_MAXTAG1 0x7fU
1230 #define V_MAXTAG1(x) ((x) << S_MAXTAG1)
1231 #define G_MAXTAG1(x) (((x) >> S_MAXTAG1) & M_MAXTAG1)
1233 #define S_MAXRSPCNT1 0
1234 #define M_MAXRSPCNT1 0xffU
1235 #define V_MAXRSPCNT1(x) ((x) << S_MAXRSPCNT1)
1236 #define G_MAXRSPCNT1(x) (((x) >> S_MAXRSPCNT1) & M_MAXRSPCNT1)
1238 #define A_SGE_PD_RSP_CREDIT23 0x10c8
1240 #define S_RSPCREDITEN2 31
1241 #define V_RSPCREDITEN2(x) ((x) << S_RSPCREDITEN2)
1242 #define F_RSPCREDITEN2 V_RSPCREDITEN2(1U)
1244 #define S_MAXTAG2 24
1245 #define M_MAXTAG2 0x7fU
1246 #define V_MAXTAG2(x) ((x) << S_MAXTAG2)
1247 #define G_MAXTAG2(x) (((x) >> S_MAXTAG2) & M_MAXTAG2)
1249 #define S_MAXRSPCNT2 16
1250 #define M_MAXRSPCNT2 0xffU
1251 #define V_MAXRSPCNT2(x) ((x) << S_MAXRSPCNT2)
1252 #define G_MAXRSPCNT2(x) (((x) >> S_MAXRSPCNT2) & M_MAXRSPCNT2)
1254 #define S_RSPCREDITEN3 15
1255 #define V_RSPCREDITEN3(x) ((x) << S_RSPCREDITEN3)
1256 #define F_RSPCREDITEN3 V_RSPCREDITEN3(1U)
1259 #define M_MAXTAG3 0x7fU
1260 #define V_MAXTAG3(x) ((x) << S_MAXTAG3)
1261 #define G_MAXTAG3(x) (((x) >> S_MAXTAG3) & M_MAXTAG3)
1263 #define S_MAXRSPCNT3 0
1264 #define M_MAXRSPCNT3 0xffU
1265 #define V_MAXRSPCNT3(x) ((x) << S_MAXRSPCNT3)
1266 #define G_MAXRSPCNT3(x) (((x) >> S_MAXRSPCNT3) & M_MAXRSPCNT3)
1268 #define A_SGE_DEBUG_INDEX 0x10cc
1269 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
1270 #define A_SGE_DEBUG_DATA_LOW 0x10d4
1271 #define A_SGE_REVISION 0x10d8
1272 #define A_SGE_INT_CAUSE4 0x10dc
1274 #define S_ERR_BAD_UPFL_INC_CREDIT3 8
1275 #define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
1276 #define F_ERR_BAD_UPFL_INC_CREDIT3 V_ERR_BAD_UPFL_INC_CREDIT3(1U)
1278 #define S_ERR_BAD_UPFL_INC_CREDIT2 7
1279 #define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
1280 #define F_ERR_BAD_UPFL_INC_CREDIT2 V_ERR_BAD_UPFL_INC_CREDIT2(1U)
1282 #define S_ERR_BAD_UPFL_INC_CREDIT1 6
1283 #define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
1284 #define F_ERR_BAD_UPFL_INC_CREDIT1 V_ERR_BAD_UPFL_INC_CREDIT1(1U)
1286 #define S_ERR_BAD_UPFL_INC_CREDIT0 5
1287 #define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
1288 #define F_ERR_BAD_UPFL_INC_CREDIT0 V_ERR_BAD_UPFL_INC_CREDIT0(1U)
1290 #define S_ERR_PHYSADDR_LEN0_IDMA1 4
1291 #define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
1292 #define F_ERR_PHYSADDR_LEN0_IDMA1 V_ERR_PHYSADDR_LEN0_IDMA1(1U)
1294 #define S_ERR_PHYSADDR_LEN0_IDMA0 3
1295 #define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
1296 #define F_ERR_PHYSADDR_LEN0_IDMA0 V_ERR_PHYSADDR_LEN0_IDMA0(1U)
1298 #define S_ERR_FLM_INVALID_PKT_DROP1 2
1299 #define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
1300 #define F_ERR_FLM_INVALID_PKT_DROP1 V_ERR_FLM_INVALID_PKT_DROP1(1U)
1302 #define S_ERR_FLM_INVALID_PKT_DROP0 1
1303 #define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
1304 #define F_ERR_FLM_INVALID_PKT_DROP0 V_ERR_FLM_INVALID_PKT_DROP0(1U)
1306 #define S_ERR_UNEXPECTED_TIMER 0
1307 #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
1308 #define F_ERR_UNEXPECTED_TIMER V_ERR_UNEXPECTED_TIMER(1U)
1310 #define A_SGE_INT_ENABLE4 0x10e0
1311 #define A_SGE_STAT_TOTAL 0x10e4
1312 #define A_SGE_STAT_MATCH 0x10e8
1313 #define A_SGE_STAT_CFG 0x10ec
1315 #define S_ITPOPMODE 8
1316 #define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
1317 #define F_ITPOPMODE V_ITPOPMODE(1U)
1319 #define S_EGRCTXTOPMODE 6
1320 #define M_EGRCTXTOPMODE 0x3U
1321 #define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
1322 #define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)
1324 #define S_INGCTXTOPMODE 4
1325 #define M_INGCTXTOPMODE 0x3U
1326 #define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
1327 #define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)
1329 #define S_STATMODE 2
1330 #define M_STATMODE 0x3U
1331 #define V_STATMODE(x) ((x) << S_STATMODE)
1332 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
1334 #define S_STATSOURCE 0
1335 #define M_STATSOURCE 0x3U
1336 #define V_STATSOURCE(x) ((x) << S_STATSOURCE)
1337 #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
1339 #define A_SGE_HINT_CFG 0x10f0
1341 #define S_HINTSALLOWEDNOHDR 6
1342 #define M_HINTSALLOWEDNOHDR 0x3fU
1343 #define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
1344 #define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
1346 #define S_HINTSALLOWEDHDR 0
1347 #define M_HINTSALLOWEDHDR 0x3fU
1348 #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
1349 #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
1351 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
1352 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
1353 #define A_SGE_PD_WRR_CONFIG 0x10fc
1355 #define S_EDMA_WEIGHT 0
1356 #define M_EDMA_WEIGHT 0x3fU
1357 #define V_EDMA_WEIGHT(x) ((x) << S_EDMA_WEIGHT)
1358 #define G_EDMA_WEIGHT(x) (((x) >> S_EDMA_WEIGHT) & M_EDMA_WEIGHT)
1360 #define A_SGE_ERROR_STATS 0x1100
1362 #define S_UNCAPTURED_ERROR 18
1363 #define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
1364 #define F_UNCAPTURED_ERROR V_UNCAPTURED_ERROR(1U)
1366 #define S_ERROR_QID_VALID 17
1367 #define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
1368 #define F_ERROR_QID_VALID V_ERROR_QID_VALID(1U)
1370 #define S_ERROR_QID 0
1371 #define M_ERROR_QID 0x1ffffU
1372 #define V_ERROR_QID(x) ((x) << S_ERROR_QID)
1373 #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
1375 #define A_SGE_SHARED_TAG_CHAN_CFG 0x1104
1377 #define S_MINTAG3 24
1378 #define M_MINTAG3 0xffU
1379 #define V_MINTAG3(x) ((x) << S_MINTAG3)
1380 #define G_MINTAG3(x) (((x) >> S_MINTAG3) & M_MINTAG3)
1382 #define S_MINTAG2 16
1383 #define M_MINTAG2 0xffU
1384 #define V_MINTAG2(x) ((x) << S_MINTAG2)
1385 #define G_MINTAG2(x) (((x) >> S_MINTAG2) & M_MINTAG2)
1388 #define M_MINTAG1 0xffU
1389 #define V_MINTAG1(x) ((x) << S_MINTAG1)
1390 #define G_MINTAG1(x) (((x) >> S_MINTAG1) & M_MINTAG1)
1393 #define M_MINTAG0 0xffU
1394 #define V_MINTAG0(x) ((x) << S_MINTAG0)
1395 #define G_MINTAG0(x) (((x) >> S_MINTAG0) & M_MINTAG0)
1397 #define A_SGE_SHARED_TAG_POOL_CFG 0x1108
1399 #define S_TAGPOOLTOTAL 0
1400 #define M_TAGPOOLTOTAL 0xffU
1401 #define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
1402 #define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
1404 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
1405 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
1406 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
1407 #define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
1408 #define A_SGE_PC0_RSP_BIST_CMD 0x11a0
1409 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
1410 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0
1411 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
1412 #define A_SGE_CTXT_CMD 0x11fc
1415 #define V_BUSY(x) ((x) << S_BUSY)
1416 #define F_BUSY V_BUSY(1U)
1419 #define M_CTXTOP 0x3U
1420 #define V_CTXTOP(x) ((x) << S_CTXTOP)
1421 #define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)
1423 #define S_CTXTTYPE 24
1424 #define M_CTXTTYPE 0x3U
1425 #define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
1426 #define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)
1429 #define M_CTXTQID 0x1ffffU
1430 #define V_CTXTQID(x) ((x) << S_CTXTQID)
1431 #define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)
1433 #define A_SGE_CTXT_DATA0 0x1200
1434 #define A_SGE_CTXT_DATA1 0x1204
1435 #define A_SGE_CTXT_DATA2 0x1208
1436 #define A_SGE_CTXT_DATA3 0x120c
1437 #define A_SGE_CTXT_DATA4 0x1210
1438 #define A_SGE_CTXT_DATA5 0x1214
1439 #define A_SGE_CTXT_DATA6 0x1218
1440 #define A_SGE_CTXT_DATA7 0x121c
1441 #define A_SGE_CTXT_MASK0 0x1220
1442 #define A_SGE_CTXT_MASK1 0x1224
1443 #define A_SGE_CTXT_MASK2 0x1228
1444 #define A_SGE_CTXT_MASK3 0x122c
1445 #define A_SGE_CTXT_MASK4 0x1230
1446 #define A_SGE_CTXT_MASK5 0x1234
1447 #define A_SGE_CTXT_MASK6 0x1238
1448 #define A_SGE_CTXT_MASK7 0x123c
1449 #define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300
1451 #define S_EGRESS_LOG2SIZE 27
1452 #define M_EGRESS_LOG2SIZE 0x1fU
1453 #define V_EGRESS_LOG2SIZE(x) ((x) << S_EGRESS_LOG2SIZE)
1454 #define G_EGRESS_LOG2SIZE(x) (((x) >> S_EGRESS_LOG2SIZE) & M_EGRESS_LOG2SIZE)
1456 #define S_EGRESS_BASE 10
1457 #define M_EGRESS_BASE 0x1ffffU
1458 #define V_EGRESS_BASE(x) ((x) << S_EGRESS_BASE)
1459 #define G_EGRESS_BASE(x) (((x) >> S_EGRESS_BASE) & M_EGRESS_BASE)
1461 #define S_INGRESS2_LOG2SIZE 5
1462 #define M_INGRESS2_LOG2SIZE 0x1fU
1463 #define V_INGRESS2_LOG2SIZE(x) ((x) << S_INGRESS2_LOG2SIZE)
1464 #define G_INGRESS2_LOG2SIZE(x) (((x) >> S_INGRESS2_LOG2SIZE) & M_INGRESS2_LOG2SIZE)
1466 #define S_INGRESS1_LOG2SIZE 0
1467 #define M_INGRESS1_LOG2SIZE 0x1fU
1468 #define V_INGRESS1_LOG2SIZE(x) ((x) << S_INGRESS1_LOG2SIZE)
1469 #define G_INGRESS1_LOG2SIZE(x) (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE)
1471 #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
1473 #define S_INGRESS2_BASE 16
1474 #define M_INGRESS2_BASE 0xffffU
1475 #define V_INGRESS2_BASE(x) ((x) << S_INGRESS2_BASE)
1476 #define G_INGRESS2_BASE(x) (((x) >> S_INGRESS2_BASE) & M_INGRESS2_BASE)
1478 #define S_INGRESS1_BASE 0
1479 #define M_INGRESS1_BASE 0xffffU
1480 #define V_INGRESS1_BASE(x) ((x) << S_INGRESS1_BASE)
1481 #define G_INGRESS1_BASE(x) (((x) >> S_INGRESS1_BASE) & M_INGRESS1_BASE)
1483 #define A_SGE_LA_RDPTR_0 0x1800
1484 #define A_SGE_LA_RDDATA_0 0x1804
1485 #define A_SGE_LA_WRPTR_0 0x1808
1486 #define A_SGE_LA_RESERVED_0 0x180c
1487 #define A_SGE_LA_RDPTR_1 0x1810
1488 #define A_SGE_LA_RDDATA_1 0x1814
1489 #define A_SGE_LA_WRPTR_1 0x1818
1490 #define A_SGE_LA_RESERVED_1 0x181c
1491 #define A_SGE_LA_RDPTR_2 0x1820
1492 #define A_SGE_LA_RDDATA_2 0x1824
1493 #define A_SGE_LA_WRPTR_2 0x1828
1494 #define A_SGE_LA_RESERVED_2 0x182c
1495 #define A_SGE_LA_RDPTR_3 0x1830
1496 #define A_SGE_LA_RDDATA_3 0x1834
1497 #define A_SGE_LA_WRPTR_3 0x1838
1498 #define A_SGE_LA_RESERVED_3 0x183c
1499 #define A_SGE_LA_RDPTR_4 0x1840
1500 #define A_SGE_LA_RDDATA_4 0x1844
1501 #define A_SGE_LA_WRPTR_4 0x1848
1502 #define A_SGE_LA_RESERVED_4 0x184c
1503 #define A_SGE_LA_RDPTR_5 0x1850
1504 #define A_SGE_LA_RDDATA_5 0x1854
1505 #define A_SGE_LA_WRPTR_5 0x1858
1506 #define A_SGE_LA_RESERVED_5 0x185c
1507 #define A_SGE_LA_RDPTR_6 0x1860
1508 #define A_SGE_LA_RDDATA_6 0x1864
1509 #define A_SGE_LA_WRPTR_6 0x1868
1510 #define A_SGE_LA_RESERVED_6 0x186c
1511 #define A_SGE_LA_RDPTR_7 0x1870
1512 #define A_SGE_LA_RDDATA_7 0x1874
1513 #define A_SGE_LA_WRPTR_7 0x1878
1514 #define A_SGE_LA_RESERVED_7 0x187c
1515 #define A_SGE_LA_RDPTR_8 0x1880
1516 #define A_SGE_LA_RDDATA_8 0x1884
1517 #define A_SGE_LA_WRPTR_8 0x1888
1518 #define A_SGE_LA_RESERVED_8 0x188c
1519 #define A_SGE_LA_RDPTR_9 0x1890
1520 #define A_SGE_LA_RDDATA_9 0x1894
1521 #define A_SGE_LA_WRPTR_9 0x1898
1522 #define A_SGE_LA_RESERVED_9 0x189c
1523 #define A_SGE_LA_RDPTR_10 0x18a0
1524 #define A_SGE_LA_RDDATA_10 0x18a4
1525 #define A_SGE_LA_WRPTR_10 0x18a8
1526 #define A_SGE_LA_RESERVED_10 0x18ac
1527 #define A_SGE_LA_RDPTR_11 0x18b0
1528 #define A_SGE_LA_RDDATA_11 0x18b4
1529 #define A_SGE_LA_WRPTR_11 0x18b8
1530 #define A_SGE_LA_RESERVED_11 0x18bc
1531 #define A_SGE_LA_RDPTR_12 0x18c0
1532 #define A_SGE_LA_RDDATA_12 0x18c4
1533 #define A_SGE_LA_WRPTR_12 0x18c8
1534 #define A_SGE_LA_RESERVED_12 0x18cc
1535 #define A_SGE_LA_RDPTR_13 0x18d0
1536 #define A_SGE_LA_RDDATA_13 0x18d4
1537 #define A_SGE_LA_WRPTR_13 0x18d8
1538 #define A_SGE_LA_RESERVED_13 0x18dc
1539 #define A_SGE_LA_RDPTR_14 0x18e0
1540 #define A_SGE_LA_RDDATA_14 0x18e4
1541 #define A_SGE_LA_WRPTR_14 0x18e8
1542 #define A_SGE_LA_RESERVED_14 0x18ec
1543 #define A_SGE_LA_RDPTR_15 0x18f0
1544 #define A_SGE_LA_RDDATA_15 0x18f4
1545 #define A_SGE_LA_WRPTR_15 0x18f8
1546 #define A_SGE_LA_RESERVED_15 0x18fc
1548 /* registers for module PCIE */
1549 #define PCIE_BASE_ADDR 0x3000
1551 #define A_PCIE_PF_CFG 0x40
1553 #define S_INTXSTAT 16
1554 #define V_INTXSTAT(x) ((x) << S_INTXSTAT)
1555 #define F_INTXSTAT V_INTXSTAT(1U)
1557 #define S_AUXPWRPMEN 15
1558 #define V_AUXPWRPMEN(x) ((x) << S_AUXPWRPMEN)
1559 #define F_AUXPWRPMEN V_AUXPWRPMEN(1U)
1561 #define S_NOSOFTRESET 14
1562 #define V_NOSOFTRESET(x) ((x) << S_NOSOFTRESET)
1563 #define F_NOSOFTRESET V_NOSOFTRESET(1U)
1566 #define M_AIVEC 0x3ffU
1567 #define V_AIVEC(x) ((x) << S_AIVEC)
1568 #define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC)
1570 #define S_INTXTYPE 2
1571 #define M_INTXTYPE 0x3U
1572 #define V_INTXTYPE(x) ((x) << S_INTXTYPE)
1573 #define G_INTXTYPE(x) (((x) >> S_INTXTYPE) & M_INTXTYPE)
1576 #define V_D3HOTEN(x) ((x) << S_D3HOTEN)
1577 #define F_D3HOTEN V_D3HOTEN(1U)
1579 #define S_CLIDECEN 0
1580 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
1581 #define F_CLIDECEN V_CLIDECEN(1U)
1583 #define A_PCIE_PF_CLI 0x44
1584 #define A_PCIE_PF_GEN_MSG 0x48
1587 #define M_MSGTYPE 0xffU
1588 #define V_MSGTYPE(x) ((x) << S_MSGTYPE)
1589 #define G_MSGTYPE(x) (((x) >> S_MSGTYPE) & M_MSGTYPE)
1591 #define A_PCIE_PF_EXPROM_OFST 0x4c
1594 #define M_OFFSET 0x3fffU
1595 #define V_OFFSET(x) ((x) << S_OFFSET)
1596 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
1598 #define A_PCIE_INT_ENABLE 0x3000
1600 #define S_NONFATALERR 30
1601 #define V_NONFATALERR(x) ((x) << S_NONFATALERR)
1602 #define F_NONFATALERR V_NONFATALERR(1U)
1604 #define S_UNXSPLCPLERR 29
1605 #define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR)
1606 #define F_UNXSPLCPLERR V_UNXSPLCPLERR(1U)
1608 #define S_PCIEPINT 28
1609 #define V_PCIEPINT(x) ((x) << S_PCIEPINT)
1610 #define F_PCIEPINT V_PCIEPINT(1U)
1612 #define S_PCIESINT 27
1613 #define V_PCIESINT(x) ((x) << S_PCIESINT)
1614 #define F_PCIESINT V_PCIESINT(1U)
1616 #define S_RPLPERR 26
1617 #define V_RPLPERR(x) ((x) << S_RPLPERR)
1618 #define F_RPLPERR V_RPLPERR(1U)
1620 #define S_RXWRPERR 25
1621 #define V_RXWRPERR(x) ((x) << S_RXWRPERR)
1622 #define F_RXWRPERR V_RXWRPERR(1U)
1624 #define S_RXCPLPERR 24
1625 #define V_RXCPLPERR(x) ((x) << S_RXCPLPERR)
1626 #define F_RXCPLPERR V_RXCPLPERR(1U)
1628 #define S_PIOTAGPERR 23
1629 #define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR)
1630 #define F_PIOTAGPERR V_PIOTAGPERR(1U)
1632 #define S_MATAGPERR 22
1633 #define V_MATAGPERR(x) ((x) << S_MATAGPERR)
1634 #define F_MATAGPERR V_MATAGPERR(1U)
1636 #define S_INTXCLRPERR 21
1637 #define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR)
1638 #define F_INTXCLRPERR V_INTXCLRPERR(1U)
1640 #define S_FIDPERR 20
1641 #define V_FIDPERR(x) ((x) << S_FIDPERR)
1642 #define F_FIDPERR V_FIDPERR(1U)
1644 #define S_CFGSNPPERR 19
1645 #define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR)
1646 #define F_CFGSNPPERR V_CFGSNPPERR(1U)
1648 #define S_HRSPPERR 18
1649 #define V_HRSPPERR(x) ((x) << S_HRSPPERR)
1650 #define F_HRSPPERR V_HRSPPERR(1U)
1652 #define S_HREQPERR 17
1653 #define V_HREQPERR(x) ((x) << S_HREQPERR)
1654 #define F_HREQPERR V_HREQPERR(1U)
1656 #define S_HCNTPERR 16
1657 #define V_HCNTPERR(x) ((x) << S_HCNTPERR)
1658 #define F_HCNTPERR V_HCNTPERR(1U)
1660 #define S_DRSPPERR 15
1661 #define V_DRSPPERR(x) ((x) << S_DRSPPERR)
1662 #define F_DRSPPERR V_DRSPPERR(1U)
1664 #define S_DREQPERR 14
1665 #define V_DREQPERR(x) ((x) << S_DREQPERR)
1666 #define F_DREQPERR V_DREQPERR(1U)
1668 #define S_DCNTPERR 13
1669 #define V_DCNTPERR(x) ((x) << S_DCNTPERR)
1670 #define F_DCNTPERR V_DCNTPERR(1U)
1672 #define S_CRSPPERR 12
1673 #define V_CRSPPERR(x) ((x) << S_CRSPPERR)
1674 #define F_CRSPPERR V_CRSPPERR(1U)
1676 #define S_CREQPERR 11
1677 #define V_CREQPERR(x) ((x) << S_CREQPERR)
1678 #define F_CREQPERR V_CREQPERR(1U)
1680 #define S_CCNTPERR 10
1681 #define V_CCNTPERR(x) ((x) << S_CCNTPERR)
1682 #define F_CCNTPERR V_CCNTPERR(1U)
1684 #define S_TARTAGPERR 9
1685 #define V_TARTAGPERR(x) ((x) << S_TARTAGPERR)
1686 #define F_TARTAGPERR V_TARTAGPERR(1U)
1688 #define S_PIOREQPERR 8
1689 #define V_PIOREQPERR(x) ((x) << S_PIOREQPERR)
1690 #define F_PIOREQPERR V_PIOREQPERR(1U)
1692 #define S_PIOCPLPERR 7
1693 #define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR)
1694 #define F_PIOCPLPERR V_PIOCPLPERR(1U)
1696 #define S_MSIXDIPERR 6
1697 #define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR)
1698 #define F_MSIXDIPERR V_MSIXDIPERR(1U)
1700 #define S_MSIXDATAPERR 5
1701 #define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR)
1702 #define F_MSIXDATAPERR V_MSIXDATAPERR(1U)
1704 #define S_MSIXADDRHPERR 4
1705 #define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR)
1706 #define F_MSIXADDRHPERR V_MSIXADDRHPERR(1U)
1708 #define S_MSIXADDRLPERR 3
1709 #define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR)
1710 #define F_MSIXADDRLPERR V_MSIXADDRLPERR(1U)
1712 #define S_MSIDATAPERR 2
1713 #define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR)
1714 #define F_MSIDATAPERR V_MSIDATAPERR(1U)
1716 #define S_MSIADDRHPERR 1
1717 #define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR)
1718 #define F_MSIADDRHPERR V_MSIADDRHPERR(1U)
1720 #define S_MSIADDRLPERR 0
1721 #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
1722 #define F_MSIADDRLPERR V_MSIADDRLPERR(1U)
1724 #define A_PCIE_INT_CAUSE 0x3004
1725 #define A_PCIE_PERR_ENABLE 0x3008
1726 #define A_PCIE_PERR_INJECT 0x300c
1729 #define V_IDE(x) ((x) << S_IDE)
1730 #define F_IDE V_IDE(1U)
1732 #define A_PCIE_NONFAT_ERR 0x3010
1734 #define S_RDRSPERR 9
1735 #define V_RDRSPERR(x) ((x) << S_RDRSPERR)
1736 #define F_RDRSPERR V_RDRSPERR(1U)
1738 #define S_VPDRSPERR 8
1739 #define V_VPDRSPERR(x) ((x) << S_VPDRSPERR)
1740 #define F_VPDRSPERR V_VPDRSPERR(1U)
1743 #define V_POPD(x) ((x) << S_POPD)
1744 #define F_POPD V_POPD(1U)
1747 #define V_POPH(x) ((x) << S_POPH)
1748 #define F_POPH V_POPH(1U)
1751 #define V_POPC(x) ((x) << S_POPC)
1752 #define F_POPC V_POPC(1U)
1755 #define V_MEMREQ(x) ((x) << S_MEMREQ)
1756 #define F_MEMREQ V_MEMREQ(1U)
1759 #define V_PIOREQ(x) ((x) << S_PIOREQ)
1760 #define F_PIOREQ V_PIOREQ(1U)
1763 #define V_TAGDROP(x) ((x) << S_TAGDROP)
1764 #define F_TAGDROP V_TAGDROP(1U)
1767 #define V_TAGCPL(x) ((x) << S_TAGCPL)
1768 #define F_TAGCPL V_TAGCPL(1U)
1771 #define V_CFGSNP(x) ((x) << S_CFGSNP)
1772 #define F_CFGSNP V_CFGSNP(1U)
1774 #define A_PCIE_CFG 0x3014
1776 #define S_CFGDMAXPYLDSZRX 26
1777 #define M_CFGDMAXPYLDSZRX 0x7U
1778 #define V_CFGDMAXPYLDSZRX(x) ((x) << S_CFGDMAXPYLDSZRX)
1779 #define G_CFGDMAXPYLDSZRX(x) (((x) >> S_CFGDMAXPYLDSZRX) & M_CFGDMAXPYLDSZRX)
1781 #define S_CFGDMAXPYLDSZTX 23
1782 #define M_CFGDMAXPYLDSZTX 0x7U
1783 #define V_CFGDMAXPYLDSZTX(x) ((x) << S_CFGDMAXPYLDSZTX)
1784 #define G_CFGDMAXPYLDSZTX(x) (((x) >> S_CFGDMAXPYLDSZTX) & M_CFGDMAXPYLDSZTX)
1786 #define S_CFGDMAXRDREQSZ 20
1787 #define M_CFGDMAXRDREQSZ 0x7U
1788 #define V_CFGDMAXRDREQSZ(x) ((x) << S_CFGDMAXRDREQSZ)
1789 #define G_CFGDMAXRDREQSZ(x) (((x) >> S_CFGDMAXRDREQSZ) & M_CFGDMAXRDREQSZ)
1791 #define S_MASYNCEN 19
1792 #define V_MASYNCEN(x) ((x) << S_MASYNCEN)
1793 #define F_MASYNCEN V_MASYNCEN(1U)
1795 #define S_DCAENDMA 18
1796 #define V_DCAENDMA(x) ((x) << S_DCAENDMA)
1797 #define F_DCAENDMA V_DCAENDMA(1U)
1799 #define S_DCAENCMD 17
1800 #define V_DCAENCMD(x) ((x) << S_DCAENCMD)
1801 #define F_DCAENCMD V_DCAENCMD(1U)
1803 #define S_VFMSIPNDEN 16
1804 #define V_VFMSIPNDEN(x) ((x) << S_VFMSIPNDEN)
1805 #define F_VFMSIPNDEN V_VFMSIPNDEN(1U)
1807 #define S_FORCETXERROR 15
1808 #define V_FORCETXERROR(x) ((x) << S_FORCETXERROR)
1809 #define F_FORCETXERROR V_FORCETXERROR(1U)
1811 #define S_VPDREQPROTECT 14
1812 #define V_VPDREQPROTECT(x) ((x) << S_VPDREQPROTECT)
1813 #define F_VPDREQPROTECT V_VPDREQPROTECT(1U)
1815 #define S_FIDTABLEINVALID 13
1816 #define V_FIDTABLEINVALID(x) ((x) << S_FIDTABLEINVALID)
1817 #define F_FIDTABLEINVALID V_FIDTABLEINVALID(1U)
1819 #define S_BYPASSMSIXCACHE 12
1820 #define V_BYPASSMSIXCACHE(x) ((x) << S_BYPASSMSIXCACHE)
1821 #define F_BYPASSMSIXCACHE V_BYPASSMSIXCACHE(1U)
1823 #define S_BYPASSMSICACHE 11
1824 #define V_BYPASSMSICACHE(x) ((x) << S_BYPASSMSICACHE)
1825 #define F_BYPASSMSICACHE V_BYPASSMSICACHE(1U)
1827 #define S_SIMSPEED 10
1828 #define V_SIMSPEED(x) ((x) << S_SIMSPEED)
1829 #define F_SIMSPEED V_SIMSPEED(1U)
1831 #define S_TC0_STAMP 9
1832 #define V_TC0_STAMP(x) ((x) << S_TC0_STAMP)
1833 #define F_TC0_STAMP V_TC0_STAMP(1U)
1835 #define S_AI_TCVAL 6
1836 #define M_AI_TCVAL 0x7U
1837 #define V_AI_TCVAL(x) ((x) << S_AI_TCVAL)
1838 #define G_AI_TCVAL(x) (((x) >> S_AI_TCVAL) & M_AI_TCVAL)
1840 #define S_DMASTOPEN 5
1841 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
1842 #define F_DMASTOPEN V_DMASTOPEN(1U)
1844 #define S_DEVSTATERSTMODE 4
1845 #define V_DEVSTATERSTMODE(x) ((x) << S_DEVSTATERSTMODE)
1846 #define F_DEVSTATERSTMODE V_DEVSTATERSTMODE(1U)
1848 #define S_HOTRSTPCIECRSTMODE 3
1849 #define V_HOTRSTPCIECRSTMODE(x) ((x) << S_HOTRSTPCIECRSTMODE)
1850 #define F_HOTRSTPCIECRSTMODE V_HOTRSTPCIECRSTMODE(1U)
1852 #define S_DLDNPCIECRSTMODE 2
1853 #define V_DLDNPCIECRSTMODE(x) ((x) << S_DLDNPCIECRSTMODE)
1854 #define F_DLDNPCIECRSTMODE V_DLDNPCIECRSTMODE(1U)
1856 #define S_DLDNPCIEPRECRSTMODE 1
1857 #define V_DLDNPCIEPRECRSTMODE(x) ((x) << S_DLDNPCIEPRECRSTMODE)
1858 #define F_DLDNPCIEPRECRSTMODE V_DLDNPCIEPRECRSTMODE(1U)
1860 #define S_LINKDNRSTEN 0
1861 #define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN)
1862 #define F_LINKDNRSTEN V_LINKDNRSTEN(1U)
1864 #define A_PCIE_DMA_CTRL 0x3018
1866 #define S_LITTLEENDIAN 7
1867 #define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN)
1868 #define F_LITTLEENDIAN V_LITTLEENDIAN(1U)
1870 #define A_PCIE_DMA_CFG 0x301c
1872 #define S_MAXPYLDSIZE 28
1873 #define M_MAXPYLDSIZE 0x7U
1874 #define V_MAXPYLDSIZE(x) ((x) << S_MAXPYLDSIZE)
1875 #define G_MAXPYLDSIZE(x) (((x) >> S_MAXPYLDSIZE) & M_MAXPYLDSIZE)
1877 #define S_MAXRDREQSIZE 25
1878 #define M_MAXRDREQSIZE 0x7U
1879 #define V_MAXRDREQSIZE(x) ((x) << S_MAXRDREQSIZE)
1880 #define G_MAXRDREQSIZE(x) (((x) >> S_MAXRDREQSIZE) & M_MAXRDREQSIZE)
1882 #define S_DMA_MAXRSPCNT 16
1883 #define M_DMA_MAXRSPCNT 0x1ffU
1884 #define V_DMA_MAXRSPCNT(x) ((x) << S_DMA_MAXRSPCNT)
1885 #define G_DMA_MAXRSPCNT(x) (((x) >> S_DMA_MAXRSPCNT) & M_DMA_MAXRSPCNT)
1887 #define S_DMA_MAXREQCNT 8
1888 #define M_DMA_MAXREQCNT 0xffU
1889 #define V_DMA_MAXREQCNT(x) ((x) << S_DMA_MAXREQCNT)
1890 #define G_DMA_MAXREQCNT(x) (((x) >> S_DMA_MAXREQCNT) & M_DMA_MAXREQCNT)
1893 #define M_MAXTAG 0x7fU
1894 #define V_MAXTAG(x) ((x) << S_MAXTAG)
1895 #define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG)
1897 #define A_PCIE_DMA_STAT 0x3020
1899 #define S_STATEREQ 28
1900 #define M_STATEREQ 0xfU
1901 #define V_STATEREQ(x) ((x) << S_STATEREQ)
1902 #define G_STATEREQ(x) (((x) >> S_STATEREQ) & M_STATEREQ)
1904 #define S_DMA_RSPCNT 16
1905 #define M_DMA_RSPCNT 0xfffU
1906 #define V_DMA_RSPCNT(x) ((x) << S_DMA_RSPCNT)
1907 #define G_DMA_RSPCNT(x) (((x) >> S_DMA_RSPCNT) & M_DMA_RSPCNT)
1909 #define S_STATEAREQ 13
1910 #define M_STATEAREQ 0x7U
1911 #define V_STATEAREQ(x) ((x) << S_STATEAREQ)
1912 #define G_STATEAREQ(x) (((x) >> S_STATEAREQ) & M_STATEAREQ)
1914 #define S_TAGFREE 12
1915 #define V_TAGFREE(x) ((x) << S_TAGFREE)
1916 #define F_TAGFREE V_TAGFREE(1U)
1918 #define S_DMA_REQCNT 0
1919 #define M_DMA_REQCNT 0x7ffU
1920 #define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT)
1921 #define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT)
1923 #define A_PCIE_CMD_CTRL 0x303c
1924 #define A_PCIE_CMD_CFG 0x3040
1926 #define S_MAXRSPCNT 16
1927 #define M_MAXRSPCNT 0xfU
1928 #define V_MAXRSPCNT(x) ((x) << S_MAXRSPCNT)
1929 #define G_MAXRSPCNT(x) (((x) >> S_MAXRSPCNT) & M_MAXRSPCNT)
1931 #define S_MAXREQCNT 8
1932 #define M_MAXREQCNT 0x1fU
1933 #define V_MAXREQCNT(x) ((x) << S_MAXREQCNT)
1934 #define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT)
1936 #define A_PCIE_CMD_STAT 0x3044
1939 #define M_RSPCNT 0x7fU
1940 #define V_RSPCNT(x) ((x) << S_RSPCNT)
1941 #define G_RSPCNT(x) (((x) >> S_RSPCNT) & M_RSPCNT)
1944 #define M_REQCNT 0xffU
1945 #define V_REQCNT(x) ((x) << S_REQCNT)
1946 #define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT)
1948 #define A_PCIE_HMA_CTRL 0x3050
1950 #define S_IPLTSSM 12
1951 #define M_IPLTSSM 0xfU
1952 #define V_IPLTSSM(x) ((x) << S_IPLTSSM)
1953 #define G_IPLTSSM(x) (((x) >> S_IPLTSSM) & M_IPLTSSM)
1955 #define S_IPCONFIGDOWN 8
1956 #define M_IPCONFIGDOWN 0x7U
1957 #define V_IPCONFIGDOWN(x) ((x) << S_IPCONFIGDOWN)
1958 #define G_IPCONFIGDOWN(x) (((x) >> S_IPCONFIGDOWN) & M_IPCONFIGDOWN)
1960 #define A_PCIE_HMA_CFG 0x3054
1962 #define S_HMA_MAXRSPCNT 16
1963 #define M_HMA_MAXRSPCNT 0x1fU
1964 #define V_HMA_MAXRSPCNT(x) ((x) << S_HMA_MAXRSPCNT)
1965 #define G_HMA_MAXRSPCNT(x) (((x) >> S_HMA_MAXRSPCNT) & M_HMA_MAXRSPCNT)
1967 #define A_PCIE_HMA_STAT 0x3058
1969 #define S_HMA_RSPCNT 16
1970 #define M_HMA_RSPCNT 0xffU
1971 #define V_HMA_RSPCNT(x) ((x) << S_HMA_RSPCNT)
1972 #define G_HMA_RSPCNT(x) (((x) >> S_HMA_RSPCNT) & M_HMA_RSPCNT)
1974 #define A_PCIE_PIO_FIFO_CFG 0x305c
1976 #define S_CPLCONFIG 16
1977 #define M_CPLCONFIG 0xffffU
1978 #define V_CPLCONFIG(x) ((x) << S_CPLCONFIG)
1979 #define G_CPLCONFIG(x) (((x) >> S_CPLCONFIG) & M_CPLCONFIG)
1981 #define S_PIOSTOPEN 12
1982 #define V_PIOSTOPEN(x) ((x) << S_PIOSTOPEN)
1983 #define F_PIOSTOPEN V_PIOSTOPEN(1U)
1985 #define S_IPLANESWAP 11
1986 #define V_IPLANESWAP(x) ((x) << S_IPLANESWAP)
1987 #define F_IPLANESWAP V_IPLANESWAP(1U)
1989 #define S_FORCESTRICTTS1 10
1990 #define V_FORCESTRICTTS1(x) ((x) << S_FORCESTRICTTS1)
1991 #define F_FORCESTRICTTS1 V_FORCESTRICTTS1(1U)
1993 #define S_FORCEPROGRESSCNT 0
1994 #define M_FORCEPROGRESSCNT 0x3ffU
1995 #define V_FORCEPROGRESSCNT(x) ((x) << S_FORCEPROGRESSCNT)
1996 #define G_FORCEPROGRESSCNT(x) (((x) >> S_FORCEPROGRESSCNT) & M_FORCEPROGRESSCNT)
1998 #define A_PCIE_CFG_SPACE_REQ 0x3060
2001 #define V_ENABLE(x) ((x) << S_ENABLE)
2002 #define F_ENABLE V_ENABLE(1U)
2005 #define V_AI(x) ((x) << S_AI)
2006 #define F_AI V_AI(1U)
2008 #define S_LOCALCFG 28
2009 #define V_LOCALCFG(x) ((x) << S_LOCALCFG)
2010 #define F_LOCALCFG V_LOCALCFG(1U)
2014 #define V_BUS(x) ((x) << S_BUS)
2015 #define G_BUS(x) (((x) >> S_BUS) & M_BUS)
2018 #define M_DEVICE 0x1fU
2019 #define V_DEVICE(x) ((x) << S_DEVICE)
2020 #define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE)
2022 #define S_FUNCTION 12
2023 #define M_FUNCTION 0x7U
2024 #define V_FUNCTION(x) ((x) << S_FUNCTION)
2025 #define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION)
2027 #define S_EXTREGISTER 8
2028 #define M_EXTREGISTER 0xfU
2029 #define V_EXTREGISTER(x) ((x) << S_EXTREGISTER)
2030 #define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER)
2032 #define S_REGISTER 0
2033 #define M_REGISTER 0xffU
2034 #define V_REGISTER(x) ((x) << S_REGISTER)
2035 #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)
2037 #define A_PCIE_CFG_SPACE_DATA 0x3064
2038 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
2040 #define S_PCIEOFST 10
2041 #define M_PCIEOFST 0x3fffffU
2042 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
2043 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
2047 #define V_BIR(x) ((x) << S_BIR)
2048 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
2051 #define M_WINDOW 0xffU
2052 #define V_WINDOW(x) ((x) << S_WINDOW)
2053 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
2055 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
2056 #define A_PCIE_MAILBOX_BASE_WIN 0x30a8
2058 #define S_MBOXPCIEOFST 6
2059 #define M_MBOXPCIEOFST 0x3ffffffU
2060 #define V_MBOXPCIEOFST(x) ((x) << S_MBOXPCIEOFST)
2061 #define G_MBOXPCIEOFST(x) (((x) >> S_MBOXPCIEOFST) & M_MBOXPCIEOFST)
2064 #define M_MBOXBIR 0x3U
2065 #define V_MBOXBIR(x) ((x) << S_MBOXBIR)
2066 #define G_MBOXBIR(x) (((x) >> S_MBOXBIR) & M_MBOXBIR)
2069 #define M_MBOXWIN 0x3U
2070 #define V_MBOXWIN(x) ((x) << S_MBOXWIN)
2071 #define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN)
2073 #define A_PCIE_MAILBOX_OFFSET 0x30ac
2074 #define A_PCIE_MA_CTRL 0x30b0
2076 #define S_MA_TAGFREE 29
2077 #define V_MA_TAGFREE(x) ((x) << S_MA_TAGFREE)
2078 #define F_MA_TAGFREE V_MA_TAGFREE(1U)
2080 #define S_MA_MAXRSPCNT 24
2081 #define M_MA_MAXRSPCNT 0x1fU
2082 #define V_MA_MAXRSPCNT(x) ((x) << S_MA_MAXRSPCNT)
2083 #define G_MA_MAXRSPCNT(x) (((x) >> S_MA_MAXRSPCNT) & M_MA_MAXRSPCNT)
2085 #define S_MA_MAXREQCNT 16
2086 #define M_MA_MAXREQCNT 0x1fU
2087 #define V_MA_MAXREQCNT(x) ((x) << S_MA_MAXREQCNT)
2088 #define G_MA_MAXREQCNT(x) (((x) >> S_MA_MAXREQCNT) & M_MA_MAXREQCNT)
2091 #define V_MA_LE(x) ((x) << S_MA_LE)
2092 #define F_MA_LE V_MA_LE(1U)
2094 #define S_MA_MAXPYLDSIZE 12
2095 #define M_MA_MAXPYLDSIZE 0x7U
2096 #define V_MA_MAXPYLDSIZE(x) ((x) << S_MA_MAXPYLDSIZE)
2097 #define G_MA_MAXPYLDSIZE(x) (((x) >> S_MA_MAXPYLDSIZE) & M_MA_MAXPYLDSIZE)
2099 #define S_MA_MAXRDREQSIZE 8
2100 #define M_MA_MAXRDREQSIZE 0x7U
2101 #define V_MA_MAXRDREQSIZE(x) ((x) << S_MA_MAXRDREQSIZE)
2102 #define G_MA_MAXRDREQSIZE(x) (((x) >> S_MA_MAXRDREQSIZE) & M_MA_MAXRDREQSIZE)
2104 #define S_MA_MAXTAG 0
2105 #define M_MA_MAXTAG 0x1fU
2106 #define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG)
2107 #define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG)
2109 #define A_PCIE_MA_SYNC 0x30b4
2110 #define A_PCIE_FW 0x30b8
2111 #define A_PCIE_FW_PF 0x30bc
2112 #define A_PCIE_PIO_PAUSE 0x30dc
2114 #define S_PIOPAUSEDONE 31
2115 #define V_PIOPAUSEDONE(x) ((x) << S_PIOPAUSEDONE)
2116 #define F_PIOPAUSEDONE V_PIOPAUSEDONE(1U)
2118 #define S_PIOPAUSETIME 4
2119 #define M_PIOPAUSETIME 0xffffffU
2120 #define V_PIOPAUSETIME(x) ((x) << S_PIOPAUSETIME)
2121 #define G_PIOPAUSETIME(x) (((x) >> S_PIOPAUSETIME) & M_PIOPAUSETIME)
2123 #define S_PIOPAUSE 0
2124 #define V_PIOPAUSE(x) ((x) << S_PIOPAUSE)
2125 #define F_PIOPAUSE V_PIOPAUSE(1U)
2127 #define A_PCIE_SYS_CFG_READY 0x30e0
2128 #define A_PCIE_STATIC_CFG1 0x30e4
2130 #define S_LINKDOWN_RESET_EN 26
2131 #define V_LINKDOWN_RESET_EN(x) ((x) << S_LINKDOWN_RESET_EN)
2132 #define F_LINKDOWN_RESET_EN V_LINKDOWN_RESET_EN(1U)
2134 #define S_IN_WR_DISCONTIG 25
2135 #define V_IN_WR_DISCONTIG(x) ((x) << S_IN_WR_DISCONTIG)
2136 #define F_IN_WR_DISCONTIG V_IN_WR_DISCONTIG(1U)
2138 #define S_IN_RD_CPLSIZE 22
2139 #define M_IN_RD_CPLSIZE 0x7U
2140 #define V_IN_RD_CPLSIZE(x) ((x) << S_IN_RD_CPLSIZE)
2141 #define G_IN_RD_CPLSIZE(x) (((x) >> S_IN_RD_CPLSIZE) & M_IN_RD_CPLSIZE)
2143 #define S_IN_RD_BUFMODE 20
2144 #define M_IN_RD_BUFMODE 0x3U
2145 #define V_IN_RD_BUFMODE(x) ((x) << S_IN_RD_BUFMODE)
2146 #define G_IN_RD_BUFMODE(x) (((x) >> S_IN_RD_BUFMODE) & M_IN_RD_BUFMODE)
2148 #define S_GBIF_NPTRANS_TOT 18
2149 #define M_GBIF_NPTRANS_TOT 0x3U
2150 #define V_GBIF_NPTRANS_TOT(x) ((x) << S_GBIF_NPTRANS_TOT)
2151 #define G_GBIF_NPTRANS_TOT(x) (((x) >> S_GBIF_NPTRANS_TOT) & M_GBIF_NPTRANS_TOT)
2153 #define S_IN_PDAT_TOT 15
2154 #define M_IN_PDAT_TOT 0x7U
2155 #define V_IN_PDAT_TOT(x) ((x) << S_IN_PDAT_TOT)
2156 #define G_IN_PDAT_TOT(x) (((x) >> S_IN_PDAT_TOT) & M_IN_PDAT_TOT)
2158 #define S_PCIE_NPTRANS_TOT 12
2159 #define M_PCIE_NPTRANS_TOT 0x7U
2160 #define V_PCIE_NPTRANS_TOT(x) ((x) << S_PCIE_NPTRANS_TOT)
2161 #define G_PCIE_NPTRANS_TOT(x) (((x) >> S_PCIE_NPTRANS_TOT) & M_PCIE_NPTRANS_TOT)
2163 #define S_OUT_PDAT_TOT 9
2164 #define M_OUT_PDAT_TOT 0x7U
2165 #define V_OUT_PDAT_TOT(x) ((x) << S_OUT_PDAT_TOT)
2166 #define G_OUT_PDAT_TOT(x) (((x) >> S_OUT_PDAT_TOT) & M_OUT_PDAT_TOT)
2168 #define S_GBIF_MAX_WRSIZE 6
2169 #define M_GBIF_MAX_WRSIZE 0x7U
2170 #define V_GBIF_MAX_WRSIZE(x) ((x) << S_GBIF_MAX_WRSIZE)
2171 #define G_GBIF_MAX_WRSIZE(x) (((x) >> S_GBIF_MAX_WRSIZE) & M_GBIF_MAX_WRSIZE)
2173 #define S_GBIF_MAX_RDSIZE 3
2174 #define M_GBIF_MAX_RDSIZE 0x7U
2175 #define V_GBIF_MAX_RDSIZE(x) ((x) << S_GBIF_MAX_RDSIZE)
2176 #define G_GBIF_MAX_RDSIZE(x) (((x) >> S_GBIF_MAX_RDSIZE) & M_GBIF_MAX_RDSIZE)
2178 #define S_PCIE_MAX_RDSIZE 0
2179 #define M_PCIE_MAX_RDSIZE 0x7U
2180 #define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE)
2181 #define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE)
2183 #define A_PCIE_DBG_INDIR_REQ 0x30ec
2185 #define S_DBGENABLE 31
2186 #define V_DBGENABLE(x) ((x) << S_DBGENABLE)
2187 #define F_DBGENABLE V_DBGENABLE(1U)
2189 #define S_DBGAUTOINC 30
2190 #define V_DBGAUTOINC(x) ((x) << S_DBGAUTOINC)
2191 #define F_DBGAUTOINC V_DBGAUTOINC(1U)
2194 #define M_POINTER 0xffffU
2195 #define V_POINTER(x) ((x) << S_POINTER)
2196 #define G_POINTER(x) (((x) >> S_POINTER) & M_POINTER)
2199 #define M_SELECT 0xfU
2200 #define V_SELECT(x) ((x) << S_SELECT)
2201 #define G_SELECT(x) (((x) >> S_SELECT) & M_SELECT)
2203 #define A_PCIE_DBG_INDIR_DATA_0 0x30f0
2204 #define A_PCIE_DBG_INDIR_DATA_1 0x30f4
2205 #define A_PCIE_DBG_INDIR_DATA_2 0x30f8
2206 #define A_PCIE_DBG_INDIR_DATA_3 0x30fc
2207 #define A_PCIE_FUNC_INT_CFG 0x3100
2209 #define S_PBAOFST 28
2210 #define M_PBAOFST 0xfU
2211 #define V_PBAOFST(x) ((x) << S_PBAOFST)
2212 #define G_PBAOFST(x) (((x) >> S_PBAOFST) & M_PBAOFST)
2214 #define S_TABOFST 24
2215 #define M_TABOFST 0xfU
2216 #define V_TABOFST(x) ((x) << S_TABOFST)
2217 #define G_TABOFST(x) (((x) >> S_TABOFST) & M_TABOFST)
2220 #define M_VECNUM 0x3ffU
2221 #define V_VECNUM(x) ((x) << S_VECNUM)
2222 #define G_VECNUM(x) (((x) >> S_VECNUM) & M_VECNUM)
2225 #define M_VECBASE 0x7ffU
2226 #define V_VECBASE(x) ((x) << S_VECBASE)
2227 #define G_VECBASE(x) (((x) >> S_VECBASE) & M_VECBASE)
2229 #define A_PCIE_FUNC_CTL_STAT 0x3104
2231 #define S_SENDFLRRSP 31
2232 #define V_SENDFLRRSP(x) ((x) << S_SENDFLRRSP)
2233 #define F_SENDFLRRSP V_SENDFLRRSP(1U)
2235 #define S_IMMFLRRSP 24
2236 #define V_IMMFLRRSP(x) ((x) << S_IMMFLRRSP)
2237 #define F_IMMFLRRSP V_IMMFLRRSP(1U)
2239 #define S_TXNDISABLE 20
2240 #define V_TXNDISABLE(x) ((x) << S_TXNDISABLE)
2241 #define F_TXNDISABLE V_TXNDISABLE(1U)
2244 #define M_PNDTXNS 0x3ffU
2245 #define V_PNDTXNS(x) ((x) << S_PNDTXNS)
2246 #define G_PNDTXNS(x) (((x) >> S_PNDTXNS) & M_PNDTXNS)
2249 #define V_VFVLD(x) ((x) << S_VFVLD)
2250 #define F_VFVLD V_VFVLD(1U)
2253 #define M_PFNUM 0x7U
2254 #define V_PFNUM(x) ((x) << S_PFNUM)
2255 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
2257 #define A_PCIE_FID 0x3900
2260 #define V_PAD(x) ((x) << S_PAD)
2261 #define F_PAD V_PAD(1U)
2265 #define V_TC(x) ((x) << S_TC)
2266 #define G_TC(x) (((x) >> S_TC) & M_TC)
2269 #define M_FUNC 0xffU
2270 #define V_FUNC(x) ((x) << S_FUNC)
2271 #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC)
2273 #define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900
2276 #define V_SMTD(x) ((x) << S_SMTD)
2277 #define F_SMTD V_SMTD(1U)
2280 #define V_SSTD(x) ((x) << S_SSTD)
2281 #define F_SSTD V_SSTD(1U)
2284 #define V_SWD0(x) ((x) << S_SWD0)
2285 #define F_SWD0 V_SWD0(1U)
2288 #define V_SWD1(x) ((x) << S_SWD1)
2289 #define F_SWD1 V_SWD1(1U)
2292 #define V_SWD2(x) ((x) << S_SWD2)
2293 #define F_SWD2 V_SWD2(1U)
2296 #define V_SWD3(x) ((x) << S_SWD3)
2297 #define F_SWD3 V_SWD3(1U)
2300 #define V_SWD4(x) ((x) << S_SWD4)
2301 #define F_SWD4 V_SWD4(1U)
2304 #define V_SWD5(x) ((x) << S_SWD5)
2305 #define F_SWD5 V_SWD5(1U)
2308 #define V_SWD6(x) ((x) << S_SWD6)
2309 #define F_SWD6 V_SWD6(1U)
2312 #define V_SWD7(x) ((x) << S_SWD7)
2313 #define F_SWD7 V_SWD7(1U)
2316 #define V_SWD8(x) ((x) << S_SWD8)
2317 #define F_SWD8 V_SWD8(1U)
2320 #define V_SRD0(x) ((x) << S_SRD0)
2321 #define F_SRD0 V_SRD0(1U)
2324 #define V_SRD1(x) ((x) << S_SRD1)
2325 #define F_SRD1 V_SRD1(1U)
2328 #define V_SRD2(x) ((x) << S_SRD2)
2329 #define F_SRD2 V_SRD2(1U)
2332 #define V_SRD3(x) ((x) << S_SRD3)
2333 #define F_SRD3 V_SRD3(1U)
2336 #define V_SRD4(x) ((x) << S_SRD4)
2337 #define F_SRD4 V_SRD4(1U)
2340 #define V_SRD5(x) ((x) << S_SRD5)
2341 #define F_SRD5 V_SRD5(1U)
2344 #define V_SRD6(x) ((x) << S_SRD6)
2345 #define F_SRD6 V_SRD6(1U)
2348 #define V_SRD7(x) ((x) << S_SRD7)
2349 #define F_SRD7 V_SRD7(1U)
2352 #define V_SRD8(x) ((x) << S_SRD8)
2353 #define F_SRD8 V_SRD8(1U)
2356 #define V_CRRE(x) ((x) << S_CRRE)
2357 #define F_CRRE V_CRRE(1U)
2361 #define V_CRMC(x) ((x) << S_CRMC)
2362 #define G_CRMC(x) (((x) >> S_CRMC) & M_CRMC)
2364 #define A_PCIE_CORE_UTL_STATUS 0x5904
2367 #define V_USBP(x) ((x) << S_USBP)
2368 #define F_USBP V_USBP(1U)
2371 #define V_UPEP(x) ((x) << S_UPEP)
2372 #define F_UPEP V_UPEP(1U)
2375 #define V_RCEP(x) ((x) << S_RCEP)
2376 #define F_RCEP V_RCEP(1U)
2379 #define V_EPEP(x) ((x) << S_EPEP)
2380 #define F_EPEP V_EPEP(1U)
2383 #define V_USBS(x) ((x) << S_USBS)
2384 #define F_USBS V_USBS(1U)
2387 #define V_UPES(x) ((x) << S_UPES)
2388 #define F_UPES V_UPES(1U)
2391 #define V_RCES(x) ((x) << S_RCES)
2392 #define F_RCES V_RCES(1U)
2395 #define V_EPES(x) ((x) << S_EPES)
2396 #define F_EPES V_EPES(1U)
2398 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
2401 #define V_RNPP(x) ((x) << S_RNPP)
2402 #define F_RNPP V_RNPP(1U)
2405 #define V_RPCP(x) ((x) << S_RPCP)
2406 #define F_RPCP V_RPCP(1U)
2409 #define V_RCIP(x) ((x) << S_RCIP)
2410 #define F_RCIP V_RCIP(1U)
2413 #define V_RCCP(x) ((x) << S_RCCP)
2414 #define F_RCCP V_RCCP(1U)
2417 #define V_RFTP(x) ((x) << S_RFTP)
2418 #define F_RFTP V_RFTP(1U)
2421 #define V_PTRP(x) ((x) << S_PTRP)
2422 #define F_PTRP V_PTRP(1U)
2424 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY 0x590c
2427 #define V_RNPS(x) ((x) << S_RNPS)
2428 #define F_RNPS V_RNPS(1U)
2431 #define V_RPCS(x) ((x) << S_RPCS)
2432 #define F_RPCS V_RPCS(1U)
2435 #define V_RCIS(x) ((x) << S_RCIS)
2436 #define F_RCIS V_RCIS(1U)
2439 #define V_RCCS(x) ((x) << S_RCCS)
2440 #define F_RCCS V_RCCS(1U)
2443 #define V_RFTS(x) ((x) << S_RFTS)
2444 #define F_RFTS V_RFTS(1U)
2446 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE 0x5910
2449 #define V_RNPI(x) ((x) << S_RNPI)
2450 #define F_RNPI V_RNPI(1U)
2453 #define V_RPCI(x) ((x) << S_RPCI)
2454 #define F_RPCI V_RPCI(1U)
2457 #define V_RCII(x) ((x) << S_RCII)
2458 #define F_RCII V_RCII(1U)
2461 #define V_RCCI(x) ((x) << S_RCCI)
2462 #define F_RCCI V_RCCI(1U)
2465 #define V_RFTI(x) ((x) << S_RFTI)
2466 #define F_RFTI V_RFTI(1U)
2468 #define A_PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION 0x5920
2472 #define V_SBRS(x) ((x) << S_SBRS)
2473 #define G_SBRS(x) (((x) >> S_SBRS) & M_SBRS)
2477 #define V_OTWS(x) ((x) << S_OTWS)
2478 #define G_OTWS(x) (((x) >> S_OTWS) & M_OTWS)
2480 #define A_PCIE_CORE_REVISION_ID 0x5924
2483 #define M_RVID 0xfffU
2484 #define V_RVID(x) ((x) << S_RVID)
2485 #define G_RVID(x) (((x) >> S_RVID) & M_RVID)
2488 #define M_BRVN 0xffU
2489 #define V_BRVN(x) ((x) << S_BRVN)
2490 #define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN)
2492 #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
2496 #define V_OP0H(x) ((x) << S_OP0H)
2497 #define G_OP0H(x) (((x) >> S_OP0H) & M_OP0H)
2501 #define V_OP1H(x) ((x) << S_OP1H)
2502 #define G_OP1H(x) (((x) >> S_OP1H) & M_OP1H)
2506 #define V_OP2H(x) ((x) << S_OP2H)
2507 #define G_OP2H(x) (((x) >> S_OP2H) & M_OP2H)
2511 #define V_OP3H(x) ((x) << S_OP3H)
2512 #define G_OP3H(x) (((x) >> S_OP3H) & M_OP3H)
2514 #define A_PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5968
2517 #define M_OP0D 0x7fU
2518 #define V_OP0D(x) ((x) << S_OP0D)
2519 #define G_OP0D(x) (((x) >> S_OP0D) & M_OP0D)
2522 #define M_OP1D 0x7fU
2523 #define V_OP1D(x) ((x) << S_OP1D)
2524 #define G_OP1D(x) (((x) >> S_OP1D) & M_OP1D)
2527 #define M_OP2D 0x7fU
2528 #define V_OP2D(x) ((x) << S_OP2D)
2529 #define G_OP2D(x) (((x) >> S_OP2D) & M_OP2D)
2532 #define M_OP3D 0x7fU
2533 #define V_OP3D(x) ((x) << S_OP3D)
2534 #define G_OP3D(x) (((x) >> S_OP3D) & M_OP3D)
2536 #define A_PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5970
2539 #define M_IP0H 0x3fU
2540 #define V_IP0H(x) ((x) << S_IP0H)
2541 #define G_IP0H(x) (((x) >> S_IP0H) & M_IP0H)
2544 #define M_IP1H 0x3fU
2545 #define V_IP1H(x) ((x) << S_IP1H)
2546 #define G_IP1H(x) (((x) >> S_IP1H) & M_IP1H)
2549 #define M_IP2H 0x3fU
2550 #define V_IP2H(x) ((x) << S_IP2H)
2551 #define G_IP2H(x) (((x) >> S_IP2H) & M_IP2H)
2554 #define M_IP3H 0x3fU
2555 #define V_IP3H(x) ((x) << S_IP3H)
2556 #define G_IP3H(x) (((x) >> S_IP3H) & M_IP3H)
2558 #define A_PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5978
2561 #define M_IP0D 0xffU
2562 #define V_IP0D(x) ((x) << S_IP0D)
2563 #define G_IP0D(x) (((x) >> S_IP0D) & M_IP0D)
2566 #define M_IP1D 0xffU
2567 #define V_IP1D(x) ((x) << S_IP1D)
2568 #define G_IP1D(x) (((x) >> S_IP1D) & M_IP1D)
2571 #define M_IP2D 0xffU
2572 #define V_IP2D(x) ((x) << S_IP2D)
2573 #define G_IP2D(x) (((x) >> S_IP2D) & M_IP2D)
2576 #define M_IP3D 0xffU
2577 #define V_IP3D(x) ((x) << S_IP3D)
2578 #define G_IP3D(x) (((x) >> S_IP3D) & M_IP3D)
2580 #define A_PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION 0x5980
2584 #define V_ON0H(x) ((x) << S_ON0H)
2585 #define G_ON0H(x) (((x) >> S_ON0H) & M_ON0H)
2589 #define V_ON1H(x) ((x) << S_ON1H)
2590 #define G_ON1H(x) (((x) >> S_ON1H) & M_ON1H)
2594 #define V_ON2H(x) ((x) << S_ON2H)
2595 #define G_ON2H(x) (((x) >> S_ON2H) & M_ON2H)
2599 #define V_ON3H(x) ((x) << S_ON3H)
2600 #define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H)
2602 #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
2605 #define M_IN0H 0x3fU
2606 #define V_IN0H(x) ((x) << S_IN0H)
2607 #define G_IN0H(x) (((x) >> S_IN0H) & M_IN0H)
2610 #define M_IN1H 0x3fU
2611 #define V_IN1H(x) ((x) << S_IN1H)
2612 #define G_IN1H(x) (((x) >> S_IN1H) & M_IN1H)
2615 #define M_IN2H 0x3fU
2616 #define V_IN2H(x) ((x) << S_IN2H)
2617 #define G_IN2H(x) (((x) >> S_IN2H) & M_IN2H)
2620 #define M_IN3H 0x3fU
2621 #define V_IN3H(x) ((x) << S_IN3H)
2622 #define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H)
2624 #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
2627 #define M_OC0T 0xffU
2628 #define V_OC0T(x) ((x) << S_OC0T)
2629 #define G_OC0T(x) (((x) >> S_OC0T) & M_OC0T)
2632 #define M_OC1T 0xffU
2633 #define V_OC1T(x) ((x) << S_OC1T)
2634 #define G_OC1T(x) (((x) >> S_OC1T) & M_OC1T)
2637 #define M_OC2T 0xffU
2638 #define V_OC2T(x) ((x) << S_OC2T)
2639 #define G_OC2T(x) (((x) >> S_OC2T) & M_OC2T)
2642 #define M_OC3T 0xffU
2643 #define V_OC3T(x) ((x) << S_OC3T)
2644 #define G_OC3T(x) (((x) >> S_OC3T) & M_OC3T)
2646 #define A_PCIE_CORE_GBIF_READ_TAGS_ALLOCATION 0x5998
2649 #define M_IC0T 0x3fU
2650 #define V_IC0T(x) ((x) << S_IC0T)
2651 #define G_IC0T(x) (((x) >> S_IC0T) & M_IC0T)
2654 #define M_IC1T 0x3fU
2655 #define V_IC1T(x) ((x) << S_IC1T)
2656 #define G_IC1T(x) (((x) >> S_IC1T) & M_IC1T)
2659 #define M_IC2T 0x3fU
2660 #define V_IC2T(x) ((x) << S_IC2T)
2661 #define G_IC2T(x) (((x) >> S_IC2T) & M_IC2T)
2664 #define M_IC3T 0x3fU
2665 #define V_IC3T(x) ((x) << S_IC3T)
2666 #define G_IC3T(x) (((x) >> S_IC3T) & M_IC3T)
2668 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL 0x59a0
2671 #define V_VRB0(x) ((x) << S_VRB0)
2672 #define F_VRB0 V_VRB0(1U)
2675 #define V_VRB1(x) ((x) << S_VRB1)
2676 #define F_VRB1 V_VRB1(1U)
2679 #define V_VRB2(x) ((x) << S_VRB2)
2680 #define F_VRB2 V_VRB2(1U)
2683 #define V_VRB3(x) ((x) << S_VRB3)
2684 #define F_VRB3 V_VRB3(1U)
2687 #define V_PSFE(x) ((x) << S_PSFE)
2688 #define F_PSFE V_PSFE(1U)
2691 #define V_RVDE(x) ((x) << S_RVDE)
2692 #define F_RVDE V_RVDE(1U)
2695 #define V_TXE0(x) ((x) << S_TXE0)
2696 #define F_TXE0 V_TXE0(1U)
2699 #define V_TXE1(x) ((x) << S_TXE1)
2700 #define F_TXE1 V_TXE1(1U)
2703 #define V_TXE2(x) ((x) << S_TXE2)
2704 #define F_TXE2 V_TXE2(1U)
2707 #define V_TXE3(x) ((x) << S_TXE3)
2708 #define F_TXE3 V_TXE3(1U)
2711 #define V_RPAM(x) ((x) << S_RPAM)
2712 #define F_RPAM V_RPAM(1U)
2716 #define V_RTOS(x) ((x) << S_RTOS)
2717 #define G_RTOS(x) (((x) >> S_RTOS) & M_RTOS)
2719 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
2722 #define V_TPCP(x) ((x) << S_TPCP)
2723 #define F_TPCP V_TPCP(1U)
2726 #define V_TNPP(x) ((x) << S_TNPP)
2727 #define F_TNPP V_TNPP(1U)
2730 #define V_TFTP(x) ((x) << S_TFTP)
2731 #define F_TFTP V_TFTP(1U)
2734 #define V_TCAP(x) ((x) << S_TCAP)
2735 #define F_TCAP V_TCAP(1U)
2738 #define V_TCIP(x) ((x) << S_TCIP)
2739 #define F_TCIP V_TCIP(1U)
2742 #define V_RCAP(x) ((x) << S_RCAP)
2743 #define F_RCAP V_RCAP(1U)
2746 #define V_PLUP(x) ((x) << S_PLUP)
2747 #define F_PLUP V_PLUP(1U)
2750 #define V_PLDN(x) ((x) << S_PLDN)
2751 #define F_PLDN V_PLDN(1U)
2754 #define V_OTDD(x) ((x) << S_OTDD)
2755 #define F_OTDD V_OTDD(1U)
2758 #define V_GTRP(x) ((x) << S_GTRP)
2759 #define F_GTRP V_GTRP(1U)
2762 #define V_RDPE(x) ((x) << S_RDPE)
2763 #define F_RDPE V_RDPE(1U)
2766 #define V_TDCE(x) ((x) << S_TDCE)
2767 #define F_TDCE V_TDCE(1U)
2770 #define V_TDUE(x) ((x) << S_TDUE)
2771 #define F_TDUE V_TDUE(1U)
2773 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY 0x59a8
2776 #define V_TPCS(x) ((x) << S_TPCS)
2777 #define F_TPCS V_TPCS(1U)
2780 #define V_TNPS(x) ((x) << S_TNPS)
2781 #define F_TNPS V_TNPS(1U)
2784 #define V_TFTS(x) ((x) << S_TFTS)
2785 #define F_TFTS V_TFTS(1U)
2788 #define V_TCAS(x) ((x) << S_TCAS)
2789 #define F_TCAS V_TCAS(1U)
2792 #define V_TCIS(x) ((x) << S_TCIS)
2793 #define F_TCIS V_TCIS(1U)
2796 #define V_RCAS(x) ((x) << S_RCAS)
2797 #define F_RCAS V_RCAS(1U)
2800 #define V_PLUS(x) ((x) << S_PLUS)
2801 #define F_PLUS V_PLUS(1U)
2804 #define V_PLDS(x) ((x) << S_PLDS)
2805 #define F_PLDS V_PLDS(1U)
2808 #define V_OTDS(x) ((x) << S_OTDS)
2809 #define F_OTDS V_OTDS(1U)
2812 #define V_RDPS(x) ((x) << S_RDPS)
2813 #define F_RDPS V_RDPS(1U)
2816 #define V_TDCS(x) ((x) << S_TDCS)
2817 #define F_TDCS V_TDCS(1U)
2820 #define V_TDUS(x) ((x) << S_TDUS)
2821 #define F_TDUS V_TDUS(1U)
2823 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE 0x59ac
2826 #define V_TPCI(x) ((x) << S_TPCI)
2827 #define F_TPCI V_TPCI(1U)
2830 #define V_TNPI(x) ((x) << S_TNPI)
2831 #define F_TNPI V_TNPI(1U)
2834 #define V_TFTI(x) ((x) << S_TFTI)
2835 #define F_TFTI V_TFTI(1U)
2838 #define V_TCAI(x) ((x) << S_TCAI)
2839 #define F_TCAI V_TCAI(1U)
2842 #define V_TCII(x) ((x) << S_TCII)
2843 #define F_TCII V_TCII(1U)
2846 #define V_RCAI(x) ((x) << S_RCAI)
2847 #define F_RCAI V_RCAI(1U)
2850 #define V_PLUI(x) ((x) << S_PLUI)
2851 #define F_PLUI V_PLUI(1U)
2854 #define V_PLDI(x) ((x) << S_PLDI)
2855 #define F_PLDI V_PLDI(1U)
2858 #define V_OTDI(x) ((x) << S_OTDI)
2859 #define F_OTDI V_OTDI(1U)
2861 #define A_PCIE_CORE_ROOT_COMPLEX_STATUS 0x59b0
2864 #define V_RLCE(x) ((x) << S_RLCE)
2865 #define F_RLCE V_RLCE(1U)
2868 #define V_RLNE(x) ((x) << S_RLNE)
2869 #define F_RLNE V_RLNE(1U)
2872 #define V_RLFE(x) ((x) << S_RLFE)
2873 #define F_RLFE V_RLFE(1U)
2876 #define V_RCPE(x) ((x) << S_RCPE)
2877 #define F_RCPE V_RCPE(1U)
2880 #define V_RCTO(x) ((x) << S_RCTO)
2881 #define F_RCTO V_RCTO(1U)
2884 #define V_PINA(x) ((x) << S_PINA)
2885 #define F_PINA V_PINA(1U)
2888 #define V_PINB(x) ((x) << S_PINB)
2889 #define F_PINB V_PINB(1U)
2892 #define V_PINC(x) ((x) << S_PINC)
2893 #define F_PINC V_PINC(1U)
2896 #define V_PIND(x) ((x) << S_PIND)
2897 #define F_PIND V_PIND(1U)
2900 #define V_ALER(x) ((x) << S_ALER)
2901 #define F_ALER V_ALER(1U)
2904 #define V_CRSE(x) ((x) << S_CRSE)
2905 #define F_CRSE V_CRSE(1U)
2907 #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
2910 #define V_RLCS(x) ((x) << S_RLCS)
2911 #define F_RLCS V_RLCS(1U)
2914 #define V_RLNS(x) ((x) << S_RLNS)
2915 #define F_RLNS V_RLNS(1U)
2918 #define V_RLFS(x) ((x) << S_RLFS)
2919 #define F_RLFS V_RLFS(1U)
2922 #define V_RCPS(x) ((x) << S_RCPS)
2923 #define F_RCPS V_RCPS(1U)
2926 #define V_RCTS(x) ((x) << S_RCTS)
2927 #define F_RCTS V_RCTS(1U)
2930 #define V_PAAS(x) ((x) << S_PAAS)
2931 #define F_PAAS V_PAAS(1U)
2934 #define V_PABS(x) ((x) << S_PABS)
2935 #define F_PABS V_PABS(1U)
2938 #define V_PACS(x) ((x) << S_PACS)
2939 #define F_PACS V_PACS(1U)
2942 #define V_PADS(x) ((x) << S_PADS)
2943 #define F_PADS V_PADS(1U)
2946 #define V_ALES(x) ((x) << S_ALES)
2947 #define F_ALES V_ALES(1U)
2950 #define V_CRSS(x) ((x) << S_CRSS)
2951 #define F_CRSS V_CRSS(1U)
2953 #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
2956 #define V_RLCI(x) ((x) << S_RLCI)
2957 #define F_RLCI V_RLCI(1U)
2960 #define V_RLNI(x) ((x) << S_RLNI)
2961 #define F_RLNI V_RLNI(1U)
2964 #define V_RLFI(x) ((x) << S_RLFI)
2965 #define F_RLFI V_RLFI(1U)
2968 #define V_RCPI(x) ((x) << S_RCPI)
2969 #define F_RCPI V_RCPI(1U)
2972 #define V_RCTI(x) ((x) << S_RCTI)
2973 #define F_RCTI V_RCTI(1U)
2976 #define V_PAAI(x) ((x) << S_PAAI)
2977 #define F_PAAI V_PAAI(1U)
2980 #define V_PABI(x) ((x) << S_PABI)
2981 #define F_PABI V_PABI(1U)
2984 #define V_PACI(x) ((x) << S_PACI)
2985 #define F_PACI V_PACI(1U)
2988 #define V_PADI(x) ((x) << S_PADI)
2989 #define F_PADI V_PADI(1U)
2992 #define V_ALEI(x) ((x) << S_ALEI)
2993 #define F_ALEI V_ALEI(1U)
2996 #define V_CRSI(x) ((x) << S_CRSI)
2997 #define F_CRSI V_CRSI(1U)
2999 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
3002 #define V_PTOM(x) ((x) << S_PTOM)
3003 #define F_PTOM V_PTOM(1U)
3006 #define V_ALEA(x) ((x) << S_ALEA)
3007 #define F_ALEA V_ALEA(1U)
3010 #define V_PMC0(x) ((x) << S_PMC0)
3011 #define F_PMC0 V_PMC0(1U)
3014 #define V_PMC1(x) ((x) << S_PMC1)
3015 #define F_PMC1 V_PMC1(1U)
3018 #define V_PMC2(x) ((x) << S_PMC2)
3019 #define F_PMC2 V_PMC2(1U)
3022 #define V_PMC3(x) ((x) << S_PMC3)
3023 #define F_PMC3 V_PMC3(1U)
3026 #define V_PMC4(x) ((x) << S_PMC4)
3027 #define F_PMC4 V_PMC4(1U)
3030 #define V_PMC5(x) ((x) << S_PMC5)
3031 #define F_PMC5 V_PMC5(1U)
3034 #define V_PMC6(x) ((x) << S_PMC6)
3035 #define F_PMC6 V_PMC6(1U)
3038 #define V_PMC7(x) ((x) << S_PMC7)
3039 #define F_PMC7 V_PMC7(1U)
3041 #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
3044 #define V_PTOS(x) ((x) << S_PTOS)
3045 #define F_PTOS V_PTOS(1U)
3048 #define V_AENS(x) ((x) << S_AENS)
3049 #define F_AENS V_AENS(1U)
3052 #define V_PC0S(x) ((x) << S_PC0S)
3053 #define F_PC0S V_PC0S(1U)
3056 #define V_PC1S(x) ((x) << S_PC1S)
3057 #define F_PC1S V_PC1S(1U)
3060 #define V_PC2S(x) ((x) << S_PC2S)
3061 #define F_PC2S V_PC2S(1U)
3064 #define V_PC3S(x) ((x) << S_PC3S)
3065 #define F_PC3S V_PC3S(1U)
3068 #define V_PC4S(x) ((x) << S_PC4S)
3069 #define F_PC4S V_PC4S(1U)
3072 #define V_PC5S(x) ((x) << S_PC5S)
3073 #define F_PC5S V_PC5S(1U)
3076 #define V_PC6S(x) ((x) << S_PC6S)
3077 #define F_PC6S V_PC6S(1U)
3080 #define V_PC7S(x) ((x) << S_PC7S)
3081 #define F_PC7S V_PC7S(1U)
3084 #define V_PME0(x) ((x) << S_PME0)
3085 #define F_PME0 V_PME0(1U)
3088 #define V_PME1(x) ((x) << S_PME1)
3089 #define F_PME1 V_PME1(1U)
3092 #define V_PME2(x) ((x) << S_PME2)
3093 #define F_PME2 V_PME2(1U)
3096 #define V_PME3(x) ((x) << S_PME3)
3097 #define F_PME3 V_PME3(1U)
3100 #define V_PME4(x) ((x) << S_PME4)
3101 #define F_PME4 V_PME4(1U)
3104 #define V_PME5(x) ((x) << S_PME5)
3105 #define F_PME5 V_PME5(1U)
3108 #define V_PME6(x) ((x) << S_PME6)
3109 #define F_PME6 V_PME6(1U)
3112 #define V_PME7(x) ((x) << S_PME7)
3113 #define F_PME7 V_PME7(1U)
3115 #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
3118 #define V_PTOI(x) ((x) << S_PTOI)
3119 #define F_PTOI V_PTOI(1U)
3122 #define V_AENI(x) ((x) << S_AENI)
3123 #define F_AENI V_AENI(1U)
3126 #define V_PC0I(x) ((x) << S_PC0I)
3127 #define F_PC0I V_PC0I(1U)
3130 #define V_PC1I(x) ((x) << S_PC1I)
3131 #define F_PC1I V_PC1I(1U)
3134 #define V_PC2I(x) ((x) << S_PC2I)
3135 #define F_PC2I V_PC2I(1U)
3138 #define V_PC3I(x) ((x) << S_PC3I)
3139 #define F_PC3I V_PC3I(1U)
3142 #define V_PC4I(x) ((x) << S_PC4I)
3143 #define F_PC4I V_PC4I(1U)
3146 #define V_PC5I(x) ((x) << S_PC5I)
3147 #define F_PC5I V_PC5I(1U)
3150 #define V_PC6I(x) ((x) << S_PC6I)
3151 #define F_PC6I V_PC6I(1U)
3154 #define V_PC7I(x) ((x) << S_PC7I)
3155 #define F_PC7I V_PC7I(1U)
3157 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8
3160 #define V_TOAK(x) ((x) << S_TOAK)
3161 #define F_TOAK V_TOAK(1U)
3164 #define V_L1RS(x) ((x) << S_L1RS)
3165 #define F_L1RS V_L1RS(1U)
3168 #define V_L23S(x) ((x) << S_L23S)
3169 #define F_L23S V_L23S(1U)
3172 #define V_AL1S(x) ((x) << S_AL1S)
3173 #define F_AL1S V_AL1S(1U)
3176 #define V_ALET(x) ((x) << S_ALET)
3177 #define F_ALET V_ALET(1U)
3179 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc
3183 #define V_CPM0(x) ((x) << S_CPM0)
3184 #define G_CPM0(x) (((x) >> S_CPM0) & M_CPM0)
3188 #define V_CPM1(x) ((x) << S_CPM1)
3189 #define G_CPM1(x) (((x) >> S_CPM1) & M_CPM1)
3193 #define V_CPM2(x) ((x) << S_CPM2)
3194 #define G_CPM2(x) (((x) >> S_CPM2) & M_CPM2)
3198 #define V_CPM3(x) ((x) << S_CPM3)
3199 #define G_CPM3(x) (((x) >> S_CPM3) & M_CPM3)
3203 #define V_CPM4(x) ((x) << S_CPM4)
3204 #define G_CPM4(x) (((x) >> S_CPM4) & M_CPM4)
3208 #define V_CPM5(x) ((x) << S_CPM5)
3209 #define G_CPM5(x) (((x) >> S_CPM5) & M_CPM5)
3213 #define V_CPM6(x) ((x) << S_CPM6)
3214 #define G_CPM6(x) (((x) >> S_CPM6) & M_CPM6)
3218 #define V_CPM7(x) ((x) << S_CPM7)
3219 #define G_CPM7(x) (((x) >> S_CPM7) & M_CPM7)
3223 #define V_OPM0(x) ((x) << S_OPM0)
3224 #define G_OPM0(x) (((x) >> S_OPM0) & M_OPM0)
3228 #define V_OPM1(x) ((x) << S_OPM1)
3229 #define G_OPM1(x) (((x) >> S_OPM1) & M_OPM1)
3233 #define V_OPM2(x) ((x) << S_OPM2)
3234 #define G_OPM2(x) (((x) >> S_OPM2) & M_OPM2)
3238 #define V_OPM3(x) ((x) << S_OPM3)
3239 #define G_OPM3(x) (((x) >> S_OPM3) & M_OPM3)
3243 #define V_OPM4(x) ((x) << S_OPM4)
3244 #define G_OPM4(x) (((x) >> S_OPM4) & M_OPM4)
3248 #define V_OPM5(x) ((x) << S_OPM5)
3249 #define G_OPM5(x) (((x) >> S_OPM5) & M_OPM5)
3253 #define V_OPM6(x) ((x) << S_OPM6)
3254 #define G_OPM6(x) (((x) >> S_OPM6) & M_OPM6)
3258 #define V_OPM7(x) ((x) << S_OPM7)
3259 #define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7)
3261 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0
3262 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
3263 #define A_PCIE_REVISION 0x5a00
3264 #define A_PCIE_PDEBUG_INDEX 0x5a04
3266 #define S_PDEBUGSELH 16
3267 #define M_PDEBUGSELH 0x3fU
3268 #define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH)
3269 #define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH)
3271 #define S_PDEBUGSELL 0
3272 #define M_PDEBUGSELL 0x3fU
3273 #define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
3274 #define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)
3276 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
3277 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
3278 #define A_PCIE_CDEBUG_INDEX 0x5a10
3280 #define S_CDEBUGSELH 16
3281 #define M_CDEBUGSELH 0xffU
3282 #define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH)
3283 #define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH)
3285 #define S_CDEBUGSELL 0
3286 #define M_CDEBUGSELL 0xffU
3287 #define V_CDEBUGSELL(x) ((x) << S_CDEBUGSELL)
3288 #define G_CDEBUGSELL(x) (((x) >> S_CDEBUGSELL) & M_CDEBUGSELL)
3290 #define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
3291 #define A_PCIE_CDEBUG_DATA_LOW 0x5a18
3292 #define A_PCIE_DMAW_SOP_CNT 0x5a1c
3296 #define V_CH3(x) ((x) << S_CH3)
3297 #define G_CH3(x) (((x) >> S_CH3) & M_CH3)
3301 #define V_CH2(x) ((x) << S_CH2)
3302 #define G_CH2(x) (((x) >> S_CH2) & M_CH2)
3306 #define V_CH1(x) ((x) << S_CH1)
3307 #define G_CH1(x) (((x) >> S_CH1) & M_CH1)
3311 #define V_CH0(x) ((x) << S_CH0)
3312 #define G_CH0(x) (((x) >> S_CH0) & M_CH0)
3314 #define A_PCIE_DMAW_EOP_CNT 0x5a20
3315 #define A_PCIE_DMAR_REQ_CNT 0x5a24
3316 #define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
3317 #define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
3318 #define A_PCIE_DMAR_RSP_ERR_CNT 0x5a30
3319 #define A_PCIE_DMAI_CNT 0x5a34
3320 #define A_PCIE_CMDW_CNT 0x5a38
3322 #define S_CH1_EOP 24
3323 #define M_CH1_EOP 0xffU
3324 #define V_CH1_EOP(x) ((x) << S_CH1_EOP)
3325 #define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP)
3327 #define S_CH1_SOP 16
3328 #define M_CH1_SOP 0xffU
3329 #define V_CH1_SOP(x) ((x) << S_CH1_SOP)
3330 #define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP)
3333 #define M_CH0_EOP 0xffU
3334 #define V_CH0_EOP(x) ((x) << S_CH0_EOP)
3335 #define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP)
3338 #define M_CH0_SOP 0xffU
3339 #define V_CH0_SOP(x) ((x) << S_CH0_SOP)
3340 #define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP)
3342 #define A_PCIE_CMDR_REQ_CNT 0x5a3c
3343 #define A_PCIE_CMDR_RSP_CNT 0x5a40
3344 #define A_PCIE_CMDR_RSP_ERR_CNT 0x5a44
3345 #define A_PCIE_HMA_REQ_CNT 0x5a48
3347 #define S_CH0_READ 16
3348 #define M_CH0_READ 0xffU
3349 #define V_CH0_READ(x) ((x) << S_CH0_READ)
3350 #define G_CH0_READ(x) (((x) >> S_CH0_READ) & M_CH0_READ)
3352 #define S_CH0_WEOP 8
3353 #define M_CH0_WEOP 0xffU
3354 #define V_CH0_WEOP(x) ((x) << S_CH0_WEOP)
3355 #define G_CH0_WEOP(x) (((x) >> S_CH0_WEOP) & M_CH0_WEOP)
3357 #define S_CH0_WSOP 0
3358 #define M_CH0_WSOP 0xffU
3359 #define V_CH0_WSOP(x) ((x) << S_CH0_WSOP)
3360 #define G_CH0_WSOP(x) (((x) >> S_CH0_WSOP) & M_CH0_WSOP)
3362 #define A_PCIE_HMA_RSP_CNT 0x5a4c
3363 #define A_PCIE_DMA10_RSP_FREE 0x5a50
3365 #define S_CH1_RSP_FREE 16
3366 #define M_CH1_RSP_FREE 0xfffU
3367 #define V_CH1_RSP_FREE(x) ((x) << S_CH1_RSP_FREE)
3368 #define G_CH1_RSP_FREE(x) (((x) >> S_CH1_RSP_FREE) & M_CH1_RSP_FREE)
3370 #define S_CH0_RSP_FREE 0
3371 #define M_CH0_RSP_FREE 0xfffU
3372 #define V_CH0_RSP_FREE(x) ((x) << S_CH0_RSP_FREE)
3373 #define G_CH0_RSP_FREE(x) (((x) >> S_CH0_RSP_FREE) & M_CH0_RSP_FREE)
3375 #define A_PCIE_DMA32_RSP_FREE 0x5a54
3377 #define S_CH3_RSP_FREE 16
3378 #define M_CH3_RSP_FREE 0xfffU
3379 #define V_CH3_RSP_FREE(x) ((x) << S_CH3_RSP_FREE)
3380 #define G_CH3_RSP_FREE(x) (((x) >> S_CH3_RSP_FREE) & M_CH3_RSP_FREE)
3382 #define S_CH2_RSP_FREE 0
3383 #define M_CH2_RSP_FREE 0xfffU
3384 #define V_CH2_RSP_FREE(x) ((x) << S_CH2_RSP_FREE)
3385 #define G_CH2_RSP_FREE(x) (((x) >> S_CH2_RSP_FREE) & M_CH2_RSP_FREE)
3387 #define A_PCIE_CMD_RSP_FREE 0x5a58
3389 #define S_CMD_CH1_RSP_FREE 16
3390 #define M_CMD_CH1_RSP_FREE 0x7fU
3391 #define V_CMD_CH1_RSP_FREE(x) ((x) << S_CMD_CH1_RSP_FREE)
3392 #define G_CMD_CH1_RSP_FREE(x) (((x) >> S_CMD_CH1_RSP_FREE) & M_CMD_CH1_RSP_FREE)
3394 #define S_CMD_CH0_RSP_FREE 0
3395 #define M_CMD_CH0_RSP_FREE 0x7fU
3396 #define V_CMD_CH0_RSP_FREE(x) ((x) << S_CMD_CH0_RSP_FREE)
3397 #define G_CMD_CH0_RSP_FREE(x) (((x) >> S_CMD_CH0_RSP_FREE) & M_CMD_CH0_RSP_FREE)
3399 #define A_PCIE_HMA_RSP_FREE 0x5a5c
3400 #define A_PCIE_BUS_MST_STAT_0 0x5a60
3401 #define A_PCIE_BUS_MST_STAT_1 0x5a64
3402 #define A_PCIE_BUS_MST_STAT_2 0x5a68
3403 #define A_PCIE_BUS_MST_STAT_3 0x5a6c
3404 #define A_PCIE_BUS_MST_STAT_4 0x5a70
3405 #define A_PCIE_BUS_MST_STAT_5 0x5a74
3406 #define A_PCIE_BUS_MST_STAT_6 0x5a78
3407 #define A_PCIE_BUS_MST_STAT_7 0x5a7c
3408 #define A_PCIE_RSP_ERR_STAT_0 0x5a80
3409 #define A_PCIE_RSP_ERR_STAT_1 0x5a84
3410 #define A_PCIE_RSP_ERR_STAT_2 0x5a88
3411 #define A_PCIE_RSP_ERR_STAT_3 0x5a8c
3412 #define A_PCIE_RSP_ERR_STAT_4 0x5a90
3413 #define A_PCIE_RSP_ERR_STAT_5 0x5a94
3414 #define A_PCIE_RSP_ERR_STAT_6 0x5a98
3415 #define A_PCIE_RSP_ERR_STAT_7 0x5a9c
3416 #define A_PCIE_MSI_EN_0 0x5aa0
3417 #define A_PCIE_MSI_EN_1 0x5aa4
3418 #define A_PCIE_MSI_EN_2 0x5aa8
3419 #define A_PCIE_MSI_EN_3 0x5aac
3420 #define A_PCIE_MSI_EN_4 0x5ab0
3421 #define A_PCIE_MSI_EN_5 0x5ab4
3422 #define A_PCIE_MSI_EN_6 0x5ab8
3423 #define A_PCIE_MSI_EN_7 0x5abc
3424 #define A_PCIE_MSIX_EN_0 0x5ac0
3425 #define A_PCIE_MSIX_EN_1 0x5ac4
3426 #define A_PCIE_MSIX_EN_2 0x5ac8
3427 #define A_PCIE_MSIX_EN_3 0x5acc
3428 #define A_PCIE_MSIX_EN_4 0x5ad0
3429 #define A_PCIE_MSIX_EN_5 0x5ad4
3430 #define A_PCIE_MSIX_EN_6 0x5ad8
3431 #define A_PCIE_MSIX_EN_7 0x5adc
3432 #define A_PCIE_DMA_BUF_CTL 0x5ae0
3434 #define S_BUFRDCNT 18
3435 #define M_BUFRDCNT 0x3fffU
3436 #define V_BUFRDCNT(x) ((x) << S_BUFRDCNT)
3437 #define G_BUFRDCNT(x) (((x) >> S_BUFRDCNT) & M_BUFRDCNT)
3439 #define S_BUFWRCNT 9
3440 #define M_BUFWRCNT 0x1ffU
3441 #define V_BUFWRCNT(x) ((x) << S_BUFWRCNT)
3442 #define G_BUFWRCNT(x) (((x) >> S_BUFWRCNT) & M_BUFWRCNT)
3444 #define S_MAXBUFWRREQ 0
3445 #define M_MAXBUFWRREQ 0x1ffU
3446 #define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ)
3447 #define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ)
3449 /* registers for module DBG */
3450 #define DBG_BASE_ADDR 0x6000
3452 #define A_DBG_DBG0_CFG 0x6000
3454 #define S_MODULESELECT 12
3455 #define M_MODULESELECT 0xffU
3456 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
3457 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
3459 #define S_REGSELECT 4
3460 #define M_REGSELECT 0xffU
3461 #define V_REGSELECT(x) ((x) << S_REGSELECT)
3462 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
3464 #define S_CLKSELECT 0
3465 #define M_CLKSELECT 0xfU
3466 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
3467 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
3469 #define A_DBG_DBG0_EN 0x6004
3471 #define S_PORTEN_PONR 16
3472 #define V_PORTEN_PONR(x) ((x) << S_PORTEN_PONR)
3473 #define F_PORTEN_PONR V_PORTEN_PONR(1U)
3475 #define S_PORTEN_POND 12
3476 #define V_PORTEN_POND(x) ((x) << S_PORTEN_POND)
3477 #define F_PORTEN_POND V_PORTEN_POND(1U)
3479 #define S_SDRHALFWORD0 8
3480 #define V_SDRHALFWORD0(x) ((x) << S_SDRHALFWORD0)
3481 #define F_SDRHALFWORD0 V_SDRHALFWORD0(1U)
3484 #define V_DDREN(x) ((x) << S_DDREN)
3485 #define F_DDREN V_DDREN(1U)
3487 #define S_DBG_PORTEN 0
3488 #define V_DBG_PORTEN(x) ((x) << S_DBG_PORTEN)
3489 #define F_DBG_PORTEN V_DBG_PORTEN(1U)
3491 #define A_DBG_DBG1_CFG 0x6008
3492 #define A_DBG_DBG1_EN 0x600c
3493 #define A_DBG_GPIO_EN 0x6010
3495 #define S_GPIO15_OEN 31
3496 #define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN)
3497 #define F_GPIO15_OEN V_GPIO15_OEN(1U)
3499 #define S_GPIO14_OEN 30
3500 #define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN)
3501 #define F_GPIO14_OEN V_GPIO14_OEN(1U)
3503 #define S_GPIO13_OEN 29
3504 #define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN)
3505 #define F_GPIO13_OEN V_GPIO13_OEN(1U)
3507 #define S_GPIO12_OEN 28
3508 #define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN)
3509 #define F_GPIO12_OEN V_GPIO12_OEN(1U)
3511 #define S_GPIO11_OEN 27
3512 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
3513 #define F_GPIO11_OEN V_GPIO11_OEN(1U)
3515 #define S_GPIO10_OEN 26
3516 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
3517 #define F_GPIO10_OEN V_GPIO10_OEN(1U)
3519 #define S_GPIO9_OEN 25
3520 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
3521 #define F_GPIO9_OEN V_GPIO9_OEN(1U)
3523 #define S_GPIO8_OEN 24
3524 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
3525 #define F_GPIO8_OEN V_GPIO8_OEN(1U)
3527 #define S_GPIO7_OEN 23
3528 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
3529 #define F_GPIO7_OEN V_GPIO7_OEN(1U)
3531 #define S_GPIO6_OEN 22
3532 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
3533 #define F_GPIO6_OEN V_GPIO6_OEN(1U)
3535 #define S_GPIO5_OEN 21
3536 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
3537 #define F_GPIO5_OEN V_GPIO5_OEN(1U)
3539 #define S_GPIO4_OEN 20
3540 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
3541 #define F_GPIO4_OEN V_GPIO4_OEN(1U)
3543 #define S_GPIO3_OEN 19
3544 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
3545 #define F_GPIO3_OEN V_GPIO3_OEN(1U)
3547 #define S_GPIO2_OEN 18
3548 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
3549 #define F_GPIO2_OEN V_GPIO2_OEN(1U)
3551 #define S_GPIO1_OEN 17
3552 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
3553 #define F_GPIO1_OEN V_GPIO1_OEN(1U)
3555 #define S_GPIO0_OEN 16
3556 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
3557 #define F_GPIO0_OEN V_GPIO0_OEN(1U)
3559 #define S_GPIO15_OUT_VAL 15
3560 #define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL)
3561 #define F_GPIO15_OUT_VAL V_GPIO15_OUT_VAL(1U)
3563 #define S_GPIO14_OUT_VAL 14
3564 #define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL)
3565 #define F_GPIO14_OUT_VAL V_GPIO14_OUT_VAL(1U)
3567 #define S_GPIO13_OUT_VAL 13
3568 #define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL)
3569 #define F_GPIO13_OUT_VAL V_GPIO13_OUT_VAL(1U)
3571 #define S_GPIO12_OUT_VAL 12
3572 #define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL)
3573 #define F_GPIO12_OUT_VAL V_GPIO12_OUT_VAL(1U)
3575 #define S_GPIO11_OUT_VAL 11
3576 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
3577 #define F_GPIO11_OUT_VAL V_GPIO11_OUT_VAL(1U)
3579 #define S_GPIO10_OUT_VAL 10
3580 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
3581 #define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U)
3583 #define S_GPIO9_OUT_VAL 9
3584 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
3585 #define F_GPIO9_OUT_VAL V_GPIO9_OUT_VAL(1U)
3587 #define S_GPIO8_OUT_VAL 8
3588 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
3589 #define F_GPIO8_OUT_VAL V_GPIO8_OUT_VAL(1U)
3591 #define S_GPIO7_OUT_VAL 7
3592 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
3593 #define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U)
3595 #define S_GPIO6_OUT_VAL 6
3596 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
3597 #define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U)
3599 #define S_GPIO5_OUT_VAL 5
3600 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
3601 #define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U)
3603 #define S_GPIO4_OUT_VAL 4
3604 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
3605 #define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U)
3607 #define S_GPIO3_OUT_VAL 3
3608 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
3609 #define F_GPIO3_OUT_VAL V_GPIO3_OUT_VAL(1U)
3611 #define S_GPIO2_OUT_VAL 2
3612 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
3613 #define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U)
3615 #define S_GPIO1_OUT_VAL 1
3616 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
3617 #define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U)
3619 #define S_GPIO0_OUT_VAL 0
3620 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
3621 #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U)
3623 #define A_DBG_GPIO_IN 0x6014
3625 #define S_GPIO15_CHG_DET 31
3626 #define V_GPIO15_CHG_DET(x) ((x) << S_GPIO15_CHG_DET)
3627 #define F_GPIO15_CHG_DET V_GPIO15_CHG_DET(1U)
3629 #define S_GPIO14_CHG_DET 30
3630 #define V_GPIO14_CHG_DET(x) ((x) << S_GPIO14_CHG_DET)
3631 #define F_GPIO14_CHG_DET V_GPIO14_CHG_DET(1U)
3633 #define S_GPIO13_CHG_DET 29
3634 #define V_GPIO13_CHG_DET(x) ((x) << S_GPIO13_CHG_DET)
3635 #define F_GPIO13_CHG_DET V_GPIO13_CHG_DET(1U)
3637 #define S_GPIO12_CHG_DET 28
3638 #define V_GPIO12_CHG_DET(x) ((x) << S_GPIO12_CHG_DET)
3639 #define F_GPIO12_CHG_DET V_GPIO12_CHG_DET(1U)
3641 #define S_GPIO11_CHG_DET 27
3642 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
3643 #define F_GPIO11_CHG_DET V_GPIO11_CHG_DET(1U)
3645 #define S_GPIO10_CHG_DET 26
3646 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
3647 #define F_GPIO10_CHG_DET V_GPIO10_CHG_DET(1U)
3649 #define S_GPIO9_CHG_DET 25
3650 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
3651 #define F_GPIO9_CHG_DET V_GPIO9_CHG_DET(1U)
3653 #define S_GPIO8_CHG_DET 24
3654 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
3655 #define F_GPIO8_CHG_DET V_GPIO8_CHG_DET(1U)
3657 #define S_GPIO7_CHG_DET 23
3658 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
3659 #define F_GPIO7_CHG_DET V_GPIO7_CHG_DET(1U)
3661 #define S_GPIO6_CHG_DET 22
3662 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
3663 #define F_GPIO6_CHG_DET V_GPIO6_CHG_DET(1U)
3665 #define S_GPIO5_CHG_DET 21
3666 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
3667 #define F_GPIO5_CHG_DET V_GPIO5_CHG_DET(1U)
3669 #define S_GPIO4_CHG_DET 20
3670 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
3671 #define F_GPIO4_CHG_DET V_GPIO4_CHG_DET(1U)
3673 #define S_GPIO3_CHG_DET 19
3674 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
3675 #define F_GPIO3_CHG_DET V_GPIO3_CHG_DET(1U)
3677 #define S_GPIO2_CHG_DET 18
3678 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
3679 #define F_GPIO2_CHG_DET V_GPIO2_CHG_DET(1U)
3681 #define S_GPIO1_CHG_DET 17
3682 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
3683 #define F_GPIO1_CHG_DET V_GPIO1_CHG_DET(1U)
3685 #define S_GPIO0_CHG_DET 16
3686 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
3687 #define F_GPIO0_CHG_DET V_GPIO0_CHG_DET(1U)
3689 #define S_GPIO15_IN 15
3690 #define V_GPIO15_IN(x) ((x) << S_GPIO15_IN)
3691 #define F_GPIO15_IN V_GPIO15_IN(1U)
3693 #define S_GPIO14_IN 14
3694 #define V_GPIO14_IN(x) ((x) << S_GPIO14_IN)
3695 #define F_GPIO14_IN V_GPIO14_IN(1U)
3697 #define S_GPIO13_IN 13
3698 #define V_GPIO13_IN(x) ((x) << S_GPIO13_IN)
3699 #define F_GPIO13_IN V_GPIO13_IN(1U)
3701 #define S_GPIO12_IN 12
3702 #define V_GPIO12_IN(x) ((x) << S_GPIO12_IN)
3703 #define F_GPIO12_IN V_GPIO12_IN(1U)
3705 #define S_GPIO11_IN 11
3706 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
3707 #define F_GPIO11_IN V_GPIO11_IN(1U)
3709 #define S_GPIO10_IN 10
3710 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
3711 #define F_GPIO10_IN V_GPIO10_IN(1U)
3713 #define S_GPIO9_IN 9
3714 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
3715 #define F_GPIO9_IN V_GPIO9_IN(1U)
3717 #define S_GPIO8_IN 8
3718 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
3719 #define F_GPIO8_IN V_GPIO8_IN(1U)
3721 #define S_GPIO7_IN 7
3722 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
3723 #define F_GPIO7_IN V_GPIO7_IN(1U)
3725 #define S_GPIO6_IN 6
3726 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
3727 #define F_GPIO6_IN V_GPIO6_IN(1U)
3729 #define S_GPIO5_IN 5
3730 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
3731 #define F_GPIO5_IN V_GPIO5_IN(1U)
3733 #define S_GPIO4_IN 4
3734 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
3735 #define F_GPIO4_IN V_GPIO4_IN(1U)
3737 #define S_GPIO3_IN 3
3738 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
3739 #define F_GPIO3_IN V_GPIO3_IN(1U)
3741 #define S_GPIO2_IN 2
3742 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
3743 #define F_GPIO2_IN V_GPIO2_IN(1U)
3745 #define S_GPIO1_IN 1
3746 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
3747 #define F_GPIO1_IN V_GPIO1_IN(1U)
3749 #define S_GPIO0_IN 0
3750 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
3751 #define F_GPIO0_IN V_GPIO0_IN(1U)
3753 #define A_DBG_INT_ENABLE 0x6018
3755 #define S_IBM_FDL_FAIL_INT_ENBL 25
3756 #define V_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_IBM_FDL_FAIL_INT_ENBL)
3757 #define F_IBM_FDL_FAIL_INT_ENBL V_IBM_FDL_FAIL_INT_ENBL(1U)
3759 #define S_ARM_FAIL_INT_ENBL 24
3760 #define V_ARM_FAIL_INT_ENBL(x) ((x) << S_ARM_FAIL_INT_ENBL)
3761 #define F_ARM_FAIL_INT_ENBL V_ARM_FAIL_INT_ENBL(1U)
3763 #define S_ARM_ERROR_OUT_INT_ENBL 23
3764 #define V_ARM_ERROR_OUT_INT_ENBL(x) ((x) << S_ARM_ERROR_OUT_INT_ENBL)
3765 #define F_ARM_ERROR_OUT_INT_ENBL V_ARM_ERROR_OUT_INT_ENBL(1U)
3767 #define S_PLL_LOCK_LOST_INT_ENBL 22
3768 #define V_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_PLL_LOCK_LOST_INT_ENBL)
3769 #define F_PLL_LOCK_LOST_INT_ENBL V_PLL_LOCK_LOST_INT_ENBL(1U)
3772 #define V_C_LOCK(x) ((x) << S_C_LOCK)
3773 #define F_C_LOCK V_C_LOCK(1U)
3776 #define V_M_LOCK(x) ((x) << S_M_LOCK)
3777 #define F_M_LOCK V_M_LOCK(1U)
3780 #define V_U_LOCK(x) ((x) << S_U_LOCK)
3781 #define F_U_LOCK V_U_LOCK(1U)
3783 #define S_PCIE_LOCK 18
3784 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
3785 #define F_PCIE_LOCK V_PCIE_LOCK(1U)
3787 #define S_KX_LOCK 17
3788 #define V_KX_LOCK(x) ((x) << S_KX_LOCK)
3789 #define F_KX_LOCK V_KX_LOCK(1U)
3791 #define S_KR_LOCK 16
3792 #define V_KR_LOCK(x) ((x) << S_KR_LOCK)
3793 #define F_KR_LOCK V_KR_LOCK(1U)
3796 #define V_GPIO15(x) ((x) << S_GPIO15)
3797 #define F_GPIO15 V_GPIO15(1U)
3800 #define V_GPIO14(x) ((x) << S_GPIO14)
3801 #define F_GPIO14 V_GPIO14(1U)
3804 #define V_GPIO13(x) ((x) << S_GPIO13)
3805 #define F_GPIO13 V_GPIO13(1U)
3808 #define V_GPIO12(x) ((x) << S_GPIO12)
3809 #define F_GPIO12 V_GPIO12(1U)
3812 #define V_GPIO11(x) ((x) << S_GPIO11)
3813 #define F_GPIO11 V_GPIO11(1U)
3816 #define V_GPIO10(x) ((x) << S_GPIO10)
3817 #define F_GPIO10 V_GPIO10(1U)
3820 #define V_GPIO9(x) ((x) << S_GPIO9)
3821 #define F_GPIO9 V_GPIO9(1U)
3824 #define V_GPIO8(x) ((x) << S_GPIO8)
3825 #define F_GPIO8 V_GPIO8(1U)
3828 #define V_GPIO7(x) ((x) << S_GPIO7)
3829 #define F_GPIO7 V_GPIO7(1U)
3832 #define V_GPIO6(x) ((x) << S_GPIO6)
3833 #define F_GPIO6 V_GPIO6(1U)
3836 #define V_GPIO5(x) ((x) << S_GPIO5)
3837 #define F_GPIO5 V_GPIO5(1U)
3840 #define V_GPIO4(x) ((x) << S_GPIO4)
3841 #define F_GPIO4 V_GPIO4(1U)
3844 #define V_GPIO3(x) ((x) << S_GPIO3)
3845 #define F_GPIO3 V_GPIO3(1U)
3848 #define V_GPIO2(x) ((x) << S_GPIO2)
3849 #define F_GPIO2 V_GPIO2(1U)
3852 #define V_GPIO1(x) ((x) << S_GPIO1)
3853 #define F_GPIO1 V_GPIO1(1U)
3856 #define V_GPIO0(x) ((x) << S_GPIO0)
3857 #define F_GPIO0 V_GPIO0(1U)
3859 #define A_DBG_INT_CAUSE 0x601c
3861 #define S_IBM_FDL_FAIL_INT_CAUSE 25
3862 #define V_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_IBM_FDL_FAIL_INT_CAUSE)
3863 #define F_IBM_FDL_FAIL_INT_CAUSE V_IBM_FDL_FAIL_INT_CAUSE(1U)
3865 #define S_ARM_FAIL_INT_CAUSE 24
3866 #define V_ARM_FAIL_INT_CAUSE(x) ((x) << S_ARM_FAIL_INT_CAUSE)
3867 #define F_ARM_FAIL_INT_CAUSE V_ARM_FAIL_INT_CAUSE(1U)
3869 #define S_ARM_ERROR_OUT_INT_CAUSE 23
3870 #define V_ARM_ERROR_OUT_INT_CAUSE(x) ((x) << S_ARM_ERROR_OUT_INT_CAUSE)
3871 #define F_ARM_ERROR_OUT_INT_CAUSE V_ARM_ERROR_OUT_INT_CAUSE(1U)
3873 #define S_PLL_LOCK_LOST_INT_CAUSE 22
3874 #define V_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_PLL_LOCK_LOST_INT_CAUSE)
3875 #define F_PLL_LOCK_LOST_INT_CAUSE V_PLL_LOCK_LOST_INT_CAUSE(1U)
3877 #define A_DBG_DBG0_RST_VALUE 0x6020
3879 #define S_DEBUGDATA 0
3880 #define M_DEBUGDATA 0xffffU
3881 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
3882 #define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
3884 #define A_DBG_OVERWRSERCFG_EN 0x6024
3886 #define S_OVERWRSERCFG_EN 0
3887 #define V_OVERWRSERCFG_EN(x) ((x) << S_OVERWRSERCFG_EN)
3888 #define F_OVERWRSERCFG_EN V_OVERWRSERCFG_EN(1U)
3890 #define A_DBG_PLL_OCLK_PAD_EN 0x6028
3892 #define S_PCIE_OCLK_EN 20
3893 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
3894 #define F_PCIE_OCLK_EN V_PCIE_OCLK_EN(1U)
3896 #define S_KX_OCLK_EN 16
3897 #define V_KX_OCLK_EN(x) ((x) << S_KX_OCLK_EN)
3898 #define F_KX_OCLK_EN V_KX_OCLK_EN(1U)
3900 #define S_U_OCLK_EN 12
3901 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
3902 #define F_U_OCLK_EN V_U_OCLK_EN(1U)
3904 #define S_KR_OCLK_EN 8
3905 #define V_KR_OCLK_EN(x) ((x) << S_KR_OCLK_EN)
3906 #define F_KR_OCLK_EN V_KR_OCLK_EN(1U)
3908 #define S_M_OCLK_EN 4
3909 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
3910 #define F_M_OCLK_EN V_M_OCLK_EN(1U)
3912 #define S_C_OCLK_EN 0
3913 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
3914 #define F_C_OCLK_EN V_C_OCLK_EN(1U)
3916 #define A_DBG_PLL_LOCK 0x602c
3918 #define S_PLL_P_LOCK 20
3919 #define V_PLL_P_LOCK(x) ((x) << S_PLL_P_LOCK)
3920 #define F_PLL_P_LOCK V_PLL_P_LOCK(1U)
3922 #define S_PLL_KX_LOCK 16
3923 #define V_PLL_KX_LOCK(x) ((x) << S_PLL_KX_LOCK)
3924 #define F_PLL_KX_LOCK V_PLL_KX_LOCK(1U)
3926 #define S_PLL_U_LOCK 12
3927 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
3928 #define F_PLL_U_LOCK V_PLL_U_LOCK(1U)
3930 #define S_PLL_KR_LOCK 8
3931 #define V_PLL_KR_LOCK(x) ((x) << S_PLL_KR_LOCK)
3932 #define F_PLL_KR_LOCK V_PLL_KR_LOCK(1U)
3934 #define S_PLL_M_LOCK 4
3935 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
3936 #define F_PLL_M_LOCK V_PLL_M_LOCK(1U)
3938 #define S_PLL_C_LOCK 0
3939 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
3940 #define F_PLL_C_LOCK V_PLL_C_LOCK(1U)
3942 #define A_DBG_GPIO_ACT_LOW 0x6030
3944 #define S_P_LOCK_ACT_LOW 21
3945 #define V_P_LOCK_ACT_LOW(x) ((x) << S_P_LOCK_ACT_LOW)
3946 #define F_P_LOCK_ACT_LOW V_P_LOCK_ACT_LOW(1U)
3948 #define S_C_LOCK_ACT_LOW 20
3949 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
3950 #define F_C_LOCK_ACT_LOW V_C_LOCK_ACT_LOW(1U)
3952 #define S_M_LOCK_ACT_LOW 19
3953 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
3954 #define F_M_LOCK_ACT_LOW V_M_LOCK_ACT_LOW(1U)
3956 #define S_U_LOCK_ACT_LOW 18
3957 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
3958 #define F_U_LOCK_ACT_LOW V_U_LOCK_ACT_LOW(1U)
3960 #define S_KR_LOCK_ACT_LOW 17
3961 #define V_KR_LOCK_ACT_LOW(x) ((x) << S_KR_LOCK_ACT_LOW)
3962 #define F_KR_LOCK_ACT_LOW V_KR_LOCK_ACT_LOW(1U)
3964 #define S_KX_LOCK_ACT_LOW 16
3965 #define V_KX_LOCK_ACT_LOW(x) ((x) << S_KX_LOCK_ACT_LOW)
3966 #define F_KX_LOCK_ACT_LOW V_KX_LOCK_ACT_LOW(1U)
3968 #define S_GPIO15_ACT_LOW 15
3969 #define V_GPIO15_ACT_LOW(x) ((x) << S_GPIO15_ACT_LOW)
3970 #define F_GPIO15_ACT_LOW V_GPIO15_ACT_LOW(1U)
3972 #define S_GPIO14_ACT_LOW 14
3973 #define V_GPIO14_ACT_LOW(x) ((x) << S_GPIO14_ACT_LOW)
3974 #define F_GPIO14_ACT_LOW V_GPIO14_ACT_LOW(1U)
3976 #define S_GPIO13_ACT_LOW 13
3977 #define V_GPIO13_ACT_LOW(x) ((x) << S_GPIO13_ACT_LOW)
3978 #define F_GPIO13_ACT_LOW V_GPIO13_ACT_LOW(1U)
3980 #define S_GPIO12_ACT_LOW 12
3981 #define V_GPIO12_ACT_LOW(x) ((x) << S_GPIO12_ACT_LOW)
3982 #define F_GPIO12_ACT_LOW V_GPIO12_ACT_LOW(1U)
3984 #define S_GPIO11_ACT_LOW 11
3985 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
3986 #define F_GPIO11_ACT_LOW V_GPIO11_ACT_LOW(1U)
3988 #define S_GPIO10_ACT_LOW 10
3989 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
3990 #define F_GPIO10_ACT_LOW V_GPIO10_ACT_LOW(1U)
3992 #define S_GPIO9_ACT_LOW 9
3993 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
3994 #define F_GPIO9_ACT_LOW V_GPIO9_ACT_LOW(1U)
3996 #define S_GPIO8_ACT_LOW 8
3997 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
3998 #define F_GPIO8_ACT_LOW V_GPIO8_ACT_LOW(1U)
4000 #define S_GPIO7_ACT_LOW 7
4001 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
4002 #define F_GPIO7_ACT_LOW V_GPIO7_ACT_LOW(1U)
4004 #define S_GPIO6_ACT_LOW 6
4005 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
4006 #define F_GPIO6_ACT_LOW V_GPIO6_ACT_LOW(1U)
4008 #define S_GPIO5_ACT_LOW 5
4009 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
4010 #define F_GPIO5_ACT_LOW V_GPIO5_ACT_LOW(1U)
4012 #define S_GPIO4_ACT_LOW 4
4013 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
4014 #define F_GPIO4_ACT_LOW V_GPIO4_ACT_LOW(1U)
4016 #define S_GPIO3_ACT_LOW 3
4017 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
4018 #define F_GPIO3_ACT_LOW V_GPIO3_ACT_LOW(1U)
4020 #define S_GPIO2_ACT_LOW 2
4021 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
4022 #define F_GPIO2_ACT_LOW V_GPIO2_ACT_LOW(1U)
4024 #define S_GPIO1_ACT_LOW 1
4025 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
4026 #define F_GPIO1_ACT_LOW V_GPIO1_ACT_LOW(1U)
4028 #define S_GPIO0_ACT_LOW 0
4029 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
4030 #define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U)
4032 #define A_DBG_EFUSE_BYTE0_3 0x6034
4033 #define A_DBG_EFUSE_BYTE4_7 0x6038
4034 #define A_DBG_EFUSE_BYTE8_11 0x603c
4035 #define A_DBG_EFUSE_BYTE12_15 0x6040
4036 #define A_DBG_STATIC_U_PLL_CONF 0x6044
4038 #define S_STATIC_U_PLL_MULT 23
4039 #define M_STATIC_U_PLL_MULT 0x1ffU
4040 #define V_STATIC_U_PLL_MULT(x) ((x) << S_STATIC_U_PLL_MULT)
4041 #define G_STATIC_U_PLL_MULT(x) (((x) >> S_STATIC_U_PLL_MULT) & M_STATIC_U_PLL_MULT)
4043 #define S_STATIC_U_PLL_PREDIV 18
4044 #define M_STATIC_U_PLL_PREDIV 0x1fU
4045 #define V_STATIC_U_PLL_PREDIV(x) ((x) << S_STATIC_U_PLL_PREDIV)
4046 #define G_STATIC_U_PLL_PREDIV(x) (((x) >> S_STATIC_U_PLL_PREDIV) & M_STATIC_U_PLL_PREDIV)
4048 #define S_STATIC_U_PLL_RANGEA 14
4049 #define M_STATIC_U_PLL_RANGEA 0xfU
4050 #define V_STATIC_U_PLL_RANGEA(x) ((x) << S_STATIC_U_PLL_RANGEA)
4051 #define G_STATIC_U_PLL_RANGEA(x) (((x) >> S_STATIC_U_PLL_RANGEA) & M_STATIC_U_PLL_RANGEA)
4053 #define S_STATIC_U_PLL_RANGEB 10
4054 #define M_STATIC_U_PLL_RANGEB 0xfU
4055 #define V_STATIC_U_PLL_RANGEB(x) ((x) << S_STATIC_U_PLL_RANGEB)
4056 #define G_STATIC_U_PLL_RANGEB(x) (((x) >> S_STATIC_U_PLL_RANGEB) & M_STATIC_U_PLL_RANGEB)
4058 #define S_STATIC_U_PLL_TUNE 0
4059 #define M_STATIC_U_PLL_TUNE 0x3ffU
4060 #define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE)
4061 #define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE)
4063 #define A_DBG_STATIC_C_PLL_CONF 0x6048
4065 #define S_STATIC_C_PLL_MULT 23
4066 #define M_STATIC_C_PLL_MULT 0x1ffU
4067 #define V_STATIC_C_PLL_MULT(x) ((x) << S_STATIC_C_PLL_MULT)
4068 #define G_STATIC_C_PLL_MULT(x) (((x) >> S_STATIC_C_PLL_MULT) & M_STATIC_C_PLL_MULT)
4070 #define S_STATIC_C_PLL_PREDIV 18
4071 #define M_STATIC_C_PLL_PREDIV 0x1fU
4072 #define V_STATIC_C_PLL_PREDIV(x) ((x) << S_STATIC_C_PLL_PREDIV)
4073 #define G_STATIC_C_PLL_PREDIV(x) (((x) >> S_STATIC_C_PLL_PREDIV) & M_STATIC_C_PLL_PREDIV)
4075 #define S_STATIC_C_PLL_RANGEA 14
4076 #define M_STATIC_C_PLL_RANGEA 0xfU
4077 #define V_STATIC_C_PLL_RANGEA(x) ((x) << S_STATIC_C_PLL_RANGEA)
4078 #define G_STATIC_C_PLL_RANGEA(x) (((x) >> S_STATIC_C_PLL_RANGEA) & M_STATIC_C_PLL_RANGEA)
4080 #define S_STATIC_C_PLL_RANGEB 10
4081 #define M_STATIC_C_PLL_RANGEB 0xfU
4082 #define V_STATIC_C_PLL_RANGEB(x) ((x) << S_STATIC_C_PLL_RANGEB)
4083 #define G_STATIC_C_PLL_RANGEB(x) (((x) >> S_STATIC_C_PLL_RANGEB) & M_STATIC_C_PLL_RANGEB)
4085 #define S_STATIC_C_PLL_TUNE 0
4086 #define M_STATIC_C_PLL_TUNE 0x3ffU
4087 #define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE)
4088 #define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE)
4090 #define A_DBG_STATIC_M_PLL_CONF 0x604c
4092 #define S_STATIC_M_PLL_MULT 23
4093 #define M_STATIC_M_PLL_MULT 0x1ffU
4094 #define V_STATIC_M_PLL_MULT(x) ((x) << S_STATIC_M_PLL_MULT)
4095 #define G_STATIC_M_PLL_MULT(x) (((x) >> S_STATIC_M_PLL_MULT) & M_STATIC_M_PLL_MULT)
4097 #define S_STATIC_M_PLL_PREDIV 18
4098 #define M_STATIC_M_PLL_PREDIV 0x1fU
4099 #define V_STATIC_M_PLL_PREDIV(x) ((x) << S_STATIC_M_PLL_PREDIV)
4100 #define G_STATIC_M_PLL_PREDIV(x) (((x) >> S_STATIC_M_PLL_PREDIV) & M_STATIC_M_PLL_PREDIV)
4102 #define S_STATIC_M_PLL_RANGEA 14
4103 #define M_STATIC_M_PLL_RANGEA 0xfU
4104 #define V_STATIC_M_PLL_RANGEA(x) ((x) << S_STATIC_M_PLL_RANGEA)
4105 #define G_STATIC_M_PLL_RANGEA(x) (((x) >> S_STATIC_M_PLL_RANGEA) & M_STATIC_M_PLL_RANGEA)
4107 #define S_STATIC_M_PLL_RANGEB 10
4108 #define M_STATIC_M_PLL_RANGEB 0xfU
4109 #define V_STATIC_M_PLL_RANGEB(x) ((x) << S_STATIC_M_PLL_RANGEB)
4110 #define G_STATIC_M_PLL_RANGEB(x) (((x) >> S_STATIC_M_PLL_RANGEB) & M_STATIC_M_PLL_RANGEB)
4112 #define S_STATIC_M_PLL_TUNE 0
4113 #define M_STATIC_M_PLL_TUNE 0x3ffU
4114 #define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE)
4115 #define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE)
4117 #define A_DBG_STATIC_KX_PLL_CONF 0x6050
4119 #define S_STATIC_KX_PLL_C 21
4120 #define M_STATIC_KX_PLL_C 0xffU
4121 #define V_STATIC_KX_PLL_C(x) ((x) << S_STATIC_KX_PLL_C)
4122 #define G_STATIC_KX_PLL_C(x) (((x) >> S_STATIC_KX_PLL_C) & M_STATIC_KX_PLL_C)
4124 #define S_STATIC_KX_PLL_M 15
4125 #define M_STATIC_KX_PLL_M 0x3fU
4126 #define V_STATIC_KX_PLL_M(x) ((x) << S_STATIC_KX_PLL_M)
4127 #define G_STATIC_KX_PLL_M(x) (((x) >> S_STATIC_KX_PLL_M) & M_STATIC_KX_PLL_M)
4129 #define S_STATIC_KX_PLL_N1 11
4130 #define M_STATIC_KX_PLL_N1 0xfU
4131 #define V_STATIC_KX_PLL_N1(x) ((x) << S_STATIC_KX_PLL_N1)
4132 #define G_STATIC_KX_PLL_N1(x) (((x) >> S_STATIC_KX_PLL_N1) & M_STATIC_KX_PLL_N1)
4134 #define S_STATIC_KX_PLL_N2 7
4135 #define M_STATIC_KX_PLL_N2 0xfU
4136 #define V_STATIC_KX_PLL_N2(x) ((x) << S_STATIC_KX_PLL_N2)
4137 #define G_STATIC_KX_PLL_N2(x) (((x) >> S_STATIC_KX_PLL_N2) & M_STATIC_KX_PLL_N2)
4139 #define S_STATIC_KX_PLL_N3 3
4140 #define M_STATIC_KX_PLL_N3 0xfU
4141 #define V_STATIC_KX_PLL_N3(x) ((x) << S_STATIC_KX_PLL_N3)
4142 #define G_STATIC_KX_PLL_N3(x) (((x) >> S_STATIC_KX_PLL_N3) & M_STATIC_KX_PLL_N3)
4144 #define S_STATIC_KX_PLL_P 0
4145 #define M_STATIC_KX_PLL_P 0x7U
4146 #define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P)
4147 #define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P)
4149 #define A_DBG_STATIC_KR_PLL_CONF 0x6054
4151 #define S_STATIC_KR_PLL_C 21
4152 #define M_STATIC_KR_PLL_C 0xffU
4153 #define V_STATIC_KR_PLL_C(x) ((x) << S_STATIC_KR_PLL_C)
4154 #define G_STATIC_KR_PLL_C(x) (((x) >> S_STATIC_KR_PLL_C) & M_STATIC_KR_PLL_C)
4156 #define S_STATIC_KR_PLL_M 15
4157 #define M_STATIC_KR_PLL_M 0x3fU
4158 #define V_STATIC_KR_PLL_M(x) ((x) << S_STATIC_KR_PLL_M)
4159 #define G_STATIC_KR_PLL_M(x) (((x) >> S_STATIC_KR_PLL_M) & M_STATIC_KR_PLL_M)
4161 #define S_STATIC_KR_PLL_N1 11
4162 #define M_STATIC_KR_PLL_N1 0xfU
4163 #define V_STATIC_KR_PLL_N1(x) ((x) << S_STATIC_KR_PLL_N1)
4164 #define G_STATIC_KR_PLL_N1(x) (((x) >> S_STATIC_KR_PLL_N1) & M_STATIC_KR_PLL_N1)
4166 #define S_STATIC_KR_PLL_N2 7
4167 #define M_STATIC_KR_PLL_N2 0xfU
4168 #define V_STATIC_KR_PLL_N2(x) ((x) << S_STATIC_KR_PLL_N2)
4169 #define G_STATIC_KR_PLL_N2(x) (((x) >> S_STATIC_KR_PLL_N2) & M_STATIC_KR_PLL_N2)
4171 #define S_STATIC_KR_PLL_N3 3
4172 #define M_STATIC_KR_PLL_N3 0xfU
4173 #define V_STATIC_KR_PLL_N3(x) ((x) << S_STATIC_KR_PLL_N3)
4174 #define G_STATIC_KR_PLL_N3(x) (((x) >> S_STATIC_KR_PLL_N3) & M_STATIC_KR_PLL_N3)
4176 #define S_STATIC_KR_PLL_P 0
4177 #define M_STATIC_KR_PLL_P 0x7U
4178 #define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P)
4179 #define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P)
4181 #define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058
4183 #define S_STATIC_M_PLL_RESET 30
4184 #define V_STATIC_M_PLL_RESET(x) ((x) << S_STATIC_M_PLL_RESET)
4185 #define F_STATIC_M_PLL_RESET V_STATIC_M_PLL_RESET(1U)
4187 #define S_STATIC_M_PLL_SLEEP 29
4188 #define V_STATIC_M_PLL_SLEEP(x) ((x) << S_STATIC_M_PLL_SLEEP)
4189 #define F_STATIC_M_PLL_SLEEP V_STATIC_M_PLL_SLEEP(1U)
4191 #define S_STATIC_M_PLL_BYPASS 28
4192 #define V_STATIC_M_PLL_BYPASS(x) ((x) << S_STATIC_M_PLL_BYPASS)
4193 #define F_STATIC_M_PLL_BYPASS V_STATIC_M_PLL_BYPASS(1U)
4195 #define S_STATIC_MPLL_CLK_SEL 27
4196 #define V_STATIC_MPLL_CLK_SEL(x) ((x) << S_STATIC_MPLL_CLK_SEL)
4197 #define F_STATIC_MPLL_CLK_SEL V_STATIC_MPLL_CLK_SEL(1U)
4199 #define S_STATIC_U_PLL_SLEEP 26
4200 #define V_STATIC_U_PLL_SLEEP(x) ((x) << S_STATIC_U_PLL_SLEEP)
4201 #define F_STATIC_U_PLL_SLEEP V_STATIC_U_PLL_SLEEP(1U)
4203 #define S_STATIC_C_PLL_SLEEP 25
4204 #define V_STATIC_C_PLL_SLEEP(x) ((x) << S_STATIC_C_PLL_SLEEP)
4205 #define F_STATIC_C_PLL_SLEEP V_STATIC_C_PLL_SLEEP(1U)
4207 #define S_STATIC_LVDS_CLKOUT_SEL 23
4208 #define M_STATIC_LVDS_CLKOUT_SEL 0x3U
4209 #define V_STATIC_LVDS_CLKOUT_SEL(x) ((x) << S_STATIC_LVDS_CLKOUT_SEL)
4210 #define G_STATIC_LVDS_CLKOUT_SEL(x) (((x) >> S_STATIC_LVDS_CLKOUT_SEL) & M_STATIC_LVDS_CLKOUT_SEL)
4212 #define S_STATIC_LVDS_CLKOUT_EN 22
4213 #define V_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_STATIC_LVDS_CLKOUT_EN)
4214 #define F_STATIC_LVDS_CLKOUT_EN V_STATIC_LVDS_CLKOUT_EN(1U)
4216 #define S_STATIC_CCLK_FREQ_SEL 20
4217 #define M_STATIC_CCLK_FREQ_SEL 0x3U
4218 #define V_STATIC_CCLK_FREQ_SEL(x) ((x) << S_STATIC_CCLK_FREQ_SEL)
4219 #define G_STATIC_CCLK_FREQ_SEL(x) (((x) >> S_STATIC_CCLK_FREQ_SEL) & M_STATIC_CCLK_FREQ_SEL)
4221 #define S_STATIC_UCLK_FREQ_SEL 18
4222 #define M_STATIC_UCLK_FREQ_SEL 0x3U
4223 #define V_STATIC_UCLK_FREQ_SEL(x) ((x) << S_STATIC_UCLK_FREQ_SEL)
4224 #define G_STATIC_UCLK_FREQ_SEL(x) (((x) >> S_STATIC_UCLK_FREQ_SEL) & M_STATIC_UCLK_FREQ_SEL)
4226 #define S_EXPHYCLK_SEL_EN 17
4227 #define V_EXPHYCLK_SEL_EN(x) ((x) << S_EXPHYCLK_SEL_EN)
4228 #define F_EXPHYCLK_SEL_EN V_EXPHYCLK_SEL_EN(1U)
4230 #define S_EXPHYCLK_SEL 15
4231 #define M_EXPHYCLK_SEL 0x3U
4232 #define V_EXPHYCLK_SEL(x) ((x) << S_EXPHYCLK_SEL)
4233 #define G_EXPHYCLK_SEL(x) (((x) >> S_EXPHYCLK_SEL) & M_EXPHYCLK_SEL)
4235 #define S_STATIC_U_PLL_BYPASS 14
4236 #define V_STATIC_U_PLL_BYPASS(x) ((x) << S_STATIC_U_PLL_BYPASS)
4237 #define F_STATIC_U_PLL_BYPASS V_STATIC_U_PLL_BYPASS(1U)
4239 #define S_STATIC_C_PLL_BYPASS 13
4240 #define V_STATIC_C_PLL_BYPASS(x) ((x) << S_STATIC_C_PLL_BYPASS)
4241 #define F_STATIC_C_PLL_BYPASS V_STATIC_C_PLL_BYPASS(1U)
4243 #define S_STATIC_KR_PLL_BYPASS 12
4244 #define V_STATIC_KR_PLL_BYPASS(x) ((x) << S_STATIC_KR_PLL_BYPASS)
4245 #define F_STATIC_KR_PLL_BYPASS V_STATIC_KR_PLL_BYPASS(1U)
4247 #define S_STATIC_KX_PLL_BYPASS 11
4248 #define V_STATIC_KX_PLL_BYPASS(x) ((x) << S_STATIC_KX_PLL_BYPASS)
4249 #define F_STATIC_KX_PLL_BYPASS V_STATIC_KX_PLL_BYPASS(1U)
4251 #define S_STATIC_KX_PLL_V 7
4252 #define M_STATIC_KX_PLL_V 0xfU
4253 #define V_STATIC_KX_PLL_V(x) ((x) << S_STATIC_KX_PLL_V)
4254 #define G_STATIC_KX_PLL_V(x) (((x) >> S_STATIC_KX_PLL_V) & M_STATIC_KX_PLL_V)
4256 #define S_STATIC_KR_PLL_V 3
4257 #define M_STATIC_KR_PLL_V 0xfU
4258 #define V_STATIC_KR_PLL_V(x) ((x) << S_STATIC_KR_PLL_V)
4259 #define G_STATIC_KR_PLL_V(x) (((x) >> S_STATIC_KR_PLL_V) & M_STATIC_KR_PLL_V)
4261 #define S_PSRO_SEL 0
4262 #define M_PSRO_SEL 0x7U
4263 #define V_PSRO_SEL(x) ((x) << S_PSRO_SEL)
4264 #define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL)
4266 #define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c
4268 #define S_M_OCLK_MUXSEL 12
4269 #define V_M_OCLK_MUXSEL(x) ((x) << S_M_OCLK_MUXSEL)
4270 #define F_M_OCLK_MUXSEL V_M_OCLK_MUXSEL(1U)
4272 #define S_C_OCLK_MUXSEL 10
4273 #define M_C_OCLK_MUXSEL 0x3U
4274 #define V_C_OCLK_MUXSEL(x) ((x) << S_C_OCLK_MUXSEL)
4275 #define G_C_OCLK_MUXSEL(x) (((x) >> S_C_OCLK_MUXSEL) & M_C_OCLK_MUXSEL)
4277 #define S_U_OCLK_MUXSEL 8
4278 #define M_U_OCLK_MUXSEL 0x3U
4279 #define V_U_OCLK_MUXSEL(x) ((x) << S_U_OCLK_MUXSEL)
4280 #define G_U_OCLK_MUXSEL(x) (((x) >> S_U_OCLK_MUXSEL) & M_U_OCLK_MUXSEL)
4282 #define S_P_OCLK_MUXSEL 6
4283 #define M_P_OCLK_MUXSEL 0x3U
4284 #define V_P_OCLK_MUXSEL(x) ((x) << S_P_OCLK_MUXSEL)
4285 #define G_P_OCLK_MUXSEL(x) (((x) >> S_P_OCLK_MUXSEL) & M_P_OCLK_MUXSEL)
4287 #define S_KX_OCLK_MUXSEL 3
4288 #define M_KX_OCLK_MUXSEL 0x7U
4289 #define V_KX_OCLK_MUXSEL(x) ((x) << S_KX_OCLK_MUXSEL)
4290 #define G_KX_OCLK_MUXSEL(x) (((x) >> S_KX_OCLK_MUXSEL) & M_KX_OCLK_MUXSEL)
4292 #define S_KR_OCLK_MUXSEL 0
4293 #define M_KR_OCLK_MUXSEL 0x7U
4294 #define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL)
4295 #define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL)
4297 #define A_DBG_TRACE0_CONF_COMPREG0 0x6060
4298 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064
4299 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068
4300 #define A_DBG_TRACE1_CONF_COMPREG1 0x606c
4301 #define A_DBG_TRACE0_CONF_MASKREG0 0x6070
4302 #define A_DBG_TRACE0_CONF_MASKREG1 0x6074
4303 #define A_DBG_TRACE1_CONF_MASKREG0 0x6078
4304 #define A_DBG_TRACE1_CONF_MASKREG1 0x607c
4305 #define A_DBG_TRACE_COUNTER 0x6080
4307 #define S_COUNTER1 16
4308 #define M_COUNTER1 0xffffU
4309 #define V_COUNTER1(x) ((x) << S_COUNTER1)
4310 #define G_COUNTER1(x) (((x) >> S_COUNTER1) & M_COUNTER1)
4312 #define S_COUNTER0 0
4313 #define M_COUNTER0 0xffffU
4314 #define V_COUNTER0(x) ((x) << S_COUNTER0)
4315 #define G_COUNTER0(x) (((x) >> S_COUNTER0) & M_COUNTER0)
4317 #define A_DBG_STATIC_REFCLK_PERIOD 0x6084
4319 #define S_STATIC_REFCLK_PERIOD 0
4320 #define M_STATIC_REFCLK_PERIOD 0xffffU
4321 #define V_STATIC_REFCLK_PERIOD(x) ((x) << S_STATIC_REFCLK_PERIOD)
4322 #define G_STATIC_REFCLK_PERIOD(x) (((x) >> S_STATIC_REFCLK_PERIOD) & M_STATIC_REFCLK_PERIOD)
4324 #define A_DBG_TRACE_CONF 0x6088
4326 #define S_DBG_TRACE_OPERATE_WITH_TRG 5
4327 #define V_DBG_TRACE_OPERATE_WITH_TRG(x) ((x) << S_DBG_TRACE_OPERATE_WITH_TRG)
4328 #define F_DBG_TRACE_OPERATE_WITH_TRG V_DBG_TRACE_OPERATE_WITH_TRG(1U)
4330 #define S_DBG_TRACE_OPERATE_EN 4
4331 #define V_DBG_TRACE_OPERATE_EN(x) ((x) << S_DBG_TRACE_OPERATE_EN)
4332 #define F_DBG_TRACE_OPERATE_EN V_DBG_TRACE_OPERATE_EN(1U)
4334 #define S_DBG_OPERATE_INDV_COMBINED 3
4335 #define V_DBG_OPERATE_INDV_COMBINED(x) ((x) << S_DBG_OPERATE_INDV_COMBINED)
4336 #define F_DBG_OPERATE_INDV_COMBINED V_DBG_OPERATE_INDV_COMBINED(1U)
4338 #define S_DBG_OPERATE_ORDER_OF_TRIGGER 2
4339 #define V_DBG_OPERATE_ORDER_OF_TRIGGER(x) ((x) << S_DBG_OPERATE_ORDER_OF_TRIGGER)
4340 #define F_DBG_OPERATE_ORDER_OF_TRIGGER V_DBG_OPERATE_ORDER_OF_TRIGGER(1U)
4342 #define S_DBG_OPERATE_SGL_DBL_TRIGGER 1
4343 #define V_DBG_OPERATE_SGL_DBL_TRIGGER(x) ((x) << S_DBG_OPERATE_SGL_DBL_TRIGGER)
4344 #define F_DBG_OPERATE_SGL_DBL_TRIGGER V_DBG_OPERATE_SGL_DBL_TRIGGER(1U)
4346 #define S_DBG_OPERATE0_OR_1 0
4347 #define V_DBG_OPERATE0_OR_1(x) ((x) << S_DBG_OPERATE0_OR_1)
4348 #define F_DBG_OPERATE0_OR_1 V_DBG_OPERATE0_OR_1(1U)
4350 #define A_DBG_TRACE_RDEN 0x608c
4352 #define S_RD_ADDR1 10
4353 #define M_RD_ADDR1 0xffU
4354 #define V_RD_ADDR1(x) ((x) << S_RD_ADDR1)
4355 #define G_RD_ADDR1(x) (((x) >> S_RD_ADDR1) & M_RD_ADDR1)
4357 #define S_RD_ADDR0 2
4358 #define M_RD_ADDR0 0xffU
4359 #define V_RD_ADDR0(x) ((x) << S_RD_ADDR0)
4360 #define G_RD_ADDR0(x) (((x) >> S_RD_ADDR0) & M_RD_ADDR0)
4363 #define V_RD_EN1(x) ((x) << S_RD_EN1)
4364 #define F_RD_EN1 V_RD_EN1(1U)
4367 #define V_RD_EN0(x) ((x) << S_RD_EN0)
4368 #define F_RD_EN0 V_RD_EN0(1U)
4370 #define A_DBG_TRACE_WRADDR 0x6090
4372 #define S_WR_POINTER_ADDR1 16
4373 #define M_WR_POINTER_ADDR1 0xffU
4374 #define V_WR_POINTER_ADDR1(x) ((x) << S_WR_POINTER_ADDR1)
4375 #define G_WR_POINTER_ADDR1(x) (((x) >> S_WR_POINTER_ADDR1) & M_WR_POINTER_ADDR1)
4377 #define S_WR_POINTER_ADDR0 0
4378 #define M_WR_POINTER_ADDR0 0xffU
4379 #define V_WR_POINTER_ADDR0(x) ((x) << S_WR_POINTER_ADDR0)
4380 #define G_WR_POINTER_ADDR0(x) (((x) >> S_WR_POINTER_ADDR0) & M_WR_POINTER_ADDR0)
4382 #define A_DBG_TRACE0_DATA_OUT 0x6094
4383 #define A_DBG_TRACE1_DATA_OUT 0x6098
4384 #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
4386 #define S_HALT_CALIBRATE 1
4387 #define V_HALT_CALIBRATE(x) ((x) << S_HALT_CALIBRATE)
4388 #define F_HALT_CALIBRATE V_HALT_CALIBRATE(1U)
4390 #define S_RESET_CALIBRATE 0
4391 #define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE)
4392 #define F_RESET_CALIBRATE V_RESET_CALIBRATE(1U)
4394 #define A_DBG_PVT_REG_UPDATE_CTL 0x6104
4396 #define S_FAST_UPDATE 8
4397 #define V_FAST_UPDATE(x) ((x) << S_FAST_UPDATE)
4398 #define F_FAST_UPDATE V_FAST_UPDATE(1U)
4400 #define S_FORCE_REG_IN_VALUE 2
4401 #define V_FORCE_REG_IN_VALUE(x) ((x) << S_FORCE_REG_IN_VALUE)
4402 #define F_FORCE_REG_IN_VALUE V_FORCE_REG_IN_VALUE(1U)
4404 #define S_HALT_UPDATE 1
4405 #define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE)
4406 #define F_HALT_UPDATE V_HALT_UPDATE(1U)
4408 #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
4410 #define S_LAST_MEASUREMENT_SELECT 8
4411 #define M_LAST_MEASUREMENT_SELECT 0x3U
4412 #define V_LAST_MEASUREMENT_SELECT(x) ((x) << S_LAST_MEASUREMENT_SELECT)
4413 #define G_LAST_MEASUREMENT_SELECT(x) (((x) >> S_LAST_MEASUREMENT_SELECT) & M_LAST_MEASUREMENT_SELECT)
4415 #define S_LAST_MEASUREMENT_RESULT_BANK_B 4
4416 #define M_LAST_MEASUREMENT_RESULT_BANK_B 0xfU
4417 #define V_LAST_MEASUREMENT_RESULT_BANK_B(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_B)
4418 #define G_LAST_MEASUREMENT_RESULT_BANK_B(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_B) & M_LAST_MEASUREMENT_RESULT_BANK_B)
4420 #define S_LAST_MEASUREMENT_RESULT_BANK_A 0
4421 #define M_LAST_MEASUREMENT_RESULT_BANK_A 0xfU
4422 #define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A)
4423 #define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A)
4425 #define A_DBG_PVT_REG_DRVN 0x610c
4427 #define S_PVT_REG_DRVN_EN 8
4428 #define V_PVT_REG_DRVN_EN(x) ((x) << S_PVT_REG_DRVN_EN)
4429 #define F_PVT_REG_DRVN_EN V_PVT_REG_DRVN_EN(1U)
4431 #define S_PVT_REG_DRVN_B 4
4432 #define M_PVT_REG_DRVN_B 0xfU
4433 #define V_PVT_REG_DRVN_B(x) ((x) << S_PVT_REG_DRVN_B)
4434 #define G_PVT_REG_DRVN_B(x) (((x) >> S_PVT_REG_DRVN_B) & M_PVT_REG_DRVN_B)
4436 #define S_PVT_REG_DRVN_A 0
4437 #define M_PVT_REG_DRVN_A 0xfU
4438 #define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A)
4439 #define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A)
4441 #define A_DBG_PVT_REG_DRVP 0x6110
4443 #define S_PVT_REG_DRVP_EN 8
4444 #define V_PVT_REG_DRVP_EN(x) ((x) << S_PVT_REG_DRVP_EN)
4445 #define F_PVT_REG_DRVP_EN V_PVT_REG_DRVP_EN(1U)
4447 #define S_PVT_REG_DRVP_B 4
4448 #define M_PVT_REG_DRVP_B 0xfU
4449 #define V_PVT_REG_DRVP_B(x) ((x) << S_PVT_REG_DRVP_B)
4450 #define G_PVT_REG_DRVP_B(x) (((x) >> S_PVT_REG_DRVP_B) & M_PVT_REG_DRVP_B)
4452 #define S_PVT_REG_DRVP_A 0
4453 #define M_PVT_REG_DRVP_A 0xfU
4454 #define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A)
4455 #define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A)
4457 #define A_DBG_PVT_REG_TERMN 0x6114
4459 #define S_PVT_REG_TERMN_EN 8
4460 #define V_PVT_REG_TERMN_EN(x) ((x) << S_PVT_REG_TERMN_EN)
4461 #define F_PVT_REG_TERMN_EN V_PVT_REG_TERMN_EN(1U)
4463 #define S_PVT_REG_TERMN_B 4
4464 #define M_PVT_REG_TERMN_B 0xfU
4465 #define V_PVT_REG_TERMN_B(x) ((x) << S_PVT_REG_TERMN_B)
4466 #define G_PVT_REG_TERMN_B(x) (((x) >> S_PVT_REG_TERMN_B) & M_PVT_REG_TERMN_B)
4468 #define S_PVT_REG_TERMN_A 0
4469 #define M_PVT_REG_TERMN_A 0xfU
4470 #define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A)
4471 #define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A)
4473 #define A_DBG_PVT_REG_TERMP 0x6118
4475 #define S_PVT_REG_TERMP_EN 8
4476 #define V_PVT_REG_TERMP_EN(x) ((x) << S_PVT_REG_TERMP_EN)
4477 #define F_PVT_REG_TERMP_EN V_PVT_REG_TERMP_EN(1U)
4479 #define S_PVT_REG_TERMP_B 4
4480 #define M_PVT_REG_TERMP_B 0xfU
4481 #define V_PVT_REG_TERMP_B(x) ((x) << S_PVT_REG_TERMP_B)
4482 #define G_PVT_REG_TERMP_B(x) (((x) >> S_PVT_REG_TERMP_B) & M_PVT_REG_TERMP_B)
4484 #define S_PVT_REG_TERMP_A 0
4485 #define M_PVT_REG_TERMP_A 0xfU
4486 #define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A)
4487 #define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A)
4489 #define A_DBG_PVT_REG_THRESHOLD 0x611c
4491 #define S_PVT_CALIBRATION_DONE 8
4492 #define V_PVT_CALIBRATION_DONE(x) ((x) << S_PVT_CALIBRATION_DONE)
4493 #define F_PVT_CALIBRATION_DONE V_PVT_CALIBRATION_DONE(1U)
4495 #define S_THRESHOLD_TERMP_MAX_SYNC 7
4496 #define V_THRESHOLD_TERMP_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMP_MAX_SYNC)
4497 #define F_THRESHOLD_TERMP_MAX_SYNC V_THRESHOLD_TERMP_MAX_SYNC(1U)
4499 #define S_THRESHOLD_TERMP_MIN_SYNC 6
4500 #define V_THRESHOLD_TERMP_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMP_MIN_SYNC)
4501 #define F_THRESHOLD_TERMP_MIN_SYNC V_THRESHOLD_TERMP_MIN_SYNC(1U)
4503 #define S_THRESHOLD_TERMN_MAX_SYNC 5
4504 #define V_THRESHOLD_TERMN_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMN_MAX_SYNC)
4505 #define F_THRESHOLD_TERMN_MAX_SYNC V_THRESHOLD_TERMN_MAX_SYNC(1U)
4507 #define S_THRESHOLD_TERMN_MIN_SYNC 4
4508 #define V_THRESHOLD_TERMN_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMN_MIN_SYNC)
4509 #define F_THRESHOLD_TERMN_MIN_SYNC V_THRESHOLD_TERMN_MIN_SYNC(1U)
4511 #define S_THRESHOLD_DRVP_MAX_SYNC 3
4512 #define V_THRESHOLD_DRVP_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVP_MAX_SYNC)
4513 #define F_THRESHOLD_DRVP_MAX_SYNC V_THRESHOLD_DRVP_MAX_SYNC(1U)
4515 #define S_THRESHOLD_DRVP_MIN_SYNC 2
4516 #define V_THRESHOLD_DRVP_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVP_MIN_SYNC)
4517 #define F_THRESHOLD_DRVP_MIN_SYNC V_THRESHOLD_DRVP_MIN_SYNC(1U)
4519 #define S_THRESHOLD_DRVN_MAX_SYNC 1
4520 #define V_THRESHOLD_DRVN_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVN_MAX_SYNC)
4521 #define F_THRESHOLD_DRVN_MAX_SYNC V_THRESHOLD_DRVN_MAX_SYNC(1U)
4523 #define S_THRESHOLD_DRVN_MIN_SYNC 0
4524 #define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC)
4525 #define F_THRESHOLD_DRVN_MIN_SYNC V_THRESHOLD_DRVN_MIN_SYNC(1U)
4527 #define A_DBG_PVT_REG_IN_TERMP 0x6120
4529 #define S_REG_IN_TERMP_B 4
4530 #define M_REG_IN_TERMP_B 0xfU
4531 #define V_REG_IN_TERMP_B(x) ((x) << S_REG_IN_TERMP_B)
4532 #define G_REG_IN_TERMP_B(x) (((x) >> S_REG_IN_TERMP_B) & M_REG_IN_TERMP_B)
4534 #define S_REG_IN_TERMP_A 0
4535 #define M_REG_IN_TERMP_A 0xfU
4536 #define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A)
4537 #define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A)
4539 #define A_DBG_PVT_REG_IN_TERMN 0x6124
4541 #define S_REG_IN_TERMN_B 4
4542 #define M_REG_IN_TERMN_B 0xfU
4543 #define V_REG_IN_TERMN_B(x) ((x) << S_REG_IN_TERMN_B)
4544 #define G_REG_IN_TERMN_B(x) (((x) >> S_REG_IN_TERMN_B) & M_REG_IN_TERMN_B)
4546 #define S_REG_IN_TERMN_A 0
4547 #define M_REG_IN_TERMN_A 0xfU
4548 #define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A)
4549 #define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A)
4551 #define A_DBG_PVT_REG_IN_DRVP 0x6128
4553 #define S_REG_IN_DRVP_B 4
4554 #define M_REG_IN_DRVP_B 0xfU
4555 #define V_REG_IN_DRVP_B(x) ((x) << S_REG_IN_DRVP_B)
4556 #define G_REG_IN_DRVP_B(x) (((x) >> S_REG_IN_DRVP_B) & M_REG_IN_DRVP_B)
4558 #define S_REG_IN_DRVP_A 0
4559 #define M_REG_IN_DRVP_A 0xfU
4560 #define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A)
4561 #define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A)
4563 #define A_DBG_PVT_REG_IN_DRVN 0x612c
4565 #define S_REG_IN_DRVN_B 4
4566 #define M_REG_IN_DRVN_B 0xfU
4567 #define V_REG_IN_DRVN_B(x) ((x) << S_REG_IN_DRVN_B)
4568 #define G_REG_IN_DRVN_B(x) (((x) >> S_REG_IN_DRVN_B) & M_REG_IN_DRVN_B)
4570 #define S_REG_IN_DRVN_A 0
4571 #define M_REG_IN_DRVN_A 0xfU
4572 #define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A)
4573 #define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A)
4575 #define A_DBG_PVT_REG_OUT_TERMP 0x6130
4577 #define S_REG_OUT_TERMP_B 4
4578 #define M_REG_OUT_TERMP_B 0xfU
4579 #define V_REG_OUT_TERMP_B(x) ((x) << S_REG_OUT_TERMP_B)
4580 #define G_REG_OUT_TERMP_B(x) (((x) >> S_REG_OUT_TERMP_B) & M_REG_OUT_TERMP_B)
4582 #define S_REG_OUT_TERMP_A 0
4583 #define M_REG_OUT_TERMP_A 0xfU
4584 #define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A)
4585 #define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A)
4587 #define A_DBG_PVT_REG_OUT_TERMN 0x6134
4589 #define S_REG_OUT_TERMN_B 4
4590 #define M_REG_OUT_TERMN_B 0xfU
4591 #define V_REG_OUT_TERMN_B(x) ((x) << S_REG_OUT_TERMN_B)
4592 #define G_REG_OUT_TERMN_B(x) (((x) >> S_REG_OUT_TERMN_B) & M_REG_OUT_TERMN_B)
4594 #define S_REG_OUT_TERMN_A 0
4595 #define M_REG_OUT_TERMN_A 0xfU
4596 #define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A)
4597 #define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A)
4599 #define A_DBG_PVT_REG_OUT_DRVP 0x6138
4601 #define S_REG_OUT_DRVP_B 4
4602 #define M_REG_OUT_DRVP_B 0xfU
4603 #define V_REG_OUT_DRVP_B(x) ((x) << S_REG_OUT_DRVP_B)
4604 #define G_REG_OUT_DRVP_B(x) (((x) >> S_REG_OUT_DRVP_B) & M_REG_OUT_DRVP_B)
4606 #define S_REG_OUT_DRVP_A 0
4607 #define M_REG_OUT_DRVP_A 0xfU
4608 #define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A)
4609 #define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A)
4611 #define A_DBG_PVT_REG_OUT_DRVN 0x613c
4613 #define S_REG_OUT_DRVN_B 4
4614 #define M_REG_OUT_DRVN_B 0xfU
4615 #define V_REG_OUT_DRVN_B(x) ((x) << S_REG_OUT_DRVN_B)
4616 #define G_REG_OUT_DRVN_B(x) (((x) >> S_REG_OUT_DRVN_B) & M_REG_OUT_DRVN_B)
4618 #define S_REG_OUT_DRVN_A 0
4619 #define M_REG_OUT_DRVN_A 0xfU
4620 #define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A)
4621 #define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A)
4623 #define A_DBG_PVT_REG_HISTORY_TERMP 0x6140
4625 #define S_TERMP_B_HISTORY 4
4626 #define M_TERMP_B_HISTORY 0xfU
4627 #define V_TERMP_B_HISTORY(x) ((x) << S_TERMP_B_HISTORY)
4628 #define G_TERMP_B_HISTORY(x) (((x) >> S_TERMP_B_HISTORY) & M_TERMP_B_HISTORY)
4630 #define S_TERMP_A_HISTORY 0
4631 #define M_TERMP_A_HISTORY 0xfU
4632 #define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY)
4633 #define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY)
4635 #define A_DBG_PVT_REG_HISTORY_TERMN 0x6144
4637 #define S_TERMN_B_HISTORY 4
4638 #define M_TERMN_B_HISTORY 0xfU
4639 #define V_TERMN_B_HISTORY(x) ((x) << S_TERMN_B_HISTORY)
4640 #define G_TERMN_B_HISTORY(x) (((x) >> S_TERMN_B_HISTORY) & M_TERMN_B_HISTORY)
4642 #define S_TERMN_A_HISTORY 0
4643 #define M_TERMN_A_HISTORY 0xfU
4644 #define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY)
4645 #define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY)
4647 #define A_DBG_PVT_REG_HISTORY_DRVP 0x6148
4649 #define S_DRVP_B_HISTORY 4
4650 #define M_DRVP_B_HISTORY 0xfU
4651 #define V_DRVP_B_HISTORY(x) ((x) << S_DRVP_B_HISTORY)
4652 #define G_DRVP_B_HISTORY(x) (((x) >> S_DRVP_B_HISTORY) & M_DRVP_B_HISTORY)
4654 #define S_DRVP_A_HISTORY 0
4655 #define M_DRVP_A_HISTORY 0xfU
4656 #define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY)
4657 #define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY)
4659 #define A_DBG_PVT_REG_HISTORY_DRVN 0x614c
4661 #define S_DRVN_B_HISTORY 4
4662 #define M_DRVN_B_HISTORY 0xfU
4663 #define V_DRVN_B_HISTORY(x) ((x) << S_DRVN_B_HISTORY)
4664 #define G_DRVN_B_HISTORY(x) (((x) >> S_DRVN_B_HISTORY) & M_DRVN_B_HISTORY)
4666 #define S_DRVN_A_HISTORY 0
4667 #define M_DRVN_A_HISTORY 0xfU
4668 #define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY)
4669 #define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY)
4671 #define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150
4673 #define S_SAMPLE_WAIT_CLKS 0
4674 #define M_SAMPLE_WAIT_CLKS 0x1fU
4675 #define V_SAMPLE_WAIT_CLKS(x) ((x) << S_SAMPLE_WAIT_CLKS)
4676 #define G_SAMPLE_WAIT_CLKS(x) (((x) >> S_SAMPLE_WAIT_CLKS) & M_SAMPLE_WAIT_CLKS)
4678 /* registers for module MC */
4679 #define MC_BASE_ADDR 0x6200
4681 #define A_MC_PCTL_SCFG 0x6200
4683 #define S_RKINF_EN 5
4684 #define V_RKINF_EN(x) ((x) << S_RKINF_EN)
4685 #define F_RKINF_EN V_RKINF_EN(1U)
4687 #define S_DUAL_PCTL_EN 4
4688 #define V_DUAL_PCTL_EN(x) ((x) << S_DUAL_PCTL_EN)
4689 #define F_DUAL_PCTL_EN V_DUAL_PCTL_EN(1U)
4691 #define S_SLAVE_MODE 3
4692 #define V_SLAVE_MODE(x) ((x) << S_SLAVE_MODE)
4693 #define F_SLAVE_MODE V_SLAVE_MODE(1U)
4695 #define S_LOOPBACK_EN 1
4696 #define V_LOOPBACK_EN(x) ((x) << S_LOOPBACK_EN)
4697 #define F_LOOPBACK_EN V_LOOPBACK_EN(1U)
4699 #define S_HW_LOW_POWER_EN 0
4700 #define V_HW_LOW_POWER_EN(x) ((x) << S_HW_LOW_POWER_EN)
4701 #define F_HW_LOW_POWER_EN V_HW_LOW_POWER_EN(1U)
4703 #define A_MC_PCTL_SCTL 0x6204
4705 #define S_STATE_CMD 0
4706 #define M_STATE_CMD 0x7U
4707 #define V_STATE_CMD(x) ((x) << S_STATE_CMD)
4708 #define G_STATE_CMD(x) (((x) >> S_STATE_CMD) & M_STATE_CMD)
4710 #define A_MC_PCTL_STAT 0x6208
4712 #define S_CTL_STAT 0
4713 #define M_CTL_STAT 0x7U
4714 #define V_CTL_STAT(x) ((x) << S_CTL_STAT)
4715 #define G_CTL_STAT(x) (((x) >> S_CTL_STAT) & M_CTL_STAT)
4717 #define A_MC_PCTL_MCMD 0x6240
4719 #define S_START_CMD 31
4720 #define V_START_CMD(x) ((x) << S_START_CMD)
4721 #define F_START_CMD V_START_CMD(1U)
4723 #define S_CMD_ADD_DEL 24
4724 #define M_CMD_ADD_DEL 0xfU
4725 #define V_CMD_ADD_DEL(x) ((x) << S_CMD_ADD_DEL)
4726 #define G_CMD_ADD_DEL(x) (((x) >> S_CMD_ADD_DEL) & M_CMD_ADD_DEL)
4728 #define S_RANK_SEL 20
4729 #define M_RANK_SEL 0xfU
4730 #define V_RANK_SEL(x) ((x) << S_RANK_SEL)
4731 #define G_RANK_SEL(x) (((x) >> S_RANK_SEL) & M_RANK_SEL)
4733 #define S_BANK_ADDR 17
4734 #define M_BANK_ADDR 0x7U
4735 #define V_BANK_ADDR(x) ((x) << S_BANK_ADDR)
4736 #define G_BANK_ADDR(x) (((x) >> S_BANK_ADDR) & M_BANK_ADDR)
4738 #define S_CMD_ADDR 4
4739 #define M_CMD_ADDR 0x1fffU
4740 #define V_CMD_ADDR(x) ((x) << S_CMD_ADDR)
4741 #define G_CMD_ADDR(x) (((x) >> S_CMD_ADDR) & M_CMD_ADDR)
4743 #define S_CMD_OPCODE 0
4744 #define M_CMD_OPCODE 0x7U
4745 #define V_CMD_OPCODE(x) ((x) << S_CMD_OPCODE)
4746 #define G_CMD_OPCODE(x) (((x) >> S_CMD_OPCODE) & M_CMD_OPCODE)
4748 #define A_MC_PCTL_POWCTL 0x6244
4750 #define S_POWER_UP_START 0
4751 #define V_POWER_UP_START(x) ((x) << S_POWER_UP_START)
4752 #define F_POWER_UP_START V_POWER_UP_START(1U)
4754 #define A_MC_PCTL_POWSTAT 0x6248
4756 #define S_PHY_CALIBDONE 1
4757 #define V_PHY_CALIBDONE(x) ((x) << S_PHY_CALIBDONE)
4758 #define F_PHY_CALIBDONE V_PHY_CALIBDONE(1U)
4760 #define S_POWER_UP_DONE 0
4761 #define V_POWER_UP_DONE(x) ((x) << S_POWER_UP_DONE)
4762 #define F_POWER_UP_DONE V_POWER_UP_DONE(1U)
4764 #define A_MC_PCTL_MCFG 0x6280
4766 #define S_TFAW_CFG 18
4767 #define M_TFAW_CFG 0x3U
4768 #define V_TFAW_CFG(x) ((x) << S_TFAW_CFG)
4769 #define G_TFAW_CFG(x) (((x) >> S_TFAW_CFG) & M_TFAW_CFG)
4771 #define S_PD_EXIT_MODE 17
4772 #define V_PD_EXIT_MODE(x) ((x) << S_PD_EXIT_MODE)
4773 #define F_PD_EXIT_MODE V_PD_EXIT_MODE(1U)
4775 #define S_PD_TYPE 16
4776 #define V_PD_TYPE(x) ((x) << S_PD_TYPE)
4777 #define F_PD_TYPE V_PD_TYPE(1U)
4780 #define M_PD_IDLE 0xffU
4781 #define V_PD_IDLE(x) ((x) << S_PD_IDLE)
4782 #define G_PD_IDLE(x) (((x) >> S_PD_IDLE) & M_PD_IDLE)
4784 #define S_PAGE_POLICY 6
4785 #define M_PAGE_POLICY 0x3U
4786 #define V_PAGE_POLICY(x) ((x) << S_PAGE_POLICY)
4787 #define G_PAGE_POLICY(x) (((x) >> S_PAGE_POLICY) & M_PAGE_POLICY)
4790 #define V_DDR3_EN(x) ((x) << S_DDR3_EN)
4791 #define F_DDR3_EN V_DDR3_EN(1U)
4793 #define S_TWO_T_EN 3
4794 #define V_TWO_T_EN(x) ((x) << S_TWO_T_EN)
4795 #define F_TWO_T_EN V_TWO_T_EN(1U)
4797 #define S_BL8INT_EN 2
4798 #define V_BL8INT_EN(x) ((x) << S_BL8INT_EN)
4799 #define F_BL8INT_EN V_BL8INT_EN(1U)
4802 #define V_MEM_BL(x) ((x) << S_MEM_BL)
4803 #define F_MEM_BL V_MEM_BL(1U)
4805 #define A_MC_PCTL_PPCFG 0x6284
4807 #define S_RPMEM_DIS 1
4808 #define M_RPMEM_DIS 0xffU
4809 #define V_RPMEM_DIS(x) ((x) << S_RPMEM_DIS)
4810 #define G_RPMEM_DIS(x) (((x) >> S_RPMEM_DIS) & M_RPMEM_DIS)
4812 #define S_PPMEM_EN 0
4813 #define V_PPMEM_EN(x) ((x) << S_PPMEM_EN)
4814 #define F_PPMEM_EN V_PPMEM_EN(1U)
4816 #define A_MC_PCTL_MSTAT 0x6288
4818 #define S_POWER_DOWN 0
4819 #define V_POWER_DOWN(x) ((x) << S_POWER_DOWN)
4820 #define F_POWER_DOWN V_POWER_DOWN(1U)
4822 #define A_MC_PCTL_ODTCFG 0x628c
4824 #define S_RANK3_ODT_DEFAULT 28
4825 #define V_RANK3_ODT_DEFAULT(x) ((x) << S_RANK3_ODT_DEFAULT)
4826 #define F_RANK3_ODT_DEFAULT V_RANK3_ODT_DEFAULT(1U)
4828 #define S_RANK3_ODT_WRITE_SEL 27
4829 #define V_RANK3_ODT_WRITE_SEL(x) ((x) << S_RANK3_ODT_WRITE_SEL)
4830 #define F_RANK3_ODT_WRITE_SEL V_RANK3_ODT_WRITE_SEL(1U)
4832 #define S_RANK3_ODT_WRITE_NSE 26
4833 #define V_RANK3_ODT_WRITE_NSE(x) ((x) << S_RANK3_ODT_WRITE_NSE)
4834 #define F_RANK3_ODT_WRITE_NSE V_RANK3_ODT_WRITE_NSE(1U)
4836 #define S_RANK3_ODT_READ_SEL 25
4837 #define V_RANK3_ODT_READ_SEL(x) ((x) << S_RANK3_ODT_READ_SEL)
4838 #define F_RANK3_ODT_READ_SEL V_RANK3_ODT_READ_SEL(1U)
4840 #define S_RANK3_ODT_READ_NSEL 24
4841 #define V_RANK3_ODT_READ_NSEL(x) ((x) << S_RANK3_ODT_READ_NSEL)
4842 #define F_RANK3_ODT_READ_NSEL V_RANK3_ODT_READ_NSEL(1U)
4844 #define S_RANK2_ODT_DEFAULT 20
4845 #define V_RANK2_ODT_DEFAULT(x) ((x) << S_RANK2_ODT_DEFAULT)
4846 #define F_RANK2_ODT_DEFAULT V_RANK2_ODT_DEFAULT(1U)
4848 #define S_RANK2_ODT_WRITE_SEL 19
4849 #define V_RANK2_ODT_WRITE_SEL(x) ((x) << S_RANK2_ODT_WRITE_SEL)
4850 #define F_RANK2_ODT_WRITE_SEL V_RANK2_ODT_WRITE_SEL(1U)
4852 #define S_RANK2_ODT_WRITE_NSEL 18
4853 #define V_RANK2_ODT_WRITE_NSEL(x) ((x) << S_RANK2_ODT_WRITE_NSEL)
4854 #define F_RANK2_ODT_WRITE_NSEL V_RANK2_ODT_WRITE_NSEL(1U)
4856 #define S_RANK2_ODT_READ_SEL 17
4857 #define V_RANK2_ODT_READ_SEL(x) ((x) << S_RANK2_ODT_READ_SEL)
4858 #define F_RANK2_ODT_READ_SEL V_RANK2_ODT_READ_SEL(1U)
4860 #define S_RANK2_ODT_READ_NSEL 16
4861 #define V_RANK2_ODT_READ_NSEL(x) ((x) << S_RANK2_ODT_READ_NSEL)
4862 #define F_RANK2_ODT_READ_NSEL V_RANK2_ODT_READ_NSEL(1U)
4864 #define S_RANK1_ODT_DEFAULT 12
4865 #define V_RANK1_ODT_DEFAULT(x) ((x) << S_RANK1_ODT_DEFAULT)
4866 #define F_RANK1_ODT_DEFAULT V_RANK1_ODT_DEFAULT(1U)
4868 #define S_RANK1_ODT_WRITE_SEL 11
4869 #define V_RANK1_ODT_WRITE_SEL(x) ((x) << S_RANK1_ODT_WRITE_SEL)
4870 #define F_RANK1_ODT_WRITE_SEL V_RANK1_ODT_WRITE_SEL(1U)
4872 #define S_RANK1_ODT_WRITE_NSEL 10
4873 #define V_RANK1_ODT_WRITE_NSEL(x) ((x) << S_RANK1_ODT_WRITE_NSEL)
4874 #define F_RANK1_ODT_WRITE_NSEL V_RANK1_ODT_WRITE_NSEL(1U)
4876 #define S_RANK1_ODT_READ_SEL 9
4877 #define V_RANK1_ODT_READ_SEL(x) ((x) << S_RANK1_ODT_READ_SEL)
4878 #define F_RANK1_ODT_READ_SEL V_RANK1_ODT_READ_SEL(1U)
4880 #define S_RANK1_ODT_READ_NSEL 8
4881 #define V_RANK1_ODT_READ_NSEL(x) ((x) << S_RANK1_ODT_READ_NSEL)
4882 #define F_RANK1_ODT_READ_NSEL V_RANK1_ODT_READ_NSEL(1U)
4884 #define S_RANK0_ODT_DEFAULT 4
4885 #define V_RANK0_ODT_DEFAULT(x) ((x) << S_RANK0_ODT_DEFAULT)
4886 #define F_RANK0_ODT_DEFAULT V_RANK0_ODT_DEFAULT(1U)
4888 #define S_RANK0_ODT_WRITE_SEL 3
4889 #define V_RANK0_ODT_WRITE_SEL(x) ((x) << S_RANK0_ODT_WRITE_SEL)
4890 #define F_RANK0_ODT_WRITE_SEL V_RANK0_ODT_WRITE_SEL(1U)
4892 #define S_RANK0_ODT_WRITE_NSEL 2
4893 #define V_RANK0_ODT_WRITE_NSEL(x) ((x) << S_RANK0_ODT_WRITE_NSEL)
4894 #define F_RANK0_ODT_WRITE_NSEL V_RANK0_ODT_WRITE_NSEL(1U)
4896 #define S_RANK0_ODT_READ_SEL 1
4897 #define V_RANK0_ODT_READ_SEL(x) ((x) << S_RANK0_ODT_READ_SEL)
4898 #define F_RANK0_ODT_READ_SEL V_RANK0_ODT_READ_SEL(1U)
4900 #define S_RANK0_ODT_READ_NSEL 0
4901 #define V_RANK0_ODT_READ_NSEL(x) ((x) << S_RANK0_ODT_READ_NSEL)
4902 #define F_RANK0_ODT_READ_NSEL V_RANK0_ODT_READ_NSEL(1U)
4904 #define A_MC_PCTL_DQSECFG 0x6290
4906 #define S_DV_ALAT 20
4907 #define M_DV_ALAT 0xfU
4908 #define V_DV_ALAT(x) ((x) << S_DV_ALAT)
4909 #define G_DV_ALAT(x) (((x) >> S_DV_ALAT) & M_DV_ALAT)
4911 #define S_DV_ALEN 16
4912 #define M_DV_ALEN 0x3U
4913 #define V_DV_ALEN(x) ((x) << S_DV_ALEN)
4914 #define G_DV_ALEN(x) (((x) >> S_DV_ALEN) & M_DV_ALEN)
4916 #define S_DSE_ALAT 12
4917 #define M_DSE_ALAT 0xfU
4918 #define V_DSE_ALAT(x) ((x) << S_DSE_ALAT)
4919 #define G_DSE_ALAT(x) (((x) >> S_DSE_ALAT) & M_DSE_ALAT)
4921 #define S_DSE_ALEN 8
4922 #define M_DSE_ALEN 0x3U
4923 #define V_DSE_ALEN(x) ((x) << S_DSE_ALEN)
4924 #define G_DSE_ALEN(x) (((x) >> S_DSE_ALEN) & M_DSE_ALEN)
4926 #define S_QSE_ALAT 4
4927 #define M_QSE_ALAT 0xfU
4928 #define V_QSE_ALAT(x) ((x) << S_QSE_ALAT)
4929 #define G_QSE_ALAT(x) (((x) >> S_QSE_ALAT) & M_QSE_ALAT)
4931 #define S_QSE_ALEN 0
4932 #define M_QSE_ALEN 0x3U
4933 #define V_QSE_ALEN(x) ((x) << S_QSE_ALEN)
4934 #define G_QSE_ALEN(x) (((x) >> S_QSE_ALEN) & M_QSE_ALEN)
4936 #define A_MC_PCTL_DTUPDES 0x6294
4938 #define S_DTU_RD_MISSING 13
4939 #define V_DTU_RD_MISSING(x) ((x) << S_DTU_RD_MISSING)
4940 #define F_DTU_RD_MISSING V_DTU_RD_MISSING(1U)
4942 #define S_DTU_EAFFL 9
4943 #define M_DTU_EAFFL 0xfU
4944 #define V_DTU_EAFFL(x) ((x) << S_DTU_EAFFL)
4945 #define G_DTU_EAFFL(x) (((x) >> S_DTU_EAFFL) & M_DTU_EAFFL)
4947 #define S_DTU_RANDOM_ERROR 8
4948 #define V_DTU_RANDOM_ERROR(x) ((x) << S_DTU_RANDOM_ERROR)
4949 #define F_DTU_RANDOM_ERROR V_DTU_RANDOM_ERROR(1U)
4951 #define S_DTU_ERROR_B7 7
4952 #define V_DTU_ERROR_B7(x) ((x) << S_DTU_ERROR_B7)
4953 #define F_DTU_ERROR_B7 V_DTU_ERROR_B7(1U)
4955 #define S_DTU_ERR_B6 6
4956 #define V_DTU_ERR_B6(x) ((x) << S_DTU_ERR_B6)
4957 #define F_DTU_ERR_B6 V_DTU_ERR_B6(1U)
4959 #define S_DTU_ERR_B5 5
4960 #define V_DTU_ERR_B5(x) ((x) << S_DTU_ERR_B5)
4961 #define F_DTU_ERR_B5 V_DTU_ERR_B5(1U)
4963 #define S_DTU_ERR_B4 4
4964 #define V_DTU_ERR_B4(x) ((x) << S_DTU_ERR_B4)
4965 #define F_DTU_ERR_B4 V_DTU_ERR_B4(1U)
4967 #define S_DTU_ERR_B3 3
4968 #define V_DTU_ERR_B3(x) ((x) << S_DTU_ERR_B3)
4969 #define F_DTU_ERR_B3 V_DTU_ERR_B3(1U)
4971 #define S_DTU_ERR_B2 2
4972 #define V_DTU_ERR_B2(x) ((x) << S_DTU_ERR_B2)
4973 #define F_DTU_ERR_B2 V_DTU_ERR_B2(1U)
4975 #define S_DTU_ERR_B1 1
4976 #define V_DTU_ERR_B1(x) ((x) << S_DTU_ERR_B1)
4977 #define F_DTU_ERR_B1 V_DTU_ERR_B1(1U)
4979 #define S_DTU_ERR_B0 0
4980 #define V_DTU_ERR_B0(x) ((x) << S_DTU_ERR_B0)
4981 #define F_DTU_ERR_B0 V_DTU_ERR_B0(1U)
4983 #define A_MC_PCTL_DTUNA 0x6298
4984 #define A_MC_PCTL_DTUNE 0x629c
4985 #define A_MC_PCTL_DTUPRDO 0x62a0
4987 #define S_DTU_ALLBITS_1 16
4988 #define M_DTU_ALLBITS_1 0xffffU
4989 #define V_DTU_ALLBITS_1(x) ((x) << S_DTU_ALLBITS_1)
4990 #define G_DTU_ALLBITS_1(x) (((x) >> S_DTU_ALLBITS_1) & M_DTU_ALLBITS_1)
4992 #define S_DTU_ALLBITS_0 0
4993 #define M_DTU_ALLBITS_0 0xffffU
4994 #define V_DTU_ALLBITS_0(x) ((x) << S_DTU_ALLBITS_0)
4995 #define G_DTU_ALLBITS_0(x) (((x) >> S_DTU_ALLBITS_0) & M_DTU_ALLBITS_0)
4997 #define A_MC_PCTL_DTUPRD1 0x62a4
4999 #define S_DTU_ALLBITS_3 16
5000 #define M_DTU_ALLBITS_3 0xffffU
5001 #define V_DTU_ALLBITS_3(x) ((x) << S_DTU_ALLBITS_3)
5002 #define G_DTU_ALLBITS_3(x) (((x) >> S_DTU_ALLBITS_3) & M_DTU_ALLBITS_3)
5004 #define S_DTU_ALLBITS_2 0
5005 #define M_DTU_ALLBITS_2 0xffffU
5006 #define V_DTU_ALLBITS_2(x) ((x) << S_DTU_ALLBITS_2)
5007 #define G_DTU_ALLBITS_2(x) (((x) >> S_DTU_ALLBITS_2) & M_DTU_ALLBITS_2)
5009 #define A_MC_PCTL_DTUPRD2 0x62a8
5011 #define S_DTU_ALLBITS_5 16
5012 #define M_DTU_ALLBITS_5 0xffffU
5013 #define V_DTU_ALLBITS_5(x) ((x) << S_DTU_ALLBITS_5)
5014 #define G_DTU_ALLBITS_5(x) (((x) >> S_DTU_ALLBITS_5) & M_DTU_ALLBITS_5)
5016 #define S_DTU_ALLBITS_4 0
5017 #define M_DTU_ALLBITS_4 0xffffU
5018 #define V_DTU_ALLBITS_4(x) ((x) << S_DTU_ALLBITS_4)
5019 #define G_DTU_ALLBITS_4(x) (((x) >> S_DTU_ALLBITS_4) & M_DTU_ALLBITS_4)
5021 #define A_MC_PCTL_DTUPRD3 0x62ac
5023 #define S_DTU_ALLBITS_7 16
5024 #define M_DTU_ALLBITS_7 0xffffU
5025 #define V_DTU_ALLBITS_7(x) ((x) << S_DTU_ALLBITS_7)
5026 #define G_DTU_ALLBITS_7(x) (((x) >> S_DTU_ALLBITS_7) & M_DTU_ALLBITS_7)
5028 #define S_DTU_ALLBITS_6 0
5029 #define M_DTU_ALLBITS_6 0xffffU
5030 #define V_DTU_ALLBITS_6(x) ((x) << S_DTU_ALLBITS_6)
5031 #define G_DTU_ALLBITS_6(x) (((x) >> S_DTU_ALLBITS_6) & M_DTU_ALLBITS_6)
5033 #define A_MC_PCTL_DTUAWDT 0x62b0
5035 #define S_NUMBER_RANKS 9
5036 #define M_NUMBER_RANKS 0x3U
5037 #define V_NUMBER_RANKS(x) ((x) << S_NUMBER_RANKS)
5038 #define G_NUMBER_RANKS(x) (((x) >> S_NUMBER_RANKS) & M_NUMBER_RANKS)
5040 #define S_ROW_ADDR_WIDTH 6
5041 #define M_ROW_ADDR_WIDTH 0x3U
5042 #define V_ROW_ADDR_WIDTH(x) ((x) << S_ROW_ADDR_WIDTH)
5043 #define G_ROW_ADDR_WIDTH(x) (((x) >> S_ROW_ADDR_WIDTH) & M_ROW_ADDR_WIDTH)
5045 #define S_BANK_ADDR_WIDTH 3
5046 #define M_BANK_ADDR_WIDTH 0x3U
5047 #define V_BANK_ADDR_WIDTH(x) ((x) << S_BANK_ADDR_WIDTH)
5048 #define G_BANK_ADDR_WIDTH(x) (((x) >> S_BANK_ADDR_WIDTH) & M_BANK_ADDR_WIDTH)
5050 #define S_COLUMN_ADDR_WIDTH 0
5051 #define M_COLUMN_ADDR_WIDTH 0x3U
5052 #define V_COLUMN_ADDR_WIDTH(x) ((x) << S_COLUMN_ADDR_WIDTH)
5053 #define G_COLUMN_ADDR_WIDTH(x) (((x) >> S_COLUMN_ADDR_WIDTH) & M_COLUMN_ADDR_WIDTH)
5055 #define A_MC_PCTL_TOGCNT1U 0x62c0
5057 #define S_TOGGLE_COUNTER_1U 0
5058 #define M_TOGGLE_COUNTER_1U 0x3ffU
5059 #define V_TOGGLE_COUNTER_1U(x) ((x) << S_TOGGLE_COUNTER_1U)
5060 #define G_TOGGLE_COUNTER_1U(x) (((x) >> S_TOGGLE_COUNTER_1U) & M_TOGGLE_COUNTER_1U)
5062 #define A_MC_PCTL_TINIT 0x62c4
5065 #define M_T_INIT 0x1ffU
5066 #define V_T_INIT(x) ((x) << S_T_INIT)
5067 #define G_T_INIT(x) (((x) >> S_T_INIT) & M_T_INIT)
5069 #define A_MC_PCTL_TRSTH 0x62c8
5072 #define M_T_RSTH 0x3ffU
5073 #define V_T_RSTH(x) ((x) << S_T_RSTH)
5074 #define G_T_RSTH(x) (((x) >> S_T_RSTH) & M_T_RSTH)
5076 #define A_MC_PCTL_TOGCNT100N 0x62cc
5078 #define S_TOGGLE_COUNTER_100N 0
5079 #define M_TOGGLE_COUNTER_100N 0x7fU
5080 #define V_TOGGLE_COUNTER_100N(x) ((x) << S_TOGGLE_COUNTER_100N)
5081 #define G_TOGGLE_COUNTER_100N(x) (((x) >> S_TOGGLE_COUNTER_100N) & M_TOGGLE_COUNTER_100N)
5083 #define A_MC_PCTL_TREFI 0x62d0
5086 #define M_T_REFI 0xffU
5087 #define V_T_REFI(x) ((x) << S_T_REFI)
5088 #define G_T_REFI(x) (((x) >> S_T_REFI) & M_T_REFI)
5090 #define A_MC_PCTL_TMRD 0x62d4
5093 #define M_T_MRD 0x7U
5094 #define V_T_MRD(x) ((x) << S_T_MRD)
5095 #define G_T_MRD(x) (((x) >> S_T_MRD) & M_T_MRD)
5097 #define A_MC_PCTL_TRFC 0x62d8
5100 #define M_T_RFC 0xffU
5101 #define V_T_RFC(x) ((x) << S_T_RFC)
5102 #define G_T_RFC(x) (((x) >> S_T_RFC) & M_T_RFC)
5104 #define A_MC_PCTL_TRP 0x62dc
5108 #define V_T_RP(x) ((x) << S_T_RP)
5109 #define G_T_RP(x) (((x) >> S_T_RP) & M_T_RP)
5111 #define A_MC_PCTL_TRTW 0x62e0
5114 #define M_T_RTW 0x7U
5115 #define V_T_RTW(x) ((x) << S_T_RTW)
5116 #define G_T_RTW(x) (((x) >> S_T_RTW) & M_T_RTW)
5118 #define A_MC_PCTL_TAL 0x62e4
5122 #define V_T_AL(x) ((x) << S_T_AL)
5123 #define G_T_AL(x) (((x) >> S_T_AL) & M_T_AL)
5125 #define A_MC_PCTL_TCL 0x62e8
5129 #define V_T_CL(x) ((x) << S_T_CL)
5130 #define G_T_CL(x) (((x) >> S_T_CL) & M_T_CL)
5132 #define A_MC_PCTL_TCWL 0x62ec
5135 #define M_T_CWL 0xfU
5136 #define V_T_CWL(x) ((x) << S_T_CWL)
5137 #define G_T_CWL(x) (((x) >> S_T_CWL) & M_T_CWL)
5139 #define A_MC_PCTL_TRAS 0x62f0
5142 #define M_T_RAS 0x3fU
5143 #define V_T_RAS(x) ((x) << S_T_RAS)
5144 #define G_T_RAS(x) (((x) >> S_T_RAS) & M_T_RAS)
5146 #define A_MC_PCTL_TRC 0x62f4
5149 #define M_T_RC 0x3fU
5150 #define V_T_RC(x) ((x) << S_T_RC)
5151 #define G_T_RC(x) (((x) >> S_T_RC) & M_T_RC)
5153 #define A_MC_PCTL_TRCD 0x62f8
5156 #define M_T_RCD 0xfU
5157 #define V_T_RCD(x) ((x) << S_T_RCD)
5158 #define G_T_RCD(x) (((x) >> S_T_RCD) & M_T_RCD)
5160 #define A_MC_PCTL_TRRD 0x62fc
5163 #define M_T_RRD 0xfU
5164 #define V_T_RRD(x) ((x) << S_T_RRD)
5165 #define G_T_RRD(x) (((x) >> S_T_RRD) & M_T_RRD)
5167 #define A_MC_PCTL_TRTP 0x6300
5170 #define M_T_RTP 0x7U
5171 #define V_T_RTP(x) ((x) << S_T_RTP)
5172 #define G_T_RTP(x) (((x) >> S_T_RTP) & M_T_RTP)
5174 #define A_MC_PCTL_TWR 0x6304
5178 #define V_T_WR(x) ((x) << S_T_WR)
5179 #define G_T_WR(x) (((x) >> S_T_WR) & M_T_WR)
5181 #define A_MC_PCTL_TWTR 0x6308
5184 #define M_T_WTR 0x7U
5185 #define V_T_WTR(x) ((x) << S_T_WTR)
5186 #define G_T_WTR(x) (((x) >> S_T_WTR) & M_T_WTR)
5188 #define A_MC_PCTL_TEXSR 0x630c
5191 #define M_T_EXSR 0x3ffU
5192 #define V_T_EXSR(x) ((x) << S_T_EXSR)
5193 #define G_T_EXSR(x) (((x) >> S_T_EXSR) & M_T_EXSR)
5195 #define A_MC_PCTL_TXP 0x6310
5199 #define V_T_XP(x) ((x) << S_T_XP)
5200 #define G_T_XP(x) (((x) >> S_T_XP) & M_T_XP)
5202 #define A_MC_PCTL_TXPDLL 0x6314
5205 #define M_T_XPDLL 0x3fU
5206 #define V_T_XPDLL(x) ((x) << S_T_XPDLL)
5207 #define G_T_XPDLL(x) (((x) >> S_T_XPDLL) & M_T_XPDLL)
5209 #define A_MC_PCTL_TZQCS 0x6318
5212 #define M_T_ZQCS 0x7fU
5213 #define V_T_ZQCS(x) ((x) << S_T_ZQCS)
5214 #define G_T_ZQCS(x) (((x) >> S_T_ZQCS) & M_T_ZQCS)
5216 #define A_MC_PCTL_TZQCSI 0x631c
5219 #define M_T_ZQCSI 0xfffU
5220 #define V_T_ZQCSI(x) ((x) << S_T_ZQCSI)
5221 #define G_T_ZQCSI(x) (((x) >> S_T_ZQCSI) & M_T_ZQCSI)
5223 #define A_MC_PCTL_TDQS 0x6320
5226 #define M_T_DQS 0x7U
5227 #define V_T_DQS(x) ((x) << S_T_DQS)
5228 #define G_T_DQS(x) (((x) >> S_T_DQS) & M_T_DQS)
5230 #define A_MC_PCTL_TCKSRE 0x6324
5233 #define M_T_CKSRE 0xfU
5234 #define V_T_CKSRE(x) ((x) << S_T_CKSRE)
5235 #define G_T_CKSRE(x) (((x) >> S_T_CKSRE) & M_T_CKSRE)
5237 #define A_MC_PCTL_TCKSRX 0x6328
5240 #define M_T_CKSRX 0xfU
5241 #define V_T_CKSRX(x) ((x) << S_T_CKSRX)
5242 #define G_T_CKSRX(x) (((x) >> S_T_CKSRX) & M_T_CKSRX)
5244 #define A_MC_PCTL_TCKE 0x632c
5247 #define M_T_CKE 0x7U
5248 #define V_T_CKE(x) ((x) << S_T_CKE)
5249 #define G_T_CKE(x) (((x) >> S_T_CKE) & M_T_CKE)
5251 #define A_MC_PCTL_TMOD 0x6330
5254 #define M_T_MOD 0xfU
5255 #define V_T_MOD(x) ((x) << S_T_MOD)
5256 #define G_T_MOD(x) (((x) >> S_T_MOD) & M_T_MOD)
5258 #define A_MC_PCTL_TRSTL 0x6334
5261 #define M_RSTHOLD 0x7fU
5262 #define V_RSTHOLD(x) ((x) << S_RSTHOLD)
5263 #define G_RSTHOLD(x) (((x) >> S_RSTHOLD) & M_RSTHOLD)
5265 #define A_MC_PCTL_TZQCL 0x6338
5268 #define M_T_ZQCL 0x3ffU
5269 #define V_T_ZQCL(x) ((x) << S_T_ZQCL)
5270 #define G_T_ZQCL(x) (((x) >> S_T_ZQCL) & M_T_ZQCL)
5272 #define A_MC_PCTL_DWLCFG0 0x6370
5274 #define S_T_ADWL_VEC 0
5275 #define M_T_ADWL_VEC 0x1ffU
5276 #define V_T_ADWL_VEC(x) ((x) << S_T_ADWL_VEC)
5277 #define G_T_ADWL_VEC(x) (((x) >> S_T_ADWL_VEC) & M_T_ADWL_VEC)
5279 #define A_MC_PCTL_DWLCFG1 0x6374
5280 #define A_MC_PCTL_DWLCFG2 0x6378
5281 #define A_MC_PCTL_DWLCFG3 0x637c
5282 #define A_MC_PCTL_ECCCFG 0x6380
5284 #define S_INLINE_SYN_EN 4
5285 #define V_INLINE_SYN_EN(x) ((x) << S_INLINE_SYN_EN)
5286 #define F_INLINE_SYN_EN V_INLINE_SYN_EN(1U)
5289 #define V_ECC_EN(x) ((x) << S_ECC_EN)
5290 #define F_ECC_EN V_ECC_EN(1U)
5292 #define S_ECC_INTR_EN 2
5293 #define V_ECC_INTR_EN(x) ((x) << S_ECC_INTR_EN)
5294 #define F_ECC_INTR_EN V_ECC_INTR_EN(1U)
5296 #define A_MC_PCTL_ECCTST 0x6384
5298 #define S_ECC_TEST_MASK 0
5299 #define M_ECC_TEST_MASK 0xffU
5300 #define V_ECC_TEST_MASK(x) ((x) << S_ECC_TEST_MASK)
5301 #define G_ECC_TEST_MASK(x) (((x) >> S_ECC_TEST_MASK) & M_ECC_TEST_MASK)
5303 #define A_MC_PCTL_ECCCLR 0x6388
5305 #define S_CLR_ECC_LOG 1
5306 #define V_CLR_ECC_LOG(x) ((x) << S_CLR_ECC_LOG)
5307 #define F_CLR_ECC_LOG V_CLR_ECC_LOG(1U)
5309 #define S_CLR_ECC_INTR 0
5310 #define V_CLR_ECC_INTR(x) ((x) << S_CLR_ECC_INTR)
5311 #define F_CLR_ECC_INTR V_CLR_ECC_INTR(1U)
5313 #define A_MC_PCTL_ECCLOG 0x638c
5314 #define A_MC_PCTL_DTUWACTL 0x6400
5316 #define S_DTU_WR_RANK 30
5317 #define M_DTU_WR_RANK 0x3U
5318 #define V_DTU_WR_RANK(x) ((x) << S_DTU_WR_RANK)
5319 #define G_DTU_WR_RANK(x) (((x) >> S_DTU_WR_RANK) & M_DTU_WR_RANK)
5321 #define S_DTU_WR_ROW 13
5322 #define M_DTU_WR_ROW 0x1ffffU
5323 #define V_DTU_WR_ROW(x) ((x) << S_DTU_WR_ROW)
5324 #define G_DTU_WR_ROW(x) (((x) >> S_DTU_WR_ROW) & M_DTU_WR_ROW)
5326 #define S_DTU_WR_BANK 10
5327 #define M_DTU_WR_BANK 0x7U
5328 #define V_DTU_WR_BANK(x) ((x) << S_DTU_WR_BANK)
5329 #define G_DTU_WR_BANK(x) (((x) >> S_DTU_WR_BANK) & M_DTU_WR_BANK)
5331 #define S_DTU_WR_COL 0
5332 #define M_DTU_WR_COL 0x3ffU
5333 #define V_DTU_WR_COL(x) ((x) << S_DTU_WR_COL)
5334 #define G_DTU_WR_COL(x) (((x) >> S_DTU_WR_COL) & M_DTU_WR_COL)
5336 #define A_MC_PCTL_DTURACTL 0x6404
5338 #define S_DTU_RD_RANK 30
5339 #define M_DTU_RD_RANK 0x3U
5340 #define V_DTU_RD_RANK(x) ((x) << S_DTU_RD_RANK)
5341 #define G_DTU_RD_RANK(x) (((x) >> S_DTU_RD_RANK) & M_DTU_RD_RANK)
5343 #define S_DTU_RD_ROW 13
5344 #define M_DTU_RD_ROW 0x1ffffU
5345 #define V_DTU_RD_ROW(x) ((x) << S_DTU_RD_ROW)
5346 #define G_DTU_RD_ROW(x) (((x) >> S_DTU_RD_ROW) & M_DTU_RD_ROW)
5348 #define S_DTU_RD_BANK 10
5349 #define M_DTU_RD_BANK 0x7U
5350 #define V_DTU_RD_BANK(x) ((x) << S_DTU_RD_BANK)
5351 #define G_DTU_RD_BANK(x) (((x) >> S_DTU_RD_BANK) & M_DTU_RD_BANK)
5353 #define S_DTU_RD_COL 0
5354 #define M_DTU_RD_COL 0x3ffU
5355 #define V_DTU_RD_COL(x) ((x) << S_DTU_RD_COL)
5356 #define G_DTU_RD_COL(x) (((x) >> S_DTU_RD_COL) & M_DTU_RD_COL)
5358 #define A_MC_PCTL_DTUCFG 0x6408
5360 #define S_DTU_ROW_INCREMENTS 16
5361 #define M_DTU_ROW_INCREMENTS 0x7fU
5362 #define V_DTU_ROW_INCREMENTS(x) ((x) << S_DTU_ROW_INCREMENTS)
5363 #define G_DTU_ROW_INCREMENTS(x) (((x) >> S_DTU_ROW_INCREMENTS) & M_DTU_ROW_INCREMENTS)
5365 #define S_DTU_WR_MULTI_RD 15
5366 #define V_DTU_WR_MULTI_RD(x) ((x) << S_DTU_WR_MULTI_RD)
5367 #define F_DTU_WR_MULTI_RD V_DTU_WR_MULTI_RD(1U)
5369 #define S_DTU_DATA_MASK_EN 14
5370 #define V_DTU_DATA_MASK_EN(x) ((x) << S_DTU_DATA_MASK_EN)
5371 #define F_DTU_DATA_MASK_EN V_DTU_DATA_MASK_EN(1U)
5373 #define S_DTU_TARGET_LANE 10
5374 #define M_DTU_TARGET_LANE 0xfU
5375 #define V_DTU_TARGET_LANE(x) ((x) << S_DTU_TARGET_LANE)
5376 #define G_DTU_TARGET_LANE(x) (((x) >> S_DTU_TARGET_LANE) & M_DTU_TARGET_LANE)
5378 #define S_DTU_GENERATE_RANDOM 9
5379 #define V_DTU_GENERATE_RANDOM(x) ((x) << S_DTU_GENERATE_RANDOM)
5380 #define F_DTU_GENERATE_RANDOM V_DTU_GENERATE_RANDOM(1U)
5382 #define S_DTU_INCR_BANKS 8
5383 #define V_DTU_INCR_BANKS(x) ((x) << S_DTU_INCR_BANKS)
5384 #define F_DTU_INCR_BANKS V_DTU_INCR_BANKS(1U)
5386 #define S_DTU_INCR_COLS 7
5387 #define V_DTU_INCR_COLS(x) ((x) << S_DTU_INCR_COLS)
5388 #define F_DTU_INCR_COLS V_DTU_INCR_COLS(1U)
5390 #define S_DTU_NALEN 1
5391 #define M_DTU_NALEN 0x3fU
5392 #define V_DTU_NALEN(x) ((x) << S_DTU_NALEN)
5393 #define G_DTU_NALEN(x) (((x) >> S_DTU_NALEN) & M_DTU_NALEN)
5395 #define S_DTU_ENABLE 0
5396 #define V_DTU_ENABLE(x) ((x) << S_DTU_ENABLE)
5397 #define F_DTU_ENABLE V_DTU_ENABLE(1U)
5399 #define A_MC_PCTL_DTUECTL 0x640c
5401 #define S_WR_MULTI_RD_RST 2
5402 #define V_WR_MULTI_RD_RST(x) ((x) << S_WR_MULTI_RD_RST)
5403 #define F_WR_MULTI_RD_RST V_WR_MULTI_RD_RST(1U)
5405 #define S_RUN_ERROR_REPORTS 1
5406 #define V_RUN_ERROR_REPORTS(x) ((x) << S_RUN_ERROR_REPORTS)
5407 #define F_RUN_ERROR_REPORTS V_RUN_ERROR_REPORTS(1U)
5410 #define V_RUN_DTU(x) ((x) << S_RUN_DTU)
5411 #define F_RUN_DTU V_RUN_DTU(1U)
5413 #define A_MC_PCTL_DTUWD0 0x6410
5415 #define S_DTU_WR_BYTE3 24
5416 #define M_DTU_WR_BYTE3 0xffU
5417 #define V_DTU_WR_BYTE3(x) ((x) << S_DTU_WR_BYTE3)
5418 #define G_DTU_WR_BYTE3(x) (((x) >> S_DTU_WR_BYTE3) & M_DTU_WR_BYTE3)
5420 #define S_DTU_WR_BYTE2 16
5421 #define M_DTU_WR_BYTE2 0xffU
5422 #define V_DTU_WR_BYTE2(x) ((x) << S_DTU_WR_BYTE2)
5423 #define G_DTU_WR_BYTE2(x) (((x) >> S_DTU_WR_BYTE2) & M_DTU_WR_BYTE2)
5425 #define S_DTU_WR_BYTE1 8
5426 #define M_DTU_WR_BYTE1 0xffU
5427 #define V_DTU_WR_BYTE1(x) ((x) << S_DTU_WR_BYTE1)
5428 #define G_DTU_WR_BYTE1(x) (((x) >> S_DTU_WR_BYTE1) & M_DTU_WR_BYTE1)
5430 #define S_DTU_WR_BYTE0 0
5431 #define M_DTU_WR_BYTE0 0xffU
5432 #define V_DTU_WR_BYTE0(x) ((x) << S_DTU_WR_BYTE0)
5433 #define G_DTU_WR_BYTE0(x) (((x) >> S_DTU_WR_BYTE0) & M_DTU_WR_BYTE0)
5435 #define A_MC_PCTL_DTUWD1 0x6414
5437 #define S_DTU_WR_BYTE7 24
5438 #define M_DTU_WR_BYTE7 0xffU
5439 #define V_DTU_WR_BYTE7(x) ((x) << S_DTU_WR_BYTE7)
5440 #define G_DTU_WR_BYTE7(x) (((x) >> S_DTU_WR_BYTE7) & M_DTU_WR_BYTE7)
5442 #define S_DTU_WR_BYTE6 16
5443 #define M_DTU_WR_BYTE6 0xffU
5444 #define V_DTU_WR_BYTE6(x) ((x) << S_DTU_WR_BYTE6)
5445 #define G_DTU_WR_BYTE6(x) (((x) >> S_DTU_WR_BYTE6) & M_DTU_WR_BYTE6)
5447 #define S_DTU_WR_BYTE5 8
5448 #define M_DTU_WR_BYTE5 0xffU
5449 #define V_DTU_WR_BYTE5(x) ((x) << S_DTU_WR_BYTE5)
5450 #define G_DTU_WR_BYTE5(x) (((x) >> S_DTU_WR_BYTE5) & M_DTU_WR_BYTE5)
5452 #define S_DTU_WR_BYTE4 0
5453 #define M_DTU_WR_BYTE4 0xffU
5454 #define V_DTU_WR_BYTE4(x) ((x) << S_DTU_WR_BYTE4)
5455 #define G_DTU_WR_BYTE4(x) (((x) >> S_DTU_WR_BYTE4) & M_DTU_WR_BYTE4)
5457 #define A_MC_PCTL_DTUWD2 0x6418
5459 #define S_DTU_WR_BYTE11 24
5460 #define M_DTU_WR_BYTE11 0xffU
5461 #define V_DTU_WR_BYTE11(x) ((x) << S_DTU_WR_BYTE11)
5462 #define G_DTU_WR_BYTE11(x) (((x) >> S_DTU_WR_BYTE11) & M_DTU_WR_BYTE11)
5464 #define S_DTU_WR_BYTE10 16
5465 #define M_DTU_WR_BYTE10 0xffU
5466 #define V_DTU_WR_BYTE10(x) ((x) << S_DTU_WR_BYTE10)
5467 #define G_DTU_WR_BYTE10(x) (((x) >> S_DTU_WR_BYTE10) & M_DTU_WR_BYTE10)
5469 #define S_DTU_WR_BYTE9 8
5470 #define M_DTU_WR_BYTE9 0xffU
5471 #define V_DTU_WR_BYTE9(x) ((x) << S_DTU_WR_BYTE9)
5472 #define G_DTU_WR_BYTE9(x) (((x) >> S_DTU_WR_BYTE9) & M_DTU_WR_BYTE9)
5474 #define S_DTU_WR_BYTE8 0
5475 #define M_DTU_WR_BYTE8 0xffU
5476 #define V_DTU_WR_BYTE8(x) ((x) << S_DTU_WR_BYTE8)
5477 #define G_DTU_WR_BYTE8(x) (((x) >> S_DTU_WR_BYTE8) & M_DTU_WR_BYTE8)
5479 #define A_MC_PCTL_DTUWD3 0x641c
5481 #define S_DTU_WR_BYTE15 24
5482 #define M_DTU_WR_BYTE15 0xffU
5483 #define V_DTU_WR_BYTE15(x) ((x) << S_DTU_WR_BYTE15)
5484 #define G_DTU_WR_BYTE15(x) (((x) >> S_DTU_WR_BYTE15) & M_DTU_WR_BYTE15)
5486 #define S_DTU_WR_BYTE14 16
5487 #define M_DTU_WR_BYTE14 0xffU
5488 #define V_DTU_WR_BYTE14(x) ((x) << S_DTU_WR_BYTE14)
5489 #define G_DTU_WR_BYTE14(x) (((x) >> S_DTU_WR_BYTE14) & M_DTU_WR_BYTE14)
5491 #define S_DTU_WR_BYTE13 8
5492 #define M_DTU_WR_BYTE13 0xffU
5493 #define V_DTU_WR_BYTE13(x) ((x) << S_DTU_WR_BYTE13)
5494 #define G_DTU_WR_BYTE13(x) (((x) >> S_DTU_WR_BYTE13) & M_DTU_WR_BYTE13)
5496 #define S_DTU_WR_BYTE12 0
5497 #define M_DTU_WR_BYTE12 0xffU
5498 #define V_DTU_WR_BYTE12(x) ((x) << S_DTU_WR_BYTE12)
5499 #define G_DTU_WR_BYTE12(x) (((x) >> S_DTU_WR_BYTE12) & M_DTU_WR_BYTE12)
5501 #define A_MC_PCTL_DTUWDM 0x6420
5503 #define S_DM_WR_BYTE0 0
5504 #define M_DM_WR_BYTE0 0xffffU
5505 #define V_DM_WR_BYTE0(x) ((x) << S_DM_WR_BYTE0)
5506 #define G_DM_WR_BYTE0(x) (((x) >> S_DM_WR_BYTE0) & M_DM_WR_BYTE0)
5508 #define A_MC_PCTL_DTURD0 0x6424
5510 #define S_DTU_RD_BYTE3 24
5511 #define M_DTU_RD_BYTE3 0xffU
5512 #define V_DTU_RD_BYTE3(x) ((x) << S_DTU_RD_BYTE3)
5513 #define G_DTU_RD_BYTE3(x) (((x) >> S_DTU_RD_BYTE3) & M_DTU_RD_BYTE3)
5515 #define S_DTU_RD_BYTE2 16
5516 #define M_DTU_RD_BYTE2 0xffU
5517 #define V_DTU_RD_BYTE2(x) ((x) << S_DTU_RD_BYTE2)
5518 #define G_DTU_RD_BYTE2(x) (((x) >> S_DTU_RD_BYTE2) & M_DTU_RD_BYTE2)
5520 #define S_DTU_RD_BYTE1 8
5521 #define M_DTU_RD_BYTE1 0xffU
5522 #define V_DTU_RD_BYTE1(x) ((x) << S_DTU_RD_BYTE1)
5523 #define G_DTU_RD_BYTE1(x) (((x) >> S_DTU_RD_BYTE1) & M_DTU_RD_BYTE1)
5525 #define S_DTU_RD_BYTE0 0
5526 #define M_DTU_RD_BYTE0 0xffU
5527 #define V_DTU_RD_BYTE0(x) ((x) << S_DTU_RD_BYTE0)
5528 #define G_DTU_RD_BYTE0(x) (((x) >> S_DTU_RD_BYTE0) & M_DTU_RD_BYTE0)
5530 #define A_MC_PCTL_DTURD1 0x6428
5532 #define S_DTU_RD_BYTE7 24
5533 #define M_DTU_RD_BYTE7 0xffU
5534 #define V_DTU_RD_BYTE7(x) ((x) << S_DTU_RD_BYTE7)
5535 #define G_DTU_RD_BYTE7(x) (((x) >> S_DTU_RD_BYTE7) & M_DTU_RD_BYTE7)
5537 #define S_DTU_RD_BYTE6 16
5538 #define M_DTU_RD_BYTE6 0xffU
5539 #define V_DTU_RD_BYTE6(x) ((x) << S_DTU_RD_BYTE6)
5540 #define G_DTU_RD_BYTE6(x) (((x) >> S_DTU_RD_BYTE6) & M_DTU_RD_BYTE6)
5542 #define S_DTU_RD_BYTE5 8
5543 #define M_DTU_RD_BYTE5 0xffU
5544 #define V_DTU_RD_BYTE5(x) ((x) << S_DTU_RD_BYTE5)
5545 #define G_DTU_RD_BYTE5(x) (((x) >> S_DTU_RD_BYTE5) & M_DTU_RD_BYTE5)
5547 #define S_DTU_RD_BYTE4 0
5548 #define M_DTU_RD_BYTE4 0xffU
5549 #define V_DTU_RD_BYTE4(x) ((x) << S_DTU_RD_BYTE4)
5550 #define G_DTU_RD_BYTE4(x) (((x) >> S_DTU_RD_BYTE4) & M_DTU_RD_BYTE4)
5552 #define A_MC_PCTL_DTURD2 0x642c
5554 #define S_DTU_RD_BYTE11 24
5555 #define M_DTU_RD_BYTE11 0xffU
5556 #define V_DTU_RD_BYTE11(x) ((x) << S_DTU_RD_BYTE11)
5557 #define G_DTU_RD_BYTE11(x) (((x) >> S_DTU_RD_BYTE11) & M_DTU_RD_BYTE11)
5559 #define S_DTU_RD_BYTE10 16
5560 #define M_DTU_RD_BYTE10 0xffU
5561 #define V_DTU_RD_BYTE10(x) ((x) << S_DTU_RD_BYTE10)
5562 #define G_DTU_RD_BYTE10(x) (((x) >> S_DTU_RD_BYTE10) & M_DTU_RD_BYTE10)
5564 #define S_DTU_RD_BYTE9 8
5565 #define M_DTU_RD_BYTE9 0xffU
5566 #define V_DTU_RD_BYTE9(x) ((x) << S_DTU_RD_BYTE9)
5567 #define G_DTU_RD_BYTE9(x) (((x) >> S_DTU_RD_BYTE9) & M_DTU_RD_BYTE9)
5569 #define S_DTU_RD_BYTE8 0
5570 #define M_DTU_RD_BYTE8 0xffU
5571 #define V_DTU_RD_BYTE8(x) ((x) << S_DTU_RD_BYTE8)
5572 #define G_DTU_RD_BYTE8(x) (((x) >> S_DTU_RD_BYTE8) & M_DTU_RD_BYTE8)
5574 #define A_MC_PCTL_DTURD3 0x6430
5576 #define S_DTU_RD_BYTE15 24
5577 #define M_DTU_RD_BYTE15 0xffU
5578 #define V_DTU_RD_BYTE15(x) ((x) << S_DTU_RD_BYTE15)
5579 #define G_DTU_RD_BYTE15(x) (((x) >> S_DTU_RD_BYTE15) & M_DTU_RD_BYTE15)
5581 #define S_DTU_RD_BYTE14 16
5582 #define M_DTU_RD_BYTE14 0xffU
5583 #define V_DTU_RD_BYTE14(x) ((x) << S_DTU_RD_BYTE14)
5584 #define G_DTU_RD_BYTE14(x) (((x) >> S_DTU_RD_BYTE14) & M_DTU_RD_BYTE14)
5586 #define S_DTU_RD_BYTE13 8
5587 #define M_DTU_RD_BYTE13 0xffU
5588 #define V_DTU_RD_BYTE13(x) ((x) << S_DTU_RD_BYTE13)
5589 #define G_DTU_RD_BYTE13(x) (((x) >> S_DTU_RD_BYTE13) & M_DTU_RD_BYTE13)
5591 #define S_DTU_RD_BYTE12 0
5592 #define M_DTU_RD_BYTE12 0xffU
5593 #define V_DTU_RD_BYTE12(x) ((x) << S_DTU_RD_BYTE12)
5594 #define G_DTU_RD_BYTE12(x) (((x) >> S_DTU_RD_BYTE12) & M_DTU_RD_BYTE12)
5596 #define A_MC_DTULFSRWD 0x6434
5597 #define A_MC_PCTL_DTULFSRRD 0x6438
5598 #define A_MC_PCTL_DTUEAF 0x643c
5600 #define S_EA_RANK 30
5601 #define M_EA_RANK 0x3U
5602 #define V_EA_RANK(x) ((x) << S_EA_RANK)
5603 #define G_EA_RANK(x) (((x) >> S_EA_RANK) & M_EA_RANK)
5606 #define M_EA_ROW 0x1ffffU
5607 #define V_EA_ROW(x) ((x) << S_EA_ROW)
5608 #define G_EA_ROW(x) (((x) >> S_EA_ROW) & M_EA_ROW)
5610 #define S_EA_BANK 10
5611 #define M_EA_BANK 0x7U
5612 #define V_EA_BANK(x) ((x) << S_EA_BANK)
5613 #define G_EA_BANK(x) (((x) >> S_EA_BANK) & M_EA_BANK)
5615 #define S_EA_COLUMN 0
5616 #define M_EA_COLUMN 0x3ffU
5617 #define V_EA_COLUMN(x) ((x) << S_EA_COLUMN)
5618 #define G_EA_COLUMN(x) (((x) >> S_EA_COLUMN) & M_EA_COLUMN)
5620 #define A_MC_PCTL_PHYPVTCFG 0x6500
5622 #define S_PVT_UPD_REQ_EN 15
5623 #define V_PVT_UPD_REQ_EN(x) ((x) << S_PVT_UPD_REQ_EN)
5624 #define F_PVT_UPD_REQ_EN V_PVT_UPD_REQ_EN(1U)
5626 #define S_PVT_UPD_TRIG_POL 14
5627 #define V_PVT_UPD_TRIG_POL(x) ((x) << S_PVT_UPD_TRIG_POL)
5628 #define F_PVT_UPD_TRIG_POL V_PVT_UPD_TRIG_POL(1U)
5630 #define S_PVT_UPD_TRIG_TYPE 12
5631 #define V_PVT_UPD_TRIG_TYPE(x) ((x) << S_PVT_UPD_TRIG_TYPE)
5632 #define F_PVT_UPD_TRIG_TYPE V_PVT_UPD_TRIG_TYPE(1U)
5634 #define S_PVT_UPD_DONE_POL 10
5635 #define V_PVT_UPD_DONE_POL(x) ((x) << S_PVT_UPD_DONE_POL)
5636 #define F_PVT_UPD_DONE_POL V_PVT_UPD_DONE_POL(1U)
5638 #define S_PVT_UPD_DONE_TYPE 8
5639 #define M_PVT_UPD_DONE_TYPE 0x3U
5640 #define V_PVT_UPD_DONE_TYPE(x) ((x) << S_PVT_UPD_DONE_TYPE)
5641 #define G_PVT_UPD_DONE_TYPE(x) (((x) >> S_PVT_UPD_DONE_TYPE) & M_PVT_UPD_DONE_TYPE)
5643 #define S_PHY_UPD_REQ_EN 7
5644 #define V_PHY_UPD_REQ_EN(x) ((x) << S_PHY_UPD_REQ_EN)
5645 #define F_PHY_UPD_REQ_EN V_PHY_UPD_REQ_EN(1U)
5647 #define S_PHY_UPD_TRIG_POL 6
5648 #define V_PHY_UPD_TRIG_POL(x) ((x) << S_PHY_UPD_TRIG_POL)
5649 #define F_PHY_UPD_TRIG_POL V_PHY_UPD_TRIG_POL(1U)
5651 #define S_PHY_UPD_TRIG_TYPE 4
5652 #define V_PHY_UPD_TRIG_TYPE(x) ((x) << S_PHY_UPD_TRIG_TYPE)
5653 #define F_PHY_UPD_TRIG_TYPE V_PHY_UPD_TRIG_TYPE(1U)
5655 #define S_PHY_UPD_DONE_POL 2
5656 #define V_PHY_UPD_DONE_POL(x) ((x) << S_PHY_UPD_DONE_POL)
5657 #define F_PHY_UPD_DONE_POL V_PHY_UPD_DONE_POL(1U)
5659 #define S_PHY_UPD_DONE_TYPE 0
5660 #define M_PHY_UPD_DONE_TYPE 0x3U
5661 #define V_PHY_UPD_DONE_TYPE(x) ((x) << S_PHY_UPD_DONE_TYPE)
5662 #define G_PHY_UPD_DONE_TYPE(x) (((x) >> S_PHY_UPD_DONE_TYPE) & M_PHY_UPD_DONE_TYPE)
5664 #define A_MC_PCTL_PHYPVTSTAT 0x6504
5666 #define S_I_PVT_UPD_TRIG 5
5667 #define V_I_PVT_UPD_TRIG(x) ((x) << S_I_PVT_UPD_TRIG)
5668 #define F_I_PVT_UPD_TRIG V_I_PVT_UPD_TRIG(1U)
5670 #define S_I_PVT_UPD_DONE 4
5671 #define V_I_PVT_UPD_DONE(x) ((x) << S_I_PVT_UPD_DONE)
5672 #define F_I_PVT_UPD_DONE V_I_PVT_UPD_DONE(1U)
5674 #define S_I_PHY_UPD_TRIG 1
5675 #define V_I_PHY_UPD_TRIG(x) ((x) << S_I_PHY_UPD_TRIG)
5676 #define F_I_PHY_UPD_TRIG V_I_PHY_UPD_TRIG(1U)
5678 #define S_I_PHY_UPD_DONE 0
5679 #define V_I_PHY_UPD_DONE(x) ((x) << S_I_PHY_UPD_DONE)
5680 #define F_I_PHY_UPD_DONE V_I_PHY_UPD_DONE(1U)
5682 #define A_MC_PCTL_PHYTUPDON 0x6508
5684 #define S_PHY_T_UPDON 0
5685 #define M_PHY_T_UPDON 0xffU
5686 #define V_PHY_T_UPDON(x) ((x) << S_PHY_T_UPDON)
5687 #define G_PHY_T_UPDON(x) (((x) >> S_PHY_T_UPDON) & M_PHY_T_UPDON)
5689 #define A_MC_PCTL_PHYTUPDDLY 0x650c
5691 #define S_PHY_T_UPDDLY 0
5692 #define M_PHY_T_UPDDLY 0xfU
5693 #define V_PHY_T_UPDDLY(x) ((x) << S_PHY_T_UPDDLY)
5694 #define G_PHY_T_UPDDLY(x) (((x) >> S_PHY_T_UPDDLY) & M_PHY_T_UPDDLY)
5696 #define A_MC_PCTL_PVTTUPON 0x6510
5698 #define S_PVT_T_UPDON 0
5699 #define M_PVT_T_UPDON 0xffU
5700 #define V_PVT_T_UPDON(x) ((x) << S_PVT_T_UPDON)
5701 #define G_PVT_T_UPDON(x) (((x) >> S_PVT_T_UPDON) & M_PVT_T_UPDON)
5703 #define A_MC_PCTL_PVTTUPDDLY 0x6514
5705 #define S_PVT_T_UPDDLY 0
5706 #define M_PVT_T_UPDDLY 0xfU
5707 #define V_PVT_T_UPDDLY(x) ((x) << S_PVT_T_UPDDLY)
5708 #define G_PVT_T_UPDDLY(x) (((x) >> S_PVT_T_UPDDLY) & M_PVT_T_UPDDLY)
5710 #define A_MC_PCTL_PHYPVTUPDI 0x6518
5712 #define S_PHYPVT_T_UPDI 0
5713 #define M_PHYPVT_T_UPDI 0xffU
5714 #define V_PHYPVT_T_UPDI(x) ((x) << S_PHYPVT_T_UPDI)
5715 #define G_PHYPVT_T_UPDI(x) (((x) >> S_PHYPVT_T_UPDI) & M_PHYPVT_T_UPDI)
5717 #define A_MC_PCTL_PHYIOCRV1 0x651c
5719 #define S_BYTE_OE_CTL 16
5720 #define M_BYTE_OE_CTL 0x3U
5721 #define V_BYTE_OE_CTL(x) ((x) << S_BYTE_OE_CTL)
5722 #define G_BYTE_OE_CTL(x) (((x) >> S_BYTE_OE_CTL) & M_BYTE_OE_CTL)
5724 #define S_DYN_SOC_ODT_ALAT 12
5725 #define M_DYN_SOC_ODT_ALAT 0xfU
5726 #define V_DYN_SOC_ODT_ALAT(x) ((x) << S_DYN_SOC_ODT_ALAT)
5727 #define G_DYN_SOC_ODT_ALAT(x) (((x) >> S_DYN_SOC_ODT_ALAT) & M_DYN_SOC_ODT_ALAT)
5729 #define S_DYN_SOC_ODT_ATEN 8
5730 #define M_DYN_SOC_ODT_ATEN 0x3U
5731 #define V_DYN_SOC_ODT_ATEN(x) ((x) << S_DYN_SOC_ODT_ATEN)
5732 #define G_DYN_SOC_ODT_ATEN(x) (((x) >> S_DYN_SOC_ODT_ATEN) & M_DYN_SOC_ODT_ATEN)
5734 #define S_DYN_SOC_ODT 2
5735 #define V_DYN_SOC_ODT(x) ((x) << S_DYN_SOC_ODT)
5736 #define F_DYN_SOC_ODT V_DYN_SOC_ODT(1U)
5738 #define S_SOC_ODT_EN 0
5739 #define V_SOC_ODT_EN(x) ((x) << S_SOC_ODT_EN)
5740 #define F_SOC_ODT_EN V_SOC_ODT_EN(1U)
5742 #define A_MC_PCTL_PHYTUPDWAIT 0x6520
5744 #define S_PHY_T_UPDWAIT 0
5745 #define M_PHY_T_UPDWAIT 0x3fU
5746 #define V_PHY_T_UPDWAIT(x) ((x) << S_PHY_T_UPDWAIT)
5747 #define G_PHY_T_UPDWAIT(x) (((x) >> S_PHY_T_UPDWAIT) & M_PHY_T_UPDWAIT)
5749 #define A_MC_PCTL_PVTTUPDWAIT 0x6524
5751 #define S_PVT_T_UPDWAIT 0
5752 #define M_PVT_T_UPDWAIT 0x3fU
5753 #define V_PVT_T_UPDWAIT(x) ((x) << S_PVT_T_UPDWAIT)
5754 #define G_PVT_T_UPDWAIT(x) (((x) >> S_PVT_T_UPDWAIT) & M_PVT_T_UPDWAIT)
5756 #define A_MC_DDR3PHYAC_GCR 0x6a00
5759 #define M_WLRANK 0x3U
5760 #define V_WLRANK(x) ((x) << S_WLRANK)
5761 #define G_WLRANK(x) (((x) >> S_WLRANK) & M_WLRANK)
5764 #define M_FDEPTH 0x3U
5765 #define V_FDEPTH(x) ((x) << S_FDEPTH)
5766 #define G_FDEPTH(x) (((x) >> S_FDEPTH) & M_FDEPTH)
5768 #define S_LPFDEPTH 4
5769 #define M_LPFDEPTH 0x3U
5770 #define V_LPFDEPTH(x) ((x) << S_LPFDEPTH)
5771 #define G_LPFDEPTH(x) (((x) >> S_LPFDEPTH) & M_LPFDEPTH)
5774 #define V_LPFEN(x) ((x) << S_LPFEN)
5775 #define F_LPFEN V_LPFEN(1U)
5778 #define V_WL(x) ((x) << S_WL)
5779 #define F_WL V_WL(1U)
5782 #define V_CAL(x) ((x) << S_CAL)
5783 #define F_CAL V_CAL(1U)
5786 #define V_MDLEN(x) ((x) << S_MDLEN)
5787 #define F_MDLEN V_MDLEN(1U)
5789 #define A_MC_DDR3PHYAC_RCR0 0x6a04
5792 #define V_OCPONR(x) ((x) << S_OCPONR)
5793 #define F_OCPONR V_OCPONR(1U)
5796 #define V_OCPOND(x) ((x) << S_OCPOND)
5797 #define F_OCPOND V_OCPOND(1U)
5800 #define V_OCOEN(x) ((x) << S_OCOEN)
5801 #define F_OCOEN V_OCOEN(1U)
5804 #define V_CKEPONR(x) ((x) << S_CKEPONR)
5805 #define F_CKEPONR V_CKEPONR(1U)
5808 #define V_CKEPOND(x) ((x) << S_CKEPOND)
5809 #define F_CKEPOND V_CKEPOND(1U)
5812 #define V_CKEOEN(x) ((x) << S_CKEOEN)
5813 #define F_CKEOEN V_CKEOEN(1U)
5816 #define V_CKPONR(x) ((x) << S_CKPONR)
5817 #define F_CKPONR V_CKPONR(1U)
5820 #define V_CKPOND(x) ((x) << S_CKPOND)
5821 #define F_CKPOND V_CKPOND(1U)
5824 #define V_CKOEN(x) ((x) << S_CKOEN)
5825 #define F_CKOEN V_CKOEN(1U)
5827 #define A_MC_DDR3PHYAC_ACCR 0x6a14
5830 #define V_ACPONR(x) ((x) << S_ACPONR)
5831 #define F_ACPONR V_ACPONR(1U)
5834 #define V_ACPOND(x) ((x) << S_ACPOND)
5835 #define F_ACPOND V_ACPOND(1U)
5838 #define V_ACOEN(x) ((x) << S_ACOEN)
5839 #define F_ACOEN V_ACOEN(1U)
5842 #define V_CK5PONR(x) ((x) << S_CK5PONR)
5843 #define F_CK5PONR V_CK5PONR(1U)
5846 #define V_CK5POND(x) ((x) << S_CK5POND)
5847 #define F_CK5POND V_CK5POND(1U)
5850 #define V_CK5OEN(x) ((x) << S_CK5OEN)
5851 #define F_CK5OEN V_CK5OEN(1U)
5854 #define V_CK4PONR(x) ((x) << S_CK4PONR)
5855 #define F_CK4PONR V_CK4PONR(1U)
5858 #define V_CK4POND(x) ((x) << S_CK4POND)
5859 #define F_CK4POND V_CK4POND(1U)
5862 #define V_CK4OEN(x) ((x) << S_CK4OEN)
5863 #define F_CK4OEN V_CK4OEN(1U)
5865 #define A_MC_DDR3PHYAC_GSR 0x6a18
5868 #define V_WLERR(x) ((x) << S_WLERR)
5869 #define F_WLERR V_WLERR(1U)
5872 #define V_INIT(x) ((x) << S_INIT)
5873 #define F_INIT V_INIT(1U)
5876 #define V_ACCAL(x) ((x) << S_ACCAL)
5877 #define F_ACCAL V_ACCAL(1U)
5879 #define A_MC_DDR3PHYAC_ECSR 0x6a1c
5882 #define V_WLDEC(x) ((x) << S_WLDEC)
5883 #define F_WLDEC V_WLDEC(1U)
5886 #define V_WLINC(x) ((x) << S_WLINC)
5887 #define F_WLINC V_WLINC(1U)
5889 #define A_MC_DDR3PHYAC_OCSR 0x6a20
5890 #define A_MC_DDR3PHYAC_MDIPR 0x6a24
5893 #define M_PRD 0x3ffU
5894 #define V_PRD(x) ((x) << S_PRD)
5895 #define G_PRD(x) (((x) >> S_PRD) & M_PRD)
5897 #define A_MC_DDR3PHYAC_MDTPR 0x6a28
5898 #define A_MC_DDR3PHYAC_MDPPR0 0x6a2c
5899 #define A_MC_DDR3PHYAC_MDPPR1 0x6a30
5900 #define A_MC_DDR3PHYAC_PMBDR0 0x6a34
5903 #define M_DFLTDLY 0x7fU
5904 #define V_DFLTDLY(x) ((x) << S_DFLTDLY)
5905 #define G_DFLTDLY(x) (((x) >> S_DFLTDLY) & M_DFLTDLY)
5907 #define A_MC_DDR3PHYAC_PMBDR1 0x6a38
5908 #define A_MC_DDR3PHYAC_ACR 0x6a60
5911 #define V_TSEL(x) ((x) << S_TSEL)
5912 #define F_TSEL V_TSEL(1U)
5916 #define V_ISEL(x) ((x) << S_ISEL)
5917 #define G_ISEL(x) (((x) >> S_ISEL) & M_ISEL)
5920 #define V_CALBYP(x) ((x) << S_CALBYP)
5921 #define F_CALBYP V_CALBYP(1U)
5923 #define S_SDRSELINV 1
5924 #define V_SDRSELINV(x) ((x) << S_SDRSELINV)
5925 #define F_SDRSELINV V_SDRSELINV(1U)
5928 #define V_CKINV(x) ((x) << S_CKINV)
5929 #define F_CKINV V_CKINV(1U)
5931 #define A_MC_DDR3PHYAC_PSCR 0x6a64
5934 #define M_PSCALE 0x3ffU
5935 #define V_PSCALE(x) ((x) << S_PSCALE)
5936 #define G_PSCALE(x) (((x) >> S_PSCALE) & M_PSCALE)
5938 #define A_MC_DDR3PHYAC_PRCR 0x6a68
5941 #define V_PHYINIT(x) ((x) << S_PHYINIT)
5942 #define F_PHYINIT V_PHYINIT(1U)
5945 #define V_PHYHRST(x) ((x) << S_PHYHRST)
5946 #define F_PHYHRST V_PHYHRST(1U)
5949 #define M_RSTCLKS 0xfU
5950 #define V_RSTCLKS(x) ((x) << S_RSTCLKS)
5951 #define G_RSTCLKS(x) (((x) >> S_RSTCLKS) & M_RSTCLKS)
5954 #define V_PLLPD(x) ((x) << S_PLLPD)
5955 #define F_PLLPD V_PLLPD(1U)
5958 #define V_PLLRST(x) ((x) << S_PLLRST)
5959 #define F_PLLRST V_PLLRST(1U)
5962 #define V_PHYRST(x) ((x) << S_PHYRST)
5963 #define F_PHYRST V_PHYRST(1U)
5965 #define A_MC_DDR3PHYAC_PLLCR0 0x6a6c
5968 #define M_RSTCXKS 0x1fU
5969 #define V_RSTCXKS(x) ((x) << S_RSTCXKS)
5970 #define G_RSTCXKS(x) (((x) >> S_RSTCXKS) & M_RSTCXKS)
5973 #define V_ICPSEL(x) ((x) << S_ICPSEL)
5974 #define F_ICPSEL V_ICPSEL(1U)
5977 #define M_TESTA 0x7U
5978 #define V_TESTA(x) ((x) << S_TESTA)
5979 #define G_TESTA(x) (((x) >> S_TESTA) & M_TESTA)
5981 #define A_MC_DDR3PHYAC_PLLCR1 0x6a70
5984 #define V_BYPASS(x) ((x) << S_BYPASS)
5985 #define F_BYPASS V_BYPASS(1U)
5989 #define V_BDIV(x) ((x) << S_BDIV)
5990 #define G_BDIV(x) (((x) >> S_BDIV) & M_BDIV)
5993 #define M_TESTD 0x7U
5994 #define V_TESTD(x) ((x) << S_TESTD)
5995 #define G_TESTD(x) (((x) >> S_TESTD) & M_TESTD)
5997 #define A_MC_DDR3PHYAC_CLKENR 0x6a78
6000 #define M_CKCLKEN 0x3fU
6001 #define V_CKCLKEN(x) ((x) << S_CKCLKEN)
6002 #define G_CKCLKEN(x) (((x) >> S_CKCLKEN) & M_CKCLKEN)
6004 #define S_HDRCLKEN 2
6005 #define V_HDRCLKEN(x) ((x) << S_HDRCLKEN)
6006 #define F_HDRCLKEN V_HDRCLKEN(1U)
6008 #define S_SDRCLKEN 1
6009 #define V_SDRCLKEN(x) ((x) << S_SDRCLKEN)
6010 #define F_SDRCLKEN V_SDRCLKEN(1U)
6012 #define S_DDRCLKEN 0
6013 #define V_DDRCLKEN(x) ((x) << S_DDRCLKEN)
6014 #define F_DDRCLKEN V_DDRCLKEN(1U)
6016 #define A_MC_DDR3PHYDATX8_GCR 0x6b00
6019 #define V_PONR(x) ((x) << S_PONR)
6020 #define F_PONR V_PONR(1U)
6023 #define V_POND(x) ((x) << S_POND)
6024 #define F_POND V_POND(1U)
6027 #define V_RDBDVT(x) ((x) << S_RDBDVT)
6028 #define F_RDBDVT V_RDBDVT(1U)
6031 #define V_WDBDVT(x) ((x) << S_WDBDVT)
6032 #define F_WDBDVT V_WDBDVT(1U)
6035 #define V_RDSDVT(x) ((x) << S_RDSDVT)
6036 #define F_RDSDVT V_RDSDVT(1U)
6039 #define V_WDSDVT(x) ((x) << S_WDSDVT)
6040 #define F_WDSDVT V_WDSDVT(1U)
6043 #define V_WLSDVT(x) ((x) << S_WLSDVT)
6044 #define F_WLSDVT V_WLSDVT(1U)
6046 #define A_MC_DDR3PHYDATX8_WDSDR 0x6b04
6048 #define S_WDSDR_DLY 0
6049 #define M_WDSDR_DLY 0x3ffU
6050 #define V_WDSDR_DLY(x) ((x) << S_WDSDR_DLY)
6051 #define G_WDSDR_DLY(x) (((x) >> S_WDSDR_DLY) & M_WDSDR_DLY)
6053 #define A_MC_DDR3PHYDATX8_WLDPR 0x6b08
6054 #define A_MC_DDR3PHYDATX8_WLDR 0x6b0c
6057 #define M_WL_DLY 0x3ffU
6058 #define V_WL_DLY(x) ((x) << S_WL_DLY)
6059 #define G_WL_DLY(x) (((x) >> S_WL_DLY) & M_WL_DLY)
6061 #define A_MC_DDR3PHYDATX8_WDBDR0 0x6b1c
6065 #define V_DLY(x) ((x) << S_DLY)
6066 #define G_DLY(x) (((x) >> S_DLY) & M_DLY)
6068 #define A_MC_DDR3PHYDATX8_WDBDR1 0x6b20
6069 #define A_MC_DDR3PHYDATX8_WDBDR2 0x6b24
6070 #define A_MC_DDR3PHYDATX8_WDBDR3 0x6b28
6071 #define A_MC_DDR3PHYDATX8_WDBDR4 0x6b2c
6072 #define A_MC_DDR3PHYDATX8_WDBDR5 0x6b30
6073 #define A_MC_DDR3PHYDATX8_WDBDR6 0x6b34
6074 #define A_MC_DDR3PHYDATX8_WDBDR7 0x6b38
6075 #define A_MC_DDR3PHYDATX8_WDBDR8 0x6b3c
6076 #define A_MC_DDR3PHYDATX8_WDBDMR 0x6b40
6079 #define M_MAXDLY 0x7fU
6080 #define V_MAXDLY(x) ((x) << S_MAXDLY)
6081 #define G_MAXDLY(x) (((x) >> S_MAXDLY) & M_MAXDLY)
6083 #define A_MC_DDR3PHYDATX8_RDSDR 0x6b44
6085 #define S_RDSDR_DLY 0
6086 #define M_RDSDR_DLY 0x3ffU
6087 #define V_RDSDR_DLY(x) ((x) << S_RDSDR_DLY)
6088 #define G_RDSDR_DLY(x) (((x) >> S_RDSDR_DLY) & M_RDSDR_DLY)
6090 #define A_MC_DDR3PHYDATX8_RDBDR0 0x6b48
6091 #define A_MC_DDR3PHYDATX8_RDBDR1 0x6b4c
6092 #define A_MC_DDR3PHYDATX8_RDBDR2 0x6b50
6093 #define A_MC_DDR3PHYDATX8_RDBDR3 0x6b54
6094 #define A_MC_DDR3PHYDATX8_RDBDR4 0x6b58
6095 #define A_MC_DDR3PHYDATX8_RDBDR5 0x6b5c
6096 #define A_MC_DDR3PHYDATX8_RDBDR6 0x6b60
6097 #define A_MC_DDR3PHYDATX8_RDBDR7 0x6b64
6098 #define A_MC_DDR3PHYDATX8_RDBDMR 0x6b68
6099 #define A_MC_DDR3PHYDATX8_PMBDR0 0x6b6c
6100 #define A_MC_DDR3PHYDATX8_PMBDR1 0x6b70
6101 #define A_MC_DDR3PHYDATX8_PMBDR2 0x6b74
6102 #define A_MC_DDR3PHYDATX8_PMBDR3 0x6b78
6103 #define A_MC_DDR3PHYDATX8_WDBDPR 0x6b7c
6106 #define M_DP_DLY 0x1ffU
6107 #define V_DP_DLY(x) ((x) << S_DP_DLY)
6108 #define G_DP_DLY(x) (((x) >> S_DP_DLY) & M_DP_DLY)
6110 #define A_MC_DDR3PHYDATX8_RDBDPR 0x6b80
6111 #define A_MC_DDR3PHYDATX8_GSR 0x6b84
6114 #define V_WLDONE(x) ((x) << S_WLDONE)
6115 #define F_WLDONE V_WLDONE(1U)
6118 #define V_WLCAL(x) ((x) << S_WLCAL)
6119 #define F_WLCAL V_WLCAL(1U)
6122 #define V_READ(x) ((x) << S_READ)
6123 #define F_READ V_READ(1U)
6126 #define V_RDQSCAL(x) ((x) << S_RDQSCAL)
6127 #define F_RDQSCAL V_RDQSCAL(1U)
6129 #define A_MC_DDR3PHYDATX8_ACR 0x6bf0
6131 #define S_PHYHSRST 9
6132 #define V_PHYHSRST(x) ((x) << S_PHYHSRST)
6133 #define F_PHYHSRST V_PHYHSRST(1U)
6136 #define V_WLSTEP(x) ((x) << S_WLSTEP)
6137 #define F_WLSTEP V_WLSTEP(1U)
6139 #define S_SDR_SEL_INV 2
6140 #define V_SDR_SEL_INV(x) ((x) << S_SDR_SEL_INV)
6141 #define F_SDR_SEL_INV V_SDR_SEL_INV(1U)
6143 #define S_DDRSELINV 1
6144 #define V_DDRSELINV(x) ((x) << S_DDRSELINV)
6145 #define F_DDRSELINV V_DDRSELINV(1U)
6148 #define V_DSINV(x) ((x) << S_DSINV)
6149 #define F_DSINV V_DSINV(1U)
6151 #define A_MC_DDR3PHYDATX8_RSR 0x6bf4
6153 #define S_WLRANKSEL 9
6154 #define V_WLRANKSEL(x) ((x) << S_WLRANKSEL)
6155 #define F_WLRANKSEL V_WLRANKSEL(1U)
6159 #define V_RANK(x) ((x) << S_RANK)
6160 #define G_RANK(x) (((x) >> S_RANK) & M_RANK)
6162 #define A_MC_DDR3PHYDATX8_CLKENR 0x6bf8
6165 #define M_DTOSEL 0x3U
6166 #define V_DTOSEL(x) ((x) << S_DTOSEL)
6167 #define G_DTOSEL(x) (((x) >> S_DTOSEL) & M_DTOSEL)
6169 #define A_MC_PVT_REG_CALIBRATE_CTL 0x7400
6170 #define A_MC_PVT_REG_UPDATE_CTL 0x7404
6171 #define A_MC_PVT_REG_LAST_MEASUREMENT 0x7408
6172 #define A_MC_PVT_REG_DRVN 0x740c
6173 #define A_MC_PVT_REG_DRVP 0x7410
6174 #define A_MC_PVT_REG_TERMN 0x7414
6175 #define A_MC_PVT_REG_TERMP 0x7418
6176 #define A_MC_PVT_REG_THRESHOLD 0x741c
6177 #define A_MC_PVT_REG_IN_TERMP 0x7420
6178 #define A_MC_PVT_REG_IN_TERMN 0x7424
6179 #define A_MC_PVT_REG_IN_DRVP 0x7428
6180 #define A_MC_PVT_REG_IN_DRVN 0x742c
6181 #define A_MC_PVT_REG_OUT_TERMP 0x7430
6182 #define A_MC_PVT_REG_OUT_TERMN 0x7434
6183 #define A_MC_PVT_REG_OUT_DRVP 0x7438
6184 #define A_MC_PVT_REG_OUT_DRVN 0x743c
6185 #define A_MC_PVT_REG_HISTORY_TERMP 0x7440
6186 #define A_MC_PVT_REG_HISTORY_TERMN 0x7444
6187 #define A_MC_PVT_REG_HISTORY_DRVP 0x7448
6188 #define A_MC_PVT_REG_HISTORY_DRVN 0x744c
6189 #define A_MC_PVT_REG_SAMPLE_WAIT_CLKS 0x7450
6190 #define A_MC_DDRPHY_RST_CTRL 0x7500
6192 #define S_DDRIO_ENABLE 1
6193 #define V_DDRIO_ENABLE(x) ((x) << S_DDRIO_ENABLE)
6194 #define F_DDRIO_ENABLE V_DDRIO_ENABLE(1U)
6196 #define S_PHY_RST_N 0
6197 #define V_PHY_RST_N(x) ((x) << S_PHY_RST_N)
6198 #define F_PHY_RST_N V_PHY_RST_N(1U)
6200 #define A_MC_PERFORMANCE_CTRL 0x7504
6202 #define S_STALL_CHK_BIT 2
6203 #define V_STALL_CHK_BIT(x) ((x) << S_STALL_CHK_BIT)
6204 #define F_STALL_CHK_BIT V_STALL_CHK_BIT(1U)
6206 #define S_DDR3_BRC_MODE 1
6207 #define V_DDR3_BRC_MODE(x) ((x) << S_DDR3_BRC_MODE)
6208 #define F_DDR3_BRC_MODE V_DDR3_BRC_MODE(1U)
6210 #define S_RMW_PERF_CTRL 0
6211 #define V_RMW_PERF_CTRL(x) ((x) << S_RMW_PERF_CTRL)
6212 #define F_RMW_PERF_CTRL V_RMW_PERF_CTRL(1U)
6214 #define A_MC_ECC_CTRL 0x7508
6216 #define S_ECC_BYPASS_BIST 1
6217 #define V_ECC_BYPASS_BIST(x) ((x) << S_ECC_BYPASS_BIST)
6218 #define F_ECC_BYPASS_BIST V_ECC_BYPASS_BIST(1U)
6220 #define S_ECC_DISABLE 0
6221 #define V_ECC_DISABLE(x) ((x) << S_ECC_DISABLE)
6222 #define F_ECC_DISABLE V_ECC_DISABLE(1U)
6224 #define A_MC_PAR_ENABLE 0x750c
6226 #define S_ECC_UE_PAR_ENABLE 3
6227 #define V_ECC_UE_PAR_ENABLE(x) ((x) << S_ECC_UE_PAR_ENABLE)
6228 #define F_ECC_UE_PAR_ENABLE V_ECC_UE_PAR_ENABLE(1U)
6230 #define S_ECC_CE_PAR_ENABLE 2
6231 #define V_ECC_CE_PAR_ENABLE(x) ((x) << S_ECC_CE_PAR_ENABLE)
6232 #define F_ECC_CE_PAR_ENABLE V_ECC_CE_PAR_ENABLE(1U)
6234 #define S_PERR_REG_INT_ENABLE 1
6235 #define V_PERR_REG_INT_ENABLE(x) ((x) << S_PERR_REG_INT_ENABLE)
6236 #define F_PERR_REG_INT_ENABLE V_PERR_REG_INT_ENABLE(1U)
6238 #define S_PERR_BLK_INT_ENABLE 0
6239 #define V_PERR_BLK_INT_ENABLE(x) ((x) << S_PERR_BLK_INT_ENABLE)
6240 #define F_PERR_BLK_INT_ENABLE V_PERR_BLK_INT_ENABLE(1U)
6242 #define A_MC_PAR_CAUSE 0x7510
6244 #define S_ECC_UE_PAR_CAUSE 3
6245 #define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE)
6246 #define F_ECC_UE_PAR_CAUSE V_ECC_UE_PAR_CAUSE(1U)
6248 #define S_ECC_CE_PAR_CAUSE 2
6249 #define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE)
6250 #define F_ECC_CE_PAR_CAUSE V_ECC_CE_PAR_CAUSE(1U)
6252 #define S_FIFOR_PAR_CAUSE 1
6253 #define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE)
6254 #define F_FIFOR_PAR_CAUSE V_FIFOR_PAR_CAUSE(1U)
6256 #define S_RDATA_FIFOR_PAR_CAUSE 0
6257 #define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE)
6258 #define F_RDATA_FIFOR_PAR_CAUSE V_RDATA_FIFOR_PAR_CAUSE(1U)
6260 #define A_MC_INT_ENABLE 0x7514
6262 #define S_ECC_UE_INT_ENABLE 2
6263 #define V_ECC_UE_INT_ENABLE(x) ((x) << S_ECC_UE_INT_ENABLE)
6264 #define F_ECC_UE_INT_ENABLE V_ECC_UE_INT_ENABLE(1U)
6266 #define S_ECC_CE_INT_ENABLE 1
6267 #define V_ECC_CE_INT_ENABLE(x) ((x) << S_ECC_CE_INT_ENABLE)
6268 #define F_ECC_CE_INT_ENABLE V_ECC_CE_INT_ENABLE(1U)
6270 #define S_PERR_INT_ENABLE 0
6271 #define V_PERR_INT_ENABLE(x) ((x) << S_PERR_INT_ENABLE)
6272 #define F_PERR_INT_ENABLE V_PERR_INT_ENABLE(1U)
6274 #define A_MC_INT_CAUSE 0x7518
6276 #define S_ECC_UE_INT_CAUSE 2
6277 #define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE)
6278 #define F_ECC_UE_INT_CAUSE V_ECC_UE_INT_CAUSE(1U)
6280 #define S_ECC_CE_INT_CAUSE 1
6281 #define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE)
6282 #define F_ECC_CE_INT_CAUSE V_ECC_CE_INT_CAUSE(1U)
6284 #define S_PERR_INT_CAUSE 0
6285 #define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE)
6286 #define F_PERR_INT_CAUSE V_PERR_INT_CAUSE(1U)
6288 #define A_MC_ECC_STATUS 0x751c
6290 #define S_ECC_CECNT 16
6291 #define M_ECC_CECNT 0xffffU
6292 #define V_ECC_CECNT(x) ((x) << S_ECC_CECNT)
6293 #define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT)
6295 #define S_ECC_UECNT 0
6296 #define M_ECC_UECNT 0xffffU
6297 #define V_ECC_UECNT(x) ((x) << S_ECC_UECNT)
6298 #define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT)
6300 #define A_MC_PHY_CTRL 0x7520
6302 #define S_CTLPHYRR 0
6303 #define V_CTLPHYRR(x) ((x) << S_CTLPHYRR)
6304 #define F_CTLPHYRR V_CTLPHYRR(1U)
6306 #define A_MC_STATIC_CFG_STATUS 0x7524
6308 #define S_STATIC_MODE 9
6309 #define V_STATIC_MODE(x) ((x) << S_STATIC_MODE)
6310 #define F_STATIC_MODE V_STATIC_MODE(1U)
6312 #define S_STATIC_DEN 6
6313 #define M_STATIC_DEN 0x7U
6314 #define V_STATIC_DEN(x) ((x) << S_STATIC_DEN)
6315 #define G_STATIC_DEN(x) (((x) >> S_STATIC_DEN) & M_STATIC_DEN)
6317 #define S_STATIC_ORG 5
6318 #define V_STATIC_ORG(x) ((x) << S_STATIC_ORG)
6319 #define F_STATIC_ORG V_STATIC_ORG(1U)
6321 #define S_STATIC_RKS 4
6322 #define V_STATIC_RKS(x) ((x) << S_STATIC_RKS)
6323 #define F_STATIC_RKS V_STATIC_RKS(1U)
6325 #define S_STATIC_WIDTH 1
6326 #define M_STATIC_WIDTH 0x7U
6327 #define V_STATIC_WIDTH(x) ((x) << S_STATIC_WIDTH)
6328 #define G_STATIC_WIDTH(x) (((x) >> S_STATIC_WIDTH) & M_STATIC_WIDTH)
6330 #define S_STATIC_SLOW 0
6331 #define V_STATIC_SLOW(x) ((x) << S_STATIC_SLOW)
6332 #define F_STATIC_SLOW V_STATIC_SLOW(1U)
6334 #define A_MC_CORE_PCTL_STAT 0x7528
6336 #define S_PCTL_ACCESS_STAT 0
6337 #define M_PCTL_ACCESS_STAT 0x7U
6338 #define V_PCTL_ACCESS_STAT(x) ((x) << S_PCTL_ACCESS_STAT)
6339 #define G_PCTL_ACCESS_STAT(x) (((x) >> S_PCTL_ACCESS_STAT) & M_PCTL_ACCESS_STAT)
6341 #define A_MC_DEBUG_CNT 0x752c
6343 #define S_WDATA_OCNT 8
6344 #define M_WDATA_OCNT 0x1fU
6345 #define V_WDATA_OCNT(x) ((x) << S_WDATA_OCNT)
6346 #define G_WDATA_OCNT(x) (((x) >> S_WDATA_OCNT) & M_WDATA_OCNT)
6348 #define S_RDATA_OCNT 0
6349 #define M_RDATA_OCNT 0x1fU
6350 #define V_RDATA_OCNT(x) ((x) << S_RDATA_OCNT)
6351 #define G_RDATA_OCNT(x) (((x) >> S_RDATA_OCNT) & M_RDATA_OCNT)
6353 #define A_MC_BONUS 0x7530
6354 #define A_MC_BIST_CMD 0x7600
6356 #define S_START_BIST 31
6357 #define V_START_BIST(x) ((x) << S_START_BIST)
6358 #define F_START_BIST V_START_BIST(1U)
6360 #define S_BIST_CMD_GAP 8
6361 #define M_BIST_CMD_GAP 0xffU
6362 #define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP)
6363 #define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP)
6365 #define S_BIST_OPCODE 0
6366 #define M_BIST_OPCODE 0x3U
6367 #define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE)
6368 #define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE)
6370 #define A_MC_BIST_CMD_ADDR 0x7604
6371 #define A_MC_BIST_CMD_LEN 0x7608
6372 #define A_MC_BIST_DATA_PATTERN 0x760c
6374 #define S_BIST_DATA_TYPE 0
6375 #define M_BIST_DATA_TYPE 0xfU
6376 #define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE)
6377 #define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE)
6379 #define A_MC_BIST_USER_WDATA0 0x7614
6380 #define A_MC_BIST_USER_WDATA1 0x7618
6381 #define A_MC_BIST_USER_WDATA2 0x761c
6383 #define S_USER_DATA2 0
6384 #define M_USER_DATA2 0xffU
6385 #define V_USER_DATA2(x) ((x) << S_USER_DATA2)
6386 #define G_USER_DATA2(x) (((x) >> S_USER_DATA2) & M_USER_DATA2)
6388 #define A_MC_BIST_NUM_ERR 0x7680
6389 #define A_MC_BIST_ERR_FIRST_ADDR 0x7684
6390 #define A_MC_BIST_STATUS_RDATA 0x7688
6392 /* registers for module MA */
6393 #define MA_BASE_ADDR 0x7700
6395 #define A_MA_CLIENT0_RD_LATENCY_THRESHOLD 0x7700
6397 #define S_THRESHOLD1 17
6398 #define M_THRESHOLD1 0x7fffU
6399 #define V_THRESHOLD1(x) ((x) << S_THRESHOLD1)
6400 #define G_THRESHOLD1(x) (((x) >> S_THRESHOLD1) & M_THRESHOLD1)
6402 #define S_THRESHOLD1_EN 16
6403 #define V_THRESHOLD1_EN(x) ((x) << S_THRESHOLD1_EN)
6404 #define F_THRESHOLD1_EN V_THRESHOLD1_EN(1U)
6406 #define S_THRESHOLD0 1
6407 #define M_THRESHOLD0 0x7fffU
6408 #define V_THRESHOLD0(x) ((x) << S_THRESHOLD0)
6409 #define G_THRESHOLD0(x) (((x) >> S_THRESHOLD0) & M_THRESHOLD0)
6411 #define S_THRESHOLD0_EN 0
6412 #define V_THRESHOLD0_EN(x) ((x) << S_THRESHOLD0_EN)
6413 #define F_THRESHOLD0_EN V_THRESHOLD0_EN(1U)
6415 #define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704
6416 #define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708
6417 #define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c
6418 #define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710
6419 #define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714
6420 #define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718
6421 #define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c
6422 #define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720
6423 #define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724
6424 #define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728
6425 #define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c
6426 #define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730
6427 #define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734
6428 #define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738
6429 #define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c
6430 #define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740
6431 #define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744
6432 #define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748
6433 #define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c
6434 #define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750
6435 #define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754
6436 #define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758
6437 #define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c
6438 #define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760
6439 #define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764
6440 #define A_MA_SGE_TH0_DEBUG_CNT 0x7768
6442 #define S_DBG_READ_DATA_CNT 24
6443 #define M_DBG_READ_DATA_CNT 0xffU
6444 #define V_DBG_READ_DATA_CNT(x) ((x) << S_DBG_READ_DATA_CNT)
6445 #define G_DBG_READ_DATA_CNT(x) (((x) >> S_DBG_READ_DATA_CNT) & M_DBG_READ_DATA_CNT)
6447 #define S_DBG_READ_REQ_CNT 16
6448 #define M_DBG_READ_REQ_CNT 0xffU
6449 #define V_DBG_READ_REQ_CNT(x) ((x) << S_DBG_READ_REQ_CNT)
6450 #define G_DBG_READ_REQ_CNT(x) (((x) >> S_DBG_READ_REQ_CNT) & M_DBG_READ_REQ_CNT)
6452 #define S_DBG_WRITE_DATA_CNT 8
6453 #define M_DBG_WRITE_DATA_CNT 0xffU
6454 #define V_DBG_WRITE_DATA_CNT(x) ((x) << S_DBG_WRITE_DATA_CNT)
6455 #define G_DBG_WRITE_DATA_CNT(x) (((x) >> S_DBG_WRITE_DATA_CNT) & M_DBG_WRITE_DATA_CNT)
6457 #define S_DBG_WRITE_REQ_CNT 0
6458 #define M_DBG_WRITE_REQ_CNT 0xffU
6459 #define V_DBG_WRITE_REQ_CNT(x) ((x) << S_DBG_WRITE_REQ_CNT)
6460 #define G_DBG_WRITE_REQ_CNT(x) (((x) >> S_DBG_WRITE_REQ_CNT) & M_DBG_WRITE_REQ_CNT)
6462 #define A_MA_SGE_TH1_DEBUG_CNT 0x776c
6463 #define A_MA_ULPTX_DEBUG_CNT 0x7770
6464 #define A_MA_ULPRX_DEBUG_CNT 0x7774
6465 #define A_MA_ULPTXRX_DEBUG_CNT 0x7778
6466 #define A_MA_TP_TH0_DEBUG_CNT 0x777c
6467 #define A_MA_TP_TH1_DEBUG_CNT 0x7780
6468 #define A_MA_LE_DEBUG_CNT 0x7784
6469 #define A_MA_CIM_DEBUG_CNT 0x7788
6470 #define A_MA_PCIE_DEBUG_CNT 0x778c
6471 #define A_MA_PMTX_DEBUG_CNT 0x7790
6472 #define A_MA_PMRX_DEBUG_CNT 0x7794
6473 #define A_MA_HMA_DEBUG_CNT 0x7798
6474 #define A_MA_EDRAM0_BAR 0x77c0
6476 #define S_EDRAM0_BASE 16
6477 #define M_EDRAM0_BASE 0xfffU
6478 #define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE)
6479 #define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE)
6481 #define S_EDRAM0_SIZE 0
6482 #define M_EDRAM0_SIZE 0xfffU
6483 #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
6484 #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
6486 #define A_MA_EDRAM1_BAR 0x77c4
6488 #define S_EDRAM1_BASE 16
6489 #define M_EDRAM1_BASE 0xfffU
6490 #define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE)
6491 #define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE)
6493 #define S_EDRAM1_SIZE 0
6494 #define M_EDRAM1_SIZE 0xfffU
6495 #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
6496 #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)
6498 #define A_MA_EXT_MEMORY_BAR 0x77c8
6500 #define S_EXT_MEM_BASE 16
6501 #define M_EXT_MEM_BASE 0xfffU
6502 #define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE)
6503 #define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE)
6505 #define S_EXT_MEM_SIZE 0
6506 #define M_EXT_MEM_SIZE 0xfffU
6507 #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
6508 #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)
6510 #define A_MA_HOST_MEMORY_BAR 0x77cc
6512 #define S_HMA_BASE 16
6513 #define M_HMA_BASE 0xfffU
6514 #define V_HMA_BASE(x) ((x) << S_HMA_BASE)
6515 #define G_HMA_BASE(x) (((x) >> S_HMA_BASE) & M_HMA_BASE)
6517 #define S_HMA_SIZE 0
6518 #define M_HMA_SIZE 0xfffU
6519 #define V_HMA_SIZE(x) ((x) << S_HMA_SIZE)
6520 #define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE)
6522 #define A_MA_EXT_MEM_PAGE_SIZE 0x77d0
6524 #define S_BRC_MODE 2
6525 #define V_BRC_MODE(x) ((x) << S_BRC_MODE)
6526 #define F_BRC_MODE V_BRC_MODE(1U)
6528 #define S_EXT_MEM_PAGE_SIZE 0
6529 #define M_EXT_MEM_PAGE_SIZE 0x3U
6530 #define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE)
6531 #define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE)
6533 #define A_MA_ARB_CTRL 0x77d4
6535 #define S_DIS_PAGE_HINT 1
6536 #define V_DIS_PAGE_HINT(x) ((x) << S_DIS_PAGE_HINT)
6537 #define F_DIS_PAGE_HINT V_DIS_PAGE_HINT(1U)
6539 #define S_DIS_ADV_ARB 0
6540 #define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB)
6541 #define F_DIS_ADV_ARB V_DIS_ADV_ARB(1U)
6543 #define A_MA_TARGET_MEM_ENABLE 0x77d8
6545 #define S_HMA_ENABLE 3
6546 #define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE)
6547 #define F_HMA_ENABLE V_HMA_ENABLE(1U)
6549 #define S_EXT_MEM_ENABLE 2
6550 #define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE)
6551 #define F_EXT_MEM_ENABLE V_EXT_MEM_ENABLE(1U)
6553 #define S_EDRAM1_ENABLE 1
6554 #define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE)
6555 #define F_EDRAM1_ENABLE V_EDRAM1_ENABLE(1U)
6557 #define S_EDRAM0_ENABLE 0
6558 #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
6559 #define F_EDRAM0_ENABLE V_EDRAM0_ENABLE(1U)
6561 #define A_MA_INT_ENABLE 0x77dc
6563 #define S_MEM_PERR_INT_ENABLE 1
6564 #define V_MEM_PERR_INT_ENABLE(x) ((x) << S_MEM_PERR_INT_ENABLE)
6565 #define F_MEM_PERR_INT_ENABLE V_MEM_PERR_INT_ENABLE(1U)
6567 #define S_MEM_WRAP_INT_ENABLE 0
6568 #define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE)
6569 #define F_MEM_WRAP_INT_ENABLE V_MEM_WRAP_INT_ENABLE(1U)
6571 #define A_MA_INT_CAUSE 0x77e0
6573 #define S_MEM_PERR_INT_CAUSE 1
6574 #define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE)
6575 #define F_MEM_PERR_INT_CAUSE V_MEM_PERR_INT_CAUSE(1U)
6577 #define S_MEM_WRAP_INT_CAUSE 0
6578 #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
6579 #define F_MEM_WRAP_INT_CAUSE V_MEM_WRAP_INT_CAUSE(1U)
6581 #define A_MA_INT_WRAP_STATUS 0x77e4
6583 #define S_MEM_WRAP_ADDRESS 4
6584 #define M_MEM_WRAP_ADDRESS 0xfffffffU
6585 #define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS)
6586 #define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS)
6588 #define S_MEM_WRAP_CLIENT_NUM 0
6589 #define M_MEM_WRAP_CLIENT_NUM 0xfU
6590 #define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM)
6591 #define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)
6593 #define A_MA_TP_THREAD1_MAPPER 0x77e8
6595 #define S_TP_THREAD1_EN 0
6596 #define M_TP_THREAD1_EN 0xffU
6597 #define V_TP_THREAD1_EN(x) ((x) << S_TP_THREAD1_EN)
6598 #define G_TP_THREAD1_EN(x) (((x) >> S_TP_THREAD1_EN) & M_TP_THREAD1_EN)
6600 #define A_MA_SGE_THREAD1_MAPPER 0x77ec
6602 #define S_SGE_THREAD1_EN 0
6603 #define M_SGE_THREAD1_EN 0xffU
6604 #define V_SGE_THREAD1_EN(x) ((x) << S_SGE_THREAD1_EN)
6605 #define G_SGE_THREAD1_EN(x) (((x) >> S_SGE_THREAD1_EN) & M_SGE_THREAD1_EN)
6607 #define A_MA_PARITY_ERROR_ENABLE 0x77f0
6609 #define S_TP_DMARBT_PAR_ERROR_EN 31
6610 #define V_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_TP_DMARBT_PAR_ERROR_EN)
6611 #define F_TP_DMARBT_PAR_ERROR_EN V_TP_DMARBT_PAR_ERROR_EN(1U)
6613 #define S_LOGIC_FIFO_PAR_ERROR_EN 30
6614 #define V_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_LOGIC_FIFO_PAR_ERROR_EN)
6615 #define F_LOGIC_FIFO_PAR_ERROR_EN V_LOGIC_FIFO_PAR_ERROR_EN(1U)
6617 #define S_ARB3_PAR_WRQUEUE_ERROR_EN 29
6618 #define V_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR_EN)
6619 #define F_ARB3_PAR_WRQUEUE_ERROR_EN V_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
6621 #define S_ARB2_PAR_WRQUEUE_ERROR_EN 28
6622 #define V_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR_EN)
6623 #define F_ARB2_PAR_WRQUEUE_ERROR_EN V_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
6625 #define S_ARB1_PAR_WRQUEUE_ERROR_EN 27
6626 #define V_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR_EN)
6627 #define F_ARB1_PAR_WRQUEUE_ERROR_EN V_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
6629 #define S_ARB0_PAR_WRQUEUE_ERROR_EN 26
6630 #define V_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR_EN)
6631 #define F_ARB0_PAR_WRQUEUE_ERROR_EN V_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
6633 #define S_ARB3_PAR_RDQUEUE_ERROR_EN 25
6634 #define V_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR_EN)
6635 #define F_ARB3_PAR_RDQUEUE_ERROR_EN V_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
6637 #define S_ARB2_PAR_RDQUEUE_ERROR_EN 24
6638 #define V_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR_EN)
6639 #define F_ARB2_PAR_RDQUEUE_ERROR_EN V_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
6641 #define S_ARB1_PAR_RDQUEUE_ERROR_EN 23
6642 #define V_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR_EN)
6643 #define F_ARB1_PAR_RDQUEUE_ERROR_EN V_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
6645 #define S_ARB0_PAR_RDQUEUE_ERROR_EN 22
6646 #define V_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR_EN)
6647 #define F_ARB0_PAR_RDQUEUE_ERROR_EN V_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
6649 #define S_CL10_PAR_WRQUEUE_ERROR_EN 21
6650 #define V_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR_EN)
6651 #define F_CL10_PAR_WRQUEUE_ERROR_EN V_CL10_PAR_WRQUEUE_ERROR_EN(1U)
6653 #define S_CL9_PAR_WRQUEUE_ERROR_EN 20
6654 #define V_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR_EN)
6655 #define F_CL9_PAR_WRQUEUE_ERROR_EN V_CL9_PAR_WRQUEUE_ERROR_EN(1U)
6657 #define S_CL8_PAR_WRQUEUE_ERROR_EN 19
6658 #define V_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR_EN)
6659 #define F_CL8_PAR_WRQUEUE_ERROR_EN V_CL8_PAR_WRQUEUE_ERROR_EN(1U)
6661 #define S_CL7_PAR_WRQUEUE_ERROR_EN 18
6662 #define V_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR_EN)
6663 #define F_CL7_PAR_WRQUEUE_ERROR_EN V_CL7_PAR_WRQUEUE_ERROR_EN(1U)
6665 #define S_CL6_PAR_WRQUEUE_ERROR_EN 17
6666 #define V_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR_EN)
6667 #define F_CL6_PAR_WRQUEUE_ERROR_EN V_CL6_PAR_WRQUEUE_ERROR_EN(1U)
6669 #define S_CL5_PAR_WRQUEUE_ERROR_EN 16
6670 #define V_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR_EN)
6671 #define F_CL5_PAR_WRQUEUE_ERROR_EN V_CL5_PAR_WRQUEUE_ERROR_EN(1U)
6673 #define S_CL4_PAR_WRQUEUE_ERROR_EN 15
6674 #define V_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR_EN)
6675 #define F_CL4_PAR_WRQUEUE_ERROR_EN V_CL4_PAR_WRQUEUE_ERROR_EN(1U)
6677 #define S_CL3_PAR_WRQUEUE_ERROR_EN 14
6678 #define V_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR_EN)
6679 #define F_CL3_PAR_WRQUEUE_ERROR_EN V_CL3_PAR_WRQUEUE_ERROR_EN(1U)
6681 #define S_CL2_PAR_WRQUEUE_ERROR_EN 13
6682 #define V_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR_EN)
6683 #define F_CL2_PAR_WRQUEUE_ERROR_EN V_CL2_PAR_WRQUEUE_ERROR_EN(1U)
6685 #define S_CL1_PAR_WRQUEUE_ERROR_EN 12
6686 #define V_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR_EN)
6687 #define F_CL1_PAR_WRQUEUE_ERROR_EN V_CL1_PAR_WRQUEUE_ERROR_EN(1U)
6689 #define S_CL0_PAR_WRQUEUE_ERROR_EN 11
6690 #define V_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR_EN)
6691 #define F_CL0_PAR_WRQUEUE_ERROR_EN V_CL0_PAR_WRQUEUE_ERROR_EN(1U)
6693 #define S_CL10_PAR_RDQUEUE_ERROR_EN 10
6694 #define V_CL10_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR_EN)
6695 #define F_CL10_PAR_RDQUEUE_ERROR_EN V_CL10_PAR_RDQUEUE_ERROR_EN(1U)
6697 #define S_CL9_PAR_RDQUEUE_ERROR_EN 9
6698 #define V_CL9_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR_EN)
6699 #define F_CL9_PAR_RDQUEUE_ERROR_EN V_CL9_PAR_RDQUEUE_ERROR_EN(1U)
6701 #define S_CL8_PAR_RDQUEUE_ERROR_EN 8
6702 #define V_CL8_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR_EN)
6703 #define F_CL8_PAR_RDQUEUE_ERROR_EN V_CL8_PAR_RDQUEUE_ERROR_EN(1U)
6705 #define S_CL7_PAR_RDQUEUE_ERROR_EN 7
6706 #define V_CL7_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR_EN)
6707 #define F_CL7_PAR_RDQUEUE_ERROR_EN V_CL7_PAR_RDQUEUE_ERROR_EN(1U)
6709 #define S_CL6_PAR_RDQUEUE_ERROR_EN 6
6710 #define V_CL6_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR_EN)
6711 #define F_CL6_PAR_RDQUEUE_ERROR_EN V_CL6_PAR_RDQUEUE_ERROR_EN(1U)
6713 #define S_CL5_PAR_RDQUEUE_ERROR_EN 5
6714 #define V_CL5_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR_EN)
6715 #define F_CL5_PAR_RDQUEUE_ERROR_EN V_CL5_PAR_RDQUEUE_ERROR_EN(1U)
6717 #define S_CL4_PAR_RDQUEUE_ERROR_EN 4
6718 #define V_CL4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR_EN)
6719 #define F_CL4_PAR_RDQUEUE_ERROR_EN V_CL4_PAR_RDQUEUE_ERROR_EN(1U)
6721 #define S_CL3_PAR_RDQUEUE_ERROR_EN 3
6722 #define V_CL3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR_EN)
6723 #define F_CL3_PAR_RDQUEUE_ERROR_EN V_CL3_PAR_RDQUEUE_ERROR_EN(1U)
6725 #define S_CL2_PAR_RDQUEUE_ERROR_EN 2
6726 #define V_CL2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR_EN)
6727 #define F_CL2_PAR_RDQUEUE_ERROR_EN V_CL2_PAR_RDQUEUE_ERROR_EN(1U)
6729 #define S_CL1_PAR_RDQUEUE_ERROR_EN 1
6730 #define V_CL1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR_EN)
6731 #define F_CL1_PAR_RDQUEUE_ERROR_EN V_CL1_PAR_RDQUEUE_ERROR_EN(1U)
6733 #define S_CL0_PAR_RDQUEUE_ERROR_EN 0
6734 #define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN)
6735 #define F_CL0_PAR_RDQUEUE_ERROR_EN V_CL0_PAR_RDQUEUE_ERROR_EN(1U)
6737 #define A_MA_PARITY_ERROR_STATUS 0x77f4
6739 #define S_TP_DMARBT_PAR_ERROR 31
6740 #define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR)
6741 #define F_TP_DMARBT_PAR_ERROR V_TP_DMARBT_PAR_ERROR(1U)
6743 #define S_LOGIC_FIFO_PAR_ERROR 30
6744 #define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR)
6745 #define F_LOGIC_FIFO_PAR_ERROR V_LOGIC_FIFO_PAR_ERROR(1U)
6747 #define S_ARB3_PAR_WRQUEUE_ERROR 29
6748 #define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR)
6749 #define F_ARB3_PAR_WRQUEUE_ERROR V_ARB3_PAR_WRQUEUE_ERROR(1U)
6751 #define S_ARB2_PAR_WRQUEUE_ERROR 28
6752 #define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR)
6753 #define F_ARB2_PAR_WRQUEUE_ERROR V_ARB2_PAR_WRQUEUE_ERROR(1U)
6755 #define S_ARB1_PAR_WRQUEUE_ERROR 27
6756 #define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR)
6757 #define F_ARB1_PAR_WRQUEUE_ERROR V_ARB1_PAR_WRQUEUE_ERROR(1U)
6759 #define S_ARB0_PAR_WRQUEUE_ERROR 26
6760 #define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR)
6761 #define F_ARB0_PAR_WRQUEUE_ERROR V_ARB0_PAR_WRQUEUE_ERROR(1U)
6763 #define S_ARB3_PAR_RDQUEUE_ERROR 25
6764 #define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR)
6765 #define F_ARB3_PAR_RDQUEUE_ERROR V_ARB3_PAR_RDQUEUE_ERROR(1U)
6767 #define S_ARB2_PAR_RDQUEUE_ERROR 24
6768 #define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR)
6769 #define F_ARB2_PAR_RDQUEUE_ERROR V_ARB2_PAR_RDQUEUE_ERROR(1U)
6771 #define S_ARB1_PAR_RDQUEUE_ERROR 23
6772 #define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR)
6773 #define F_ARB1_PAR_RDQUEUE_ERROR V_ARB1_PAR_RDQUEUE_ERROR(1U)
6775 #define S_ARB0_PAR_RDQUEUE_ERROR 22
6776 #define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR)
6777 #define F_ARB0_PAR_RDQUEUE_ERROR V_ARB0_PAR_RDQUEUE_ERROR(1U)
6779 #define S_CL10_PAR_WRQUEUE_ERROR 21
6780 #define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR)
6781 #define F_CL10_PAR_WRQUEUE_ERROR V_CL10_PAR_WRQUEUE_ERROR(1U)
6783 #define S_CL9_PAR_WRQUEUE_ERROR 20
6784 #define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR)
6785 #define F_CL9_PAR_WRQUEUE_ERROR V_CL9_PAR_WRQUEUE_ERROR(1U)
6787 #define S_CL8_PAR_WRQUEUE_ERROR 19
6788 #define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR)
6789 #define F_CL8_PAR_WRQUEUE_ERROR V_CL8_PAR_WRQUEUE_ERROR(1U)
6791 #define S_CL7_PAR_WRQUEUE_ERROR 18
6792 #define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR)
6793 #define F_CL7_PAR_WRQUEUE_ERROR V_CL7_PAR_WRQUEUE_ERROR(1U)
6795 #define S_CL6_PAR_WRQUEUE_ERROR 17
6796 #define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR)
6797 #define F_CL6_PAR_WRQUEUE_ERROR V_CL6_PAR_WRQUEUE_ERROR(1U)
6799 #define S_CL5_PAR_WRQUEUE_ERROR 16
6800 #define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR)
6801 #define F_CL5_PAR_WRQUEUE_ERROR V_CL5_PAR_WRQUEUE_ERROR(1U)
6803 #define S_CL4_PAR_WRQUEUE_ERROR 15
6804 #define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR)
6805 #define F_CL4_PAR_WRQUEUE_ERROR V_CL4_PAR_WRQUEUE_ERROR(1U)
6807 #define S_CL3_PAR_WRQUEUE_ERROR 14
6808 #define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR)
6809 #define F_CL3_PAR_WRQUEUE_ERROR V_CL3_PAR_WRQUEUE_ERROR(1U)
6811 #define S_CL2_PAR_WRQUEUE_ERROR 13
6812 #define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR)
6813 #define F_CL2_PAR_WRQUEUE_ERROR V_CL2_PAR_WRQUEUE_ERROR(1U)
6815 #define S_CL1_PAR_WRQUEUE_ERROR 12
6816 #define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR)
6817 #define F_CL1_PAR_WRQUEUE_ERROR V_CL1_PAR_WRQUEUE_ERROR(1U)
6819 #define S_CL0_PAR_WRQUEUE_ERROR 11
6820 #define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR)
6821 #define F_CL0_PAR_WRQUEUE_ERROR V_CL0_PAR_WRQUEUE_ERROR(1U)
6823 #define S_CL10_PAR_RDQUEUE_ERROR 10
6824 #define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR)
6825 #define F_CL10_PAR_RDQUEUE_ERROR V_CL10_PAR_RDQUEUE_ERROR(1U)
6827 #define S_CL9_PAR_RDQUEUE_ERROR 9
6828 #define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR)
6829 #define F_CL9_PAR_RDQUEUE_ERROR V_CL9_PAR_RDQUEUE_ERROR(1U)
6831 #define S_CL8_PAR_RDQUEUE_ERROR 8
6832 #define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR)
6833 #define F_CL8_PAR_RDQUEUE_ERROR V_CL8_PAR_RDQUEUE_ERROR(1U)
6835 #define S_CL7_PAR_RDQUEUE_ERROR 7
6836 #define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR)
6837 #define F_CL7_PAR_RDQUEUE_ERROR V_CL7_PAR_RDQUEUE_ERROR(1U)
6839 #define S_CL6_PAR_RDQUEUE_ERROR 6
6840 #define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR)
6841 #define F_CL6_PAR_RDQUEUE_ERROR V_CL6_PAR_RDQUEUE_ERROR(1U)
6843 #define S_CL5_PAR_RDQUEUE_ERROR 5
6844 #define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR)
6845 #define F_CL5_PAR_RDQUEUE_ERROR V_CL5_PAR_RDQUEUE_ERROR(1U)
6847 #define S_CL4_PAR_RDQUEUE_ERROR 4
6848 #define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR)
6849 #define F_CL4_PAR_RDQUEUE_ERROR V_CL4_PAR_RDQUEUE_ERROR(1U)
6851 #define S_CL3_PAR_RDQUEUE_ERROR 3
6852 #define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR)
6853 #define F_CL3_PAR_RDQUEUE_ERROR V_CL3_PAR_RDQUEUE_ERROR(1U)
6855 #define S_CL2_PAR_RDQUEUE_ERROR 2
6856 #define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR)
6857 #define F_CL2_PAR_RDQUEUE_ERROR V_CL2_PAR_RDQUEUE_ERROR(1U)
6859 #define S_CL1_PAR_RDQUEUE_ERROR 1
6860 #define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR)
6861 #define F_CL1_PAR_RDQUEUE_ERROR V_CL1_PAR_RDQUEUE_ERROR(1U)
6863 #define S_CL0_PAR_RDQUEUE_ERROR 0
6864 #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
6865 #define F_CL0_PAR_RDQUEUE_ERROR V_CL0_PAR_RDQUEUE_ERROR(1U)
6867 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
6869 #define S_BONUS_REG 6
6870 #define M_BONUS_REG 0x3ffffffU
6871 #define V_BONUS_REG(x) ((x) << S_BONUS_REG)
6872 #define G_BONUS_REG(x) (((x) >> S_BONUS_REG) & M_BONUS_REG)
6874 #define S_COHERANCY_CMD_TYPE 4
6875 #define M_COHERANCY_CMD_TYPE 0x3U
6876 #define V_COHERANCY_CMD_TYPE(x) ((x) << S_COHERANCY_CMD_TYPE)
6877 #define G_COHERANCY_CMD_TYPE(x) (((x) >> S_COHERANCY_CMD_TYPE) & M_COHERANCY_CMD_TYPE)
6879 #define S_COHERANCY_THREAD_NUM 1
6880 #define M_COHERANCY_THREAD_NUM 0x7U
6881 #define V_COHERANCY_THREAD_NUM(x) ((x) << S_COHERANCY_THREAD_NUM)
6882 #define G_COHERANCY_THREAD_NUM(x) (((x) >> S_COHERANCY_THREAD_NUM) & M_COHERANCY_THREAD_NUM)
6884 #define S_COHERANCY_ENABLE 0
6885 #define V_COHERANCY_ENABLE(x) ((x) << S_COHERANCY_ENABLE)
6886 #define F_COHERANCY_ENABLE V_COHERANCY_ENABLE(1U)
6888 #define A_MA_ERROR_ENABLE 0x77fc
6890 #define S_UE_ENABLE 0
6891 #define V_UE_ENABLE(x) ((x) << S_UE_ENABLE)
6892 #define F_UE_ENABLE V_UE_ENABLE(1U)
6894 /* registers for module EDC_0 */
6895 #define EDC_0_BASE_ADDR 0x7900
6897 #define A_EDC_REF 0x7900
6899 #define S_EDC_INST_NUM 18
6900 #define V_EDC_INST_NUM(x) ((x) << S_EDC_INST_NUM)
6901 #define F_EDC_INST_NUM V_EDC_INST_NUM(1U)
6903 #define S_ENABLE_PERF 17
6904 #define V_ENABLE_PERF(x) ((x) << S_ENABLE_PERF)
6905 #define F_ENABLE_PERF V_ENABLE_PERF(1U)
6907 #define S_ECC_BYPASS 16
6908 #define V_ECC_BYPASS(x) ((x) << S_ECC_BYPASS)
6909 #define F_ECC_BYPASS V_ECC_BYPASS(1U)
6912 #define M_REFFREQ 0xffffU
6913 #define V_REFFREQ(x) ((x) << S_REFFREQ)
6914 #define G_REFFREQ(x) (((x) >> S_REFFREQ) & M_REFFREQ)
6916 #define A_EDC_BIST_CMD 0x7904
6917 #define A_EDC_BIST_CMD_ADDR 0x7908
6918 #define A_EDC_BIST_CMD_LEN 0x790c
6919 #define A_EDC_BIST_DATA_PATTERN 0x7910
6920 #define A_EDC_BIST_USER_WDATA0 0x7914
6921 #define A_EDC_BIST_USER_WDATA1 0x7918
6922 #define A_EDC_BIST_USER_WDATA2 0x791c
6923 #define A_EDC_BIST_NUM_ERR 0x7920
6924 #define A_EDC_BIST_ERR_FIRST_ADDR 0x7924
6925 #define A_EDC_BIST_STATUS_RDATA 0x7928
6926 #define A_EDC_PAR_ENABLE 0x7970
6929 #define V_ECC_UE(x) ((x) << S_ECC_UE)
6930 #define F_ECC_UE V_ECC_UE(1U)
6933 #define V_ECC_CE(x) ((x) << S_ECC_CE)
6934 #define F_ECC_CE V_ECC_CE(1U)
6936 #define A_EDC_INT_ENABLE 0x7974
6937 #define A_EDC_INT_CAUSE 0x7978
6939 #define S_ECC_UE_PAR 5
6940 #define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR)
6941 #define F_ECC_UE_PAR V_ECC_UE_PAR(1U)
6943 #define S_ECC_CE_PAR 4
6944 #define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR)
6945 #define F_ECC_CE_PAR V_ECC_CE_PAR(1U)
6947 #define S_PERR_PAR_CAUSE 3
6948 #define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE)
6949 #define F_PERR_PAR_CAUSE V_PERR_PAR_CAUSE(1U)
6951 #define A_EDC_ECC_STATUS 0x797c
6953 /* registers for module EDC_1 */
6954 #define EDC_1_BASE_ADDR 0x7980
6956 /* registers for module HMA */
6957 #define HMA_BASE_ADDR 0x7a00
6959 /* registers for module CIM */
6960 #define CIM_BASE_ADDR 0x7b00
6962 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
6964 #define S_VFMBGENERIC 4
6965 #define M_VFMBGENERIC 0xfU
6966 #define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC)
6967 #define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC)
6969 #define A_CIM_VF_EXT_MAILBOX_STATUS 0x4
6971 #define S_MBVFREADY 0
6972 #define V_MBVFREADY(x) ((x) << S_MBVFREADY)
6973 #define F_MBVFREADY V_MBVFREADY(1U)
6975 #define A_CIM_PF_MAILBOX_DATA 0x240
6976 #define A_CIM_PF_MAILBOX_CTRL 0x280
6978 #define S_MBGENERIC 4
6979 #define M_MBGENERIC 0xfffffffU
6980 #define V_MBGENERIC(x) ((x) << S_MBGENERIC)
6981 #define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC)
6983 #define S_MBMSGVALID 3
6984 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
6985 #define F_MBMSGVALID V_MBMSGVALID(1U)
6987 #define S_MBINTREQ 2
6988 #define V_MBINTREQ(x) ((x) << S_MBINTREQ)
6989 #define F_MBINTREQ V_MBINTREQ(1U)
6992 #define M_MBOWNER 0x3U
6993 #define V_MBOWNER(x) ((x) << S_MBOWNER)
6994 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
6996 #define A_CIM_PF_MAILBOX_ACC_STATUS 0x284
6998 #define S_MBWRBUSY 31
6999 #define V_MBWRBUSY(x) ((x) << S_MBWRBUSY)
7000 #define F_MBWRBUSY V_MBWRBUSY(1U)
7002 #define A_CIM_PF_HOST_INT_ENABLE 0x288
7004 #define S_MBMSGRDYINTEN 19
7005 #define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN)
7006 #define F_MBMSGRDYINTEN V_MBMSGRDYINTEN(1U)
7008 #define A_CIM_PF_HOST_INT_CAUSE 0x28c
7010 #define S_MBMSGRDYINT 19
7011 #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
7012 #define F_MBMSGRDYINT V_MBMSGRDYINT(1U)
7014 #define A_CIM_BOOT_CFG 0x7b00
7016 #define S_BOOTADDR 8
7017 #define M_BOOTADDR 0xffffffU
7018 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
7019 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
7022 #define M_UPGEN 0x3fU
7023 #define V_UPGEN(x) ((x) << S_UPGEN)
7024 #define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN)
7026 #define S_BOOTSDRAM 1
7027 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
7028 #define F_BOOTSDRAM V_BOOTSDRAM(1U)
7031 #define V_UPCRST(x) ((x) << S_UPCRST)
7032 #define F_UPCRST V_UPCRST(1U)
7034 #define A_CIM_FLASH_BASE_ADDR 0x7b04
7036 #define S_FLASHBASEADDR 6
7037 #define M_FLASHBASEADDR 0x3ffffU
7038 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
7039 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
7041 #define A_CIM_FLASH_ADDR_SIZE 0x7b08
7043 #define S_FLASHADDRSIZE 4
7044 #define M_FLASHADDRSIZE 0xfffffU
7045 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
7046 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
7048 #define A_CIM_EEPROM_BASE_ADDR 0x7b0c
7050 #define S_EEPROMBASEADDR 6
7051 #define M_EEPROMBASEADDR 0x3ffffU
7052 #define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR)
7053 #define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR)
7055 #define A_CIM_EEPROM_ADDR_SIZE 0x7b10
7057 #define S_EEPROMADDRSIZE 4
7058 #define M_EEPROMADDRSIZE 0xfffffU
7059 #define V_EEPROMADDRSIZE(x) ((x) << S_EEPROMADDRSIZE)
7060 #define G_EEPROMADDRSIZE(x) (((x) >> S_EEPROMADDRSIZE) & M_EEPROMADDRSIZE)
7062 #define A_CIM_SDRAM_BASE_ADDR 0x7b14
7064 #define S_SDRAMBASEADDR 6
7065 #define M_SDRAMBASEADDR 0x3ffffffU
7066 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
7067 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
7069 #define A_CIM_SDRAM_ADDR_SIZE 0x7b18
7071 #define S_SDRAMADDRSIZE 4
7072 #define M_SDRAMADDRSIZE 0xfffffffU
7073 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
7074 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
7076 #define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c
7078 #define S_EXTMEM2BASEADDR 6
7079 #define M_EXTMEM2BASEADDR 0x3ffffffU
7080 #define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR)
7081 #define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR)
7083 #define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20
7085 #define S_EXTMEM2ADDRSIZE 4
7086 #define M_EXTMEM2ADDRSIZE 0xfffffffU
7087 #define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE)
7088 #define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE)
7090 #define A_CIM_UP_SPARE_INT 0x7b24
7092 #define S_TDEBUGINT 4
7093 #define V_TDEBUGINT(x) ((x) << S_TDEBUGINT)
7094 #define F_TDEBUGINT V_TDEBUGINT(1U)
7096 #define S_BOOTVECSEL 3
7097 #define V_BOOTVECSEL(x) ((x) << S_BOOTVECSEL)
7098 #define F_BOOTVECSEL V_BOOTVECSEL(1U)
7100 #define S_UPSPAREINT 0
7101 #define M_UPSPAREINT 0x7U
7102 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
7103 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
7105 #define A_CIM_HOST_INT_ENABLE 0x7b28
7107 #define S_TIEQOUTPARERRINTEN 20
7108 #define V_TIEQOUTPARERRINTEN(x) ((x) << S_TIEQOUTPARERRINTEN)
7109 #define F_TIEQOUTPARERRINTEN V_TIEQOUTPARERRINTEN(1U)
7111 #define S_TIEQINPARERRINTEN 19
7112 #define V_TIEQINPARERRINTEN(x) ((x) << S_TIEQINPARERRINTEN)
7113 #define F_TIEQINPARERRINTEN V_TIEQINPARERRINTEN(1U)
7115 #define S_MBHOSTPARERR 18
7116 #define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR)
7117 #define F_MBHOSTPARERR V_MBHOSTPARERR(1U)
7119 #define S_MBUPPARERR 17
7120 #define V_MBUPPARERR(x) ((x) << S_MBUPPARERR)
7121 #define F_MBUPPARERR V_MBUPPARERR(1U)
7123 #define S_IBQTP0PARERR 16
7124 #define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR)
7125 #define F_IBQTP0PARERR V_IBQTP0PARERR(1U)
7127 #define S_IBQTP1PARERR 15
7128 #define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR)
7129 #define F_IBQTP1PARERR V_IBQTP1PARERR(1U)
7131 #define S_IBQULPPARERR 14
7132 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
7133 #define F_IBQULPPARERR V_IBQULPPARERR(1U)
7135 #define S_IBQSGELOPARERR 13
7136 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
7137 #define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U)
7139 #define S_IBQSGEHIPARERR 12
7140 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
7141 #define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U)
7143 #define S_IBQNCSIPARERR 11
7144 #define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR)
7145 #define F_IBQNCSIPARERR V_IBQNCSIPARERR(1U)
7147 #define S_OBQULP0PARERR 10
7148 #define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR)
7149 #define F_OBQULP0PARERR V_OBQULP0PARERR(1U)
7151 #define S_OBQULP1PARERR 9
7152 #define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR)
7153 #define F_OBQULP1PARERR V_OBQULP1PARERR(1U)
7155 #define S_OBQULP2PARERR 8
7156 #define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR)
7157 #define F_OBQULP2PARERR V_OBQULP2PARERR(1U)
7159 #define S_OBQULP3PARERR 7
7160 #define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR)
7161 #define F_OBQULP3PARERR V_OBQULP3PARERR(1U)
7163 #define S_OBQSGEPARERR 6
7164 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
7165 #define F_OBQSGEPARERR V_OBQSGEPARERR(1U)
7167 #define S_OBQNCSIPARERR 5
7168 #define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR)
7169 #define F_OBQNCSIPARERR V_OBQNCSIPARERR(1U)
7171 #define S_TIMER1INTEN 3
7172 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
7173 #define F_TIMER1INTEN V_TIMER1INTEN(1U)
7175 #define S_TIMER0INTEN 2
7176 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
7177 #define F_TIMER0INTEN V_TIMER0INTEN(1U)
7179 #define S_PREFDROPINTEN 1
7180 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
7181 #define F_PREFDROPINTEN V_PREFDROPINTEN(1U)
7183 #define A_CIM_HOST_INT_CAUSE 0x7b2c
7185 #define S_TIEQOUTPARERRINT 20
7186 #define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT)
7187 #define F_TIEQOUTPARERRINT V_TIEQOUTPARERRINT(1U)
7189 #define S_TIEQINPARERRINT 19
7190 #define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT)
7191 #define F_TIEQINPARERRINT V_TIEQINPARERRINT(1U)
7193 #define S_TIMER1INT 3
7194 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
7195 #define F_TIMER1INT V_TIMER1INT(1U)
7197 #define S_TIMER0INT 2
7198 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
7199 #define F_TIMER0INT V_TIMER0INT(1U)
7201 #define S_PREFDROPINT 1
7202 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
7203 #define F_PREFDROPINT V_PREFDROPINT(1U)
7205 #define S_UPACCNONZERO 0
7206 #define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO)
7207 #define F_UPACCNONZERO V_UPACCNONZERO(1U)
7209 #define A_CIM_HOST_UPACC_INT_ENABLE 0x7b30
7211 #define S_EEPROMWRINTEN 30
7212 #define V_EEPROMWRINTEN(x) ((x) << S_EEPROMWRINTEN)
7213 #define F_EEPROMWRINTEN V_EEPROMWRINTEN(1U)
7215 #define S_TIMEOUTMAINTEN 29
7216 #define V_TIMEOUTMAINTEN(x) ((x) << S_TIMEOUTMAINTEN)
7217 #define F_TIMEOUTMAINTEN V_TIMEOUTMAINTEN(1U)
7219 #define S_TIMEOUTINTEN 28
7220 #define V_TIMEOUTINTEN(x) ((x) << S_TIMEOUTINTEN)
7221 #define F_TIMEOUTINTEN V_TIMEOUTINTEN(1U)
7223 #define S_RSPOVRLOOKUPINTEN 27
7224 #define V_RSPOVRLOOKUPINTEN(x) ((x) << S_RSPOVRLOOKUPINTEN)
7225 #define F_RSPOVRLOOKUPINTEN V_RSPOVRLOOKUPINTEN(1U)
7227 #define S_REQOVRLOOKUPINTEN 26
7228 #define V_REQOVRLOOKUPINTEN(x) ((x) << S_REQOVRLOOKUPINTEN)
7229 #define F_REQOVRLOOKUPINTEN V_REQOVRLOOKUPINTEN(1U)
7231 #define S_BLKWRPLINTEN 25
7232 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
7233 #define F_BLKWRPLINTEN V_BLKWRPLINTEN(1U)
7235 #define S_BLKRDPLINTEN 24
7236 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
7237 #define F_BLKRDPLINTEN V_BLKRDPLINTEN(1U)
7239 #define S_SGLWRPLINTEN 23
7240 #define V_SGLWRPLINTEN(x) ((x) << S_SGLWRPLINTEN)
7241 #define F_SGLWRPLINTEN V_SGLWRPLINTEN(1U)
7243 #define S_SGLRDPLINTEN 22
7244 #define V_SGLRDPLINTEN(x) ((x) << S_SGLRDPLINTEN)
7245 #define F_SGLRDPLINTEN V_SGLRDPLINTEN(1U)
7247 #define S_BLKWRCTLINTEN 21
7248 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
7249 #define F_BLKWRCTLINTEN V_BLKWRCTLINTEN(1U)
7251 #define S_BLKRDCTLINTEN 20
7252 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
7253 #define F_BLKRDCTLINTEN V_BLKRDCTLINTEN(1U)
7255 #define S_SGLWRCTLINTEN 19
7256 #define V_SGLWRCTLINTEN(x) ((x) << S_SGLWRCTLINTEN)
7257 #define F_SGLWRCTLINTEN V_SGLWRCTLINTEN(1U)
7259 #define S_SGLRDCTLINTEN 18
7260 #define V_SGLRDCTLINTEN(x) ((x) << S_SGLRDCTLINTEN)
7261 #define F_SGLRDCTLINTEN V_SGLRDCTLINTEN(1U)
7263 #define S_BLKWREEPROMINTEN 17
7264 #define V_BLKWREEPROMINTEN(x) ((x) << S_BLKWREEPROMINTEN)
7265 #define F_BLKWREEPROMINTEN V_BLKWREEPROMINTEN(1U)
7267 #define S_BLKRDEEPROMINTEN 16
7268 #define V_BLKRDEEPROMINTEN(x) ((x) << S_BLKRDEEPROMINTEN)
7269 #define F_BLKRDEEPROMINTEN V_BLKRDEEPROMINTEN(1U)
7271 #define S_SGLWREEPROMINTEN 15
7272 #define V_SGLWREEPROMINTEN(x) ((x) << S_SGLWREEPROMINTEN)
7273 #define F_SGLWREEPROMINTEN V_SGLWREEPROMINTEN(1U)
7275 #define S_SGLRDEEPROMINTEN 14
7276 #define V_SGLRDEEPROMINTEN(x) ((x) << S_SGLRDEEPROMINTEN)
7277 #define F_SGLRDEEPROMINTEN V_SGLRDEEPROMINTEN(1U)
7279 #define S_BLKWRFLASHINTEN 13
7280 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
7281 #define F_BLKWRFLASHINTEN V_BLKWRFLASHINTEN(1U)
7283 #define S_BLKRDFLASHINTEN 12
7284 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
7285 #define F_BLKRDFLASHINTEN V_BLKRDFLASHINTEN(1U)
7287 #define S_SGLWRFLASHINTEN 11
7288 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
7289 #define F_SGLWRFLASHINTEN V_SGLWRFLASHINTEN(1U)
7291 #define S_SGLRDFLASHINTEN 10
7292 #define V_SGLRDFLASHINTEN(x) ((x) << S_SGLRDFLASHINTEN)
7293 #define F_SGLRDFLASHINTEN V_SGLRDFLASHINTEN(1U)
7295 #define S_BLKWRBOOTINTEN 9
7296 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
7297 #define F_BLKWRBOOTINTEN V_BLKWRBOOTINTEN(1U)
7299 #define S_BLKRDBOOTINTEN 8
7300 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
7301 #define F_BLKRDBOOTINTEN V_BLKRDBOOTINTEN(1U)
7303 #define S_SGLWRBOOTINTEN 7
7304 #define V_SGLWRBOOTINTEN(x) ((x) << S_SGLWRBOOTINTEN)
7305 #define F_SGLWRBOOTINTEN V_SGLWRBOOTINTEN(1U)
7307 #define S_SGLRDBOOTINTEN 6
7308 #define V_SGLRDBOOTINTEN(x) ((x) << S_SGLRDBOOTINTEN)
7309 #define F_SGLRDBOOTINTEN V_SGLRDBOOTINTEN(1U)
7311 #define S_ILLWRBEINTEN 5
7312 #define V_ILLWRBEINTEN(x) ((x) << S_ILLWRBEINTEN)
7313 #define F_ILLWRBEINTEN V_ILLWRBEINTEN(1U)
7315 #define S_ILLRDBEINTEN 4
7316 #define V_ILLRDBEINTEN(x) ((x) << S_ILLRDBEINTEN)
7317 #define F_ILLRDBEINTEN V_ILLRDBEINTEN(1U)
7319 #define S_ILLRDINTEN 3
7320 #define V_ILLRDINTEN(x) ((x) << S_ILLRDINTEN)
7321 #define F_ILLRDINTEN V_ILLRDINTEN(1U)
7323 #define S_ILLWRINTEN 2
7324 #define V_ILLWRINTEN(x) ((x) << S_ILLWRINTEN)
7325 #define F_ILLWRINTEN V_ILLWRINTEN(1U)
7327 #define S_ILLTRANSINTEN 1
7328 #define V_ILLTRANSINTEN(x) ((x) << S_ILLTRANSINTEN)
7329 #define F_ILLTRANSINTEN V_ILLTRANSINTEN(1U)
7331 #define S_RSVDSPACEINTEN 0
7332 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
7333 #define F_RSVDSPACEINTEN V_RSVDSPACEINTEN(1U)
7335 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
7337 #define S_EEPROMWRINT 30
7338 #define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT)
7339 #define F_EEPROMWRINT V_EEPROMWRINT(1U)
7341 #define S_TIMEOUTMAINT 29
7342 #define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT)
7343 #define F_TIMEOUTMAINT V_TIMEOUTMAINT(1U)
7345 #define S_TIMEOUTINT 28
7346 #define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT)
7347 #define F_TIMEOUTINT V_TIMEOUTINT(1U)
7349 #define S_RSPOVRLOOKUPINT 27
7350 #define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT)
7351 #define F_RSPOVRLOOKUPINT V_RSPOVRLOOKUPINT(1U)
7353 #define S_REQOVRLOOKUPINT 26
7354 #define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT)
7355 #define F_REQOVRLOOKUPINT V_REQOVRLOOKUPINT(1U)
7357 #define S_BLKWRPLINT 25
7358 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
7359 #define F_BLKWRPLINT V_BLKWRPLINT(1U)
7361 #define S_BLKRDPLINT 24
7362 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
7363 #define F_BLKRDPLINT V_BLKRDPLINT(1U)
7365 #define S_SGLWRPLINT 23
7366 #define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT)
7367 #define F_SGLWRPLINT V_SGLWRPLINT(1U)
7369 #define S_SGLRDPLINT 22
7370 #define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT)
7371 #define F_SGLRDPLINT V_SGLRDPLINT(1U)
7373 #define S_BLKWRCTLINT 21
7374 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
7375 #define F_BLKWRCTLINT V_BLKWRCTLINT(1U)
7377 #define S_BLKRDCTLINT 20
7378 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
7379 #define F_BLKRDCTLINT V_BLKRDCTLINT(1U)
7381 #define S_SGLWRCTLINT 19
7382 #define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT)
7383 #define F_SGLWRCTLINT V_SGLWRCTLINT(1U)
7385 #define S_SGLRDCTLINT 18
7386 #define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT)
7387 #define F_SGLRDCTLINT V_SGLRDCTLINT(1U)
7389 #define S_BLKWREEPROMINT 17
7390 #define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT)
7391 #define F_BLKWREEPROMINT V_BLKWREEPROMINT(1U)
7393 #define S_BLKRDEEPROMINT 16
7394 #define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT)
7395 #define F_BLKRDEEPROMINT V_BLKRDEEPROMINT(1U)
7397 #define S_SGLWREEPROMINT 15
7398 #define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT)
7399 #define F_SGLWREEPROMINT V_SGLWREEPROMINT(1U)
7401 #define S_SGLRDEEPROMINT 14
7402 #define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT)
7403 #define F_SGLRDEEPROMINT V_SGLRDEEPROMINT(1U)
7405 #define S_BLKWRFLASHINT 13
7406 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
7407 #define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U)
7409 #define S_BLKRDFLASHINT 12
7410 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
7411 #define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U)
7413 #define S_SGLWRFLASHINT 11
7414 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
7415 #define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U)
7417 #define S_SGLRDFLASHINT 10
7418 #define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT)
7419 #define F_SGLRDFLASHINT V_SGLRDFLASHINT(1U)
7421 #define S_BLKWRBOOTINT 9
7422 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
7423 #define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U)
7425 #define S_BLKRDBOOTINT 8
7426 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
7427 #define F_BLKRDBOOTINT V_BLKRDBOOTINT(1U)
7429 #define S_SGLWRBOOTINT 7
7430 #define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT)
7431 #define F_SGLWRBOOTINT V_SGLWRBOOTINT(1U)
7433 #define S_SGLRDBOOTINT 6
7434 #define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT)
7435 #define F_SGLRDBOOTINT V_SGLRDBOOTINT(1U)
7437 #define S_ILLWRBEINT 5
7438 #define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT)
7439 #define F_ILLWRBEINT V_ILLWRBEINT(1U)
7441 #define S_ILLRDBEINT 4
7442 #define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT)
7443 #define F_ILLRDBEINT V_ILLRDBEINT(1U)
7445 #define S_ILLRDINT 3
7446 #define V_ILLRDINT(x) ((x) << S_ILLRDINT)
7447 #define F_ILLRDINT V_ILLRDINT(1U)
7449 #define S_ILLWRINT 2
7450 #define V_ILLWRINT(x) ((x) << S_ILLWRINT)
7451 #define F_ILLWRINT V_ILLWRINT(1U)
7453 #define S_ILLTRANSINT 1
7454 #define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT)
7455 #define F_ILLTRANSINT V_ILLTRANSINT(1U)
7457 #define S_RSVDSPACEINT 0
7458 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
7459 #define F_RSVDSPACEINT V_RSVDSPACEINT(1U)
7461 #define A_CIM_UP_INT_ENABLE 0x7b38
7463 #define S_MSTPLINTEN 4
7464 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
7465 #define F_MSTPLINTEN V_MSTPLINTEN(1U)
7467 #define A_CIM_UP_INT_CAUSE 0x7b3c
7469 #define S_MSTPLINT 4
7470 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
7471 #define F_MSTPLINT V_MSTPLINT(1U)
7473 #define A_CIM_UP_ACC_INT_ENABLE 0x7b40
7474 #define A_CIM_UP_ACC_INT_CAUSE 0x7b44
7475 #define A_CIM_QUEUE_CONFIG_REF 0x7b48
7477 #define S_OBQSELECT 4
7478 #define V_OBQSELECT(x) ((x) << S_OBQSELECT)
7479 #define F_OBQSELECT V_OBQSELECT(1U)
7481 #define S_IBQSELECT 3
7482 #define V_IBQSELECT(x) ((x) << S_IBQSELECT)
7483 #define F_IBQSELECT V_IBQSELECT(1U)
7485 #define S_QUENUMSELECT 0
7486 #define M_QUENUMSELECT 0x7U
7487 #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
7488 #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)
7490 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
7492 #define S_CIMQSIZE 24
7493 #define M_CIMQSIZE 0x3fU
7494 #define V_CIMQSIZE(x) ((x) << S_CIMQSIZE)
7495 #define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE)
7497 #define S_CIMQBASE 16
7498 #define M_CIMQBASE 0x3fU
7499 #define V_CIMQBASE(x) ((x) << S_CIMQBASE)
7500 #define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE)
7502 #define S_CIMQDBG8BEN 9
7503 #define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN)
7504 #define F_CIMQDBG8BEN V_CIMQDBG8BEN(1U)
7506 #define S_QUEFULLTHRSH 0
7507 #define M_QUEFULLTHRSH 0x1ffU
7508 #define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
7509 #define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)
7511 #define A_CIM_HOST_ACC_CTRL 0x7b50
7513 #define S_HOSTBUSY 17
7514 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
7515 #define F_HOSTBUSY V_HOSTBUSY(1U)
7517 #define S_HOSTWRITE 16
7518 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
7519 #define F_HOSTWRITE V_HOSTWRITE(1U)
7521 #define S_HOSTADDR 0
7522 #define M_HOSTADDR 0xffffU
7523 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
7524 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
7526 #define A_CIM_HOST_ACC_DATA 0x7b54
7527 #define A_CIM_CDEBUGDATA 0x7b58
7529 #define S_CDEBUGDATAH 16
7530 #define M_CDEBUGDATAH 0xffffU
7531 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
7532 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
7534 #define S_CDEBUGDATAL 0
7535 #define M_CDEBUGDATAL 0xffffU
7536 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
7537 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
7539 #define A_CIM_IBQ_DBG_CFG 0x7b60
7541 #define S_IBQDBGADDR 16
7542 #define M_IBQDBGADDR 0xfffU
7543 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
7544 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
7546 #define S_IBQDBGWR 2
7547 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
7548 #define F_IBQDBGWR V_IBQDBGWR(1U)
7550 #define S_IBQDBGBUSY 1
7551 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
7552 #define F_IBQDBGBUSY V_IBQDBGBUSY(1U)
7554 #define S_IBQDBGEN 0
7555 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
7556 #define F_IBQDBGEN V_IBQDBGEN(1U)
7558 #define A_CIM_OBQ_DBG_CFG 0x7b64
7560 #define S_OBQDBGADDR 16
7561 #define M_OBQDBGADDR 0xfffU
7562 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
7563 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
7565 #define S_OBQDBGWR 2
7566 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
7567 #define F_OBQDBGWR V_OBQDBGWR(1U)
7569 #define S_OBQDBGBUSY 1
7570 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
7571 #define F_OBQDBGBUSY V_OBQDBGBUSY(1U)
7573 #define S_OBQDBGEN 0
7574 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
7575 #define F_OBQDBGEN V_OBQDBGEN(1U)
7577 #define A_CIM_IBQ_DBG_DATA 0x7b68
7578 #define A_CIM_OBQ_DBG_DATA 0x7b6c
7579 #define A_CIM_DEBUGCFG 0x7b70
7581 #define S_POLADBGRDPTR 23
7582 #define M_POLADBGRDPTR 0x1ffU
7583 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
7584 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
7586 #define S_PILADBGRDPTR 14
7587 #define M_PILADBGRDPTR 0x1ffU
7588 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
7589 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
7591 #define S_LAMASKTRIG 13
7592 #define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG)
7593 #define F_LAMASKTRIG V_LAMASKTRIG(1U)
7595 #define S_LADBGEN 12
7596 #define V_LADBGEN(x) ((x) << S_LADBGEN)
7597 #define F_LADBGEN V_LADBGEN(1U)
7599 #define S_LAFILLONCE 11
7600 #define V_LAFILLONCE(x) ((x) << S_LAFILLONCE)
7601 #define F_LAFILLONCE V_LAFILLONCE(1U)
7603 #define S_LAMASKSTOP 10
7604 #define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP)
7605 #define F_LAMASKSTOP V_LAMASKSTOP(1U)
7607 #define S_DEBUGSELH 5
7608 #define M_DEBUGSELH 0x1fU
7609 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
7610 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
7612 #define S_DEBUGSELL 0
7613 #define M_DEBUGSELL 0x1fU
7614 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
7615 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
7617 #define A_CIM_DEBUGSTS 0x7b74
7619 #define S_LARESET 31
7620 #define V_LARESET(x) ((x) << S_LARESET)
7621 #define F_LARESET V_LARESET(1U)
7623 #define S_POLADBGWRPTR 16
7624 #define M_POLADBGWRPTR 0x1ffU
7625 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
7626 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
7628 #define S_PILADBGWRPTR 0
7629 #define M_PILADBGWRPTR 0x1ffU
7630 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
7631 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
7633 #define A_CIM_PO_LA_DEBUGDATA 0x7b78
7634 #define A_CIM_PI_LA_DEBUGDATA 0x7b7c
7635 #define A_CIM_PO_LA_MADEBUGDATA 0x7b80
7636 #define A_CIM_PI_LA_MADEBUGDATA 0x7b84
7637 #define A_CIM_PO_LA_PIFSMDEBUGDATA 0x7b8c
7638 #define A_CIM_MEM_ZONE0_VA 0x7b90
7640 #define S_MEM_ZONE_VA 4
7641 #define M_MEM_ZONE_VA 0xfffffffU
7642 #define V_MEM_ZONE_VA(x) ((x) << S_MEM_ZONE_VA)
7643 #define G_MEM_ZONE_VA(x) (((x) >> S_MEM_ZONE_VA) & M_MEM_ZONE_VA)
7645 #define A_CIM_MEM_ZONE0_BA 0x7b94
7647 #define S_MEM_ZONE_BA 6
7648 #define M_MEM_ZONE_BA 0x3ffffffU
7649 #define V_MEM_ZONE_BA(x) ((x) << S_MEM_ZONE_BA)
7650 #define G_MEM_ZONE_BA(x) (((x) >> S_MEM_ZONE_BA) & M_MEM_ZONE_BA)
7652 #define S_PBT_ENABLE 5
7653 #define V_PBT_ENABLE(x) ((x) << S_PBT_ENABLE)
7654 #define F_PBT_ENABLE V_PBT_ENABLE(1U)
7656 #define S_ZONE_DST 0
7657 #define M_ZONE_DST 0x3U
7658 #define V_ZONE_DST(x) ((x) << S_ZONE_DST)
7659 #define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST)
7661 #define A_CIM_MEM_ZONE0_LEN 0x7b98
7663 #define S_MEM_ZONE_LEN 4
7664 #define M_MEM_ZONE_LEN 0xfffffffU
7665 #define V_MEM_ZONE_LEN(x) ((x) << S_MEM_ZONE_LEN)
7666 #define G_MEM_ZONE_LEN(x) (((x) >> S_MEM_ZONE_LEN) & M_MEM_ZONE_LEN)
7668 #define A_CIM_MEM_ZONE1_VA 0x7b9c
7669 #define A_CIM_MEM_ZONE1_BA 0x7ba0
7670 #define A_CIM_MEM_ZONE1_LEN 0x7ba4
7671 #define A_CIM_MEM_ZONE2_VA 0x7ba8
7672 #define A_CIM_MEM_ZONE2_BA 0x7bac
7673 #define A_CIM_MEM_ZONE2_LEN 0x7bb0
7674 #define A_CIM_MEM_ZONE3_VA 0x7bb4
7675 #define A_CIM_MEM_ZONE3_BA 0x7bb8
7676 #define A_CIM_MEM_ZONE3_LEN 0x7bbc
7677 #define A_CIM_MEM_ZONE4_VA 0x7bc0
7678 #define A_CIM_MEM_ZONE4_BA 0x7bc4
7679 #define A_CIM_MEM_ZONE4_LEN 0x7bc8
7680 #define A_CIM_MEM_ZONE5_VA 0x7bcc
7681 #define A_CIM_MEM_ZONE5_BA 0x7bd0
7682 #define A_CIM_MEM_ZONE5_LEN 0x7bd4
7683 #define A_CIM_MEM_ZONE6_VA 0x7bd8
7684 #define A_CIM_MEM_ZONE6_BA 0x7bdc
7685 #define A_CIM_MEM_ZONE6_LEN 0x7be0
7686 #define A_CIM_MEM_ZONE7_VA 0x7be4
7687 #define A_CIM_MEM_ZONE7_BA 0x7be8
7688 #define A_CIM_MEM_ZONE7_LEN 0x7bec
7689 #define A_CIM_BOOT_LEN 0x7bf0
7692 #define M_BOOTLEN 0xfffffffU
7693 #define V_BOOTLEN(x) ((x) << S_BOOTLEN)
7694 #define G_BOOTLEN(x) (((x) >> S_BOOTLEN) & M_BOOTLEN)
7696 #define A_CIM_GLB_TIMER_CTL 0x7bf4
7698 #define S_TIMER1EN 4
7699 #define V_TIMER1EN(x) ((x) << S_TIMER1EN)
7700 #define F_TIMER1EN V_TIMER1EN(1U)
7702 #define S_TIMER0EN 3
7703 #define V_TIMER0EN(x) ((x) << S_TIMER0EN)
7704 #define F_TIMER0EN V_TIMER0EN(1U)
7707 #define V_TIMEREN(x) ((x) << S_TIMEREN)
7708 #define F_TIMEREN V_TIMEREN(1U)
7710 #define A_CIM_GLB_TIMER 0x7bf8
7711 #define A_CIM_GLB_TIMER_TICK 0x7bfc
7713 #define S_GLBLTTICK 0
7714 #define M_GLBLTTICK 0xffffU
7715 #define V_GLBLTTICK(x) ((x) << S_GLBLTTICK)
7716 #define G_GLBLTTICK(x) (((x) >> S_GLBLTTICK) & M_GLBLTTICK)
7718 #define A_CIM_TIMER0 0x7c00
7719 #define A_CIM_TIMER1 0x7c04
7720 #define A_CIM_DEBUG_ADDR_TIMEOUT 0x7c08
7722 #define S_DADDRTIMEOUT 2
7723 #define M_DADDRTIMEOUT 0x3fffffffU
7724 #define V_DADDRTIMEOUT(x) ((x) << S_DADDRTIMEOUT)
7725 #define G_DADDRTIMEOUT(x) (((x) >> S_DADDRTIMEOUT) & M_DADDRTIMEOUT)
7727 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
7729 #define S_DADDRILLEGAL 2
7730 #define M_DADDRILLEGAL 0x3fffffffU
7731 #define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
7732 #define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)
7734 #define A_CIM_DEBUG_PIF_CAUSE_MASK 0x7c10
7736 #define S_DPIFHOSTMASK 0
7737 #define M_DPIFHOSTMASK 0x1fffffU
7738 #define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK)
7739 #define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK)
7741 #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
7743 #define S_DPIFHUPAMASK 0
7744 #define M_DPIFHUPAMASK 0x7fffffffU
7745 #define V_DPIFHUPAMASK(x) ((x) << S_DPIFHUPAMASK)
7746 #define G_DPIFHUPAMASK(x) (((x) >> S_DPIFHUPAMASK) & M_DPIFHUPAMASK)
7748 #define A_CIM_DEBUG_UP_CAUSE_MASK 0x7c18
7751 #define M_DUPMASK 0x1fffffU
7752 #define V_DUPMASK(x) ((x) << S_DUPMASK)
7753 #define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK)
7755 #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
7757 #define S_DUPUACCMASK 0
7758 #define M_DUPUACCMASK 0x7fffffffU
7759 #define V_DUPUACCMASK(x) ((x) << S_DUPUACCMASK)
7760 #define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK)
7762 #define A_CIM_PERR_INJECT 0x7c20
7763 #define A_CIM_PERR_ENABLE 0x7c24
7766 #define M_PERREN 0x1fffffU
7767 #define V_PERREN(x) ((x) << S_PERREN)
7768 #define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN)
7770 #define A_CIM_EEPROM_BUSY_BIT 0x7c28
7772 #define S_EEPROMBUSY 0
7773 #define V_EEPROMBUSY(x) ((x) << S_EEPROMBUSY)
7774 #define F_EEPROMBUSY V_EEPROMBUSY(1U)
7776 #define A_CIM_MA_TIMER_EN 0x7c2c
7778 #define S_MA_TIMER_ENABLE 0
7779 #define V_MA_TIMER_ENABLE(x) ((x) << S_MA_TIMER_ENABLE)
7780 #define F_MA_TIMER_ENABLE V_MA_TIMER_ENABLE(1U)
7782 #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
7784 #define S_UP_PO_SINGLE_OUTSTANDING 0
7785 #define V_UP_PO_SINGLE_OUTSTANDING(x) ((x) << S_UP_PO_SINGLE_OUTSTANDING)
7786 #define F_UP_PO_SINGLE_OUTSTANDING V_UP_PO_SINGLE_OUTSTANDING(1U)
7788 #define A_CIM_CIM_DEBUG_SPARE 0x7c34
7789 #define A_CIM_UP_OPERATION_FREQ 0x7c38
7791 /* registers for module TP */
7792 #define TP_BASE_ADDR 0x7d00
7794 #define A_TP_IN_CONFIG 0x7d00
7796 #define S_TCPOPTPARSERDISCH3 27
7797 #define V_TCPOPTPARSERDISCH3(x) ((x) << S_TCPOPTPARSERDISCH3)
7798 #define F_TCPOPTPARSERDISCH3 V_TCPOPTPARSERDISCH3(1U)
7800 #define S_TCPOPTPARSERDISCH2 26
7801 #define V_TCPOPTPARSERDISCH2(x) ((x) << S_TCPOPTPARSERDISCH2)
7802 #define F_TCPOPTPARSERDISCH2 V_TCPOPTPARSERDISCH2(1U)
7804 #define S_TCPOPTPARSERDISCH1 25
7805 #define V_TCPOPTPARSERDISCH1(x) ((x) << S_TCPOPTPARSERDISCH1)
7806 #define F_TCPOPTPARSERDISCH1 V_TCPOPTPARSERDISCH1(1U)
7808 #define S_TCPOPTPARSERDISCH0 24
7809 #define V_TCPOPTPARSERDISCH0(x) ((x) << S_TCPOPTPARSERDISCH0)
7810 #define F_TCPOPTPARSERDISCH0 V_TCPOPTPARSERDISCH0(1U)
7812 #define S_CRCPASSPRT3 23
7813 #define V_CRCPASSPRT3(x) ((x) << S_CRCPASSPRT3)
7814 #define F_CRCPASSPRT3 V_CRCPASSPRT3(1U)
7816 #define S_CRCPASSPRT2 22
7817 #define V_CRCPASSPRT2(x) ((x) << S_CRCPASSPRT2)
7818 #define F_CRCPASSPRT2 V_CRCPASSPRT2(1U)
7820 #define S_CRCPASSPRT1 21
7821 #define V_CRCPASSPRT1(x) ((x) << S_CRCPASSPRT1)
7822 #define F_CRCPASSPRT1 V_CRCPASSPRT1(1U)
7824 #define S_CRCPASSPRT0 20
7825 #define V_CRCPASSPRT0(x) ((x) << S_CRCPASSPRT0)
7826 #define F_CRCPASSPRT0 V_CRCPASSPRT0(1U)
7828 #define S_VEPAMODE 19
7829 #define V_VEPAMODE(x) ((x) << S_VEPAMODE)
7830 #define F_VEPAMODE V_VEPAMODE(1U)
7832 #define S_FIPUPEN 18
7833 #define V_FIPUPEN(x) ((x) << S_FIPUPEN)
7834 #define F_FIPUPEN V_FIPUPEN(1U)
7836 #define S_FCOEUPEN 17
7837 #define V_FCOEUPEN(x) ((x) << S_FCOEUPEN)
7838 #define F_FCOEUPEN V_FCOEUPEN(1U)
7840 #define S_FCOEENABLE 16
7841 #define V_FCOEENABLE(x) ((x) << S_FCOEENABLE)
7842 #define F_FCOEENABLE V_FCOEENABLE(1U)
7844 #define S_IPV6ENABLE 15
7845 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
7846 #define F_IPV6ENABLE V_IPV6ENABLE(1U)
7848 #define S_NICMODE 14
7849 #define V_NICMODE(x) ((x) << S_NICMODE)
7850 #define F_NICMODE V_NICMODE(1U)
7852 #define S_ECHECKSUMCHECKTCP 13
7853 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
7854 #define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U)
7856 #define S_ECHECKSUMCHECKIP 12
7857 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
7858 #define F_ECHECKSUMCHECKIP V_ECHECKSUMCHECKIP(1U)
7860 #define S_EREPORTUDPHDRLEN 11
7861 #define V_EREPORTUDPHDRLEN(x) ((x) << S_EREPORTUDPHDRLEN)
7862 #define F_EREPORTUDPHDRLEN V_EREPORTUDPHDRLEN(1U)
7864 #define S_IN_ECPL 10
7865 #define V_IN_ECPL(x) ((x) << S_IN_ECPL)
7866 #define F_IN_ECPL V_IN_ECPL(1U)
7868 #define S_VNTAGENABLE 9
7869 #define V_VNTAGENABLE(x) ((x) << S_VNTAGENABLE)
7870 #define F_VNTAGENABLE V_VNTAGENABLE(1U)
7873 #define V_IN_EETH(x) ((x) << S_IN_EETH)
7874 #define F_IN_EETH V_IN_EETH(1U)
7876 #define S_CCHECKSUMCHECKTCP 6
7877 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
7878 #define F_CCHECKSUMCHECKTCP V_CCHECKSUMCHECKTCP(1U)
7880 #define S_CCHECKSUMCHECKIP 5
7881 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
7882 #define F_CCHECKSUMCHECKIP V_CCHECKSUMCHECKIP(1U)
7885 #define V_CTAG(x) ((x) << S_CTAG)
7886 #define F_CTAG V_CTAG(1U)
7889 #define V_IN_CCPL(x) ((x) << S_IN_CCPL)
7890 #define F_IN_CCPL V_IN_CCPL(1U)
7893 #define V_IN_CETH(x) ((x) << S_IN_CETH)
7894 #define F_IN_CETH V_IN_CETH(1U)
7897 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
7898 #define F_CTUNNEL V_CTUNNEL(1U)
7900 #define A_TP_OUT_CONFIG 0x7d04
7902 #define S_PORTQFCEN 28
7903 #define M_PORTQFCEN 0xfU
7904 #define V_PORTQFCEN(x) ((x) << S_PORTQFCEN)
7905 #define G_PORTQFCEN(x) (((x) >> S_PORTQFCEN) & M_PORTQFCEN)
7907 #define S_EPKTDISTCHN3 23
7908 #define V_EPKTDISTCHN3(x) ((x) << S_EPKTDISTCHN3)
7909 #define F_EPKTDISTCHN3 V_EPKTDISTCHN3(1U)
7911 #define S_EPKTDISTCHN2 22
7912 #define V_EPKTDISTCHN2(x) ((x) << S_EPKTDISTCHN2)
7913 #define F_EPKTDISTCHN2 V_EPKTDISTCHN2(1U)
7915 #define S_EPKTDISTCHN1 21
7916 #define V_EPKTDISTCHN1(x) ((x) << S_EPKTDISTCHN1)
7917 #define F_EPKTDISTCHN1 V_EPKTDISTCHN1(1U)
7919 #define S_EPKTDISTCHN0 20
7920 #define V_EPKTDISTCHN0(x) ((x) << S_EPKTDISTCHN0)
7921 #define F_EPKTDISTCHN0 V_EPKTDISTCHN0(1U)
7923 #define S_TTLMODE 19
7924 #define V_TTLMODE(x) ((x) << S_TTLMODE)
7925 #define F_TTLMODE V_TTLMODE(1U)
7927 #define S_EQFCDMAC 18
7928 #define V_EQFCDMAC(x) ((x) << S_EQFCDMAC)
7929 #define F_EQFCDMAC V_EQFCDMAC(1U)
7931 #define S_ELPBKINCMPSSTAT 17
7932 #define V_ELPBKINCMPSSTAT(x) ((x) << S_ELPBKINCMPSSTAT)
7933 #define F_ELPBKINCMPSSTAT V_ELPBKINCMPSSTAT(1U)
7935 #define S_IPIDSPLITMODE 16
7936 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
7937 #define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U)
7939 #define S_VLANEXTENABLEPORT3 15
7940 #define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3)
7941 #define F_VLANEXTENABLEPORT3 V_VLANEXTENABLEPORT3(1U)
7943 #define S_VLANEXTENABLEPORT2 14
7944 #define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2)
7945 #define F_VLANEXTENABLEPORT2 V_VLANEXTENABLEPORT2(1U)
7947 #define S_VLANEXTENABLEPORT1 13
7948 #define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1)
7949 #define F_VLANEXTENABLEPORT1 V_VLANEXTENABLEPORT1(1U)
7951 #define S_VLANEXTENABLEPORT0 12
7952 #define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0)
7953 #define F_VLANEXTENABLEPORT0 V_VLANEXTENABLEPORT0(1U)
7955 #define S_ECHECKSUMINSERTTCP 11
7956 #define V_ECHECKSUMINSERTTCP(x) ((x) << S_ECHECKSUMINSERTTCP)
7957 #define F_ECHECKSUMINSERTTCP V_ECHECKSUMINSERTTCP(1U)
7959 #define S_ECHECKSUMINSERTIP 10
7960 #define V_ECHECKSUMINSERTIP(x) ((x) << S_ECHECKSUMINSERTIP)
7961 #define F_ECHECKSUMINSERTIP V_ECHECKSUMINSERTIP(1U)
7964 #define V_ECPL(x) ((x) << S_ECPL)
7965 #define F_ECPL V_ECPL(1U)
7967 #define S_EPRIORITY 7
7968 #define V_EPRIORITY(x) ((x) << S_EPRIORITY)
7969 #define F_EPRIORITY V_EPRIORITY(1U)
7971 #define S_EETHERNET 6
7972 #define V_EETHERNET(x) ((x) << S_EETHERNET)
7973 #define F_EETHERNET V_EETHERNET(1U)
7975 #define S_CCHECKSUMINSERTTCP 5
7976 #define V_CCHECKSUMINSERTTCP(x) ((x) << S_CCHECKSUMINSERTTCP)
7977 #define F_CCHECKSUMINSERTTCP V_CCHECKSUMINSERTTCP(1U)
7979 #define S_CCHECKSUMINSERTIP 4
7980 #define V_CCHECKSUMINSERTIP(x) ((x) << S_CCHECKSUMINSERTIP)
7981 #define F_CCHECKSUMINSERTIP V_CCHECKSUMINSERTIP(1U)
7984 #define V_CCPL(x) ((x) << S_CCPL)
7985 #define F_CCPL V_CCPL(1U)
7987 #define S_CETHERNET 0
7988 #define V_CETHERNET(x) ((x) << S_CETHERNET)
7989 #define F_CETHERNET V_CETHERNET(1U)
7991 #define A_TP_GLOBAL_CONFIG 0x7d08
7993 #define S_SYNCOOKIEPARAMS 26
7994 #define M_SYNCOOKIEPARAMS 0x3fU
7995 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
7996 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
7998 #define S_RXFLOWCONTROLDISABLE 25
7999 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
8000 #define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U)
8002 #define S_TXPACINGENABLE 24
8003 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
8004 #define F_TXPACINGENABLE V_TXPACINGENABLE(1U)
8006 #define S_ATTACKFILTERENABLE 23
8007 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
8008 #define F_ATTACKFILTERENABLE V_ATTACKFILTERENABLE(1U)
8010 #define S_SYNCOOKIENOOPTIONS 22
8011 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
8012 #define F_SYNCOOKIENOOPTIONS V_SYNCOOKIENOOPTIONS(1U)
8014 #define S_PROTECTEDMODE 21
8015 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
8016 #define F_PROTECTEDMODE V_PROTECTEDMODE(1U)
8018 #define S_PINGDROP 20
8019 #define V_PINGDROP(x) ((x) << S_PINGDROP)
8020 #define F_PINGDROP V_PINGDROP(1U)
8022 #define S_FRAGMENTDROP 19
8023 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
8024 #define F_FRAGMENTDROP V_FRAGMENTDROP(1U)
8026 #define S_FIVETUPLELOOKUP 17
8027 #define M_FIVETUPLELOOKUP 0x3U
8028 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
8029 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
8031 #define S_OFDMPSSTATS 16
8032 #define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS)
8033 #define F_OFDMPSSTATS V_OFDMPSSTATS(1U)
8035 #define S_DONTFRAGMENT 15
8036 #define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT)
8037 #define F_DONTFRAGMENT V_DONTFRAGMENT(1U)
8039 #define S_IPIDENTSPLIT 14
8040 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
8041 #define F_IPIDENTSPLIT V_IPIDENTSPLIT(1U)
8043 #define S_IPCHECKSUMOFFLOAD 13
8044 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
8045 #define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U)
8047 #define S_UDPCHECKSUMOFFLOAD 12
8048 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
8049 #define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U)
8051 #define S_TCPCHECKSUMOFFLOAD 11
8052 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
8053 #define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U)
8055 #define S_RSSLOOPBACKENABLE 10
8056 #define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE)
8057 #define F_RSSLOOPBACKENABLE V_RSSLOOPBACKENABLE(1U)
8059 #define S_TCAMSERVERUSE 8
8060 #define M_TCAMSERVERUSE 0x3U
8061 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
8062 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
8065 #define M_IPTTL 0xffU
8066 #define V_IPTTL(x) ((x) << S_IPTTL)
8067 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
8069 #define A_TP_DB_CONFIG 0x7d0c
8071 #define S_DBMAXOPCNT 24
8072 #define M_DBMAXOPCNT 0xffU
8073 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
8074 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
8076 #define S_CXMAXOPCNTDISABLE 23
8077 #define V_CXMAXOPCNTDISABLE(x) ((x) << S_CXMAXOPCNTDISABLE)
8078 #define F_CXMAXOPCNTDISABLE V_CXMAXOPCNTDISABLE(1U)
8080 #define S_CXMAXOPCNT 16
8081 #define M_CXMAXOPCNT 0x7fU
8082 #define V_CXMAXOPCNT(x) ((x) << S_CXMAXOPCNT)
8083 #define G_CXMAXOPCNT(x) (((x) >> S_CXMAXOPCNT) & M_CXMAXOPCNT)
8085 #define S_TXMAXOPCNTDISABLE 15
8086 #define V_TXMAXOPCNTDISABLE(x) ((x) << S_TXMAXOPCNTDISABLE)
8087 #define F_TXMAXOPCNTDISABLE V_TXMAXOPCNTDISABLE(1U)
8089 #define S_TXMAXOPCNT 8
8090 #define M_TXMAXOPCNT 0x7fU
8091 #define V_TXMAXOPCNT(x) ((x) << S_TXMAXOPCNT)
8092 #define G_TXMAXOPCNT(x) (((x) >> S_TXMAXOPCNT) & M_TXMAXOPCNT)
8094 #define S_RXMAXOPCNTDISABLE 7
8095 #define V_RXMAXOPCNTDISABLE(x) ((x) << S_RXMAXOPCNTDISABLE)
8096 #define F_RXMAXOPCNTDISABLE V_RXMAXOPCNTDISABLE(1U)
8098 #define S_RXMAXOPCNT 0
8099 #define M_RXMAXOPCNT 0x7fU
8100 #define V_RXMAXOPCNT(x) ((x) << S_RXMAXOPCNT)
8101 #define G_RXMAXOPCNT(x) (((x) >> S_RXMAXOPCNT) & M_RXMAXOPCNT)
8103 #define A_TP_CMM_TCB_BASE 0x7d10
8104 #define A_TP_CMM_MM_BASE 0x7d14
8105 #define A_TP_CMM_TIMER_BASE 0x7d18
8106 #define A_TP_CMM_MM_FLST_SIZE 0x7d1c
8108 #define S_RXPOOLSIZE 16
8109 #define M_RXPOOLSIZE 0xffffU
8110 #define V_RXPOOLSIZE(x) ((x) << S_RXPOOLSIZE)
8111 #define G_RXPOOLSIZE(x) (((x) >> S_RXPOOLSIZE) & M_RXPOOLSIZE)
8113 #define S_TXPOOLSIZE 0
8114 #define M_TXPOOLSIZE 0xffffU
8115 #define V_TXPOOLSIZE(x) ((x) << S_TXPOOLSIZE)
8116 #define G_TXPOOLSIZE(x) (((x) >> S_TXPOOLSIZE) & M_TXPOOLSIZE)
8118 #define A_TP_PMM_TX_BASE 0x7d20
8119 #define A_TP_PMM_DEFRAG_BASE 0x7d24
8120 #define A_TP_PMM_RX_BASE 0x7d28
8121 #define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
8122 #define A_TP_PMM_RX_MAX_PAGE 0x7d30
8124 #define S_PMRXNUMCHN 31
8125 #define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN)
8126 #define F_PMRXNUMCHN V_PMRXNUMCHN(1U)
8128 #define S_PMRXMAXPAGE 0
8129 #define M_PMRXMAXPAGE 0x1fffffU
8130 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
8131 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
8133 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34
8134 #define A_TP_PMM_TX_MAX_PAGE 0x7d38
8136 #define S_PMTXNUMCHN 30
8137 #define M_PMTXNUMCHN 0x3U
8138 #define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN)
8139 #define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN)
8141 #define S_PMTXMAXPAGE 0
8142 #define M_PMTXMAXPAGE 0x1fffffU
8143 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
8144 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
8146 #define A_TP_TCP_OPTIONS 0x7d40
8148 #define S_MTUDEFAULT 16
8149 #define M_MTUDEFAULT 0xffffU
8150 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
8151 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
8153 #define S_MTUENABLE 10
8154 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
8155 #define F_MTUENABLE V_MTUENABLE(1U)
8158 #define V_SACKTX(x) ((x) << S_SACKTX)
8159 #define F_SACKTX V_SACKTX(1U)
8162 #define V_SACKRX(x) ((x) << S_SACKRX)
8163 #define F_SACKRX V_SACKRX(1U)
8165 #define S_SACKMODE 4
8166 #define M_SACKMODE 0x3U
8167 #define V_SACKMODE(x) ((x) << S_SACKMODE)
8168 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
8170 #define S_WINDOWSCALEMODE 2
8171 #define M_WINDOWSCALEMODE 0x3U
8172 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
8173 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
8175 #define S_TIMESTAMPSMODE 0
8176 #define M_TIMESTAMPSMODE 0x3U
8177 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
8178 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
8180 #define A_TP_DACK_CONFIG 0x7d44
8182 #define S_AUTOSTATE3 30
8183 #define M_AUTOSTATE3 0x3U
8184 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
8185 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
8187 #define S_AUTOSTATE2 28
8188 #define M_AUTOSTATE2 0x3U
8189 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
8190 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
8192 #define S_AUTOSTATE1 26
8193 #define M_AUTOSTATE1 0x3U
8194 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
8195 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
8197 #define S_BYTETHRESHOLD 8
8198 #define M_BYTETHRESHOLD 0x3ffffU
8199 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
8200 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
8202 #define S_MSSTHRESHOLD 4
8203 #define M_MSSTHRESHOLD 0x7U
8204 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
8205 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
8207 #define S_AUTOCAREFUL 2
8208 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
8209 #define F_AUTOCAREFUL V_AUTOCAREFUL(1U)
8211 #define S_AUTOENABLE 1
8212 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
8213 #define F_AUTOENABLE V_AUTOENABLE(1U)
8216 #define V_MODE(x) ((x) << S_MODE)
8217 #define F_MODE V_MODE(1U)
8219 #define A_TP_PC_CONFIG 0x7d48
8221 #define S_CMCACHEDISABLE 31
8222 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
8223 #define F_CMCACHEDISABLE V_CMCACHEDISABLE(1U)
8225 #define S_ENABLEOCSPIFULL 30
8226 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
8227 #define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U)
8229 #define S_ENABLEFLMERRORDDP 29
8230 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
8231 #define F_ENABLEFLMERRORDDP V_ENABLEFLMERRORDDP(1U)
8233 #define S_LOCKTID 28
8234 #define V_LOCKTID(x) ((x) << S_LOCKTID)
8235 #define F_LOCKTID V_LOCKTID(1U)
8237 #define S_DISABLEINVPEND 27
8238 #define V_DISABLEINVPEND(x) ((x) << S_DISABLEINVPEND)
8239 #define F_DISABLEINVPEND V_DISABLEINVPEND(1U)
8241 #define S_ENABLEFILTERCOUNT 26
8242 #define V_ENABLEFILTERCOUNT(x) ((x) << S_ENABLEFILTERCOUNT)
8243 #define F_ENABLEFILTERCOUNT V_ENABLEFILTERCOUNT(1U)
8245 #define S_RDDPCONGEN 25
8246 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
8247 #define F_RDDPCONGEN V_RDDPCONGEN(1U)
8249 #define S_ENABLEONFLYPDU 24
8250 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
8251 #define F_ENABLEONFLYPDU V_ENABLEONFLYPDU(1U)
8253 #define S_ENABLEMINRCVWND 23
8254 #define V_ENABLEMINRCVWND(x) ((x) << S_ENABLEMINRCVWND)
8255 #define F_ENABLEMINRCVWND V_ENABLEMINRCVWND(1U)
8257 #define S_ENABLEMAXRCVWND 22
8258 #define V_ENABLEMAXRCVWND(x) ((x) << S_ENABLEMAXRCVWND)
8259 #define F_ENABLEMAXRCVWND V_ENABLEMAXRCVWND(1U)
8261 #define S_TXDATAACKRATEENABLE 21
8262 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
8263 #define F_TXDATAACKRATEENABLE V_TXDATAACKRATEENABLE(1U)
8265 #define S_TXDEFERENABLE 20
8266 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
8267 #define F_TXDEFERENABLE V_TXDEFERENABLE(1U)
8269 #define S_RXCONGESTIONMODE 19
8270 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
8271 #define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U)
8273 #define S_HEARBEATONCEDACK 18
8274 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
8275 #define F_HEARBEATONCEDACK V_HEARBEATONCEDACK(1U)
8277 #define S_HEARBEATONCEHEAP 17
8278 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
8279 #define F_HEARBEATONCEHEAP V_HEARBEATONCEHEAP(1U)
8281 #define S_HEARBEATDACK 16
8282 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
8283 #define F_HEARBEATDACK V_HEARBEATDACK(1U)
8285 #define S_TXCONGESTIONMODE 15
8286 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
8287 #define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U)
8289 #define S_ACCEPTLATESTRCVADV 14
8290 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
8291 #define F_ACCEPTLATESTRCVADV V_ACCEPTLATESTRCVADV(1U)
8293 #define S_DISABLESYNDATA 13
8294 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
8295 #define F_DISABLESYNDATA V_DISABLESYNDATA(1U)
8297 #define S_DISABLEWINDOWPSH 12
8298 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
8299 #define F_DISABLEWINDOWPSH V_DISABLEWINDOWPSH(1U)
8301 #define S_DISABLEFINOLDDATA 11
8302 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
8303 #define F_DISABLEFINOLDDATA V_DISABLEFINOLDDATA(1U)
8305 #define S_ENABLEFLMERROR 10
8306 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
8307 #define F_ENABLEFLMERROR V_ENABLEFLMERROR(1U)
8309 #define S_ENABLEOPTMTU 9
8310 #define V_ENABLEOPTMTU(x) ((x) << S_ENABLEOPTMTU)
8311 #define F_ENABLEOPTMTU V_ENABLEOPTMTU(1U)
8313 #define S_FILTERPEERFIN 8
8314 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
8315 #define F_FILTERPEERFIN V_FILTERPEERFIN(1U)
8317 #define S_ENABLEFEEDBACKSEND 7
8318 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
8319 #define F_ENABLEFEEDBACKSEND V_ENABLEFEEDBACKSEND(1U)
8321 #define S_ENABLERDMAERROR 6
8322 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
8323 #define F_ENABLERDMAERROR V_ENABLERDMAERROR(1U)
8325 #define S_ENABLEDDPFLOWCONTROL 5
8326 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
8327 #define F_ENABLEDDPFLOWCONTROL V_ENABLEDDPFLOWCONTROL(1U)
8329 #define S_DISABLEHELDFIN 4
8330 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
8331 #define F_DISABLEHELDFIN V_DISABLEHELDFIN(1U)
8333 #define S_ENABLEOFDOVLAN 3
8334 #define V_ENABLEOFDOVLAN(x) ((x) << S_ENABLEOFDOVLAN)
8335 #define F_ENABLEOFDOVLAN V_ENABLEOFDOVLAN(1U)
8337 #define S_DISABLETIMEWAIT 2
8338 #define V_DISABLETIMEWAIT(x) ((x) << S_DISABLETIMEWAIT)
8339 #define F_DISABLETIMEWAIT V_DISABLETIMEWAIT(1U)
8341 #define S_ENABLEVLANCHECK 1
8342 #define V_ENABLEVLANCHECK(x) ((x) << S_ENABLEVLANCHECK)
8343 #define F_ENABLEVLANCHECK V_ENABLEVLANCHECK(1U)
8345 #define S_TXDATAACKPAGEENABLE 0
8346 #define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE)
8347 #define F_TXDATAACKPAGEENABLE V_TXDATAACKPAGEENABLE(1U)
8349 #define A_TP_PC_CONFIG2 0x7d4c
8351 #define S_ENABLEMTUVFMODE 31
8352 #define V_ENABLEMTUVFMODE(x) ((x) << S_ENABLEMTUVFMODE)
8353 #define F_ENABLEMTUVFMODE V_ENABLEMTUVFMODE(1U)
8355 #define S_ENABLEMIBVFMODE 30
8356 #define V_ENABLEMIBVFMODE(x) ((x) << S_ENABLEMIBVFMODE)
8357 #define F_ENABLEMIBVFMODE V_ENABLEMIBVFMODE(1U)
8359 #define S_DISABLELBKCHECK 29
8360 #define V_DISABLELBKCHECK(x) ((x) << S_DISABLELBKCHECK)
8361 #define F_DISABLELBKCHECK V_DISABLELBKCHECK(1U)
8363 #define S_ENABLEURGDDPOFF 28
8364 #define V_ENABLEURGDDPOFF(x) ((x) << S_ENABLEURGDDPOFF)
8365 #define F_ENABLEURGDDPOFF V_ENABLEURGDDPOFF(1U)
8367 #define S_ENABLEFILTERLPBK 27
8368 #define V_ENABLEFILTERLPBK(x) ((x) << S_ENABLEFILTERLPBK)
8369 #define F_ENABLEFILTERLPBK V_ENABLEFILTERLPBK(1U)
8371 #define S_DISABLETBLMMGR 26
8372 #define V_DISABLETBLMMGR(x) ((x) << S_DISABLETBLMMGR)
8373 #define F_DISABLETBLMMGR V_DISABLETBLMMGR(1U)
8375 #define S_CNGRECSNDNXT 25
8376 #define V_CNGRECSNDNXT(x) ((x) << S_CNGRECSNDNXT)
8377 #define F_CNGRECSNDNXT V_CNGRECSNDNXT(1U)
8379 #define S_ENABLELBKCHN 24
8380 #define V_ENABLELBKCHN(x) ((x) << S_ENABLELBKCHN)
8381 #define F_ENABLELBKCHN V_ENABLELBKCHN(1U)
8383 #define S_ENABLELROECN 23
8384 #define V_ENABLELROECN(x) ((x) << S_ENABLELROECN)
8385 #define F_ENABLELROECN V_ENABLELROECN(1U)
8387 #define S_ENABLEPCMDCHECK 22
8388 #define V_ENABLEPCMDCHECK(x) ((x) << S_ENABLEPCMDCHECK)
8389 #define F_ENABLEPCMDCHECK V_ENABLEPCMDCHECK(1U)
8391 #define S_ENABLEELBKAFULL 21
8392 #define V_ENABLEELBKAFULL(x) ((x) << S_ENABLEELBKAFULL)
8393 #define F_ENABLEELBKAFULL V_ENABLEELBKAFULL(1U)
8395 #define S_ENABLECLBKAFULL 20
8396 #define V_ENABLECLBKAFULL(x) ((x) << S_ENABLECLBKAFULL)
8397 #define F_ENABLECLBKAFULL V_ENABLECLBKAFULL(1U)
8399 #define S_ENABLEOESPIFULL 19
8400 #define V_ENABLEOESPIFULL(x) ((x) << S_ENABLEOESPIFULL)
8401 #define F_ENABLEOESPIFULL V_ENABLEOESPIFULL(1U)
8403 #define S_DISABLEHITCHECK 18
8404 #define V_DISABLEHITCHECK(x) ((x) << S_DISABLEHITCHECK)
8405 #define F_DISABLEHITCHECK V_DISABLEHITCHECK(1U)
8407 #define S_ENABLERSSERRCHECK 17
8408 #define V_ENABLERSSERRCHECK(x) ((x) << S_ENABLERSSERRCHECK)
8409 #define F_ENABLERSSERRCHECK V_ENABLERSSERRCHECK(1U)
8411 #define S_DISABLENEWPSHFLAG 16
8412 #define V_DISABLENEWPSHFLAG(x) ((x) << S_DISABLENEWPSHFLAG)
8413 #define F_DISABLENEWPSHFLAG V_DISABLENEWPSHFLAG(1U)
8415 #define S_ENABLERDDPRCVADVCLR 15
8416 #define V_ENABLERDDPRCVADVCLR(x) ((x) << S_ENABLERDDPRCVADVCLR)
8417 #define F_ENABLERDDPRCVADVCLR V_ENABLERDDPRCVADVCLR(1U)
8419 #define S_ENABLETXDATAARPMISS 14
8420 #define V_ENABLETXDATAARPMISS(x) ((x) << S_ENABLETXDATAARPMISS)
8421 #define F_ENABLETXDATAARPMISS V_ENABLETXDATAARPMISS(1U)
8423 #define S_ENABLEARPMISS 13
8424 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
8425 #define F_ENABLEARPMISS V_ENABLEARPMISS(1U)
8427 #define S_ENABLERSTPAWS 12
8428 #define V_ENABLERSTPAWS(x) ((x) << S_ENABLERSTPAWS)
8429 #define F_ENABLERSTPAWS V_ENABLERSTPAWS(1U)
8431 #define S_ENABLEIPV6RSS 11
8432 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
8433 #define F_ENABLEIPV6RSS V_ENABLEIPV6RSS(1U)
8435 #define S_ENABLENONOFDHYBRSS 10
8436 #define V_ENABLENONOFDHYBRSS(x) ((x) << S_ENABLENONOFDHYBRSS)
8437 #define F_ENABLENONOFDHYBRSS V_ENABLENONOFDHYBRSS(1U)
8439 #define S_ENABLEUDP4TUPRSS 9
8440 #define V_ENABLEUDP4TUPRSS(x) ((x) << S_ENABLEUDP4TUPRSS)
8441 #define F_ENABLEUDP4TUPRSS V_ENABLEUDP4TUPRSS(1U)
8443 #define S_ENABLERXPKTTMSTPRSS 8
8444 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
8445 #define F_ENABLERXPKTTMSTPRSS V_ENABLERXPKTTMSTPRSS(1U)
8447 #define S_ENABLEEPCMDAFULL 7
8448 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
8449 #define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U)
8451 #define S_ENABLECPCMDAFULL 6
8452 #define V_ENABLECPCMDAFULL(x) ((x) << S_ENABLECPCMDAFULL)
8453 #define F_ENABLECPCMDAFULL V_ENABLECPCMDAFULL(1U)
8455 #define S_ENABLEEHDRAFULL 5
8456 #define V_ENABLEEHDRAFULL(x) ((x) << S_ENABLEEHDRAFULL)
8457 #define F_ENABLEEHDRAFULL V_ENABLEEHDRAFULL(1U)
8459 #define S_ENABLECHDRAFULL 4
8460 #define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
8461 #define F_ENABLECHDRAFULL V_ENABLECHDRAFULL(1U)
8463 #define S_ENABLEEMACAFULL 3
8464 #define V_ENABLEEMACAFULL(x) ((x) << S_ENABLEEMACAFULL)
8465 #define F_ENABLEEMACAFULL V_ENABLEEMACAFULL(1U)
8467 #define S_ENABLENONOFDTIDRSS 2
8468 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
8469 #define F_ENABLENONOFDTIDRSS V_ENABLENONOFDTIDRSS(1U)
8471 #define S_ENABLENONOFDTCBRSS 1
8472 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
8473 #define F_ENABLENONOFDTCBRSS V_ENABLENONOFDTCBRSS(1U)
8475 #define S_ENABLETNLOFDCLOSED 0
8476 #define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED)
8477 #define F_ENABLETNLOFDCLOSED V_ENABLETNLOFDCLOSED(1U)
8479 #define A_TP_TCP_BACKOFF_REG0 0x7d50
8481 #define S_TIMERBACKOFFINDEX3 24
8482 #define M_TIMERBACKOFFINDEX3 0xffU
8483 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
8484 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
8486 #define S_TIMERBACKOFFINDEX2 16
8487 #define M_TIMERBACKOFFINDEX2 0xffU
8488 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
8489 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
8491 #define S_TIMERBACKOFFINDEX1 8
8492 #define M_TIMERBACKOFFINDEX1 0xffU
8493 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
8494 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
8496 #define S_TIMERBACKOFFINDEX0 0
8497 #define M_TIMERBACKOFFINDEX0 0xffU
8498 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
8499 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
8501 #define A_TP_TCP_BACKOFF_REG1 0x7d54
8503 #define S_TIMERBACKOFFINDEX7 24
8504 #define M_TIMERBACKOFFINDEX7 0xffU
8505 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
8506 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
8508 #define S_TIMERBACKOFFINDEX6 16
8509 #define M_TIMERBACKOFFINDEX6 0xffU
8510 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
8511 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
8513 #define S_TIMERBACKOFFINDEX5 8
8514 #define M_TIMERBACKOFFINDEX5 0xffU
8515 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
8516 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
8518 #define S_TIMERBACKOFFINDEX4 0
8519 #define M_TIMERBACKOFFINDEX4 0xffU
8520 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
8521 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
8523 #define A_TP_TCP_BACKOFF_REG2 0x7d58
8525 #define S_TIMERBACKOFFINDEX11 24
8526 #define M_TIMERBACKOFFINDEX11 0xffU
8527 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
8528 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
8530 #define S_TIMERBACKOFFINDEX10 16
8531 #define M_TIMERBACKOFFINDEX10 0xffU
8532 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
8533 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
8535 #define S_TIMERBACKOFFINDEX9 8
8536 #define M_TIMERBACKOFFINDEX9 0xffU
8537 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
8538 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
8540 #define S_TIMERBACKOFFINDEX8 0
8541 #define M_TIMERBACKOFFINDEX8 0xffU
8542 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
8543 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
8545 #define A_TP_TCP_BACKOFF_REG3 0x7d5c
8547 #define S_TIMERBACKOFFINDEX15 24
8548 #define M_TIMERBACKOFFINDEX15 0xffU
8549 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
8550 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
8552 #define S_TIMERBACKOFFINDEX14 16
8553 #define M_TIMERBACKOFFINDEX14 0xffU
8554 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
8555 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
8557 #define S_TIMERBACKOFFINDEX13 8
8558 #define M_TIMERBACKOFFINDEX13 0xffU
8559 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
8560 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
8562 #define S_TIMERBACKOFFINDEX12 0
8563 #define M_TIMERBACKOFFINDEX12 0xffU
8564 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
8565 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
8567 #define A_TP_PARA_REG0 0x7d60
8569 #define S_INITCWNDIDLE 27
8570 #define V_INITCWNDIDLE(x) ((x) << S_INITCWNDIDLE)
8571 #define F_INITCWNDIDLE V_INITCWNDIDLE(1U)
8573 #define S_INITCWND 24
8574 #define M_INITCWND 0x7U
8575 #define V_INITCWND(x) ((x) << S_INITCWND)
8576 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
8578 #define S_DUPACKTHRESH 20
8579 #define M_DUPACKTHRESH 0xfU
8580 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
8581 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
8583 #define S_CPLERRENABLE 12
8584 #define V_CPLERRENABLE(x) ((x) << S_CPLERRENABLE)
8585 #define F_CPLERRENABLE V_CPLERRENABLE(1U)
8587 #define S_FASTTNLCNT 11
8588 #define V_FASTTNLCNT(x) ((x) << S_FASTTNLCNT)
8589 #define F_FASTTNLCNT V_FASTTNLCNT(1U)
8591 #define S_FASTTBLCNT 10
8592 #define V_FASTTBLCNT(x) ((x) << S_FASTTBLCNT)
8593 #define F_FASTTBLCNT V_FASTTBLCNT(1U)
8595 #define S_TPTCAMKEY 9
8596 #define V_TPTCAMKEY(x) ((x) << S_TPTCAMKEY)
8597 #define F_TPTCAMKEY V_TPTCAMKEY(1U)
8600 #define V_SWSMODE(x) ((x) << S_SWSMODE)
8601 #define F_SWSMODE V_SWSMODE(1U)
8603 #define S_TSMPMODE 6
8604 #define M_TSMPMODE 0x3U
8605 #define V_TSMPMODE(x) ((x) << S_TSMPMODE)
8606 #define G_TSMPMODE(x) (((x) >> S_TSMPMODE) & M_TSMPMODE)
8608 #define S_BYTECOUNTLIMIT 4
8609 #define M_BYTECOUNTLIMIT 0x3U
8610 #define V_BYTECOUNTLIMIT(x) ((x) << S_BYTECOUNTLIMIT)
8611 #define G_BYTECOUNTLIMIT(x) (((x) >> S_BYTECOUNTLIMIT) & M_BYTECOUNTLIMIT)
8613 #define S_SWSSHOVE 3
8614 #define V_SWSSHOVE(x) ((x) << S_SWSSHOVE)
8615 #define F_SWSSHOVE V_SWSSHOVE(1U)
8617 #define S_TBLTIMER 2
8618 #define V_TBLTIMER(x) ((x) << S_TBLTIMER)
8619 #define F_TBLTIMER V_TBLTIMER(1U)
8622 #define V_RXTPACE(x) ((x) << S_RXTPACE)
8623 #define F_RXTPACE V_RXTPACE(1U)
8625 #define S_SWSTIMER 0
8626 #define V_SWSTIMER(x) ((x) << S_SWSTIMER)
8627 #define F_SWSTIMER V_SWSTIMER(1U)
8629 #define A_TP_PARA_REG1 0x7d64
8631 #define S_INITRWND 16
8632 #define M_INITRWND 0xffffU
8633 #define V_INITRWND(x) ((x) << S_INITRWND)
8634 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
8636 #define S_INITIALSSTHRESH 0
8637 #define M_INITIALSSTHRESH 0xffffU
8638 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
8639 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
8641 #define A_TP_PARA_REG2 0x7d68
8643 #define S_MAXRXDATA 16
8644 #define M_MAXRXDATA 0xffffU
8645 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
8646 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
8648 #define S_RXCOALESCESIZE 0
8649 #define M_RXCOALESCESIZE 0xffffU
8650 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
8651 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
8653 #define A_TP_PARA_REG3 0x7d6c
8655 #define S_ENABLETNLCNGLPBK 31
8656 #define V_ENABLETNLCNGLPBK(x) ((x) << S_ENABLETNLCNGLPBK)
8657 #define F_ENABLETNLCNGLPBK V_ENABLETNLCNGLPBK(1U)
8659 #define S_ENABLETNLCNGFIFO 30
8660 #define V_ENABLETNLCNGFIFO(x) ((x) << S_ENABLETNLCNGFIFO)
8661 #define F_ENABLETNLCNGFIFO V_ENABLETNLCNGFIFO(1U)
8663 #define S_ENABLETNLCNGHDR 29
8664 #define V_ENABLETNLCNGHDR(x) ((x) << S_ENABLETNLCNGHDR)
8665 #define F_ENABLETNLCNGHDR V_ENABLETNLCNGHDR(1U)
8667 #define S_ENABLETNLCNGSGE 28
8668 #define V_ENABLETNLCNGSGE(x) ((x) << S_ENABLETNLCNGSGE)
8669 #define F_ENABLETNLCNGSGE V_ENABLETNLCNGSGE(1U)
8671 #define S_RXMACCHECK 27
8672 #define V_RXMACCHECK(x) ((x) << S_RXMACCHECK)
8673 #define F_RXMACCHECK V_RXMACCHECK(1U)
8675 #define S_RXSYNFILTER 26
8676 #define V_RXSYNFILTER(x) ((x) << S_RXSYNFILTER)
8677 #define F_RXSYNFILTER V_RXSYNFILTER(1U)
8679 #define S_CNGCTRLECN 25
8680 #define V_CNGCTRLECN(x) ((x) << S_CNGCTRLECN)
8681 #define F_CNGCTRLECN V_CNGCTRLECN(1U)
8683 #define S_RXDDPOFFINIT 24
8684 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
8685 #define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U)
8687 #define S_TUNNELCNGDROP3 23
8688 #define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3)
8689 #define F_TUNNELCNGDROP3 V_TUNNELCNGDROP3(1U)
8691 #define S_TUNNELCNGDROP2 22
8692 #define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2)
8693 #define F_TUNNELCNGDROP2 V_TUNNELCNGDROP2(1U)
8695 #define S_TUNNELCNGDROP1 21
8696 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
8697 #define F_TUNNELCNGDROP1 V_TUNNELCNGDROP1(1U)
8699 #define S_TUNNELCNGDROP0 20
8700 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
8701 #define F_TUNNELCNGDROP0 V_TUNNELCNGDROP0(1U)
8703 #define S_TXDATAACKIDX 16
8704 #define M_TXDATAACKIDX 0xfU
8705 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
8706 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
8708 #define S_RXFRAGENABLE 12
8709 #define M_RXFRAGENABLE 0x7U
8710 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
8711 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
8713 #define S_TXPACEFIXEDSTRICT 11
8714 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
8715 #define F_TXPACEFIXEDSTRICT V_TXPACEFIXEDSTRICT(1U)
8717 #define S_TXPACEAUTOSTRICT 10
8718 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
8719 #define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U)
8721 #define S_TXPACEFIXED 9
8722 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
8723 #define F_TXPACEFIXED V_TXPACEFIXED(1U)
8725 #define S_TXPACEAUTO 8
8726 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
8727 #define F_TXPACEAUTO V_TXPACEAUTO(1U)
8729 #define S_RXCHNTUNNEL 7
8730 #define V_RXCHNTUNNEL(x) ((x) << S_RXCHNTUNNEL)
8731 #define F_RXCHNTUNNEL V_RXCHNTUNNEL(1U)
8733 #define S_RXURGTUNNEL 6
8734 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
8735 #define F_RXURGTUNNEL V_RXURGTUNNEL(1U)
8737 #define S_RXURGMODE 5
8738 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
8739 #define F_RXURGMODE V_RXURGMODE(1U)
8741 #define S_TXURGMODE 4
8742 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
8743 #define F_TXURGMODE V_TXURGMODE(1U)
8745 #define S_CNGCTRLMODE 2
8746 #define M_CNGCTRLMODE 0x3U
8747 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
8748 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
8750 #define S_RXCOALESCEENABLE 1
8751 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
8752 #define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U)
8754 #define S_RXCOALESCEPSHEN 0
8755 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
8756 #define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U)
8758 #define A_TP_PARA_REG4 0x7d70
8760 #define S_HIGHSPEEDCFG 24
8761 #define M_HIGHSPEEDCFG 0xffU
8762 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
8763 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
8765 #define S_NEWRENOCFG 16
8766 #define M_NEWRENOCFG 0xffU
8767 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
8768 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
8770 #define S_TAHOECFG 8
8771 #define M_TAHOECFG 0xffU
8772 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
8773 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
8776 #define M_RENOCFG 0xffU
8777 #define V_RENOCFG(x) ((x) << S_RENOCFG)
8778 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
8780 #define A_TP_PARA_REG5 0x7d74
8782 #define S_INDICATESIZE 16
8783 #define M_INDICATESIZE 0xffffU
8784 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
8785 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
8787 #define S_MAXPROXYSIZE 12
8788 #define M_MAXPROXYSIZE 0xfU
8789 #define V_MAXPROXYSIZE(x) ((x) << S_MAXPROXYSIZE)
8790 #define G_MAXPROXYSIZE(x) (((x) >> S_MAXPROXYSIZE) & M_MAXPROXYSIZE)
8792 #define S_ENABLEREADPDU 11
8793 #define V_ENABLEREADPDU(x) ((x) << S_ENABLEREADPDU)
8794 #define F_ENABLEREADPDU V_ENABLEREADPDU(1U)
8796 #define S_RXREADAHEAD 10
8797 #define V_RXREADAHEAD(x) ((x) << S_RXREADAHEAD)
8798 #define F_RXREADAHEAD V_RXREADAHEAD(1U)
8800 #define S_EMPTYRQENABLE 9
8801 #define V_EMPTYRQENABLE(x) ((x) << S_EMPTYRQENABLE)
8802 #define F_EMPTYRQENABLE V_EMPTYRQENABLE(1U)
8804 #define S_SCHDENABLE 8
8805 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
8806 #define F_SCHDENABLE V_SCHDENABLE(1U)
8808 #define S_REARMDDPOFFSET 4
8809 #define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET)
8810 #define F_REARMDDPOFFSET V_REARMDDPOFFSET(1U)
8812 #define S_RESETDDPOFFSET 3
8813 #define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET)
8814 #define F_RESETDDPOFFSET V_RESETDDPOFFSET(1U)
8816 #define S_ONFLYDDPENABLE 2
8817 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
8818 #define F_ONFLYDDPENABLE V_ONFLYDDPENABLE(1U)
8820 #define S_DACKTIMERSPIN 1
8821 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
8822 #define F_DACKTIMERSPIN V_DACKTIMERSPIN(1U)
8824 #define S_PUSHTIMERENABLE 0
8825 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
8826 #define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U)
8828 #define A_TP_PARA_REG6 0x7d78
8830 #define S_TXPDUSIZEADJ 24
8831 #define M_TXPDUSIZEADJ 0xffU
8832 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
8833 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
8835 #define S_LIMITEDTRANSMIT 20
8836 #define M_LIMITEDTRANSMIT 0xfU
8837 #define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT)
8838 #define G_LIMITEDTRANSMIT(x) (((x) >> S_LIMITEDTRANSMIT) & M_LIMITEDTRANSMIT)
8840 #define S_ENABLECSAV 19
8841 #define V_ENABLECSAV(x) ((x) << S_ENABLECSAV)
8842 #define F_ENABLECSAV V_ENABLECSAV(1U)
8844 #define S_ENABLEDEFERPDU 18
8845 #define V_ENABLEDEFERPDU(x) ((x) << S_ENABLEDEFERPDU)
8846 #define F_ENABLEDEFERPDU V_ENABLEDEFERPDU(1U)
8848 #define S_ENABLEFLUSH 17
8849 #define V_ENABLEFLUSH(x) ((x) << S_ENABLEFLUSH)
8850 #define F_ENABLEFLUSH V_ENABLEFLUSH(1U)
8852 #define S_ENABLEBYTEPERSIST 16
8853 #define V_ENABLEBYTEPERSIST(x) ((x) << S_ENABLEBYTEPERSIST)
8854 #define F_ENABLEBYTEPERSIST V_ENABLEBYTEPERSIST(1U)
8856 #define S_DISABLETMOCNG 15
8857 #define V_DISABLETMOCNG(x) ((x) << S_DISABLETMOCNG)
8858 #define F_DISABLETMOCNG V_DISABLETMOCNG(1U)
8860 #define S_TXREADAHEAD 14
8861 #define V_TXREADAHEAD(x) ((x) << S_TXREADAHEAD)
8862 #define F_TXREADAHEAD V_TXREADAHEAD(1U)
8864 #define S_ALLOWEXEPTION 13
8865 #define V_ALLOWEXEPTION(x) ((x) << S_ALLOWEXEPTION)
8866 #define F_ALLOWEXEPTION V_ALLOWEXEPTION(1U)
8868 #define S_ENABLEDEFERACK 12
8869 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
8870 #define F_ENABLEDEFERACK V_ENABLEDEFERACK(1U)
8872 #define S_ENABLEESND 11
8873 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
8874 #define F_ENABLEESND V_ENABLEESND(1U)
8876 #define S_ENABLECSND 10
8877 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
8878 #define F_ENABLECSND V_ENABLECSND(1U)
8880 #define S_ENABLEPDUE 9
8881 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
8882 #define F_ENABLEPDUE V_ENABLEPDUE(1U)
8884 #define S_ENABLEPDUC 8
8885 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
8886 #define F_ENABLEPDUC V_ENABLEPDUC(1U)
8888 #define S_ENABLEBUFI 7
8889 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
8890 #define F_ENABLEBUFI V_ENABLEBUFI(1U)
8892 #define S_ENABLEBUFE 6
8893 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
8894 #define F_ENABLEBUFE V_ENABLEBUFE(1U)
8896 #define S_ENABLEDEFER 5
8897 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
8898 #define F_ENABLEDEFER V_ENABLEDEFER(1U)
8900 #define S_ENABLECLEARRXMTOOS 4
8901 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
8902 #define F_ENABLECLEARRXMTOOS V_ENABLECLEARRXMTOOS(1U)
8904 #define S_DISABLEPDUCNG 3
8905 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
8906 #define F_DISABLEPDUCNG V_DISABLEPDUCNG(1U)
8908 #define S_DISABLEPDUTIMEOUT 2
8909 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
8910 #define F_DISABLEPDUTIMEOUT V_DISABLEPDUTIMEOUT(1U)
8912 #define S_DISABLEPDURXMT 1
8913 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
8914 #define F_DISABLEPDURXMT V_DISABLEPDURXMT(1U)
8916 #define S_DISABLEPDUXMT 0
8917 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
8918 #define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U)
8920 #define A_TP_PARA_REG7 0x7d7c
8922 #define S_PMMAXXFERLEN1 16
8923 #define M_PMMAXXFERLEN1 0xffffU
8924 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
8925 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
8927 #define S_PMMAXXFERLEN0 0
8928 #define M_PMMAXXFERLEN0 0xffffU
8929 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
8930 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
8932 #define A_TP_ENG_CONFIG 0x7d80
8934 #define S_TABLELATENCYDONE 28
8935 #define M_TABLELATENCYDONE 0xfU
8936 #define V_TABLELATENCYDONE(x) ((x) << S_TABLELATENCYDONE)
8937 #define G_TABLELATENCYDONE(x) (((x) >> S_TABLELATENCYDONE) & M_TABLELATENCYDONE)
8939 #define S_TABLELATENCYSTART 24
8940 #define M_TABLELATENCYSTART 0xfU
8941 #define V_TABLELATENCYSTART(x) ((x) << S_TABLELATENCYSTART)
8942 #define G_TABLELATENCYSTART(x) (((x) >> S_TABLELATENCYSTART) & M_TABLELATENCYSTART)
8944 #define S_ENGINELATENCYDELTA 16
8945 #define M_ENGINELATENCYDELTA 0xfU
8946 #define V_ENGINELATENCYDELTA(x) ((x) << S_ENGINELATENCYDELTA)
8947 #define G_ENGINELATENCYDELTA(x) (((x) >> S_ENGINELATENCYDELTA) & M_ENGINELATENCYDELTA)
8949 #define S_ENGINELATENCYMMGR 12
8950 #define M_ENGINELATENCYMMGR 0xfU
8951 #define V_ENGINELATENCYMMGR(x) ((x) << S_ENGINELATENCYMMGR)
8952 #define G_ENGINELATENCYMMGR(x) (((x) >> S_ENGINELATENCYMMGR) & M_ENGINELATENCYMMGR)
8954 #define S_ENGINELATENCYWIREIP6 8
8955 #define M_ENGINELATENCYWIREIP6 0xfU
8956 #define V_ENGINELATENCYWIREIP6(x) ((x) << S_ENGINELATENCYWIREIP6)
8957 #define G_ENGINELATENCYWIREIP6(x) (((x) >> S_ENGINELATENCYWIREIP6) & M_ENGINELATENCYWIREIP6)
8959 #define S_ENGINELATENCYWIRE 4
8960 #define M_ENGINELATENCYWIRE 0xfU
8961 #define V_ENGINELATENCYWIRE(x) ((x) << S_ENGINELATENCYWIRE)
8962 #define G_ENGINELATENCYWIRE(x) (((x) >> S_ENGINELATENCYWIRE) & M_ENGINELATENCYWIRE)
8964 #define S_ENGINELATENCYBASE 0
8965 #define M_ENGINELATENCYBASE 0xfU
8966 #define V_ENGINELATENCYBASE(x) ((x) << S_ENGINELATENCYBASE)
8967 #define G_ENGINELATENCYBASE(x) (((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE)
8969 #define A_TP_ERR_CONFIG 0x7d8c
8971 #define S_TNLERRORPING 30
8972 #define V_TNLERRORPING(x) ((x) << S_TNLERRORPING)
8973 #define F_TNLERRORPING V_TNLERRORPING(1U)
8975 #define S_TNLERRORCSUM 29
8976 #define V_TNLERRORCSUM(x) ((x) << S_TNLERRORCSUM)
8977 #define F_TNLERRORCSUM V_TNLERRORCSUM(1U)
8979 #define S_TNLERRORCSUMIP 28
8980 #define V_TNLERRORCSUMIP(x) ((x) << S_TNLERRORCSUMIP)
8981 #define F_TNLERRORCSUMIP V_TNLERRORCSUMIP(1U)
8983 #define S_TNLERRORTCPOPT 25
8984 #define V_TNLERRORTCPOPT(x) ((x) << S_TNLERRORTCPOPT)
8985 #define F_TNLERRORTCPOPT V_TNLERRORTCPOPT(1U)
8987 #define S_TNLERRORPKTLEN 24
8988 #define V_TNLERRORPKTLEN(x) ((x) << S_TNLERRORPKTLEN)
8989 #define F_TNLERRORPKTLEN V_TNLERRORPKTLEN(1U)
8991 #define S_TNLERRORTCPHDRLEN 23
8992 #define V_TNLERRORTCPHDRLEN(x) ((x) << S_TNLERRORTCPHDRLEN)
8993 #define F_TNLERRORTCPHDRLEN V_TNLERRORTCPHDRLEN(1U)
8995 #define S_TNLERRORIPHDRLEN 22
8996 #define V_TNLERRORIPHDRLEN(x) ((x) << S_TNLERRORIPHDRLEN)
8997 #define F_TNLERRORIPHDRLEN V_TNLERRORIPHDRLEN(1U)
8999 #define S_TNLERRORETHHDRLEN 21
9000 #define V_TNLERRORETHHDRLEN(x) ((x) << S_TNLERRORETHHDRLEN)
9001 #define F_TNLERRORETHHDRLEN V_TNLERRORETHHDRLEN(1U)
9003 #define S_TNLERRORATTACK 20
9004 #define V_TNLERRORATTACK(x) ((x) << S_TNLERRORATTACK)
9005 #define F_TNLERRORATTACK V_TNLERRORATTACK(1U)
9007 #define S_TNLERRORFRAG 19
9008 #define V_TNLERRORFRAG(x) ((x) << S_TNLERRORFRAG)
9009 #define F_TNLERRORFRAG V_TNLERRORFRAG(1U)
9011 #define S_TNLERRORIPVER 18
9012 #define V_TNLERRORIPVER(x) ((x) << S_TNLERRORIPVER)
9013 #define F_TNLERRORIPVER V_TNLERRORIPVER(1U)
9015 #define S_TNLERRORMAC 17
9016 #define V_TNLERRORMAC(x) ((x) << S_TNLERRORMAC)
9017 #define F_TNLERRORMAC V_TNLERRORMAC(1U)
9019 #define S_TNLERRORANY 16
9020 #define V_TNLERRORANY(x) ((x) << S_TNLERRORANY)
9021 #define F_TNLERRORANY V_TNLERRORANY(1U)
9023 #define S_DROPERRORPING 14
9024 #define V_DROPERRORPING(x) ((x) << S_DROPERRORPING)
9025 #define F_DROPERRORPING V_DROPERRORPING(1U)
9027 #define S_DROPERRORCSUM 13
9028 #define V_DROPERRORCSUM(x) ((x) << S_DROPERRORCSUM)
9029 #define F_DROPERRORCSUM V_DROPERRORCSUM(1U)
9031 #define S_DROPERRORCSUMIP 12
9032 #define V_DROPERRORCSUMIP(x) ((x) << S_DROPERRORCSUMIP)
9033 #define F_DROPERRORCSUMIP V_DROPERRORCSUMIP(1U)
9035 #define S_DROPERRORTCPOPT 9
9036 #define V_DROPERRORTCPOPT(x) ((x) << S_DROPERRORTCPOPT)
9037 #define F_DROPERRORTCPOPT V_DROPERRORTCPOPT(1U)
9039 #define S_DROPERRORPKTLEN 8
9040 #define V_DROPERRORPKTLEN(x) ((x) << S_DROPERRORPKTLEN)
9041 #define F_DROPERRORPKTLEN V_DROPERRORPKTLEN(1U)
9043 #define S_DROPERRORTCPHDRLEN 7
9044 #define V_DROPERRORTCPHDRLEN(x) ((x) << S_DROPERRORTCPHDRLEN)
9045 #define F_DROPERRORTCPHDRLEN V_DROPERRORTCPHDRLEN(1U)
9047 #define S_DROPERRORIPHDRLEN 6
9048 #define V_DROPERRORIPHDRLEN(x) ((x) << S_DROPERRORIPHDRLEN)
9049 #define F_DROPERRORIPHDRLEN V_DROPERRORIPHDRLEN(1U)
9051 #define S_DROPERRORETHHDRLEN 5
9052 #define V_DROPERRORETHHDRLEN(x) ((x) << S_DROPERRORETHHDRLEN)
9053 #define F_DROPERRORETHHDRLEN V_DROPERRORETHHDRLEN(1U)
9055 #define S_DROPERRORATTACK 4
9056 #define V_DROPERRORATTACK(x) ((x) << S_DROPERRORATTACK)
9057 #define F_DROPERRORATTACK V_DROPERRORATTACK(1U)
9059 #define S_DROPERRORFRAG 3
9060 #define V_DROPERRORFRAG(x) ((x) << S_DROPERRORFRAG)
9061 #define F_DROPERRORFRAG V_DROPERRORFRAG(1U)
9063 #define S_DROPERRORIPVER 2
9064 #define V_DROPERRORIPVER(x) ((x) << S_DROPERRORIPVER)
9065 #define F_DROPERRORIPVER V_DROPERRORIPVER(1U)
9067 #define S_DROPERRORMAC 1
9068 #define V_DROPERRORMAC(x) ((x) << S_DROPERRORMAC)
9069 #define F_DROPERRORMAC V_DROPERRORMAC(1U)
9071 #define S_DROPERRORANY 0
9072 #define V_DROPERRORANY(x) ((x) << S_DROPERRORANY)
9073 #define F_DROPERRORANY V_DROPERRORANY(1U)
9075 #define A_TP_TIMER_RESOLUTION 0x7d90
9077 #define S_TIMERRESOLUTION 16
9078 #define M_TIMERRESOLUTION 0xffU
9079 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
9080 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
9082 #define S_TIMESTAMPRESOLUTION 8
9083 #define M_TIMESTAMPRESOLUTION 0xffU
9084 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
9085 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
9087 #define S_DELAYEDACKRESOLUTION 0
9088 #define M_DELAYEDACKRESOLUTION 0xffU
9089 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
9090 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
9092 #define A_TP_MSL 0x7d94
9095 #define M_MSL 0x3fffffffU
9096 #define V_MSL(x) ((x) << S_MSL)
9097 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
9099 #define A_TP_RXT_MIN 0x7d98
9102 #define M_RXTMIN 0x3fffffffU
9103 #define V_RXTMIN(x) ((x) << S_RXTMIN)
9104 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
9106 #define A_TP_RXT_MAX 0x7d9c
9109 #define M_RXTMAX 0x3fffffffU
9110 #define V_RXTMAX(x) ((x) << S_RXTMAX)
9111 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
9113 #define A_TP_PERS_MIN 0x7da0
9116 #define M_PERSMIN 0x3fffffffU
9117 #define V_PERSMIN(x) ((x) << S_PERSMIN)
9118 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
9120 #define A_TP_PERS_MAX 0x7da4
9123 #define M_PERSMAX 0x3fffffffU
9124 #define V_PERSMAX(x) ((x) << S_PERSMAX)
9125 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
9127 #define A_TP_KEEP_IDLE 0x7da8
9129 #define S_KEEPALIVEIDLE 0
9130 #define M_KEEPALIVEIDLE 0x3fffffffU
9131 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
9132 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
9134 #define A_TP_KEEP_INTVL 0x7dac
9136 #define S_KEEPALIVEINTVL 0
9137 #define M_KEEPALIVEINTVL 0x3fffffffU
9138 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
9139 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
9141 #define A_TP_INIT_SRTT 0x7db0
9144 #define M_MAXRTT 0xffffU
9145 #define V_MAXRTT(x) ((x) << S_MAXRTT)
9146 #define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT)
9148 #define S_INITSRTT 0
9149 #define M_INITSRTT 0xffffU
9150 #define V_INITSRTT(x) ((x) << S_INITSRTT)
9151 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
9153 #define A_TP_DACK_TIMER 0x7db4
9155 #define S_DACKTIME 0
9156 #define M_DACKTIME 0xfffU
9157 #define V_DACKTIME(x) ((x) << S_DACKTIME)
9158 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
9160 #define A_TP_FINWAIT2_TIMER 0x7db8
9162 #define S_FINWAIT2TIME 0
9163 #define M_FINWAIT2TIME 0x3fffffffU
9164 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
9165 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
9167 #define A_TP_FAST_FINWAIT2_TIMER 0x7dbc
9169 #define S_FASTFINWAIT2TIME 0
9170 #define M_FASTFINWAIT2TIME 0x3fffffffU
9171 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
9172 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
9174 #define A_TP_SHIFT_CNT 0x7dc0
9176 #define S_SYNSHIFTMAX 24
9177 #define M_SYNSHIFTMAX 0xffU
9178 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
9179 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
9181 #define S_RXTSHIFTMAXR1 20
9182 #define M_RXTSHIFTMAXR1 0xfU
9183 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
9184 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
9186 #define S_RXTSHIFTMAXR2 16
9187 #define M_RXTSHIFTMAXR2 0xfU
9188 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
9189 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
9191 #define S_PERSHIFTBACKOFFMAX 12
9192 #define M_PERSHIFTBACKOFFMAX 0xfU
9193 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
9194 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
9196 #define S_PERSHIFTMAX 8
9197 #define M_PERSHIFTMAX 0xfU
9198 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
9199 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
9201 #define S_KEEPALIVEMAXR1 4
9202 #define M_KEEPALIVEMAXR1 0xfU
9203 #define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1)
9204 #define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1)
9206 #define S_KEEPALIVEMAXR2 0
9207 #define M_KEEPALIVEMAXR2 0xfU
9208 #define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
9209 #define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)
9211 #define A_TP_TM_CONFIG 0x7dc4
9213 #define S_CMTIMERMAXNUM 0
9214 #define M_CMTIMERMAXNUM 0x7U
9215 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
9216 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
9218 #define A_TP_TIME_LO 0x7dc8
9219 #define A_TP_TIME_HI 0x7dcc
9220 #define A_TP_PORT_MTU_0 0x7dd0
9222 #define S_PORT1MTUVALUE 16
9223 #define M_PORT1MTUVALUE 0xffffU
9224 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
9225 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
9227 #define S_PORT0MTUVALUE 0
9228 #define M_PORT0MTUVALUE 0xffffU
9229 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
9230 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
9232 #define A_TP_PORT_MTU_1 0x7dd4
9234 #define S_PORT3MTUVALUE 16
9235 #define M_PORT3MTUVALUE 0xffffU
9236 #define V_PORT3MTUVALUE(x) ((x) << S_PORT3MTUVALUE)
9237 #define G_PORT3MTUVALUE(x) (((x) >> S_PORT3MTUVALUE) & M_PORT3MTUVALUE)
9239 #define S_PORT2MTUVALUE 0
9240 #define M_PORT2MTUVALUE 0xffffU
9241 #define V_PORT2MTUVALUE(x) ((x) << S_PORT2MTUVALUE)
9242 #define G_PORT2MTUVALUE(x) (((x) >> S_PORT2MTUVALUE) & M_PORT2MTUVALUE)
9244 #define A_TP_PACE_TABLE 0x7dd8
9245 #define A_TP_CCTRL_TABLE 0x7ddc
9247 #define S_ROWINDEX 16
9248 #define M_ROWINDEX 0xffffU
9249 #define V_ROWINDEX(x) ((x) << S_ROWINDEX)
9250 #define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX)
9252 #define S_ROWVALUE 0
9253 #define M_ROWVALUE 0xffffU
9254 #define V_ROWVALUE(x) ((x) << S_ROWVALUE)
9255 #define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE)
9257 #define A_TP_MTU_TABLE 0x7de4
9259 #define S_MTUINDEX 24
9260 #define M_MTUINDEX 0xffU
9261 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
9262 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
9264 #define S_MTUWIDTH 16
9265 #define M_MTUWIDTH 0xfU
9266 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
9267 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
9269 #define S_MTUVALUE 0
9270 #define M_MTUVALUE 0x3fffU
9271 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
9272 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
9274 #define A_TP_ULP_TABLE 0x7de8
9276 #define S_ULPTYPE7FIELD 28
9277 #define M_ULPTYPE7FIELD 0xfU
9278 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
9279 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
9281 #define S_ULPTYPE6FIELD 24
9282 #define M_ULPTYPE6FIELD 0xfU
9283 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
9284 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
9286 #define S_ULPTYPE5FIELD 20
9287 #define M_ULPTYPE5FIELD 0xfU
9288 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
9289 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
9291 #define S_ULPTYPE4FIELD 16
9292 #define M_ULPTYPE4FIELD 0xfU
9293 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
9294 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
9296 #define S_ULPTYPE3FIELD 12
9297 #define M_ULPTYPE3FIELD 0xfU
9298 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
9299 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
9301 #define S_ULPTYPE2FIELD 8
9302 #define M_ULPTYPE2FIELD 0xfU
9303 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
9304 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
9306 #define S_ULPTYPE1FIELD 4
9307 #define M_ULPTYPE1FIELD 0xfU
9308 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
9309 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
9311 #define S_ULPTYPE0FIELD 0
9312 #define M_ULPTYPE0FIELD 0xfU
9313 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
9314 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
9316 #define A_TP_RSS_LKP_TABLE 0x7dec
9318 #define S_LKPTBLROWVLD 31
9319 #define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD)
9320 #define F_LKPTBLROWVLD V_LKPTBLROWVLD(1U)
9322 #define S_LKPTBLROWIDX 20
9323 #define M_LKPTBLROWIDX 0x3ffU
9324 #define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX)
9325 #define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX)
9327 #define S_LKPTBLQUEUE1 10
9328 #define M_LKPTBLQUEUE1 0x3ffU
9329 #define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1)
9330 #define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1)
9332 #define S_LKPTBLQUEUE0 0
9333 #define M_LKPTBLQUEUE0 0x3ffU
9334 #define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
9335 #define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)
9337 #define A_TP_RSS_CONFIG 0x7df0
9339 #define S_TNL4TUPENIPV6 31
9340 #define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6)
9341 #define F_TNL4TUPENIPV6 V_TNL4TUPENIPV6(1U)
9343 #define S_TNL2TUPENIPV6 30
9344 #define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6)
9345 #define F_TNL2TUPENIPV6 V_TNL2TUPENIPV6(1U)
9347 #define S_TNL4TUPENIPV4 29
9348 #define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4)
9349 #define F_TNL4TUPENIPV4 V_TNL4TUPENIPV4(1U)
9351 #define S_TNL2TUPENIPV4 28
9352 #define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4)
9353 #define F_TNL2TUPENIPV4 V_TNL2TUPENIPV4(1U)
9355 #define S_TNLTCPSEL 27
9356 #define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL)
9357 #define F_TNLTCPSEL V_TNLTCPSEL(1U)
9359 #define S_TNLIP6SEL 26
9360 #define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL)
9361 #define F_TNLIP6SEL V_TNLIP6SEL(1U)
9363 #define S_TNLVRTSEL 25
9364 #define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL)
9365 #define F_TNLVRTSEL V_TNLVRTSEL(1U)
9367 #define S_TNLMAPEN 24
9368 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
9369 #define F_TNLMAPEN V_TNLMAPEN(1U)
9371 #define S_OFDHASHSAVE 19
9372 #define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE)
9373 #define F_OFDHASHSAVE V_OFDHASHSAVE(1U)
9375 #define S_OFDVRTSEL 18
9376 #define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL)
9377 #define F_OFDVRTSEL V_OFDVRTSEL(1U)
9379 #define S_OFDMAPEN 17
9380 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
9381 #define F_OFDMAPEN V_OFDMAPEN(1U)
9383 #define S_OFDLKPEN 16
9384 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
9385 #define F_OFDLKPEN V_OFDLKPEN(1U)
9387 #define S_SYN4TUPENIPV6 15
9388 #define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6)
9389 #define F_SYN4TUPENIPV6 V_SYN4TUPENIPV6(1U)
9391 #define S_SYN2TUPENIPV6 14
9392 #define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6)
9393 #define F_SYN2TUPENIPV6 V_SYN2TUPENIPV6(1U)
9395 #define S_SYN4TUPENIPV4 13
9396 #define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4)
9397 #define F_SYN4TUPENIPV4 V_SYN4TUPENIPV4(1U)
9399 #define S_SYN2TUPENIPV4 12
9400 #define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4)
9401 #define F_SYN2TUPENIPV4 V_SYN2TUPENIPV4(1U)
9403 #define S_SYNIP6SEL 11
9404 #define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL)
9405 #define F_SYNIP6SEL V_SYNIP6SEL(1U)
9407 #define S_SYNVRTSEL 10
9408 #define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL)
9409 #define F_SYNVRTSEL V_SYNVRTSEL(1U)
9411 #define S_SYNMAPEN 9
9412 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
9413 #define F_SYNMAPEN V_SYNMAPEN(1U)
9415 #define S_SYNLKPEN 8
9416 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
9417 #define F_SYNLKPEN V_SYNLKPEN(1U)
9419 #define S_CHANNELENABLE 7
9420 #define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE)
9421 #define F_CHANNELENABLE V_CHANNELENABLE(1U)
9423 #define S_PORTENABLE 6
9424 #define V_PORTENABLE(x) ((x) << S_PORTENABLE)
9425 #define F_PORTENABLE V_PORTENABLE(1U)
9427 #define S_TNLALLLOOKUP 5
9428 #define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP)
9429 #define F_TNLALLLOOKUP V_TNLALLLOOKUP(1U)
9431 #define S_VIRTENABLE 4
9432 #define V_VIRTENABLE(x) ((x) << S_VIRTENABLE)
9433 #define F_VIRTENABLE V_VIRTENABLE(1U)
9435 #define S_CONGESTIONENABLE 3
9436 #define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE)
9437 #define F_CONGESTIONENABLE V_CONGESTIONENABLE(1U)
9439 #define S_HASHTOEPLITZ 2
9440 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
9441 #define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U)
9443 #define S_UDPENABLE 1
9444 #define V_UDPENABLE(x) ((x) << S_UDPENABLE)
9445 #define F_UDPENABLE V_UDPENABLE(1U)
9448 #define V_DISABLE(x) ((x) << S_DISABLE)
9449 #define F_DISABLE V_DISABLE(1U)
9451 #define A_TP_RSS_CONFIG_TNL 0x7df4
9453 #define S_MASKSIZE 28
9454 #define M_MASKSIZE 0xfU
9455 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
9456 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
9458 #define S_MASKFILTER 16
9459 #define M_MASKFILTER 0x7ffU
9460 #define V_MASKFILTER(x) ((x) << S_MASKFILTER)
9461 #define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER)
9463 #define S_USEWIRECH 0
9464 #define V_USEWIRECH(x) ((x) << S_USEWIRECH)
9465 #define F_USEWIRECH V_USEWIRECH(1U)
9467 #define A_TP_RSS_CONFIG_OFD 0x7df8
9469 #define S_RRCPLMAPEN 20
9470 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
9471 #define F_RRCPLMAPEN V_RRCPLMAPEN(1U)
9473 #define S_RRCPLQUEWIDTH 16
9474 #define M_RRCPLQUEWIDTH 0xfU
9475 #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
9476 #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)
9478 #define A_TP_RSS_CONFIG_SYN 0x7dfc
9479 #define A_TP_RSS_CONFIG_VRT 0x7e00
9482 #define V_VFRDRG(x) ((x) << S_VFRDRG)
9483 #define F_VFRDRG V_VFRDRG(1U)
9486 #define V_VFRDEN(x) ((x) << S_VFRDEN)
9487 #define F_VFRDEN V_VFRDEN(1U)
9489 #define S_VFPERREN 23
9490 #define V_VFPERREN(x) ((x) << S_VFPERREN)
9491 #define F_VFPERREN V_VFPERREN(1U)
9493 #define S_KEYPERREN 22
9494 #define V_KEYPERREN(x) ((x) << S_KEYPERREN)
9495 #define F_KEYPERREN V_KEYPERREN(1U)
9497 #define S_DISABLEVLAN 21
9498 #define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN)
9499 #define F_DISABLEVLAN V_DISABLEVLAN(1U)
9501 #define S_ENABLEUP0 20
9502 #define V_ENABLEUP0(x) ((x) << S_ENABLEUP0)
9503 #define F_ENABLEUP0 V_ENABLEUP0(1U)
9505 #define S_HASHDELAY 16
9506 #define M_HASHDELAY 0xfU
9507 #define V_HASHDELAY(x) ((x) << S_HASHDELAY)
9508 #define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY)
9510 #define S_VFWRADDR 8
9511 #define M_VFWRADDR 0x7fU
9512 #define V_VFWRADDR(x) ((x) << S_VFWRADDR)
9513 #define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR)
9516 #define M_KEYMODE 0x3U
9517 #define V_KEYMODE(x) ((x) << S_KEYMODE)
9518 #define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)
9521 #define V_VFWREN(x) ((x) << S_VFWREN)
9522 #define F_VFWREN V_VFWREN(1U)
9525 #define V_KEYWREN(x) ((x) << S_KEYWREN)
9526 #define F_KEYWREN V_KEYWREN(1U)
9528 #define S_KEYWRADDR 0
9529 #define M_KEYWRADDR 0xfU
9530 #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
9531 #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)
9533 #define A_TP_RSS_CONFIG_CNG 0x7e04
9535 #define S_CHNCOUNT3 31
9536 #define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3)
9537 #define F_CHNCOUNT3 V_CHNCOUNT3(1U)
9539 #define S_CHNCOUNT2 30
9540 #define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2)
9541 #define F_CHNCOUNT2 V_CHNCOUNT2(1U)
9543 #define S_CHNCOUNT1 29
9544 #define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1)
9545 #define F_CHNCOUNT1 V_CHNCOUNT1(1U)
9547 #define S_CHNCOUNT0 28
9548 #define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0)
9549 #define F_CHNCOUNT0 V_CHNCOUNT0(1U)
9551 #define S_CHNUNDFLOW3 27
9552 #define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3)
9553 #define F_CHNUNDFLOW3 V_CHNUNDFLOW3(1U)
9555 #define S_CHNUNDFLOW2 26
9556 #define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2)
9557 #define F_CHNUNDFLOW2 V_CHNUNDFLOW2(1U)
9559 #define S_CHNUNDFLOW1 25
9560 #define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1)
9561 #define F_CHNUNDFLOW1 V_CHNUNDFLOW1(1U)
9563 #define S_CHNUNDFLOW0 24
9564 #define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0)
9565 #define F_CHNUNDFLOW0 V_CHNUNDFLOW0(1U)
9567 #define S_CHNOVRFLOW3 23
9568 #define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3)
9569 #define F_CHNOVRFLOW3 V_CHNOVRFLOW3(1U)
9571 #define S_CHNOVRFLOW2 22
9572 #define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2)
9573 #define F_CHNOVRFLOW2 V_CHNOVRFLOW2(1U)
9575 #define S_CHNOVRFLOW1 21
9576 #define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1)
9577 #define F_CHNOVRFLOW1 V_CHNOVRFLOW1(1U)
9579 #define S_CHNOVRFLOW0 20
9580 #define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0)
9581 #define F_CHNOVRFLOW0 V_CHNOVRFLOW0(1U)
9583 #define S_RSTCHN3 19
9584 #define V_RSTCHN3(x) ((x) << S_RSTCHN3)
9585 #define F_RSTCHN3 V_RSTCHN3(1U)
9587 #define S_RSTCHN2 18
9588 #define V_RSTCHN2(x) ((x) << S_RSTCHN2)
9589 #define F_RSTCHN2 V_RSTCHN2(1U)
9591 #define S_RSTCHN1 17
9592 #define V_RSTCHN1(x) ((x) << S_RSTCHN1)
9593 #define F_RSTCHN1 V_RSTCHN1(1U)
9595 #define S_RSTCHN0 16
9596 #define V_RSTCHN0(x) ((x) << S_RSTCHN0)
9597 #define F_RSTCHN0 V_RSTCHN0(1U)
9600 #define V_UPDVLD(x) ((x) << S_UPDVLD)
9601 #define F_UPDVLD V_UPDVLD(1U)
9604 #define V_XOFF(x) ((x) << S_XOFF)
9605 #define F_XOFF V_XOFF(1U)
9607 #define S_UPDCHN3 13
9608 #define V_UPDCHN3(x) ((x) << S_UPDCHN3)
9609 #define F_UPDCHN3 V_UPDCHN3(1U)
9611 #define S_UPDCHN2 12
9612 #define V_UPDCHN2(x) ((x) << S_UPDCHN2)
9613 #define F_UPDCHN2 V_UPDCHN2(1U)
9615 #define S_UPDCHN1 11
9616 #define V_UPDCHN1(x) ((x) << S_UPDCHN1)
9617 #define F_UPDCHN1 V_UPDCHN1(1U)
9619 #define S_UPDCHN0 10
9620 #define V_UPDCHN0(x) ((x) << S_UPDCHN0)
9621 #define F_UPDCHN0 V_UPDCHN0(1U)
9624 #define M_QUEUE 0x3ffU
9625 #define V_QUEUE(x) ((x) << S_QUEUE)
9626 #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)
9628 #define A_TP_LA_TABLE_0 0x7e10
9630 #define S_VIRTPORT1TABLE 16
9631 #define M_VIRTPORT1TABLE 0xffffU
9632 #define V_VIRTPORT1TABLE(x) ((x) << S_VIRTPORT1TABLE)
9633 #define G_VIRTPORT1TABLE(x) (((x) >> S_VIRTPORT1TABLE) & M_VIRTPORT1TABLE)
9635 #define S_VIRTPORT0TABLE 0
9636 #define M_VIRTPORT0TABLE 0xffffU
9637 #define V_VIRTPORT0TABLE(x) ((x) << S_VIRTPORT0TABLE)
9638 #define G_VIRTPORT0TABLE(x) (((x) >> S_VIRTPORT0TABLE) & M_VIRTPORT0TABLE)
9640 #define A_TP_LA_TABLE_1 0x7e14
9642 #define S_VIRTPORT3TABLE 16
9643 #define M_VIRTPORT3TABLE 0xffffU
9644 #define V_VIRTPORT3TABLE(x) ((x) << S_VIRTPORT3TABLE)
9645 #define G_VIRTPORT3TABLE(x) (((x) >> S_VIRTPORT3TABLE) & M_VIRTPORT3TABLE)
9647 #define S_VIRTPORT2TABLE 0
9648 #define M_VIRTPORT2TABLE 0xffffU
9649 #define V_VIRTPORT2TABLE(x) ((x) << S_VIRTPORT2TABLE)
9650 #define G_VIRTPORT2TABLE(x) (((x) >> S_VIRTPORT2TABLE) & M_VIRTPORT2TABLE)
9652 #define A_TP_TM_PIO_ADDR 0x7e18
9653 #define A_TP_TM_PIO_DATA 0x7e1c
9654 #define A_TP_MOD_CONFIG 0x7e24
9656 #define S_RXCHANNELWEIGHT1 24
9657 #define M_RXCHANNELWEIGHT1 0xffU
9658 #define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1)
9659 #define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1)
9661 #define S_RXCHANNELWEIGHT0 16
9662 #define M_RXCHANNELWEIGHT0 0xffU
9663 #define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0)
9664 #define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0)
9666 #define S_TIMERMODE 8
9667 #define M_TIMERMODE 0xffU
9668 #define V_TIMERMODE(x) ((x) << S_TIMERMODE)
9669 #define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE)
9671 #define S_TXCHANNELXOFFEN 0
9672 #define M_TXCHANNELXOFFEN 0xfU
9673 #define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN)
9674 #define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN)
9676 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
9678 #define S_RX_MOD_WEIGHT 24
9679 #define M_RX_MOD_WEIGHT 0xffU
9680 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
9681 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
9683 #define S_TX_MOD_WEIGHT 16
9684 #define M_TX_MOD_WEIGHT 0xffU
9685 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
9686 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
9688 #define S_TX_MOD_QUEUE_REQ_MAP 0
9689 #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU
9690 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
9691 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
9693 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c
9695 #define S_TX_MODQ_WEIGHT7 24
9696 #define M_TX_MODQ_WEIGHT7 0xffU
9697 #define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7)
9698 #define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7)
9700 #define S_TX_MODQ_WEIGHT6 16
9701 #define M_TX_MODQ_WEIGHT6 0xffU
9702 #define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6)
9703 #define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6)
9705 #define S_TX_MODQ_WEIGHT5 8
9706 #define M_TX_MODQ_WEIGHT5 0xffU
9707 #define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5)
9708 #define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5)
9710 #define S_TX_MODQ_WEIGHT4 0
9711 #define M_TX_MODQ_WEIGHT4 0xffU
9712 #define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4)
9713 #define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4)
9715 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
9717 #define S_TX_MODQ_WEIGHT3 24
9718 #define M_TX_MODQ_WEIGHT3 0xffU
9719 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
9720 #define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3)
9722 #define S_TX_MODQ_WEIGHT2 16
9723 #define M_TX_MODQ_WEIGHT2 0xffU
9724 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
9725 #define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2)
9727 #define S_TX_MODQ_WEIGHT1 8
9728 #define M_TX_MODQ_WEIGHT1 0xffU
9729 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
9730 #define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1)
9732 #define S_TX_MODQ_WEIGHT0 0
9733 #define M_TX_MODQ_WEIGHT0 0xffU
9734 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
9735 #define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0)
9737 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
9738 #define A_TP_MOD_RATE_LIMIT 0x7e38
9740 #define S_RX_MOD_RATE_LIMIT_INC 24
9741 #define M_RX_MOD_RATE_LIMIT_INC 0xffU
9742 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
9743 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
9745 #define S_RX_MOD_RATE_LIMIT_TICK 16
9746 #define M_RX_MOD_RATE_LIMIT_TICK 0xffU
9747 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
9748 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
9750 #define S_TX_MOD_RATE_LIMIT_INC 8
9751 #define M_TX_MOD_RATE_LIMIT_INC 0xffU
9752 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
9753 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
9755 #define S_TX_MOD_RATE_LIMIT_TICK 0
9756 #define M_TX_MOD_RATE_LIMIT_TICK 0xffU
9757 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
9758 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
9760 #define A_TP_PIO_ADDR 0x7e40
9761 #define A_TP_PIO_DATA 0x7e44
9762 #define A_TP_RESET 0x7e4c
9764 #define S_FLSTINITENABLE 1
9765 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
9766 #define F_FLSTINITENABLE V_FLSTINITENABLE(1U)
9769 #define V_TPRESET(x) ((x) << S_TPRESET)
9770 #define F_TPRESET V_TPRESET(1U)
9772 #define A_TP_MIB_INDEX 0x7e50
9773 #define A_TP_MIB_DATA 0x7e54
9774 #define A_TP_SYNC_TIME_HI 0x7e58
9775 #define A_TP_SYNC_TIME_LO 0x7e5c
9776 #define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
9777 #define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
9778 #define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
9779 #define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c
9781 #define S_CMMAXPSTRUCT 0
9782 #define M_CMMAXPSTRUCT 0x1fffffU
9783 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
9784 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
9786 #define A_TP_INT_ENABLE 0x7e70
9788 #define S_FLMTXFLSTEMPTY 30
9789 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
9790 #define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U)
9792 #define S_RSSLKPPERR 29
9793 #define V_RSSLKPPERR(x) ((x) << S_RSSLKPPERR)
9794 #define F_RSSLKPPERR V_RSSLKPPERR(1U)
9796 #define S_FLMPERRSET 28
9797 #define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
9798 #define F_FLMPERRSET V_FLMPERRSET(1U)
9800 #define S_PROTOCOLSRAMPERR 27
9801 #define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
9802 #define F_PROTOCOLSRAMPERR V_PROTOCOLSRAMPERR(1U)
9804 #define S_ARPLUTPERR 26
9805 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
9806 #define F_ARPLUTPERR V_ARPLUTPERR(1U)
9808 #define S_CMRCFOPPERR 25
9809 #define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
9810 #define F_CMRCFOPPERR V_CMRCFOPPERR(1U)
9812 #define S_CMCACHEPERR 24
9813 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
9814 #define F_CMCACHEPERR V_CMCACHEPERR(1U)
9816 #define S_CMRCFDATAPERR 23
9817 #define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
9818 #define F_CMRCFDATAPERR V_CMRCFDATAPERR(1U)
9820 #define S_DBL2TLUTPERR 22
9821 #define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
9822 #define F_DBL2TLUTPERR V_DBL2TLUTPERR(1U)
9824 #define S_DBTXTIDPERR 21
9825 #define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
9826 #define F_DBTXTIDPERR V_DBTXTIDPERR(1U)
9828 #define S_DBEXTPERR 20
9829 #define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
9830 #define F_DBEXTPERR V_DBEXTPERR(1U)
9832 #define S_DBOPPERR 19
9833 #define V_DBOPPERR(x) ((x) << S_DBOPPERR)
9834 #define F_DBOPPERR V_DBOPPERR(1U)
9836 #define S_TMCACHEPERR 18
9837 #define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
9838 #define F_TMCACHEPERR V_TMCACHEPERR(1U)
9840 #define S_ETPOUTCPLFIFOPERR 17
9841 #define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
9842 #define F_ETPOUTCPLFIFOPERR V_ETPOUTCPLFIFOPERR(1U)
9844 #define S_ETPOUTTCPFIFOPERR 16
9845 #define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
9846 #define F_ETPOUTTCPFIFOPERR V_ETPOUTTCPFIFOPERR(1U)
9848 #define S_ETPOUTIPFIFOPERR 15
9849 #define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
9850 #define F_ETPOUTIPFIFOPERR V_ETPOUTIPFIFOPERR(1U)
9852 #define S_ETPOUTETHFIFOPERR 14
9853 #define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
9854 #define F_ETPOUTETHFIFOPERR V_ETPOUTETHFIFOPERR(1U)
9856 #define S_ETPINCPLFIFOPERR 13
9857 #define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
9858 #define F_ETPINCPLFIFOPERR V_ETPINCPLFIFOPERR(1U)
9860 #define S_ETPINTCPOPTFIFOPERR 12
9861 #define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
9862 #define F_ETPINTCPOPTFIFOPERR V_ETPINTCPOPTFIFOPERR(1U)
9864 #define S_ETPINTCPFIFOPERR 11
9865 #define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
9866 #define F_ETPINTCPFIFOPERR V_ETPINTCPFIFOPERR(1U)
9868 #define S_ETPINIPFIFOPERR 10
9869 #define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
9870 #define F_ETPINIPFIFOPERR V_ETPINIPFIFOPERR(1U)
9872 #define S_ETPINETHFIFOPERR 9
9873 #define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
9874 #define F_ETPINETHFIFOPERR V_ETPINETHFIFOPERR(1U)
9876 #define S_CTPOUTCPLFIFOPERR 8
9877 #define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
9878 #define F_CTPOUTCPLFIFOPERR V_CTPOUTCPLFIFOPERR(1U)
9880 #define S_CTPOUTTCPFIFOPERR 7
9881 #define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
9882 #define F_CTPOUTTCPFIFOPERR V_CTPOUTTCPFIFOPERR(1U)
9884 #define S_CTPOUTIPFIFOPERR 6
9885 #define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
9886 #define F_CTPOUTIPFIFOPERR V_CTPOUTIPFIFOPERR(1U)
9888 #define S_CTPOUTETHFIFOPERR 5
9889 #define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
9890 #define F_CTPOUTETHFIFOPERR V_CTPOUTETHFIFOPERR(1U)
9892 #define S_CTPINCPLFIFOPERR 4
9893 #define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
9894 #define F_CTPINCPLFIFOPERR V_CTPINCPLFIFOPERR(1U)
9896 #define S_CTPINTCPOPFIFOPERR 3
9897 #define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
9898 #define F_CTPINTCPOPFIFOPERR V_CTPINTCPOPFIFOPERR(1U)
9900 #define S_PDUFBKFIFOPERR 2
9901 #define V_PDUFBKFIFOPERR(x) ((x) << S_PDUFBKFIFOPERR)
9902 #define F_PDUFBKFIFOPERR V_PDUFBKFIFOPERR(1U)
9904 #define S_CMOPEXTFIFOPERR 1
9905 #define V_CMOPEXTFIFOPERR(x) ((x) << S_CMOPEXTFIFOPERR)
9906 #define F_CMOPEXTFIFOPERR V_CMOPEXTFIFOPERR(1U)
9908 #define S_DELINVFIFOPERR 0
9909 #define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR)
9910 #define F_DELINVFIFOPERR V_DELINVFIFOPERR(1U)
9912 #define A_TP_INT_CAUSE 0x7e74
9913 #define A_TP_PER_ENABLE 0x7e78
9914 #define A_TP_FLM_FREE_PS_CNT 0x7e80
9916 #define S_FREEPSTRUCTCOUNT 0
9917 #define M_FREEPSTRUCTCOUNT 0x1fffffU
9918 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
9919 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
9921 #define A_TP_FLM_FREE_RX_CNT 0x7e84
9923 #define S_FREERXPAGECHN 28
9924 #define V_FREERXPAGECHN(x) ((x) << S_FREERXPAGECHN)
9925 #define F_FREERXPAGECHN V_FREERXPAGECHN(1U)
9927 #define S_FREERXPAGECOUNT 0
9928 #define M_FREERXPAGECOUNT 0x1fffffU
9929 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
9930 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
9932 #define A_TP_FLM_FREE_TX_CNT 0x7e88
9934 #define S_FREETXPAGECHN 28
9935 #define M_FREETXPAGECHN 0x3U
9936 #define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN)
9937 #define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN)
9939 #define S_FREETXPAGECOUNT 0
9940 #define M_FREETXPAGECOUNT 0x1fffffU
9941 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
9942 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
9944 #define A_TP_TM_HEAP_PUSH_CNT 0x7e8c
9945 #define A_TP_TM_HEAP_POP_CNT 0x7e90
9946 #define A_TP_TM_DACK_PUSH_CNT 0x7e94
9947 #define A_TP_TM_DACK_POP_CNT 0x7e98
9948 #define A_TP_TM_MOD_PUSH_CNT 0x7e9c
9949 #define A_TP_MOD_POP_CNT 0x7ea0
9950 #define A_TP_TIMER_SEPARATOR 0x7ea4
9952 #define S_TIMERSEPARATOR 16
9953 #define M_TIMERSEPARATOR 0xffffU
9954 #define V_TIMERSEPARATOR(x) ((x) << S_TIMERSEPARATOR)
9955 #define G_TIMERSEPARATOR(x) (((x) >> S_TIMERSEPARATOR) & M_TIMERSEPARATOR)
9957 #define S_DISABLETIMEFREEZE 0
9958 #define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE)
9959 #define F_DISABLETIMEFREEZE V_DISABLETIMEFREEZE(1U)
9961 #define A_TP_DEBUG_FLAGS 0x7eac
9963 #define S_RXTIMERDACKFIRST 26
9964 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
9965 #define F_RXTIMERDACKFIRST V_RXTIMERDACKFIRST(1U)
9967 #define S_RXTIMERDACK 25
9968 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
9969 #define F_RXTIMERDACK V_RXTIMERDACK(1U)
9971 #define S_RXTIMERHEARTBEAT 24
9972 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
9973 #define F_RXTIMERHEARTBEAT V_RXTIMERHEARTBEAT(1U)
9975 #define S_RXPAWSDROP 23
9976 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
9977 #define F_RXPAWSDROP V_RXPAWSDROP(1U)
9979 #define S_RXURGDATADROP 22
9980 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
9981 #define F_RXURGDATADROP V_RXURGDATADROP(1U)
9983 #define S_RXFUTUREDATA 21
9984 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
9985 #define F_RXFUTUREDATA V_RXFUTUREDATA(1U)
9987 #define S_RXRCVRXMDATA 20
9988 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
9989 #define F_RXRCVRXMDATA V_RXRCVRXMDATA(1U)
9991 #define S_RXRCVOOODATAFIN 19
9992 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
9993 #define F_RXRCVOOODATAFIN V_RXRCVOOODATAFIN(1U)
9995 #define S_RXRCVOOODATA 18
9996 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
9997 #define F_RXRCVOOODATA V_RXRCVOOODATA(1U)
9999 #define S_RXRCVWNDZERO 17
10000 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
10001 #define F_RXRCVWNDZERO V_RXRCVWNDZERO(1U)
10003 #define S_RXRCVWNDLTMSS 16
10004 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
10005 #define F_RXRCVWNDLTMSS V_RXRCVWNDLTMSS(1U)
10007 #define S_TXDUPACKINC 11
10008 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
10009 #define F_TXDUPACKINC V_TXDUPACKINC(1U)
10011 #define S_TXRXMURG 10
10012 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
10013 #define F_TXRXMURG V_TXRXMURG(1U)
10015 #define S_TXRXMFIN 9
10016 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
10017 #define F_TXRXMFIN V_TXRXMFIN(1U)
10019 #define S_TXRXMSYN 8
10020 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
10021 #define F_TXRXMSYN V_TXRXMSYN(1U)
10023 #define S_TXRXMNEWRENO 7
10024 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
10025 #define F_TXRXMNEWRENO V_TXRXMNEWRENO(1U)
10027 #define S_TXRXMFAST 6
10028 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
10029 #define F_TXRXMFAST V_TXRXMFAST(1U)
10031 #define S_TXRXMTIMER 5
10032 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
10033 #define F_TXRXMTIMER V_TXRXMTIMER(1U)
10035 #define S_TXRXMTIMERKEEPALIVE 4
10036 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
10037 #define F_TXRXMTIMERKEEPALIVE V_TXRXMTIMERKEEPALIVE(1U)
10039 #define S_TXRXMTIMERPERSIST 3
10040 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
10041 #define F_TXRXMTIMERPERSIST V_TXRXMTIMERPERSIST(1U)
10043 #define S_TXRCVADVSHRUNK 2
10044 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
10045 #define F_TXRCVADVSHRUNK V_TXRCVADVSHRUNK(1U)
10047 #define S_TXRCVADVZERO 1
10048 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
10049 #define F_TXRCVADVZERO V_TXRCVADVZERO(1U)
10051 #define S_TXRCVADVLTMSS 0
10052 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
10053 #define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U)
10055 #define A_TP_RX_SCHED 0x7eb0
10057 #define S_RXCOMMITRESET1 31
10058 #define V_RXCOMMITRESET1(x) ((x) << S_RXCOMMITRESET1)
10059 #define F_RXCOMMITRESET1 V_RXCOMMITRESET1(1U)
10061 #define S_RXCOMMITRESET0 30
10062 #define V_RXCOMMITRESET0(x) ((x) << S_RXCOMMITRESET0)
10063 #define F_RXCOMMITRESET0 V_RXCOMMITRESET0(1U)
10065 #define S_RXFORCECONG1 29
10066 #define V_RXFORCECONG1(x) ((x) << S_RXFORCECONG1)
10067 #define F_RXFORCECONG1 V_RXFORCECONG1(1U)
10069 #define S_RXFORCECONG0 28
10070 #define V_RXFORCECONG0(x) ((x) << S_RXFORCECONG0)
10071 #define F_RXFORCECONG0 V_RXFORCECONG0(1U)
10073 #define S_ENABLELPBKFULL1 26
10074 #define M_ENABLELPBKFULL1 0x3U
10075 #define V_ENABLELPBKFULL1(x) ((x) << S_ENABLELPBKFULL1)
10076 #define G_ENABLELPBKFULL1(x) (((x) >> S_ENABLELPBKFULL1) & M_ENABLELPBKFULL1)
10078 #define S_ENABLELPBKFULL0 24
10079 #define M_ENABLELPBKFULL0 0x3U
10080 #define V_ENABLELPBKFULL0(x) ((x) << S_ENABLELPBKFULL0)
10081 #define G_ENABLELPBKFULL0(x) (((x) >> S_ENABLELPBKFULL0) & M_ENABLELPBKFULL0)
10083 #define S_ENABLEFIFOFULL1 22
10084 #define M_ENABLEFIFOFULL1 0x3U
10085 #define V_ENABLEFIFOFULL1(x) ((x) << S_ENABLEFIFOFULL1)
10086 #define G_ENABLEFIFOFULL1(x) (((x) >> S_ENABLEFIFOFULL1) & M_ENABLEFIFOFULL1)
10088 #define S_ENABLEPCMDFULL1 20
10089 #define M_ENABLEPCMDFULL1 0x3U
10090 #define V_ENABLEPCMDFULL1(x) ((x) << S_ENABLEPCMDFULL1)
10091 #define G_ENABLEPCMDFULL1(x) (((x) >> S_ENABLEPCMDFULL1) & M_ENABLEPCMDFULL1)
10093 #define S_ENABLEHDRFULL1 18
10094 #define M_ENABLEHDRFULL1 0x3U
10095 #define V_ENABLEHDRFULL1(x) ((x) << S_ENABLEHDRFULL1)
10096 #define G_ENABLEHDRFULL1(x) (((x) >> S_ENABLEHDRFULL1) & M_ENABLEHDRFULL1)
10098 #define S_ENABLEFIFOFULL0 16
10099 #define M_ENABLEFIFOFULL0 0x3U
10100 #define V_ENABLEFIFOFULL0(x) ((x) << S_ENABLEFIFOFULL0)
10101 #define G_ENABLEFIFOFULL0(x) (((x) >> S_ENABLEFIFOFULL0) & M_ENABLEFIFOFULL0)
10103 #define S_ENABLEPCMDFULL0 14
10104 #define M_ENABLEPCMDFULL0 0x3U
10105 #define V_ENABLEPCMDFULL0(x) ((x) << S_ENABLEPCMDFULL0)
10106 #define G_ENABLEPCMDFULL0(x) (((x) >> S_ENABLEPCMDFULL0) & M_ENABLEPCMDFULL0)
10108 #define S_ENABLEHDRFULL0 12
10109 #define M_ENABLEHDRFULL0 0x3U
10110 #define V_ENABLEHDRFULL0(x) ((x) << S_ENABLEHDRFULL0)
10111 #define G_ENABLEHDRFULL0(x) (((x) >> S_ENABLEHDRFULL0) & M_ENABLEHDRFULL0)
10113 #define S_COMMITLIMIT1 6
10114 #define M_COMMITLIMIT1 0x3fU
10115 #define V_COMMITLIMIT1(x) ((x) << S_COMMITLIMIT1)
10116 #define G_COMMITLIMIT1(x) (((x) >> S_COMMITLIMIT1) & M_COMMITLIMIT1)
10118 #define S_COMMITLIMIT0 0
10119 #define M_COMMITLIMIT0 0x3fU
10120 #define V_COMMITLIMIT0(x) ((x) << S_COMMITLIMIT0)
10121 #define G_COMMITLIMIT0(x) (((x) >> S_COMMITLIMIT0) & M_COMMITLIMIT0)
10123 #define A_TP_TX_SCHED 0x7eb4
10125 #define S_COMMITRESET3 31
10126 #define V_COMMITRESET3(x) ((x) << S_COMMITRESET3)
10127 #define F_COMMITRESET3 V_COMMITRESET3(1U)
10129 #define S_COMMITRESET2 30
10130 #define V_COMMITRESET2(x) ((x) << S_COMMITRESET2)
10131 #define F_COMMITRESET2 V_COMMITRESET2(1U)
10133 #define S_COMMITRESET1 29
10134 #define V_COMMITRESET1(x) ((x) << S_COMMITRESET1)
10135 #define F_COMMITRESET1 V_COMMITRESET1(1U)
10137 #define S_COMMITRESET0 28
10138 #define V_COMMITRESET0(x) ((x) << S_COMMITRESET0)
10139 #define F_COMMITRESET0 V_COMMITRESET0(1U)
10141 #define S_FORCECONG3 27
10142 #define V_FORCECONG3(x) ((x) << S_FORCECONG3)
10143 #define F_FORCECONG3 V_FORCECONG3(1U)
10145 #define S_FORCECONG2 26
10146 #define V_FORCECONG2(x) ((x) << S_FORCECONG2)
10147 #define F_FORCECONG2 V_FORCECONG2(1U)
10149 #define S_FORCECONG1 25
10150 #define V_FORCECONG1(x) ((x) << S_FORCECONG1)
10151 #define F_FORCECONG1 V_FORCECONG1(1U)
10153 #define S_FORCECONG0 24
10154 #define V_FORCECONG0(x) ((x) << S_FORCECONG0)
10155 #define F_FORCECONG0 V_FORCECONG0(1U)
10157 #define S_COMMITLIMIT3 18
10158 #define M_COMMITLIMIT3 0x3fU
10159 #define V_COMMITLIMIT3(x) ((x) << S_COMMITLIMIT3)
10160 #define G_COMMITLIMIT3(x) (((x) >> S_COMMITLIMIT3) & M_COMMITLIMIT3)
10162 #define S_COMMITLIMIT2 12
10163 #define M_COMMITLIMIT2 0x3fU
10164 #define V_COMMITLIMIT2(x) ((x) << S_COMMITLIMIT2)
10165 #define G_COMMITLIMIT2(x) (((x) >> S_COMMITLIMIT2) & M_COMMITLIMIT2)
10167 #define A_TP_FX_SCHED 0x7eb8
10169 #define S_TXCHNXOFF3 19
10170 #define V_TXCHNXOFF3(x) ((x) << S_TXCHNXOFF3)
10171 #define F_TXCHNXOFF3 V_TXCHNXOFF3(1U)
10173 #define S_TXCHNXOFF2 18
10174 #define V_TXCHNXOFF2(x) ((x) << S_TXCHNXOFF2)
10175 #define F_TXCHNXOFF2 V_TXCHNXOFF2(1U)
10177 #define S_TXCHNXOFF1 17
10178 #define V_TXCHNXOFF1(x) ((x) << S_TXCHNXOFF1)
10179 #define F_TXCHNXOFF1 V_TXCHNXOFF1(1U)
10181 #define S_TXCHNXOFF0 16
10182 #define V_TXCHNXOFF0(x) ((x) << S_TXCHNXOFF0)
10183 #define F_TXCHNXOFF0 V_TXCHNXOFF0(1U)
10185 #define S_TXMODXOFF7 15
10186 #define V_TXMODXOFF7(x) ((x) << S_TXMODXOFF7)
10187 #define F_TXMODXOFF7 V_TXMODXOFF7(1U)
10189 #define S_TXMODXOFF6 14
10190 #define V_TXMODXOFF6(x) ((x) << S_TXMODXOFF6)
10191 #define F_TXMODXOFF6 V_TXMODXOFF6(1U)
10193 #define S_TXMODXOFF5 13
10194 #define V_TXMODXOFF5(x) ((x) << S_TXMODXOFF5)
10195 #define F_TXMODXOFF5 V_TXMODXOFF5(1U)
10197 #define S_TXMODXOFF4 12
10198 #define V_TXMODXOFF4(x) ((x) << S_TXMODXOFF4)
10199 #define F_TXMODXOFF4 V_TXMODXOFF4(1U)
10201 #define S_TXMODXOFF3 11
10202 #define V_TXMODXOFF3(x) ((x) << S_TXMODXOFF3)
10203 #define F_TXMODXOFF3 V_TXMODXOFF3(1U)
10205 #define S_TXMODXOFF2 10
10206 #define V_TXMODXOFF2(x) ((x) << S_TXMODXOFF2)
10207 #define F_TXMODXOFF2 V_TXMODXOFF2(1U)
10209 #define S_TXMODXOFF1 9
10210 #define V_TXMODXOFF1(x) ((x) << S_TXMODXOFF1)
10211 #define F_TXMODXOFF1 V_TXMODXOFF1(1U)
10213 #define S_TXMODXOFF0 8
10214 #define V_TXMODXOFF0(x) ((x) << S_TXMODXOFF0)
10215 #define F_TXMODXOFF0 V_TXMODXOFF0(1U)
10217 #define S_RXCHNXOFF3 7
10218 #define V_RXCHNXOFF3(x) ((x) << S_RXCHNXOFF3)
10219 #define F_RXCHNXOFF3 V_RXCHNXOFF3(1U)
10221 #define S_RXCHNXOFF2 6
10222 #define V_RXCHNXOFF2(x) ((x) << S_RXCHNXOFF2)
10223 #define F_RXCHNXOFF2 V_RXCHNXOFF2(1U)
10225 #define S_RXCHNXOFF1 5
10226 #define V_RXCHNXOFF1(x) ((x) << S_RXCHNXOFF1)
10227 #define F_RXCHNXOFF1 V_RXCHNXOFF1(1U)
10229 #define S_RXCHNXOFF0 4
10230 #define V_RXCHNXOFF0(x) ((x) << S_RXCHNXOFF0)
10231 #define F_RXCHNXOFF0 V_RXCHNXOFF0(1U)
10233 #define S_RXMODXOFF1 1
10234 #define V_RXMODXOFF1(x) ((x) << S_RXMODXOFF1)
10235 #define F_RXMODXOFF1 V_RXMODXOFF1(1U)
10237 #define S_RXMODXOFF0 0
10238 #define V_RXMODXOFF0(x) ((x) << S_RXMODXOFF0)
10239 #define F_RXMODXOFF0 V_RXMODXOFF0(1U)
10241 #define A_TP_TX_ORATE 0x7ebc
10243 #define S_OFDRATE3 24
10244 #define M_OFDRATE3 0xffU
10245 #define V_OFDRATE3(x) ((x) << S_OFDRATE3)
10246 #define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3)
10248 #define S_OFDRATE2 16
10249 #define M_OFDRATE2 0xffU
10250 #define V_OFDRATE2(x) ((x) << S_OFDRATE2)
10251 #define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2)
10253 #define S_OFDRATE1 8
10254 #define M_OFDRATE1 0xffU
10255 #define V_OFDRATE1(x) ((x) << S_OFDRATE1)
10256 #define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1)
10258 #define S_OFDRATE0 0
10259 #define M_OFDRATE0 0xffU
10260 #define V_OFDRATE0(x) ((x) << S_OFDRATE0)
10261 #define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0)
10263 #define A_TP_IX_SCHED0 0x7ec0
10264 #define A_TP_IX_SCHED1 0x7ec4
10265 #define A_TP_IX_SCHED2 0x7ec8
10266 #define A_TP_IX_SCHED3 0x7ecc
10267 #define A_TP_TX_TRATE 0x7ed0
10269 #define S_TNLRATE3 24
10270 #define M_TNLRATE3 0xffU
10271 #define V_TNLRATE3(x) ((x) << S_TNLRATE3)
10272 #define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3)
10274 #define S_TNLRATE2 16
10275 #define M_TNLRATE2 0xffU
10276 #define V_TNLRATE2(x) ((x) << S_TNLRATE2)
10277 #define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2)
10279 #define S_TNLRATE1 8
10280 #define M_TNLRATE1 0xffU
10281 #define V_TNLRATE1(x) ((x) << S_TNLRATE1)
10282 #define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1)
10284 #define S_TNLRATE0 0
10285 #define M_TNLRATE0 0xffU
10286 #define V_TNLRATE0(x) ((x) << S_TNLRATE0)
10287 #define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0)
10289 #define A_TP_DBG_LA_CONFIG 0x7ed4
10291 #define S_DBGLAOPCENABLE 24
10292 #define M_DBGLAOPCENABLE 0xffU
10293 #define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE)
10294 #define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE)
10296 #define S_DBGLAWHLF 23
10297 #define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF)
10298 #define F_DBGLAWHLF V_DBGLAWHLF(1U)
10300 #define S_DBGLAWPTR 16
10301 #define M_DBGLAWPTR 0x7fU
10302 #define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR)
10303 #define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR)
10305 #define S_DBGLAMODE 14
10306 #define M_DBGLAMODE 0x3U
10307 #define V_DBGLAMODE(x) ((x) << S_DBGLAMODE)
10308 #define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE)
10310 #define S_DBGLAFATALFREEZE 13
10311 #define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE)
10312 #define F_DBGLAFATALFREEZE V_DBGLAFATALFREEZE(1U)
10314 #define S_DBGLAENABLE 12
10315 #define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE)
10316 #define F_DBGLAENABLE V_DBGLAENABLE(1U)
10318 #define S_DBGLARPTR 0
10319 #define M_DBGLARPTR 0x7fU
10320 #define V_DBGLARPTR(x) ((x) << S_DBGLARPTR)
10321 #define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR)
10323 #define A_TP_DBG_LA_DATAL 0x7ed8
10324 #define A_TP_DBG_LA_DATAH 0x7edc
10325 #define A_TP_PROTOCOL_CNTRL 0x7ee8
10327 #define S_WRITEENABLE 31
10328 #define V_WRITEENABLE(x) ((x) << S_WRITEENABLE)
10329 #define F_WRITEENABLE V_WRITEENABLE(1U)
10331 #define S_TCAMENABLE 10
10332 #define V_TCAMENABLE(x) ((x) << S_TCAMENABLE)
10333 #define F_TCAMENABLE V_TCAMENABLE(1U)
10335 #define S_BLOCKSELECT 8
10336 #define M_BLOCKSELECT 0x3U
10337 #define V_BLOCKSELECT(x) ((x) << S_BLOCKSELECT)
10338 #define G_BLOCKSELECT(x) (((x) >> S_BLOCKSELECT) & M_BLOCKSELECT)
10340 #define S_LINEADDRESS 1
10341 #define M_LINEADDRESS 0x7fU
10342 #define V_LINEADDRESS(x) ((x) << S_LINEADDRESS)
10343 #define G_LINEADDRESS(x) (((x) >> S_LINEADDRESS) & M_LINEADDRESS)
10345 #define S_REQUESTDONE 0
10346 #define V_REQUESTDONE(x) ((x) << S_REQUESTDONE)
10347 #define F_REQUESTDONE V_REQUESTDONE(1U)
10349 #define A_TP_PROTOCOL_DATA0 0x7eec
10350 #define A_TP_PROTOCOL_DATA1 0x7ef0
10351 #define A_TP_PROTOCOL_DATA2 0x7ef4
10352 #define A_TP_PROTOCOL_DATA3 0x7ef8
10353 #define A_TP_PROTOCOL_DATA4 0x7efc
10355 #define S_PROTOCOLDATAFIELD 0
10356 #define M_PROTOCOLDATAFIELD 0xfU
10357 #define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD)
10358 #define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD)
10360 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
10362 #define S_TXTIMERSEPQ7 16
10363 #define M_TXTIMERSEPQ7 0xffffU
10364 #define V_TXTIMERSEPQ7(x) ((x) << S_TXTIMERSEPQ7)
10365 #define G_TXTIMERSEPQ7(x) (((x) >> S_TXTIMERSEPQ7) & M_TXTIMERSEPQ7)
10367 #define S_TXTIMERSEPQ6 0
10368 #define M_TXTIMERSEPQ6 0xffffU
10369 #define V_TXTIMERSEPQ6(x) ((x) << S_TXTIMERSEPQ6)
10370 #define G_TXTIMERSEPQ6(x) (((x) >> S_TXTIMERSEPQ6) & M_TXTIMERSEPQ6)
10372 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
10374 #define S_TXTIMERSEPQ5 16
10375 #define M_TXTIMERSEPQ5 0xffffU
10376 #define V_TXTIMERSEPQ5(x) ((x) << S_TXTIMERSEPQ5)
10377 #define G_TXTIMERSEPQ5(x) (((x) >> S_TXTIMERSEPQ5) & M_TXTIMERSEPQ5)
10379 #define S_TXTIMERSEPQ4 0
10380 #define M_TXTIMERSEPQ4 0xffffU
10381 #define V_TXTIMERSEPQ4(x) ((x) << S_TXTIMERSEPQ4)
10382 #define G_TXTIMERSEPQ4(x) (((x) >> S_TXTIMERSEPQ4) & M_TXTIMERSEPQ4)
10384 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
10386 #define S_TXTIMERSEPQ3 16
10387 #define M_TXTIMERSEPQ3 0xffffU
10388 #define V_TXTIMERSEPQ3(x) ((x) << S_TXTIMERSEPQ3)
10389 #define G_TXTIMERSEPQ3(x) (((x) >> S_TXTIMERSEPQ3) & M_TXTIMERSEPQ3)
10391 #define S_TXTIMERSEPQ2 0
10392 #define M_TXTIMERSEPQ2 0xffffU
10393 #define V_TXTIMERSEPQ2(x) ((x) << S_TXTIMERSEPQ2)
10394 #define G_TXTIMERSEPQ2(x) (((x) >> S_TXTIMERSEPQ2) & M_TXTIMERSEPQ2)
10396 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
10398 #define S_TXTIMERSEPQ1 16
10399 #define M_TXTIMERSEPQ1 0xffffU
10400 #define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1)
10401 #define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1)
10403 #define S_TXTIMERSEPQ0 0
10404 #define M_TXTIMERSEPQ0 0xffffU
10405 #define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0)
10406 #define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0)
10408 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
10410 #define S_RXTIMERSEPQ1 16
10411 #define M_RXTIMERSEPQ1 0xffffU
10412 #define V_RXTIMERSEPQ1(x) ((x) << S_RXTIMERSEPQ1)
10413 #define G_RXTIMERSEPQ1(x) (((x) >> S_RXTIMERSEPQ1) & M_RXTIMERSEPQ1)
10415 #define S_RXTIMERSEPQ0 0
10416 #define M_RXTIMERSEPQ0 0xffffU
10417 #define V_RXTIMERSEPQ0(x) ((x) << S_RXTIMERSEPQ0)
10418 #define G_RXTIMERSEPQ0(x) (((x) >> S_RXTIMERSEPQ0) & M_RXTIMERSEPQ0)
10420 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
10422 #define S_TXRATEINCQ7 24
10423 #define M_TXRATEINCQ7 0xffU
10424 #define V_TXRATEINCQ7(x) ((x) << S_TXRATEINCQ7)
10425 #define G_TXRATEINCQ7(x) (((x) >> S_TXRATEINCQ7) & M_TXRATEINCQ7)
10427 #define S_TXRATETCKQ7 16
10428 #define M_TXRATETCKQ7 0xffU
10429 #define V_TXRATETCKQ7(x) ((x) << S_TXRATETCKQ7)
10430 #define G_TXRATETCKQ7(x) (((x) >> S_TXRATETCKQ7) & M_TXRATETCKQ7)
10432 #define S_TXRATEINCQ6 8
10433 #define M_TXRATEINCQ6 0xffU
10434 #define V_TXRATEINCQ6(x) ((x) << S_TXRATEINCQ6)
10435 #define G_TXRATEINCQ6(x) (((x) >> S_TXRATEINCQ6) & M_TXRATEINCQ6)
10437 #define S_TXRATETCKQ6 0
10438 #define M_TXRATETCKQ6 0xffU
10439 #define V_TXRATETCKQ6(x) ((x) << S_TXRATETCKQ6)
10440 #define G_TXRATETCKQ6(x) (((x) >> S_TXRATETCKQ6) & M_TXRATETCKQ6)
10442 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
10444 #define S_TXRATEINCQ5 24
10445 #define M_TXRATEINCQ5 0xffU
10446 #define V_TXRATEINCQ5(x) ((x) << S_TXRATEINCQ5)
10447 #define G_TXRATEINCQ5(x) (((x) >> S_TXRATEINCQ5) & M_TXRATEINCQ5)
10449 #define S_TXRATETCKQ5 16
10450 #define M_TXRATETCKQ5 0xffU
10451 #define V_TXRATETCKQ5(x) ((x) << S_TXRATETCKQ5)
10452 #define G_TXRATETCKQ5(x) (((x) >> S_TXRATETCKQ5) & M_TXRATETCKQ5)
10454 #define S_TXRATEINCQ4 8
10455 #define M_TXRATEINCQ4 0xffU
10456 #define V_TXRATEINCQ4(x) ((x) << S_TXRATEINCQ4)
10457 #define G_TXRATEINCQ4(x) (((x) >> S_TXRATEINCQ4) & M_TXRATEINCQ4)
10459 #define S_TXRATETCKQ4 0
10460 #define M_TXRATETCKQ4 0xffU
10461 #define V_TXRATETCKQ4(x) ((x) << S_TXRATETCKQ4)
10462 #define G_TXRATETCKQ4(x) (((x) >> S_TXRATETCKQ4) & M_TXRATETCKQ4)
10464 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
10466 #define S_TXRATEINCQ3 24
10467 #define M_TXRATEINCQ3 0xffU
10468 #define V_TXRATEINCQ3(x) ((x) << S_TXRATEINCQ3)
10469 #define G_TXRATEINCQ3(x) (((x) >> S_TXRATEINCQ3) & M_TXRATEINCQ3)
10471 #define S_TXRATETCKQ3 16
10472 #define M_TXRATETCKQ3 0xffU
10473 #define V_TXRATETCKQ3(x) ((x) << S_TXRATETCKQ3)
10474 #define G_TXRATETCKQ3(x) (((x) >> S_TXRATETCKQ3) & M_TXRATETCKQ3)
10476 #define S_TXRATEINCQ2 8
10477 #define M_TXRATEINCQ2 0xffU
10478 #define V_TXRATEINCQ2(x) ((x) << S_TXRATEINCQ2)
10479 #define G_TXRATEINCQ2(x) (((x) >> S_TXRATEINCQ2) & M_TXRATEINCQ2)
10481 #define S_TXRATETCKQ2 0
10482 #define M_TXRATETCKQ2 0xffU
10483 #define V_TXRATETCKQ2(x) ((x) << S_TXRATETCKQ2)
10484 #define G_TXRATETCKQ2(x) (((x) >> S_TXRATETCKQ2) & M_TXRATETCKQ2)
10486 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
10488 #define S_TXRATEINCQ1 24
10489 #define M_TXRATEINCQ1 0xffU
10490 #define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1)
10491 #define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1)
10493 #define S_TXRATETCKQ1 16
10494 #define M_TXRATETCKQ1 0xffU
10495 #define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1)
10496 #define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1)
10498 #define S_TXRATEINCQ0 8
10499 #define M_TXRATEINCQ0 0xffU
10500 #define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0)
10501 #define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0)
10503 #define S_TXRATETCKQ0 0
10504 #define M_TXRATETCKQ0 0xffU
10505 #define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0)
10506 #define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0)
10508 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
10510 #define S_RXRATEINCQ1 24
10511 #define M_RXRATEINCQ1 0xffU
10512 #define V_RXRATEINCQ1(x) ((x) << S_RXRATEINCQ1)
10513 #define G_RXRATEINCQ1(x) (((x) >> S_RXRATEINCQ1) & M_RXRATEINCQ1)
10515 #define S_RXRATETCKQ1 16
10516 #define M_RXRATETCKQ1 0xffU
10517 #define V_RXRATETCKQ1(x) ((x) << S_RXRATETCKQ1)
10518 #define G_RXRATETCKQ1(x) (((x) >> S_RXRATETCKQ1) & M_RXRATETCKQ1)
10520 #define S_RXRATEINCQ0 8
10521 #define M_RXRATEINCQ0 0xffU
10522 #define V_RXRATEINCQ0(x) ((x) << S_RXRATEINCQ0)
10523 #define G_RXRATEINCQ0(x) (((x) >> S_RXRATEINCQ0) & M_RXRATEINCQ0)
10525 #define S_RXRATETCKQ0 0
10526 #define M_RXRATETCKQ0 0xffU
10527 #define V_RXRATETCKQ0(x) ((x) << S_RXRATETCKQ0)
10528 #define G_RXRATETCKQ0(x) (((x) >> S_RXRATETCKQ0) & M_RXRATETCKQ0)
10530 #define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa
10531 #define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb
10532 #define A_TP_RX_SCHED_MAP 0x20
10534 #define S_RXMAPCHANNEL3 24
10535 #define M_RXMAPCHANNEL3 0xffU
10536 #define V_RXMAPCHANNEL3(x) ((x) << S_RXMAPCHANNEL3)
10537 #define G_RXMAPCHANNEL3(x) (((x) >> S_RXMAPCHANNEL3) & M_RXMAPCHANNEL3)
10539 #define S_RXMAPCHANNEL2 16
10540 #define M_RXMAPCHANNEL2 0xffU
10541 #define V_RXMAPCHANNEL2(x) ((x) << S_RXMAPCHANNEL2)
10542 #define G_RXMAPCHANNEL2(x) (((x) >> S_RXMAPCHANNEL2) & M_RXMAPCHANNEL2)
10544 #define S_RXMAPCHANNEL1 8
10545 #define M_RXMAPCHANNEL1 0xffU
10546 #define V_RXMAPCHANNEL1(x) ((x) << S_RXMAPCHANNEL1)
10547 #define G_RXMAPCHANNEL1(x) (((x) >> S_RXMAPCHANNEL1) & M_RXMAPCHANNEL1)
10549 #define S_RXMAPCHANNEL0 0
10550 #define M_RXMAPCHANNEL0 0xffU
10551 #define V_RXMAPCHANNEL0(x) ((x) << S_RXMAPCHANNEL0)
10552 #define G_RXMAPCHANNEL0(x) (((x) >> S_RXMAPCHANNEL0) & M_RXMAPCHANNEL0)
10554 #define A_TP_RX_SCHED_SGE 0x21
10556 #define S_RXSGEMOD1 12
10557 #define M_RXSGEMOD1 0xfU
10558 #define V_RXSGEMOD1(x) ((x) << S_RXSGEMOD1)
10559 #define G_RXSGEMOD1(x) (((x) >> S_RXSGEMOD1) & M_RXSGEMOD1)
10561 #define S_RXSGEMOD0 8
10562 #define M_RXSGEMOD0 0xfU
10563 #define V_RXSGEMOD0(x) ((x) << S_RXSGEMOD0)
10564 #define G_RXSGEMOD0(x) (((x) >> S_RXSGEMOD0) & M_RXSGEMOD0)
10566 #define S_RXSGECHANNEL3 3
10567 #define V_RXSGECHANNEL3(x) ((x) << S_RXSGECHANNEL3)
10568 #define F_RXSGECHANNEL3 V_RXSGECHANNEL3(1U)
10570 #define S_RXSGECHANNEL2 2
10571 #define V_RXSGECHANNEL2(x) ((x) << S_RXSGECHANNEL2)
10572 #define F_RXSGECHANNEL2 V_RXSGECHANNEL2(1U)
10574 #define S_RXSGECHANNEL1 1
10575 #define V_RXSGECHANNEL1(x) ((x) << S_RXSGECHANNEL1)
10576 #define F_RXSGECHANNEL1 V_RXSGECHANNEL1(1U)
10578 #define S_RXSGECHANNEL0 0
10579 #define V_RXSGECHANNEL0(x) ((x) << S_RXSGECHANNEL0)
10580 #define F_RXSGECHANNEL0 V_RXSGECHANNEL0(1U)
10582 #define A_TP_TX_SCHED_MAP 0x22
10584 #define S_TXMAPCHANNEL3 12
10585 #define M_TXMAPCHANNEL3 0xfU
10586 #define V_TXMAPCHANNEL3(x) ((x) << S_TXMAPCHANNEL3)
10587 #define G_TXMAPCHANNEL3(x) (((x) >> S_TXMAPCHANNEL3) & M_TXMAPCHANNEL3)
10589 #define S_TXMAPCHANNEL2 8
10590 #define M_TXMAPCHANNEL2 0xfU
10591 #define V_TXMAPCHANNEL2(x) ((x) << S_TXMAPCHANNEL2)
10592 #define G_TXMAPCHANNEL2(x) (((x) >> S_TXMAPCHANNEL2) & M_TXMAPCHANNEL2)
10594 #define S_TXMAPCHANNEL1 4
10595 #define M_TXMAPCHANNEL1 0xfU
10596 #define V_TXMAPCHANNEL1(x) ((x) << S_TXMAPCHANNEL1)
10597 #define G_TXMAPCHANNEL1(x) (((x) >> S_TXMAPCHANNEL1) & M_TXMAPCHANNEL1)
10599 #define S_TXMAPCHANNEL0 0
10600 #define M_TXMAPCHANNEL0 0xfU
10601 #define V_TXMAPCHANNEL0(x) ((x) << S_TXMAPCHANNEL0)
10602 #define G_TXMAPCHANNEL0(x) (((x) >> S_TXMAPCHANNEL0) & M_TXMAPCHANNEL0)
10604 #define A_TP_TX_SCHED_HDR 0x23
10606 #define S_TXMAPHDRCHANNEL7 28
10607 #define M_TXMAPHDRCHANNEL7 0xfU
10608 #define V_TXMAPHDRCHANNEL7(x) ((x) << S_TXMAPHDRCHANNEL7)
10609 #define G_TXMAPHDRCHANNEL7(x) (((x) >> S_TXMAPHDRCHANNEL7) & M_TXMAPHDRCHANNEL7)
10611 #define S_TXMAPHDRCHANNEL6 24
10612 #define M_TXMAPHDRCHANNEL6 0xfU
10613 #define V_TXMAPHDRCHANNEL6(x) ((x) << S_TXMAPHDRCHANNEL6)
10614 #define G_TXMAPHDRCHANNEL6(x) (((x) >> S_TXMAPHDRCHANNEL6) & M_TXMAPHDRCHANNEL6)
10616 #define S_TXMAPHDRCHANNEL5 20
10617 #define M_TXMAPHDRCHANNEL5 0xfU
10618 #define V_TXMAPHDRCHANNEL5(x) ((x) << S_TXMAPHDRCHANNEL5)
10619 #define G_TXMAPHDRCHANNEL5(x) (((x) >> S_TXMAPHDRCHANNEL5) & M_TXMAPHDRCHANNEL5)
10621 #define S_TXMAPHDRCHANNEL4 16
10622 #define M_TXMAPHDRCHANNEL4 0xfU
10623 #define V_TXMAPHDRCHANNEL4(x) ((x) << S_TXMAPHDRCHANNEL4)
10624 #define G_TXMAPHDRCHANNEL4(x) (((x) >> S_TXMAPHDRCHANNEL4) & M_TXMAPHDRCHANNEL4)
10626 #define S_TXMAPHDRCHANNEL3 12
10627 #define M_TXMAPHDRCHANNEL3 0xfU
10628 #define V_TXMAPHDRCHANNEL3(x) ((x) << S_TXMAPHDRCHANNEL3)
10629 #define G_TXMAPHDRCHANNEL3(x) (((x) >> S_TXMAPHDRCHANNEL3) & M_TXMAPHDRCHANNEL3)
10631 #define S_TXMAPHDRCHANNEL2 8
10632 #define M_TXMAPHDRCHANNEL2 0xfU
10633 #define V_TXMAPHDRCHANNEL2(x) ((x) << S_TXMAPHDRCHANNEL2)
10634 #define G_TXMAPHDRCHANNEL2(x) (((x) >> S_TXMAPHDRCHANNEL2) & M_TXMAPHDRCHANNEL2)
10636 #define S_TXMAPHDRCHANNEL1 4
10637 #define M_TXMAPHDRCHANNEL1 0xfU
10638 #define V_TXMAPHDRCHANNEL1(x) ((x) << S_TXMAPHDRCHANNEL1)
10639 #define G_TXMAPHDRCHANNEL1(x) (((x) >> S_TXMAPHDRCHANNEL1) & M_TXMAPHDRCHANNEL1)
10641 #define S_TXMAPHDRCHANNEL0 0
10642 #define M_TXMAPHDRCHANNEL0 0xfU
10643 #define V_TXMAPHDRCHANNEL0(x) ((x) << S_TXMAPHDRCHANNEL0)
10644 #define G_TXMAPHDRCHANNEL0(x) (((x) >> S_TXMAPHDRCHANNEL0) & M_TXMAPHDRCHANNEL0)
10646 #define A_TP_TX_SCHED_FIFO 0x24
10648 #define S_TXMAPFIFOCHANNEL7 28
10649 #define M_TXMAPFIFOCHANNEL7 0xfU
10650 #define V_TXMAPFIFOCHANNEL7(x) ((x) << S_TXMAPFIFOCHANNEL7)
10651 #define G_TXMAPFIFOCHANNEL7(x) (((x) >> S_TXMAPFIFOCHANNEL7) & M_TXMAPFIFOCHANNEL7)
10653 #define S_TXMAPFIFOCHANNEL6 24
10654 #define M_TXMAPFIFOCHANNEL6 0xfU
10655 #define V_TXMAPFIFOCHANNEL6(x) ((x) << S_TXMAPFIFOCHANNEL6)
10656 #define G_TXMAPFIFOCHANNEL6(x) (((x) >> S_TXMAPFIFOCHANNEL6) & M_TXMAPFIFOCHANNEL6)
10658 #define S_TXMAPFIFOCHANNEL5 20
10659 #define M_TXMAPFIFOCHANNEL5 0xfU
10660 #define V_TXMAPFIFOCHANNEL5(x) ((x) << S_TXMAPFIFOCHANNEL5)
10661 #define G_TXMAPFIFOCHANNEL5(x) (((x) >> S_TXMAPFIFOCHANNEL5) & M_TXMAPFIFOCHANNEL5)
10663 #define S_TXMAPFIFOCHANNEL4 16
10664 #define M_TXMAPFIFOCHANNEL4 0xfU
10665 #define V_TXMAPFIFOCHANNEL4(x) ((x) << S_TXMAPFIFOCHANNEL4)
10666 #define G_TXMAPFIFOCHANNEL4(x) (((x) >> S_TXMAPFIFOCHANNEL4) & M_TXMAPFIFOCHANNEL4)
10668 #define S_TXMAPFIFOCHANNEL3 12
10669 #define M_TXMAPFIFOCHANNEL3 0xfU
10670 #define V_TXMAPFIFOCHANNEL3(x) ((x) << S_TXMAPFIFOCHANNEL3)
10671 #define G_TXMAPFIFOCHANNEL3(x) (((x) >> S_TXMAPFIFOCHANNEL3) & M_TXMAPFIFOCHANNEL3)
10673 #define S_TXMAPFIFOCHANNEL2 8
10674 #define M_TXMAPFIFOCHANNEL2 0xfU
10675 #define V_TXMAPFIFOCHANNEL2(x) ((x) << S_TXMAPFIFOCHANNEL2)
10676 #define G_TXMAPFIFOCHANNEL2(x) (((x) >> S_TXMAPFIFOCHANNEL2) & M_TXMAPFIFOCHANNEL2)
10678 #define S_TXMAPFIFOCHANNEL1 4
10679 #define M_TXMAPFIFOCHANNEL1 0xfU
10680 #define V_TXMAPFIFOCHANNEL1(x) ((x) << S_TXMAPFIFOCHANNEL1)
10681 #define G_TXMAPFIFOCHANNEL1(x) (((x) >> S_TXMAPFIFOCHANNEL1) & M_TXMAPFIFOCHANNEL1)
10683 #define S_TXMAPFIFOCHANNEL0 0
10684 #define M_TXMAPFIFOCHANNEL0 0xfU
10685 #define V_TXMAPFIFOCHANNEL0(x) ((x) << S_TXMAPFIFOCHANNEL0)
10686 #define G_TXMAPFIFOCHANNEL0(x) (((x) >> S_TXMAPFIFOCHANNEL0) & M_TXMAPFIFOCHANNEL0)
10688 #define A_TP_TX_SCHED_PCMD 0x25
10690 #define S_TXMAPPCMDCHANNEL7 28
10691 #define M_TXMAPPCMDCHANNEL7 0xfU
10692 #define V_TXMAPPCMDCHANNEL7(x) ((x) << S_TXMAPPCMDCHANNEL7)
10693 #define G_TXMAPPCMDCHANNEL7(x) (((x) >> S_TXMAPPCMDCHANNEL7) & M_TXMAPPCMDCHANNEL7)
10695 #define S_TXMAPPCMDCHANNEL6 24
10696 #define M_TXMAPPCMDCHANNEL6 0xfU
10697 #define V_TXMAPPCMDCHANNEL6(x) ((x) << S_TXMAPPCMDCHANNEL6)
10698 #define G_TXMAPPCMDCHANNEL6(x) (((x) >> S_TXMAPPCMDCHANNEL6) & M_TXMAPPCMDCHANNEL6)
10700 #define S_TXMAPPCMDCHANNEL5 20
10701 #define M_TXMAPPCMDCHANNEL5 0xfU
10702 #define V_TXMAPPCMDCHANNEL5(x) ((x) << S_TXMAPPCMDCHANNEL5)
10703 #define G_TXMAPPCMDCHANNEL5(x) (((x) >> S_TXMAPPCMDCHANNEL5) & M_TXMAPPCMDCHANNEL5)
10705 #define S_TXMAPPCMDCHANNEL4 16
10706 #define M_TXMAPPCMDCHANNEL4 0xfU
10707 #define V_TXMAPPCMDCHANNEL4(x) ((x) << S_TXMAPPCMDCHANNEL4)
10708 #define G_TXMAPPCMDCHANNEL4(x) (((x) >> S_TXMAPPCMDCHANNEL4) & M_TXMAPPCMDCHANNEL4)
10710 #define S_TXMAPPCMDCHANNEL3 12
10711 #define M_TXMAPPCMDCHANNEL3 0xfU
10712 #define V_TXMAPPCMDCHANNEL3(x) ((x) << S_TXMAPPCMDCHANNEL3)
10713 #define G_TXMAPPCMDCHANNEL3(x) (((x) >> S_TXMAPPCMDCHANNEL3) & M_TXMAPPCMDCHANNEL3)
10715 #define S_TXMAPPCMDCHANNEL2 8
10716 #define M_TXMAPPCMDCHANNEL2 0xfU
10717 #define V_TXMAPPCMDCHANNEL2(x) ((x) << S_TXMAPPCMDCHANNEL2)
10718 #define G_TXMAPPCMDCHANNEL2(x) (((x) >> S_TXMAPPCMDCHANNEL2) & M_TXMAPPCMDCHANNEL2)
10720 #define S_TXMAPPCMDCHANNEL1 4
10721 #define M_TXMAPPCMDCHANNEL1 0xfU
10722 #define V_TXMAPPCMDCHANNEL1(x) ((x) << S_TXMAPPCMDCHANNEL1)
10723 #define G_TXMAPPCMDCHANNEL1(x) (((x) >> S_TXMAPPCMDCHANNEL1) & M_TXMAPPCMDCHANNEL1)
10725 #define S_TXMAPPCMDCHANNEL0 0
10726 #define M_TXMAPPCMDCHANNEL0 0xfU
10727 #define V_TXMAPPCMDCHANNEL0(x) ((x) << S_TXMAPPCMDCHANNEL0)
10728 #define G_TXMAPPCMDCHANNEL0(x) (((x) >> S_TXMAPPCMDCHANNEL0) & M_TXMAPPCMDCHANNEL0)
10730 #define A_TP_TX_SCHED_LPBK 0x26
10732 #define S_TXMAPLPBKCHANNEL7 28
10733 #define M_TXMAPLPBKCHANNEL7 0xfU
10734 #define V_TXMAPLPBKCHANNEL7(x) ((x) << S_TXMAPLPBKCHANNEL7)
10735 #define G_TXMAPLPBKCHANNEL7(x) (((x) >> S_TXMAPLPBKCHANNEL7) & M_TXMAPLPBKCHANNEL7)
10737 #define S_TXMAPLPBKCHANNEL6 24
10738 #define M_TXMAPLPBKCHANNEL6 0xfU
10739 #define V_TXMAPLPBKCHANNEL6(x) ((x) << S_TXMAPLPBKCHANNEL6)
10740 #define G_TXMAPLPBKCHANNEL6(x) (((x) >> S_TXMAPLPBKCHANNEL6) & M_TXMAPLPBKCHANNEL6)
10742 #define S_TXMAPLPBKCHANNEL5 20
10743 #define M_TXMAPLPBKCHANNEL5 0xfU
10744 #define V_TXMAPLPBKCHANNEL5(x) ((x) << S_TXMAPLPBKCHANNEL5)
10745 #define G_TXMAPLPBKCHANNEL5(x) (((x) >> S_TXMAPLPBKCHANNEL5) & M_TXMAPLPBKCHANNEL5)
10747 #define S_TXMAPLPBKCHANNEL4 16
10748 #define M_TXMAPLPBKCHANNEL4 0xfU
10749 #define V_TXMAPLPBKCHANNEL4(x) ((x) << S_TXMAPLPBKCHANNEL4)
10750 #define G_TXMAPLPBKCHANNEL4(x) (((x) >> S_TXMAPLPBKCHANNEL4) & M_TXMAPLPBKCHANNEL4)
10752 #define S_TXMAPLPBKCHANNEL3 12
10753 #define M_TXMAPLPBKCHANNEL3 0xfU
10754 #define V_TXMAPLPBKCHANNEL3(x) ((x) << S_TXMAPLPBKCHANNEL3)
10755 #define G_TXMAPLPBKCHANNEL3(x) (((x) >> S_TXMAPLPBKCHANNEL3) & M_TXMAPLPBKCHANNEL3)
10757 #define S_TXMAPLPBKCHANNEL2 8
10758 #define M_TXMAPLPBKCHANNEL2 0xfU
10759 #define V_TXMAPLPBKCHANNEL2(x) ((x) << S_TXMAPLPBKCHANNEL2)
10760 #define G_TXMAPLPBKCHANNEL2(x) (((x) >> S_TXMAPLPBKCHANNEL2) & M_TXMAPLPBKCHANNEL2)
10762 #define S_TXMAPLPBKCHANNEL1 4
10763 #define M_TXMAPLPBKCHANNEL1 0xfU
10764 #define V_TXMAPLPBKCHANNEL1(x) ((x) << S_TXMAPLPBKCHANNEL1)
10765 #define G_TXMAPLPBKCHANNEL1(x) (((x) >> S_TXMAPLPBKCHANNEL1) & M_TXMAPLPBKCHANNEL1)
10767 #define S_TXMAPLPBKCHANNEL0 0
10768 #define M_TXMAPLPBKCHANNEL0 0xfU
10769 #define V_TXMAPLPBKCHANNEL0(x) ((x) << S_TXMAPLPBKCHANNEL0)
10770 #define G_TXMAPLPBKCHANNEL0(x) (((x) >> S_TXMAPLPBKCHANNEL0) & M_TXMAPLPBKCHANNEL0)
10772 #define A_TP_CHANNEL_MAP 0x27
10774 #define S_RXMAPCHANNELELN 16
10775 #define M_RXMAPCHANNELELN 0xfU
10776 #define V_RXMAPCHANNELELN(x) ((x) << S_RXMAPCHANNELELN)
10777 #define G_RXMAPCHANNELELN(x) (((x) >> S_RXMAPCHANNELELN) & M_RXMAPCHANNELELN)
10779 #define S_RXMAPE2LCHANNEL3 14
10780 #define M_RXMAPE2LCHANNEL3 0x3U
10781 #define V_RXMAPE2LCHANNEL3(x) ((x) << S_RXMAPE2LCHANNEL3)
10782 #define G_RXMAPE2LCHANNEL3(x) (((x) >> S_RXMAPE2LCHANNEL3) & M_RXMAPE2LCHANNEL3)
10784 #define S_RXMAPE2LCHANNEL2 12
10785 #define M_RXMAPE2LCHANNEL2 0x3U
10786 #define V_RXMAPE2LCHANNEL2(x) ((x) << S_RXMAPE2LCHANNEL2)
10787 #define G_RXMAPE2LCHANNEL2(x) (((x) >> S_RXMAPE2LCHANNEL2) & M_RXMAPE2LCHANNEL2)
10789 #define S_RXMAPE2LCHANNEL1 10
10790 #define M_RXMAPE2LCHANNEL1 0x3U
10791 #define V_RXMAPE2LCHANNEL1(x) ((x) << S_RXMAPE2LCHANNEL1)
10792 #define G_RXMAPE2LCHANNEL1(x) (((x) >> S_RXMAPE2LCHANNEL1) & M_RXMAPE2LCHANNEL1)
10794 #define S_RXMAPE2LCHANNEL0 8
10795 #define M_RXMAPE2LCHANNEL0 0x3U
10796 #define V_RXMAPE2LCHANNEL0(x) ((x) << S_RXMAPE2LCHANNEL0)
10797 #define G_RXMAPE2LCHANNEL0(x) (((x) >> S_RXMAPE2LCHANNEL0) & M_RXMAPE2LCHANNEL0)
10799 #define S_RXMAPC2CCHANNEL3 7
10800 #define V_RXMAPC2CCHANNEL3(x) ((x) << S_RXMAPC2CCHANNEL3)
10801 #define F_RXMAPC2CCHANNEL3 V_RXMAPC2CCHANNEL3(1U)
10803 #define S_RXMAPC2CCHANNEL2 6
10804 #define V_RXMAPC2CCHANNEL2(x) ((x) << S_RXMAPC2CCHANNEL2)
10805 #define F_RXMAPC2CCHANNEL2 V_RXMAPC2CCHANNEL2(1U)
10807 #define S_RXMAPC2CCHANNEL1 5
10808 #define V_RXMAPC2CCHANNEL1(x) ((x) << S_RXMAPC2CCHANNEL1)
10809 #define F_RXMAPC2CCHANNEL1 V_RXMAPC2CCHANNEL1(1U)
10811 #define S_RXMAPC2CCHANNEL0 4
10812 #define V_RXMAPC2CCHANNEL0(x) ((x) << S_RXMAPC2CCHANNEL0)
10813 #define F_RXMAPC2CCHANNEL0 V_RXMAPC2CCHANNEL0(1U)
10815 #define S_RXMAPE2CCHANNEL3 3
10816 #define V_RXMAPE2CCHANNEL3(x) ((x) << S_RXMAPE2CCHANNEL3)
10817 #define F_RXMAPE2CCHANNEL3 V_RXMAPE2CCHANNEL3(1U)
10819 #define S_RXMAPE2CCHANNEL2 2
10820 #define V_RXMAPE2CCHANNEL2(x) ((x) << S_RXMAPE2CCHANNEL2)
10821 #define F_RXMAPE2CCHANNEL2 V_RXMAPE2CCHANNEL2(1U)
10823 #define S_RXMAPE2CCHANNEL1 1
10824 #define V_RXMAPE2CCHANNEL1(x) ((x) << S_RXMAPE2CCHANNEL1)
10825 #define F_RXMAPE2CCHANNEL1 V_RXMAPE2CCHANNEL1(1U)
10827 #define S_RXMAPE2CCHANNEL0 0
10828 #define V_RXMAPE2CCHANNEL0(x) ((x) << S_RXMAPE2CCHANNEL0)
10829 #define F_RXMAPE2CCHANNEL0 V_RXMAPE2CCHANNEL0(1U)
10831 #define A_TP_RX_LPBK 0x28
10832 #define A_TP_TX_LPBK 0x29
10833 #define A_TP_TX_SCHED_PPP 0x2a
10835 #define S_TXPPPENPORT3 24
10836 #define M_TXPPPENPORT3 0xffU
10837 #define V_TXPPPENPORT3(x) ((x) << S_TXPPPENPORT3)
10838 #define G_TXPPPENPORT3(x) (((x) >> S_TXPPPENPORT3) & M_TXPPPENPORT3)
10840 #define S_TXPPPENPORT2 16
10841 #define M_TXPPPENPORT2 0xffU
10842 #define V_TXPPPENPORT2(x) ((x) << S_TXPPPENPORT2)
10843 #define G_TXPPPENPORT2(x) (((x) >> S_TXPPPENPORT2) & M_TXPPPENPORT2)
10845 #define S_TXPPPENPORT1 8
10846 #define M_TXPPPENPORT1 0xffU
10847 #define V_TXPPPENPORT1(x) ((x) << S_TXPPPENPORT1)
10848 #define G_TXPPPENPORT1(x) (((x) >> S_TXPPPENPORT1) & M_TXPPPENPORT1)
10850 #define S_TXPPPENPORT0 0
10851 #define M_TXPPPENPORT0 0xffU
10852 #define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0)
10853 #define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0)
10855 #define A_TP_IPMI_CFG1 0x2e
10857 #define S_VLANENABLE 31
10858 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
10859 #define F_VLANENABLE V_VLANENABLE(1U)
10861 #define S_PRIMARYPORTENABLE 30
10862 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
10863 #define F_PRIMARYPORTENABLE V_PRIMARYPORTENABLE(1U)
10865 #define S_SECUREPORTENABLE 29
10866 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
10867 #define F_SECUREPORTENABLE V_SECUREPORTENABLE(1U)
10869 #define S_ARPENABLE 28
10870 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
10871 #define F_ARPENABLE V_ARPENABLE(1U)
10873 #define S_IPMI_VLAN 0
10874 #define M_IPMI_VLAN 0xffffU
10875 #define V_IPMI_VLAN(x) ((x) << S_IPMI_VLAN)
10876 #define G_IPMI_VLAN(x) (((x) >> S_IPMI_VLAN) & M_IPMI_VLAN)
10878 #define A_TP_IPMI_CFG2 0x2f
10880 #define S_SECUREPORT 16
10881 #define M_SECUREPORT 0xffffU
10882 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
10883 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
10885 #define S_PRIMARYPORT 0
10886 #define M_PRIMARYPORT 0xffffU
10887 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
10888 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
10890 #define A_TP_RSS_PF0_CONFIG 0x30
10892 #define S_MAPENABLE 31
10893 #define V_MAPENABLE(x) ((x) << S_MAPENABLE)
10894 #define F_MAPENABLE V_MAPENABLE(1U)
10896 #define S_CHNENABLE 30
10897 #define V_CHNENABLE(x) ((x) << S_CHNENABLE)
10898 #define F_CHNENABLE V_CHNENABLE(1U)
10900 #define S_PRTENABLE 29
10901 #define V_PRTENABLE(x) ((x) << S_PRTENABLE)
10902 #define F_PRTENABLE V_PRTENABLE(1U)
10904 #define S_UDPFOURTUPEN 28
10905 #define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN)
10906 #define F_UDPFOURTUPEN V_UDPFOURTUPEN(1U)
10908 #define S_IP6FOURTUPEN 27
10909 #define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN)
10910 #define F_IP6FOURTUPEN V_IP6FOURTUPEN(1U)
10912 #define S_IP6TWOTUPEN 26
10913 #define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN)
10914 #define F_IP6TWOTUPEN V_IP6TWOTUPEN(1U)
10916 #define S_IP4FOURTUPEN 25
10917 #define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN)
10918 #define F_IP4FOURTUPEN V_IP4FOURTUPEN(1U)
10920 #define S_IP4TWOTUPEN 24
10921 #define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN)
10922 #define F_IP4TWOTUPEN V_IP4TWOTUPEN(1U)
10924 #define S_IVFWIDTH 20
10925 #define M_IVFWIDTH 0xfU
10926 #define V_IVFWIDTH(x) ((x) << S_IVFWIDTH)
10927 #define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH)
10929 #define S_CH1DEFAULTQUEUE 10
10930 #define M_CH1DEFAULTQUEUE 0x3ffU
10931 #define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE)
10932 #define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE)
10934 #define S_CH0DEFAULTQUEUE 0
10935 #define M_CH0DEFAULTQUEUE 0x3ffU
10936 #define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
10937 #define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)
10939 #define A_TP_RSS_PF1_CONFIG 0x31
10940 #define A_TP_RSS_PF2_CONFIG 0x32
10941 #define A_TP_RSS_PF3_CONFIG 0x33
10942 #define A_TP_RSS_PF4_CONFIG 0x34
10943 #define A_TP_RSS_PF5_CONFIG 0x35
10944 #define A_TP_RSS_PF6_CONFIG 0x36
10945 #define A_TP_RSS_PF7_CONFIG 0x37
10946 #define A_TP_RSS_PF_MAP 0x38
10948 #define S_LKPIDXSIZE 24
10949 #define M_LKPIDXSIZE 0x3U
10950 #define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE)
10951 #define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE)
10953 #define S_PF7LKPIDX 21
10954 #define M_PF7LKPIDX 0x7U
10955 #define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX)
10956 #define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX)
10958 #define S_PF6LKPIDX 18
10959 #define M_PF6LKPIDX 0x7U
10960 #define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX)
10961 #define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX)
10963 #define S_PF5LKPIDX 15
10964 #define M_PF5LKPIDX 0x7U
10965 #define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX)
10966 #define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX)
10968 #define S_PF4LKPIDX 12
10969 #define M_PF4LKPIDX 0x7U
10970 #define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX)
10971 #define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX)
10973 #define S_PF3LKPIDX 9
10974 #define M_PF3LKPIDX 0x7U
10975 #define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX)
10976 #define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX)
10978 #define S_PF2LKPIDX 6
10979 #define M_PF2LKPIDX 0x7U
10980 #define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX)
10981 #define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX)
10983 #define S_PF1LKPIDX 3
10984 #define M_PF1LKPIDX 0x7U
10985 #define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX)
10986 #define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX)
10988 #define S_PF0LKPIDX 0
10989 #define M_PF0LKPIDX 0x7U
10990 #define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX)
10991 #define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX)
10993 #define A_TP_RSS_PF_MSK 0x39
10995 #define S_PF7MSKSIZE 28
10996 #define M_PF7MSKSIZE 0xfU
10997 #define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE)
10998 #define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE)
11000 #define S_PF6MSKSIZE 24
11001 #define M_PF6MSKSIZE 0xfU
11002 #define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE)
11003 #define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE)
11005 #define S_PF5MSKSIZE 20
11006 #define M_PF5MSKSIZE 0xfU
11007 #define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE)
11008 #define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE)
11010 #define S_PF4MSKSIZE 16
11011 #define M_PF4MSKSIZE 0xfU
11012 #define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE)
11013 #define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE)
11015 #define S_PF3MSKSIZE 12
11016 #define M_PF3MSKSIZE 0xfU
11017 #define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE)
11018 #define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE)
11020 #define S_PF2MSKSIZE 8
11021 #define M_PF2MSKSIZE 0xfU
11022 #define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE)
11023 #define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE)
11025 #define S_PF1MSKSIZE 4
11026 #define M_PF1MSKSIZE 0xfU
11027 #define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE)
11028 #define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE)
11030 #define S_PF0MSKSIZE 0
11031 #define M_PF0MSKSIZE 0xfU
11032 #define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE)
11033 #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)
11035 #define A_TP_RSS_VFL_CONFIG 0x3a
11036 #define A_TP_RSS_VFH_CONFIG 0x3b
11038 #define S_ENABLEUDPHASH 31
11039 #define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH)
11040 #define F_ENABLEUDPHASH V_ENABLEUDPHASH(1U)
11042 #define S_VFUPEN 30
11043 #define V_VFUPEN(x) ((x) << S_VFUPEN)
11044 #define F_VFUPEN V_VFUPEN(1U)
11046 #define S_VFVLNEX 28
11047 #define V_VFVLNEX(x) ((x) << S_VFVLNEX)
11048 #define F_VFVLNEX V_VFVLNEX(1U)
11050 #define S_VFPRTEN 27
11051 #define V_VFPRTEN(x) ((x) << S_VFPRTEN)
11052 #define F_VFPRTEN V_VFPRTEN(1U)
11054 #define S_VFCHNEN 26
11055 #define V_VFCHNEN(x) ((x) << S_VFCHNEN)
11056 #define F_VFCHNEN V_VFCHNEN(1U)
11058 #define S_DEFAULTQUEUE 16
11059 #define M_DEFAULTQUEUE 0x3ffU
11060 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
11061 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
11063 #define S_VFLKPIDX 8
11064 #define M_VFLKPIDX 0xffU
11065 #define V_VFLKPIDX(x) ((x) << S_VFLKPIDX)
11066 #define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX)
11068 #define S_VFIP6FOURTUPEN 7
11069 #define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN)
11070 #define F_VFIP6FOURTUPEN V_VFIP6FOURTUPEN(1U)
11072 #define S_VFIP6TWOTUPEN 6
11073 #define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN)
11074 #define F_VFIP6TWOTUPEN V_VFIP6TWOTUPEN(1U)
11076 #define S_VFIP4FOURTUPEN 5
11077 #define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN)
11078 #define F_VFIP4FOURTUPEN V_VFIP4FOURTUPEN(1U)
11080 #define S_VFIP4TWOTUPEN 4
11081 #define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN)
11082 #define F_VFIP4TWOTUPEN V_VFIP4TWOTUPEN(1U)
11084 #define S_KEYINDEX 0
11085 #define M_KEYINDEX 0xfU
11086 #define V_KEYINDEX(x) ((x) << S_KEYINDEX)
11087 #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)
11089 #define A_TP_RSS_SECRET_KEY0 0x40
11090 #define A_TP_RSS_SECRET_KEY1 0x41
11091 #define A_TP_RSS_SECRET_KEY2 0x42
11092 #define A_TP_RSS_SECRET_KEY3 0x43
11093 #define A_TP_RSS_SECRET_KEY4 0x44
11094 #define A_TP_RSS_SECRET_KEY5 0x45
11095 #define A_TP_RSS_SECRET_KEY6 0x46
11096 #define A_TP_RSS_SECRET_KEY7 0x47
11097 #define A_TP_RSS_SECRET_KEY8 0x48
11098 #define A_TP_RSS_SECRET_KEY9 0x49
11099 #define A_TP_ETHER_TYPE_VL 0x50
11101 #define S_CQFCTYPE 16
11102 #define M_CQFCTYPE 0xffffU
11103 #define V_CQFCTYPE(x) ((x) << S_CQFCTYPE)
11104 #define G_CQFCTYPE(x) (((x) >> S_CQFCTYPE) & M_CQFCTYPE)
11106 #define S_VLANTYPE 0
11107 #define M_VLANTYPE 0xffffU
11108 #define V_VLANTYPE(x) ((x) << S_VLANTYPE)
11109 #define G_VLANTYPE(x) (((x) >> S_VLANTYPE) & M_VLANTYPE)
11111 #define A_TP_ETHER_TYPE_IP 0x51
11113 #define S_IPV6TYPE 16
11114 #define M_IPV6TYPE 0xffffU
11115 #define V_IPV6TYPE(x) ((x) << S_IPV6TYPE)
11116 #define G_IPV6TYPE(x) (((x) >> S_IPV6TYPE) & M_IPV6TYPE)
11118 #define S_IPV4TYPE 0
11119 #define M_IPV4TYPE 0xffffU
11120 #define V_IPV4TYPE(x) ((x) << S_IPV4TYPE)
11121 #define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE)
11123 #define A_TP_DBG_CLEAR 0x60
11124 #define A_TP_DBG_CORE_HDR0 0x61
11126 #define S_E_TCP_OP_SRDY 16
11127 #define V_E_TCP_OP_SRDY(x) ((x) << S_E_TCP_OP_SRDY)
11128 #define F_E_TCP_OP_SRDY V_E_TCP_OP_SRDY(1U)
11130 #define S_E_PLD_TXZEROP_SRDY 15
11131 #define V_E_PLD_TXZEROP_SRDY(x) ((x) << S_E_PLD_TXZEROP_SRDY)
11132 #define F_E_PLD_TXZEROP_SRDY V_E_PLD_TXZEROP_SRDY(1U)
11134 #define S_E_PLD_RX_SRDY 14
11135 #define V_E_PLD_RX_SRDY(x) ((x) << S_E_PLD_RX_SRDY)
11136 #define F_E_PLD_RX_SRDY V_E_PLD_RX_SRDY(1U)
11138 #define S_E_RX_ERROR_SRDY 13
11139 #define V_E_RX_ERROR_SRDY(x) ((x) << S_E_RX_ERROR_SRDY)
11140 #define F_E_RX_ERROR_SRDY V_E_RX_ERROR_SRDY(1U)
11142 #define S_E_RX_ISS_SRDY 12
11143 #define V_E_RX_ISS_SRDY(x) ((x) << S_E_RX_ISS_SRDY)
11144 #define F_E_RX_ISS_SRDY V_E_RX_ISS_SRDY(1U)
11146 #define S_C_TCP_OP_SRDY 11
11147 #define V_C_TCP_OP_SRDY(x) ((x) << S_C_TCP_OP_SRDY)
11148 #define F_C_TCP_OP_SRDY V_C_TCP_OP_SRDY(1U)
11150 #define S_C_PLD_TXZEROP_SRDY 10
11151 #define V_C_PLD_TXZEROP_SRDY(x) ((x) << S_C_PLD_TXZEROP_SRDY)
11152 #define F_C_PLD_TXZEROP_SRDY V_C_PLD_TXZEROP_SRDY(1U)
11154 #define S_C_PLD_RX_SRDY 9
11155 #define V_C_PLD_RX_SRDY(x) ((x) << S_C_PLD_RX_SRDY)
11156 #define F_C_PLD_RX_SRDY V_C_PLD_RX_SRDY(1U)
11158 #define S_C_RX_ERROR_SRDY 8
11159 #define V_C_RX_ERROR_SRDY(x) ((x) << S_C_RX_ERROR_SRDY)
11160 #define F_C_RX_ERROR_SRDY V_C_RX_ERROR_SRDY(1U)
11162 #define S_C_RX_ISS_SRDY 7
11163 #define V_C_RX_ISS_SRDY(x) ((x) << S_C_RX_ISS_SRDY)
11164 #define F_C_RX_ISS_SRDY V_C_RX_ISS_SRDY(1U)
11166 #define S_E_CPL5_TXVALID 6
11167 #define V_E_CPL5_TXVALID(x) ((x) << S_E_CPL5_TXVALID)
11168 #define F_E_CPL5_TXVALID V_E_CPL5_TXVALID(1U)
11170 #define S_E_ETH_TXVALID 5
11171 #define V_E_ETH_TXVALID(x) ((x) << S_E_ETH_TXVALID)
11172 #define F_E_ETH_TXVALID V_E_ETH_TXVALID(1U)
11174 #define S_E_IP_TXVALID 4
11175 #define V_E_IP_TXVALID(x) ((x) << S_E_IP_TXVALID)
11176 #define F_E_IP_TXVALID V_E_IP_TXVALID(1U)
11178 #define S_E_TCP_TXVALID 3
11179 #define V_E_TCP_TXVALID(x) ((x) << S_E_TCP_TXVALID)
11180 #define F_E_TCP_TXVALID V_E_TCP_TXVALID(1U)
11182 #define S_C_CPL5_RXVALID 2
11183 #define V_C_CPL5_RXVALID(x) ((x) << S_C_CPL5_RXVALID)
11184 #define F_C_CPL5_RXVALID V_C_CPL5_RXVALID(1U)
11186 #define S_C_CPL5_TXVALID 1
11187 #define V_C_CPL5_TXVALID(x) ((x) << S_C_CPL5_TXVALID)
11188 #define F_C_CPL5_TXVALID V_C_CPL5_TXVALID(1U)
11190 #define S_E_TCP_OPT_RXVALID 0
11191 #define V_E_TCP_OPT_RXVALID(x) ((x) << S_E_TCP_OPT_RXVALID)
11192 #define F_E_TCP_OPT_RXVALID V_E_TCP_OPT_RXVALID(1U)
11194 #define A_TP_DBG_CORE_HDR1 0x62
11196 #define S_E_CPL5_TXFULL 6
11197 #define V_E_CPL5_TXFULL(x) ((x) << S_E_CPL5_TXFULL)
11198 #define F_E_CPL5_TXFULL V_E_CPL5_TXFULL(1U)
11200 #define S_E_ETH_TXFULL 5
11201 #define V_E_ETH_TXFULL(x) ((x) << S_E_ETH_TXFULL)
11202 #define F_E_ETH_TXFULL V_E_ETH_TXFULL(1U)
11204 #define S_E_IP_TXFULL 4
11205 #define V_E_IP_TXFULL(x) ((x) << S_E_IP_TXFULL)
11206 #define F_E_IP_TXFULL V_E_IP_TXFULL(1U)
11208 #define S_E_TCP_TXFULL 3
11209 #define V_E_TCP_TXFULL(x) ((x) << S_E_TCP_TXFULL)
11210 #define F_E_TCP_TXFULL V_E_TCP_TXFULL(1U)
11212 #define S_C_CPL5_RXFULL 2
11213 #define V_C_CPL5_RXFULL(x) ((x) << S_C_CPL5_RXFULL)
11214 #define F_C_CPL5_RXFULL V_C_CPL5_RXFULL(1U)
11216 #define S_C_CPL5_TXFULL 1
11217 #define V_C_CPL5_TXFULL(x) ((x) << S_C_CPL5_TXFULL)
11218 #define F_C_CPL5_TXFULL V_C_CPL5_TXFULL(1U)
11220 #define S_E_TCP_OPT_RXFULL 0
11221 #define V_E_TCP_OPT_RXFULL(x) ((x) << S_E_TCP_OPT_RXFULL)
11222 #define F_E_TCP_OPT_RXFULL V_E_TCP_OPT_RXFULL(1U)
11224 #define A_TP_DBG_CORE_FATAL 0x63
11226 #define S_EMSGFATAL 31
11227 #define V_EMSGFATAL(x) ((x) << S_EMSGFATAL)
11228 #define F_EMSGFATAL V_EMSGFATAL(1U)
11230 #define S_CMSGFATAL 30
11231 #define V_CMSGFATAL(x) ((x) << S_CMSGFATAL)
11232 #define F_CMSGFATAL V_CMSGFATAL(1U)
11234 #define S_PAWSFATAL 29
11235 #define V_PAWSFATAL(x) ((x) << S_PAWSFATAL)
11236 #define F_PAWSFATAL V_PAWSFATAL(1U)
11238 #define S_SRAMFATAL 28
11239 #define V_SRAMFATAL(x) ((x) << S_SRAMFATAL)
11240 #define F_SRAMFATAL V_SRAMFATAL(1U)
11242 #define S_EPCMDCONG 24
11243 #define M_EPCMDCONG 0xfU
11244 #define V_EPCMDCONG(x) ((x) << S_EPCMDCONG)
11245 #define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG)
11247 #define S_CPCMDCONG 22
11248 #define M_CPCMDCONG 0x3U
11249 #define V_CPCMDCONG(x) ((x) << S_CPCMDCONG)
11250 #define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG)
11252 #define S_CPCMDLENFATAL 21
11253 #define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL)
11254 #define F_CPCMDLENFATAL V_CPCMDLENFATAL(1U)
11256 #define S_EPCMDLENFATAL 20
11257 #define V_EPCMDLENFATAL(x) ((x) << S_EPCMDLENFATAL)
11258 #define F_EPCMDLENFATAL V_EPCMDLENFATAL(1U)
11260 #define S_CPCMDVALID 16
11261 #define M_CPCMDVALID 0xfU
11262 #define V_CPCMDVALID(x) ((x) << S_CPCMDVALID)
11263 #define G_CPCMDVALID(x) (((x) >> S_CPCMDVALID) & M_CPCMDVALID)
11265 #define S_CPCMDAFULL 12
11266 #define M_CPCMDAFULL 0xfU
11267 #define V_CPCMDAFULL(x) ((x) << S_CPCMDAFULL)
11268 #define G_CPCMDAFULL(x) (((x) >> S_CPCMDAFULL) & M_CPCMDAFULL)
11270 #define S_EPCMDVALID 10
11271 #define M_EPCMDVALID 0x3U
11272 #define V_EPCMDVALID(x) ((x) << S_EPCMDVALID)
11273 #define G_EPCMDVALID(x) (((x) >> S_EPCMDVALID) & M_EPCMDVALID)
11275 #define S_EPCMDAFULL 8
11276 #define M_EPCMDAFULL 0x3U
11277 #define V_EPCMDAFULL(x) ((x) << S_EPCMDAFULL)
11278 #define G_EPCMDAFULL(x) (((x) >> S_EPCMDAFULL) & M_EPCMDAFULL)
11280 #define S_CPCMDEOIFATAL 7
11281 #define V_CPCMDEOIFATAL(x) ((x) << S_CPCMDEOIFATAL)
11282 #define F_CPCMDEOIFATAL V_CPCMDEOIFATAL(1U)
11284 #define S_CMDBRQFATAL 4
11285 #define V_CMDBRQFATAL(x) ((x) << S_CMDBRQFATAL)
11286 #define F_CMDBRQFATAL V_CMDBRQFATAL(1U)
11288 #define S_CNONZEROPPOPCNT 2
11289 #define M_CNONZEROPPOPCNT 0x3U
11290 #define V_CNONZEROPPOPCNT(x) ((x) << S_CNONZEROPPOPCNT)
11291 #define G_CNONZEROPPOPCNT(x) (((x) >> S_CNONZEROPPOPCNT) & M_CNONZEROPPOPCNT)
11293 #define S_CPCMDEOICNT 0
11294 #define M_CPCMDEOICNT 0x3U
11295 #define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT)
11296 #define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT)
11298 #define A_TP_DBG_CORE_OUT 0x64
11300 #define S_CCPLENC 26
11301 #define V_CCPLENC(x) ((x) << S_CCPLENC)
11302 #define F_CCPLENC V_CCPLENC(1U)
11304 #define S_CWRCPLPKT 25
11305 #define V_CWRCPLPKT(x) ((x) << S_CWRCPLPKT)
11306 #define F_CWRCPLPKT V_CWRCPLPKT(1U)
11308 #define S_CWRETHPKT 24
11309 #define V_CWRETHPKT(x) ((x) << S_CWRETHPKT)
11310 #define F_CWRETHPKT V_CWRETHPKT(1U)
11312 #define S_CWRIPPKT 23
11313 #define V_CWRIPPKT(x) ((x) << S_CWRIPPKT)
11314 #define F_CWRIPPKT V_CWRIPPKT(1U)
11316 #define S_CWRTCPPKT 22
11317 #define V_CWRTCPPKT(x) ((x) << S_CWRTCPPKT)
11318 #define F_CWRTCPPKT V_CWRTCPPKT(1U)
11320 #define S_CWRZEROP 21
11321 #define V_CWRZEROP(x) ((x) << S_CWRZEROP)
11322 #define F_CWRZEROP V_CWRZEROP(1U)
11324 #define S_CCPLTXFULL 20
11325 #define V_CCPLTXFULL(x) ((x) << S_CCPLTXFULL)
11326 #define F_CCPLTXFULL V_CCPLTXFULL(1U)
11328 #define S_CETHTXFULL 19
11329 #define V_CETHTXFULL(x) ((x) << S_CETHTXFULL)
11330 #define F_CETHTXFULL V_CETHTXFULL(1U)
11332 #define S_CIPTXFULL 18
11333 #define V_CIPTXFULL(x) ((x) << S_CIPTXFULL)
11334 #define F_CIPTXFULL V_CIPTXFULL(1U)
11336 #define S_CTCPTXFULL 17
11337 #define V_CTCPTXFULL(x) ((x) << S_CTCPTXFULL)
11338 #define F_CTCPTXFULL V_CTCPTXFULL(1U)
11340 #define S_CPLDTXZEROPDRDY 16
11341 #define V_CPLDTXZEROPDRDY(x) ((x) << S_CPLDTXZEROPDRDY)
11342 #define F_CPLDTXZEROPDRDY V_CPLDTXZEROPDRDY(1U)
11344 #define S_ECPLENC 10
11345 #define V_ECPLENC(x) ((x) << S_ECPLENC)
11346 #define F_ECPLENC V_ECPLENC(1U)
11348 #define S_EWRCPLPKT 9
11349 #define V_EWRCPLPKT(x) ((x) << S_EWRCPLPKT)
11350 #define F_EWRCPLPKT V_EWRCPLPKT(1U)
11352 #define S_EWRETHPKT 8
11353 #define V_EWRETHPKT(x) ((x) << S_EWRETHPKT)
11354 #define F_EWRETHPKT V_EWRETHPKT(1U)
11356 #define S_EWRIPPKT 7
11357 #define V_EWRIPPKT(x) ((x) << S_EWRIPPKT)
11358 #define F_EWRIPPKT V_EWRIPPKT(1U)
11360 #define S_EWRTCPPKT 6
11361 #define V_EWRTCPPKT(x) ((x) << S_EWRTCPPKT)
11362 #define F_EWRTCPPKT V_EWRTCPPKT(1U)
11364 #define S_EWRZEROP 5
11365 #define V_EWRZEROP(x) ((x) << S_EWRZEROP)
11366 #define F_EWRZEROP V_EWRZEROP(1U)
11368 #define S_ECPLTXFULL 4
11369 #define V_ECPLTXFULL(x) ((x) << S_ECPLTXFULL)
11370 #define F_ECPLTXFULL V_ECPLTXFULL(1U)
11372 #define S_EETHTXFULL 3
11373 #define V_EETHTXFULL(x) ((x) << S_EETHTXFULL)
11374 #define F_EETHTXFULL V_EETHTXFULL(1U)
11376 #define S_EIPTXFULL 2
11377 #define V_EIPTXFULL(x) ((x) << S_EIPTXFULL)
11378 #define F_EIPTXFULL V_EIPTXFULL(1U)
11380 #define S_ETCPTXFULL 1
11381 #define V_ETCPTXFULL(x) ((x) << S_ETCPTXFULL)
11382 #define F_ETCPTXFULL V_ETCPTXFULL(1U)
11384 #define S_EPLDTXZEROPDRDY 0
11385 #define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY)
11386 #define F_EPLDTXZEROPDRDY V_EPLDTXZEROPDRDY(1U)
11388 #define A_TP_DBG_CORE_TID 0x65
11390 #define S_LINENUMBER 24
11391 #define M_LINENUMBER 0x7fU
11392 #define V_LINENUMBER(x) ((x) << S_LINENUMBER)
11393 #define G_LINENUMBER(x) (((x) >> S_LINENUMBER) & M_LINENUMBER)
11395 #define S_SPURIOUSMSG 23
11396 #define V_SPURIOUSMSG(x) ((x) << S_SPURIOUSMSG)
11397 #define F_SPURIOUSMSG V_SPURIOUSMSG(1U)
11399 #define S_SYNLEARNED 20
11400 #define V_SYNLEARNED(x) ((x) << S_SYNLEARNED)
11401 #define F_SYNLEARNED V_SYNLEARNED(1U)
11403 #define S_TIDVALUE 0
11404 #define M_TIDVALUE 0xfffffU
11405 #define V_TIDVALUE(x) ((x) << S_TIDVALUE)
11406 #define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE)
11408 #define A_TP_DBG_ENG_RES0 0x66
11410 #define S_RESOURCESREADY 31
11411 #define V_RESOURCESREADY(x) ((x) << S_RESOURCESREADY)
11412 #define F_RESOURCESREADY V_RESOURCESREADY(1U)
11414 #define S_RCFOPCODEOUTSRDY 30
11415 #define V_RCFOPCODEOUTSRDY(x) ((x) << S_RCFOPCODEOUTSRDY)
11416 #define F_RCFOPCODEOUTSRDY V_RCFOPCODEOUTSRDY(1U)
11418 #define S_RCFDATAOUTSRDY 29
11419 #define V_RCFDATAOUTSRDY(x) ((x) << S_RCFDATAOUTSRDY)
11420 #define F_RCFDATAOUTSRDY V_RCFDATAOUTSRDY(1U)
11422 #define S_FLUSHINPUTMSG 28
11423 #define V_FLUSHINPUTMSG(x) ((x) << S_FLUSHINPUTMSG)
11424 #define F_FLUSHINPUTMSG V_FLUSHINPUTMSG(1U)
11426 #define S_RCFOPSRCOUT 26
11427 #define M_RCFOPSRCOUT 0x3U
11428 #define V_RCFOPSRCOUT(x) ((x) << S_RCFOPSRCOUT)
11429 #define G_RCFOPSRCOUT(x) (((x) >> S_RCFOPSRCOUT) & M_RCFOPSRCOUT)
11432 #define V_C_MSG(x) ((x) << S_C_MSG)
11433 #define F_C_MSG V_C_MSG(1U)
11436 #define V_E_MSG(x) ((x) << S_E_MSG)
11437 #define F_E_MSG V_E_MSG(1U)
11439 #define S_RCFOPCODEOUT 20
11440 #define M_RCFOPCODEOUT 0xfU
11441 #define V_RCFOPCODEOUT(x) ((x) << S_RCFOPCODEOUT)
11442 #define G_RCFOPCODEOUT(x) (((x) >> S_RCFOPCODEOUT) & M_RCFOPCODEOUT)
11444 #define S_EFFRCFOPCODEOUT 16
11445 #define M_EFFRCFOPCODEOUT 0xfU
11446 #define V_EFFRCFOPCODEOUT(x) ((x) << S_EFFRCFOPCODEOUT)
11447 #define G_EFFRCFOPCODEOUT(x) (((x) >> S_EFFRCFOPCODEOUT) & M_EFFRCFOPCODEOUT)
11449 #define S_SEENRESOURCESREADY 15
11450 #define V_SEENRESOURCESREADY(x) ((x) << S_SEENRESOURCESREADY)
11451 #define F_SEENRESOURCESREADY V_SEENRESOURCESREADY(1U)
11453 #define S_RESOURCESREADYCOPY 14
11454 #define V_RESOURCESREADYCOPY(x) ((x) << S_RESOURCESREADYCOPY)
11455 #define F_RESOURCESREADYCOPY V_RESOURCESREADYCOPY(1U)
11457 #define S_OPCODEWAITSFORDATA 13
11458 #define V_OPCODEWAITSFORDATA(x) ((x) << S_OPCODEWAITSFORDATA)
11459 #define F_OPCODEWAITSFORDATA V_OPCODEWAITSFORDATA(1U)
11461 #define S_CPLDRXSRDY 12
11462 #define V_CPLDRXSRDY(x) ((x) << S_CPLDRXSRDY)
11463 #define F_CPLDRXSRDY V_CPLDRXSRDY(1U)
11465 #define S_CPLDRXZEROPSRDY 11
11466 #define V_CPLDRXZEROPSRDY(x) ((x) << S_CPLDRXZEROPSRDY)
11467 #define F_CPLDRXZEROPSRDY V_CPLDRXZEROPSRDY(1U)
11469 #define S_EPLDRXZEROPSRDY 10
11470 #define V_EPLDRXZEROPSRDY(x) ((x) << S_EPLDRXZEROPSRDY)
11471 #define F_EPLDRXZEROPSRDY V_EPLDRXZEROPSRDY(1U)
11473 #define S_ERXERRORSRDY 9
11474 #define V_ERXERRORSRDY(x) ((x) << S_ERXERRORSRDY)
11475 #define F_ERXERRORSRDY V_ERXERRORSRDY(1U)
11477 #define S_EPLDRXSRDY 8
11478 #define V_EPLDRXSRDY(x) ((x) << S_EPLDRXSRDY)
11479 #define F_EPLDRXSRDY V_EPLDRXSRDY(1U)
11481 #define S_CRXBUSY 7
11482 #define V_CRXBUSY(x) ((x) << S_CRXBUSY)
11483 #define F_CRXBUSY V_CRXBUSY(1U)
11485 #define S_ERXBUSY 6
11486 #define V_ERXBUSY(x) ((x) << S_ERXBUSY)
11487 #define F_ERXBUSY V_ERXBUSY(1U)
11489 #define S_TIMERINSERTBUSY 5
11490 #define V_TIMERINSERTBUSY(x) ((x) << S_TIMERINSERTBUSY)
11491 #define F_TIMERINSERTBUSY V_TIMERINSERTBUSY(1U)
11493 #define S_WCFBUSY 4
11494 #define V_WCFBUSY(x) ((x) << S_WCFBUSY)
11495 #define F_WCFBUSY V_WCFBUSY(1U)
11497 #define S_CTXBUSY 3
11498 #define V_CTXBUSY(x) ((x) << S_CTXBUSY)
11499 #define F_CTXBUSY V_CTXBUSY(1U)
11501 #define S_CPCMDBUSY 2
11502 #define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY)
11503 #define F_CPCMDBUSY V_CPCMDBUSY(1U)
11505 #define S_ETXBUSY 1
11506 #define V_ETXBUSY(x) ((x) << S_ETXBUSY)
11507 #define F_ETXBUSY V_ETXBUSY(1U)
11509 #define S_EPCMDBUSY 0
11510 #define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY)
11511 #define F_EPCMDBUSY V_EPCMDBUSY(1U)
11513 #define A_TP_DBG_ENG_RES1 0x67
11515 #define S_RXCPLSRDY 31
11516 #define V_RXCPLSRDY(x) ((x) << S_RXCPLSRDY)
11517 #define F_RXCPLSRDY V_RXCPLSRDY(1U)
11519 #define S_RXOPTSRDY 30
11520 #define V_RXOPTSRDY(x) ((x) << S_RXOPTSRDY)
11521 #define F_RXOPTSRDY V_RXOPTSRDY(1U)
11523 #define S_RXPLDLENSRDY 29
11524 #define V_RXPLDLENSRDY(x) ((x) << S_RXPLDLENSRDY)
11525 #define F_RXPLDLENSRDY V_RXPLDLENSRDY(1U)
11527 #define S_RXNOTBUSY 28
11528 #define V_RXNOTBUSY(x) ((x) << S_RXNOTBUSY)
11529 #define F_RXNOTBUSY V_RXNOTBUSY(1U)
11531 #define S_CPLCMDIN 20
11532 #define M_CPLCMDIN 0xffU
11533 #define V_CPLCMDIN(x) ((x) << S_CPLCMDIN)
11534 #define G_CPLCMDIN(x) (((x) >> S_CPLCMDIN) & M_CPLCMDIN)
11536 #define S_RCFPTIDSRDY 19
11537 #define V_RCFPTIDSRDY(x) ((x) << S_RCFPTIDSRDY)
11538 #define F_RCFPTIDSRDY V_RCFPTIDSRDY(1U)
11540 #define S_EPDUHDRSRDY 18
11541 #define V_EPDUHDRSRDY(x) ((x) << S_EPDUHDRSRDY)
11542 #define F_EPDUHDRSRDY V_EPDUHDRSRDY(1U)
11544 #define S_TUNNELPKTREG 17
11545 #define V_TUNNELPKTREG(x) ((x) << S_TUNNELPKTREG)
11546 #define F_TUNNELPKTREG V_TUNNELPKTREG(1U)
11548 #define S_TXPKTCSUMSRDY 16
11549 #define V_TXPKTCSUMSRDY(x) ((x) << S_TXPKTCSUMSRDY)
11550 #define F_TXPKTCSUMSRDY V_TXPKTCSUMSRDY(1U)
11552 #define S_TABLEACCESSLATENCY 12
11553 #define M_TABLEACCESSLATENCY 0xfU
11554 #define V_TABLEACCESSLATENCY(x) ((x) << S_TABLEACCESSLATENCY)
11555 #define G_TABLEACCESSLATENCY(x) (((x) >> S_TABLEACCESSLATENCY) & M_TABLEACCESSLATENCY)
11557 #define S_MMGRDONE 11
11558 #define V_MMGRDONE(x) ((x) << S_MMGRDONE)
11559 #define F_MMGRDONE V_MMGRDONE(1U)
11561 #define S_SEENMMGRDONE 10
11562 #define V_SEENMMGRDONE(x) ((x) << S_SEENMMGRDONE)
11563 #define F_SEENMMGRDONE V_SEENMMGRDONE(1U)
11565 #define S_RXERRORSRDY 9
11566 #define V_RXERRORSRDY(x) ((x) << S_RXERRORSRDY)
11567 #define F_RXERRORSRDY V_RXERRORSRDY(1U)
11569 #define S_RCFOPTIONSTCPSRDY 8
11570 #define V_RCFOPTIONSTCPSRDY(x) ((x) << S_RCFOPTIONSTCPSRDY)
11571 #define F_RCFOPTIONSTCPSRDY V_RCFOPTIONSTCPSRDY(1U)
11573 #define S_ENGINESTATE 6
11574 #define M_ENGINESTATE 0x3U
11575 #define V_ENGINESTATE(x) ((x) << S_ENGINESTATE)
11576 #define G_ENGINESTATE(x) (((x) >> S_ENGINESTATE) & M_ENGINESTATE)
11578 #define S_TABLEACCESINCREMENT 5
11579 #define V_TABLEACCESINCREMENT(x) ((x) << S_TABLEACCESINCREMENT)
11580 #define F_TABLEACCESINCREMENT V_TABLEACCESINCREMENT(1U)
11582 #define S_TABLEACCESCOMPLETE 4
11583 #define V_TABLEACCESCOMPLETE(x) ((x) << S_TABLEACCESCOMPLETE)
11584 #define F_TABLEACCESCOMPLETE V_TABLEACCESCOMPLETE(1U)
11586 #define S_RCFOPCODEOUTUSABLE 3
11587 #define V_RCFOPCODEOUTUSABLE(x) ((x) << S_RCFOPCODEOUTUSABLE)
11588 #define F_RCFOPCODEOUTUSABLE V_RCFOPCODEOUTUSABLE(1U)
11590 #define S_RCFDATAOUTUSABLE 2
11591 #define V_RCFDATAOUTUSABLE(x) ((x) << S_RCFDATAOUTUSABLE)
11592 #define F_RCFDATAOUTUSABLE V_RCFDATAOUTUSABLE(1U)
11594 #define S_RCFDATAWAITAFTERRD 1
11595 #define V_RCFDATAWAITAFTERRD(x) ((x) << S_RCFDATAWAITAFTERRD)
11596 #define F_RCFDATAWAITAFTERRD V_RCFDATAWAITAFTERRD(1U)
11598 #define S_RCFDATACMRDY 0
11599 #define V_RCFDATACMRDY(x) ((x) << S_RCFDATACMRDY)
11600 #define F_RCFDATACMRDY V_RCFDATACMRDY(1U)
11602 #define A_TP_DBG_ENG_RES2 0x68
11604 #define S_CPLCMDRAW 24
11605 #define M_CPLCMDRAW 0xffU
11606 #define V_CPLCMDRAW(x) ((x) << S_CPLCMDRAW)
11607 #define G_CPLCMDRAW(x) (((x) >> S_CPLCMDRAW) & M_CPLCMDRAW)
11609 #define S_RXMACPORT 20
11610 #define M_RXMACPORT 0xfU
11611 #define V_RXMACPORT(x) ((x) << S_RXMACPORT)
11612 #define G_RXMACPORT(x) (((x) >> S_RXMACPORT) & M_RXMACPORT)
11614 #define S_TXECHANNEL 18
11615 #define M_TXECHANNEL 0x3U
11616 #define V_TXECHANNEL(x) ((x) << S_TXECHANNEL)
11617 #define G_TXECHANNEL(x) (((x) >> S_TXECHANNEL) & M_TXECHANNEL)
11619 #define S_RXECHANNEL 16
11620 #define M_RXECHANNEL 0x3U
11621 #define V_RXECHANNEL(x) ((x) << S_RXECHANNEL)
11622 #define G_RXECHANNEL(x) (((x) >> S_RXECHANNEL) & M_RXECHANNEL)
11624 #define S_CDATAOUT 15
11625 #define V_CDATAOUT(x) ((x) << S_CDATAOUT)
11626 #define F_CDATAOUT V_CDATAOUT(1U)
11628 #define S_CREADPDU 14
11629 #define V_CREADPDU(x) ((x) << S_CREADPDU)
11630 #define F_CREADPDU V_CREADPDU(1U)
11632 #define S_EDATAOUT 13
11633 #define V_EDATAOUT(x) ((x) << S_EDATAOUT)
11634 #define F_EDATAOUT V_EDATAOUT(1U)
11636 #define S_EREADPDU 12
11637 #define V_EREADPDU(x) ((x) << S_EREADPDU)
11638 #define F_EREADPDU V_EREADPDU(1U)
11640 #define S_ETCPOPSRDY 11
11641 #define V_ETCPOPSRDY(x) ((x) << S_ETCPOPSRDY)
11642 #define F_ETCPOPSRDY V_ETCPOPSRDY(1U)
11644 #define S_CTCPOPSRDY 10
11645 #define V_CTCPOPSRDY(x) ((x) << S_CTCPOPSRDY)
11646 #define F_CTCPOPSRDY V_CTCPOPSRDY(1U)
11648 #define S_CPKTOUT 9
11649 #define V_CPKTOUT(x) ((x) << S_CPKTOUT)
11650 #define F_CPKTOUT V_CPKTOUT(1U)
11652 #define S_CMDBRSPSRDY 8
11653 #define V_CMDBRSPSRDY(x) ((x) << S_CMDBRSPSRDY)
11654 #define F_CMDBRSPSRDY V_CMDBRSPSRDY(1U)
11656 #define S_RXPSTRUCTSFULL 6
11657 #define M_RXPSTRUCTSFULL 0x3U
11658 #define V_RXPSTRUCTSFULL(x) ((x) << S_RXPSTRUCTSFULL)
11659 #define G_RXPSTRUCTSFULL(x) (((x) >> S_RXPSTRUCTSFULL) & M_RXPSTRUCTSFULL)
11661 #define S_RXPAGEPOOLFULL 4
11662 #define M_RXPAGEPOOLFULL 0x3U
11663 #define V_RXPAGEPOOLFULL(x) ((x) << S_RXPAGEPOOLFULL)
11664 #define G_RXPAGEPOOLFULL(x) (((x) >> S_RXPAGEPOOLFULL) & M_RXPAGEPOOLFULL)
11666 #define S_RCFREASONOUT 0
11667 #define M_RCFREASONOUT 0xfU
11668 #define V_RCFREASONOUT(x) ((x) << S_RCFREASONOUT)
11669 #define G_RCFREASONOUT(x) (((x) >> S_RCFREASONOUT) & M_RCFREASONOUT)
11671 #define A_TP_DBG_CORE_PCMD 0x69
11673 #define S_CPCMDEOPCNT 30
11674 #define M_CPCMDEOPCNT 0x3U
11675 #define V_CPCMDEOPCNT(x) ((x) << S_CPCMDEOPCNT)
11676 #define G_CPCMDEOPCNT(x) (((x) >> S_CPCMDEOPCNT) & M_CPCMDEOPCNT)
11678 #define S_CPCMDLENSAVE 16
11679 #define M_CPCMDLENSAVE 0x3fffU
11680 #define V_CPCMDLENSAVE(x) ((x) << S_CPCMDLENSAVE)
11681 #define G_CPCMDLENSAVE(x) (((x) >> S_CPCMDLENSAVE) & M_CPCMDLENSAVE)
11683 #define S_EPCMDEOPCNT 14
11684 #define M_EPCMDEOPCNT 0x3U
11685 #define V_EPCMDEOPCNT(x) ((x) << S_EPCMDEOPCNT)
11686 #define G_EPCMDEOPCNT(x) (((x) >> S_EPCMDEOPCNT) & M_EPCMDEOPCNT)
11688 #define S_EPCMDLENSAVE 0
11689 #define M_EPCMDLENSAVE 0x3fffU
11690 #define V_EPCMDLENSAVE(x) ((x) << S_EPCMDLENSAVE)
11691 #define G_EPCMDLENSAVE(x) (((x) >> S_EPCMDLENSAVE) & M_EPCMDLENSAVE)
11693 #define A_TP_DBG_SCHED_TX 0x6a
11695 #define S_TXCHNXOFF 28
11696 #define M_TXCHNXOFF 0xfU
11697 #define V_TXCHNXOFF(x) ((x) << S_TXCHNXOFF)
11698 #define G_TXCHNXOFF(x) (((x) >> S_TXCHNXOFF) & M_TXCHNXOFF)
11700 #define S_TXFIFOCNG 24
11701 #define M_TXFIFOCNG 0xfU
11702 #define V_TXFIFOCNG(x) ((x) << S_TXFIFOCNG)
11703 #define G_TXFIFOCNG(x) (((x) >> S_TXFIFOCNG) & M_TXFIFOCNG)
11705 #define S_TXPCMDCNG 20
11706 #define M_TXPCMDCNG 0xfU
11707 #define V_TXPCMDCNG(x) ((x) << S_TXPCMDCNG)
11708 #define G_TXPCMDCNG(x) (((x) >> S_TXPCMDCNG) & M_TXPCMDCNG)
11710 #define S_TXLPBKCNG 16
11711 #define M_TXLPBKCNG 0xfU
11712 #define V_TXLPBKCNG(x) ((x) << S_TXLPBKCNG)
11713 #define G_TXLPBKCNG(x) (((x) >> S_TXLPBKCNG) & M_TXLPBKCNG)
11715 #define S_TXHDRCNG 8
11716 #define M_TXHDRCNG 0xffU
11717 #define V_TXHDRCNG(x) ((x) << S_TXHDRCNG)
11718 #define G_TXHDRCNG(x) (((x) >> S_TXHDRCNG) & M_TXHDRCNG)
11720 #define S_TXMODXOFF 0
11721 #define M_TXMODXOFF 0xffU
11722 #define V_TXMODXOFF(x) ((x) << S_TXMODXOFF)
11723 #define G_TXMODXOFF(x) (((x) >> S_TXMODXOFF) & M_TXMODXOFF)
11725 #define A_TP_DBG_SCHED_RX 0x6b
11727 #define S_RXCHNXOFF 28
11728 #define M_RXCHNXOFF 0xfU
11729 #define V_RXCHNXOFF(x) ((x) << S_RXCHNXOFF)
11730 #define G_RXCHNXOFF(x) (((x) >> S_RXCHNXOFF) & M_RXCHNXOFF)
11732 #define S_RXSGECNG 24
11733 #define M_RXSGECNG 0xfU
11734 #define V_RXSGECNG(x) ((x) << S_RXSGECNG)
11735 #define G_RXSGECNG(x) (((x) >> S_RXSGECNG) & M_RXSGECNG)
11737 #define S_RXFIFOCNG 22
11738 #define M_RXFIFOCNG 0x3U
11739 #define V_RXFIFOCNG(x) ((x) << S_RXFIFOCNG)
11740 #define G_RXFIFOCNG(x) (((x) >> S_RXFIFOCNG) & M_RXFIFOCNG)
11742 #define S_RXPCMDCNG 20
11743 #define M_RXPCMDCNG 0x3U
11744 #define V_RXPCMDCNG(x) ((x) << S_RXPCMDCNG)
11745 #define G_RXPCMDCNG(x) (((x) >> S_RXPCMDCNG) & M_RXPCMDCNG)
11747 #define S_RXLPBKCNG 16
11748 #define M_RXLPBKCNG 0xfU
11749 #define V_RXLPBKCNG(x) ((x) << S_RXLPBKCNG)
11750 #define G_RXLPBKCNG(x) (((x) >> S_RXLPBKCNG) & M_RXLPBKCNG)
11752 #define S_RXHDRCNG 8
11753 #define M_RXHDRCNG 0xfU
11754 #define V_RXHDRCNG(x) ((x) << S_RXHDRCNG)
11755 #define G_RXHDRCNG(x) (((x) >> S_RXHDRCNG) & M_RXHDRCNG)
11757 #define S_RXMODXOFF 0
11758 #define M_RXMODXOFF 0x3U
11759 #define V_RXMODXOFF(x) ((x) << S_RXMODXOFF)
11760 #define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF)
11762 #define A_TP_TX_DROP_CFG_CH0 0x12b
11764 #define S_TIMERENABLED 31
11765 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
11766 #define F_TIMERENABLED V_TIMERENABLED(1U)
11768 #define S_TIMERERRORENABLE 30
11769 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
11770 #define F_TIMERERRORENABLE V_TIMERERRORENABLE(1U)
11772 #define S_TIMERTHRESHOLD 4
11773 #define M_TIMERTHRESHOLD 0x3ffffffU
11774 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
11775 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
11777 #define S_PACKETDROPS 0
11778 #define M_PACKETDROPS 0xfU
11779 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
11780 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
11782 #define A_TP_TX_DROP_CFG_CH1 0x12c
11783 #define A_TP_TX_DROP_CNT_CH0 0x12d
11785 #define S_TXDROPCNTCH0SENT 16
11786 #define M_TXDROPCNTCH0SENT 0xffffU
11787 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
11788 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
11790 #define S_TXDROPCNTCH0RCVD 0
11791 #define M_TXDROPCNTCH0RCVD 0xffffU
11792 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
11793 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
11795 #define A_TP_TX_DROP_CNT_CH1 0x12e
11797 #define S_TXDROPCNTCH1SENT 16
11798 #define M_TXDROPCNTCH1SENT 0xffffU
11799 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
11800 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
11802 #define S_TXDROPCNTCH1RCVD 0
11803 #define M_TXDROPCNTCH1RCVD 0xffffU
11804 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
11805 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
11807 #define A_TP_TX_DROP_MODE 0x12f
11809 #define S_TXDROPMODECH3 3
11810 #define V_TXDROPMODECH3(x) ((x) << S_TXDROPMODECH3)
11811 #define F_TXDROPMODECH3 V_TXDROPMODECH3(1U)
11813 #define S_TXDROPMODECH2 2
11814 #define V_TXDROPMODECH2(x) ((x) << S_TXDROPMODECH2)
11815 #define F_TXDROPMODECH2 V_TXDROPMODECH2(1U)
11817 #define S_TXDROPMODECH1 1
11818 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
11819 #define F_TXDROPMODECH1 V_TXDROPMODECH1(1U)
11821 #define S_TXDROPMODECH0 0
11822 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
11823 #define F_TXDROPMODECH0 V_TXDROPMODECH0(1U)
11825 #define A_TP_DBG_ESIDE_PKT0 0x130
11827 #define S_ETXSOPCNT 28
11828 #define M_ETXSOPCNT 0xfU
11829 #define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT)
11830 #define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT)
11832 #define S_ETXEOPCNT 24
11833 #define M_ETXEOPCNT 0xfU
11834 #define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT)
11835 #define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT)
11837 #define S_ETXPLDSOPCNT 20
11838 #define M_ETXPLDSOPCNT 0xfU
11839 #define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT)
11840 #define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT)
11842 #define S_ETXPLDEOPCNT 16
11843 #define M_ETXPLDEOPCNT 0xfU
11844 #define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT)
11845 #define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT)
11847 #define S_ERXSOPCNT 12
11848 #define M_ERXSOPCNT 0xfU
11849 #define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT)
11850 #define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT)
11852 #define S_ERXEOPCNT 8
11853 #define M_ERXEOPCNT 0xfU
11854 #define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT)
11855 #define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT)
11857 #define S_ERXPLDSOPCNT 4
11858 #define M_ERXPLDSOPCNT 0xfU
11859 #define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT)
11860 #define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT)
11862 #define S_ERXPLDEOPCNT 0
11863 #define M_ERXPLDEOPCNT 0xfU
11864 #define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT)
11865 #define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT)
11867 #define A_TP_DBG_ESIDE_PKT1 0x131
11868 #define A_TP_DBG_ESIDE_PKT2 0x132
11869 #define A_TP_DBG_ESIDE_PKT3 0x133
11870 #define A_TP_DBG_ESIDE_FIFO0 0x134
11872 #define S_PLDRXCSUMVALID1 31
11873 #define V_PLDRXCSUMVALID1(x) ((x) << S_PLDRXCSUMVALID1)
11874 #define F_PLDRXCSUMVALID1 V_PLDRXCSUMVALID1(1U)
11876 #define S_PLDRXZEROPSRDY1 30
11877 #define V_PLDRXZEROPSRDY1(x) ((x) << S_PLDRXZEROPSRDY1)
11878 #define F_PLDRXZEROPSRDY1 V_PLDRXZEROPSRDY1(1U)
11880 #define S_PLDRXVALID1 29
11881 #define V_PLDRXVALID1(x) ((x) << S_PLDRXVALID1)
11882 #define F_PLDRXVALID1 V_PLDRXVALID1(1U)
11884 #define S_TCPRXVALID1 28
11885 #define V_TCPRXVALID1(x) ((x) << S_TCPRXVALID1)
11886 #define F_TCPRXVALID1 V_TCPRXVALID1(1U)
11888 #define S_IPRXVALID1 27
11889 #define V_IPRXVALID1(x) ((x) << S_IPRXVALID1)
11890 #define F_IPRXVALID1 V_IPRXVALID1(1U)
11892 #define S_ETHRXVALID1 26
11893 #define V_ETHRXVALID1(x) ((x) << S_ETHRXVALID1)
11894 #define F_ETHRXVALID1 V_ETHRXVALID1(1U)
11896 #define S_CPLRXVALID1 25
11897 #define V_CPLRXVALID1(x) ((x) << S_CPLRXVALID1)
11898 #define F_CPLRXVALID1 V_CPLRXVALID1(1U)
11900 #define S_FSTATIC1 24
11901 #define V_FSTATIC1(x) ((x) << S_FSTATIC1)
11902 #define F_FSTATIC1 V_FSTATIC1(1U)
11904 #define S_ERRORSRDY1 23
11905 #define V_ERRORSRDY1(x) ((x) << S_ERRORSRDY1)
11906 #define F_ERRORSRDY1 V_ERRORSRDY1(1U)
11908 #define S_PLDTXSRDY1 22
11909 #define V_PLDTXSRDY1(x) ((x) << S_PLDTXSRDY1)
11910 #define F_PLDTXSRDY1 V_PLDTXSRDY1(1U)
11912 #define S_DBVLD1 21
11913 #define V_DBVLD1(x) ((x) << S_DBVLD1)
11914 #define F_DBVLD1 V_DBVLD1(1U)
11916 #define S_PLDTXVALID1 20
11917 #define V_PLDTXVALID1(x) ((x) << S_PLDTXVALID1)
11918 #define F_PLDTXVALID1 V_PLDTXVALID1(1U)
11920 #define S_ETXVALID1 19
11921 #define V_ETXVALID1(x) ((x) << S_ETXVALID1)
11922 #define F_ETXVALID1 V_ETXVALID1(1U)
11924 #define S_ETXFULL1 18
11925 #define V_ETXFULL1(x) ((x) << S_ETXFULL1)
11926 #define F_ETXFULL1 V_ETXFULL1(1U)
11928 #define S_ERXVALID1 17
11929 #define V_ERXVALID1(x) ((x) << S_ERXVALID1)
11930 #define F_ERXVALID1 V_ERXVALID1(1U)
11932 #define S_ERXFULL1 16
11933 #define V_ERXFULL1(x) ((x) << S_ERXFULL1)
11934 #define F_ERXFULL1 V_ERXFULL1(1U)
11936 #define S_PLDRXCSUMVALID0 15
11937 #define V_PLDRXCSUMVALID0(x) ((x) << S_PLDRXCSUMVALID0)
11938 #define F_PLDRXCSUMVALID0 V_PLDRXCSUMVALID0(1U)
11940 #define S_PLDRXZEROPSRDY0 14
11941 #define V_PLDRXZEROPSRDY0(x) ((x) << S_PLDRXZEROPSRDY0)
11942 #define F_PLDRXZEROPSRDY0 V_PLDRXZEROPSRDY0(1U)
11944 #define S_PLDRXVALID0 13
11945 #define V_PLDRXVALID0(x) ((x) << S_PLDRXVALID0)
11946 #define F_PLDRXVALID0 V_PLDRXVALID0(1U)
11948 #define S_TCPRXVALID0 12
11949 #define V_TCPRXVALID0(x) ((x) << S_TCPRXVALID0)
11950 #define F_TCPRXVALID0 V_TCPRXVALID0(1U)
11952 #define S_IPRXVALID0 11
11953 #define V_IPRXVALID0(x) ((x) << S_IPRXVALID0)
11954 #define F_IPRXVALID0 V_IPRXVALID0(1U)
11956 #define S_ETHRXVALID0 10
11957 #define V_ETHRXVALID0(x) ((x) << S_ETHRXVALID0)
11958 #define F_ETHRXVALID0 V_ETHRXVALID0(1U)
11960 #define S_CPLRXVALID0 9
11961 #define V_CPLRXVALID0(x) ((x) << S_CPLRXVALID0)
11962 #define F_CPLRXVALID0 V_CPLRXVALID0(1U)
11964 #define S_FSTATIC0 8
11965 #define V_FSTATIC0(x) ((x) << S_FSTATIC0)
11966 #define F_FSTATIC0 V_FSTATIC0(1U)
11968 #define S_ERRORSRDY0 7
11969 #define V_ERRORSRDY0(x) ((x) << S_ERRORSRDY0)
11970 #define F_ERRORSRDY0 V_ERRORSRDY0(1U)
11972 #define S_PLDTXSRDY0 6
11973 #define V_PLDTXSRDY0(x) ((x) << S_PLDTXSRDY0)
11974 #define F_PLDTXSRDY0 V_PLDTXSRDY0(1U)
11977 #define V_DBVLD0(x) ((x) << S_DBVLD0)
11978 #define F_DBVLD0 V_DBVLD0(1U)
11980 #define S_PLDTXVALID0 4
11981 #define V_PLDTXVALID0(x) ((x) << S_PLDTXVALID0)
11982 #define F_PLDTXVALID0 V_PLDTXVALID0(1U)
11984 #define S_ETXVALID0 3
11985 #define V_ETXVALID0(x) ((x) << S_ETXVALID0)
11986 #define F_ETXVALID0 V_ETXVALID0(1U)
11988 #define S_ETXFULL0 2
11989 #define V_ETXFULL0(x) ((x) << S_ETXFULL0)
11990 #define F_ETXFULL0 V_ETXFULL0(1U)
11992 #define S_ERXVALID0 1
11993 #define V_ERXVALID0(x) ((x) << S_ERXVALID0)
11994 #define F_ERXVALID0 V_ERXVALID0(1U)
11996 #define S_ERXFULL0 0
11997 #define V_ERXFULL0(x) ((x) << S_ERXFULL0)
11998 #define F_ERXFULL0 V_ERXFULL0(1U)
12000 #define A_TP_DBG_ESIDE_FIFO1 0x135
12002 #define S_PLDRXCSUMVALID3 31
12003 #define V_PLDRXCSUMVALID3(x) ((x) << S_PLDRXCSUMVALID3)
12004 #define F_PLDRXCSUMVALID3 V_PLDRXCSUMVALID3(1U)
12006 #define S_PLDRXZEROPSRDY3 30
12007 #define V_PLDRXZEROPSRDY3(x) ((x) << S_PLDRXZEROPSRDY3)
12008 #define F_PLDRXZEROPSRDY3 V_PLDRXZEROPSRDY3(1U)
12010 #define S_PLDRXVALID3 29
12011 #define V_PLDRXVALID3(x) ((x) << S_PLDRXVALID3)
12012 #define F_PLDRXVALID3 V_PLDRXVALID3(1U)
12014 #define S_TCPRXVALID3 28
12015 #define V_TCPRXVALID3(x) ((x) << S_TCPRXVALID3)
12016 #define F_TCPRXVALID3 V_TCPRXVALID3(1U)
12018 #define S_IPRXVALID3 27
12019 #define V_IPRXVALID3(x) ((x) << S_IPRXVALID3)
12020 #define F_IPRXVALID3 V_IPRXVALID3(1U)
12022 #define S_ETHRXVALID3 26
12023 #define V_ETHRXVALID3(x) ((x) << S_ETHRXVALID3)
12024 #define F_ETHRXVALID3 V_ETHRXVALID3(1U)
12026 #define S_CPLRXVALID3 25
12027 #define V_CPLRXVALID3(x) ((x) << S_CPLRXVALID3)
12028 #define F_CPLRXVALID3 V_CPLRXVALID3(1U)
12030 #define S_FSTATIC3 24
12031 #define V_FSTATIC3(x) ((x) << S_FSTATIC3)
12032 #define F_FSTATIC3 V_FSTATIC3(1U)
12034 #define S_ERRORSRDY3 23
12035 #define V_ERRORSRDY3(x) ((x) << S_ERRORSRDY3)
12036 #define F_ERRORSRDY3 V_ERRORSRDY3(1U)
12038 #define S_PLDTXSRDY3 22
12039 #define V_PLDTXSRDY3(x) ((x) << S_PLDTXSRDY3)
12040 #define F_PLDTXSRDY3 V_PLDTXSRDY3(1U)
12042 #define S_DBVLD3 21
12043 #define V_DBVLD3(x) ((x) << S_DBVLD3)
12044 #define F_DBVLD3 V_DBVLD3(1U)
12046 #define S_PLDTXVALID3 20
12047 #define V_PLDTXVALID3(x) ((x) << S_PLDTXVALID3)
12048 #define F_PLDTXVALID3 V_PLDTXVALID3(1U)
12050 #define S_ETXVALID3 19
12051 #define V_ETXVALID3(x) ((x) << S_ETXVALID3)
12052 #define F_ETXVALID3 V_ETXVALID3(1U)
12054 #define S_ETXFULL3 18
12055 #define V_ETXFULL3(x) ((x) << S_ETXFULL3)
12056 #define F_ETXFULL3 V_ETXFULL3(1U)
12058 #define S_ERXVALID3 17
12059 #define V_ERXVALID3(x) ((x) << S_ERXVALID3)
12060 #define F_ERXVALID3 V_ERXVALID3(1U)
12062 #define S_ERXFULL3 16
12063 #define V_ERXFULL3(x) ((x) << S_ERXFULL3)
12064 #define F_ERXFULL3 V_ERXFULL3(1U)
12066 #define S_PLDRXCSUMVALID2 15
12067 #define V_PLDRXCSUMVALID2(x) ((x) << S_PLDRXCSUMVALID2)
12068 #define F_PLDRXCSUMVALID2 V_PLDRXCSUMVALID2(1U)
12070 #define S_PLDRXZEROPSRDY2 14
12071 #define V_PLDRXZEROPSRDY2(x) ((x) << S_PLDRXZEROPSRDY2)
12072 #define F_PLDRXZEROPSRDY2 V_PLDRXZEROPSRDY2(1U)
12074 #define S_PLDRXVALID2 13
12075 #define V_PLDRXVALID2(x) ((x) << S_PLDRXVALID2)
12076 #define F_PLDRXVALID2 V_PLDRXVALID2(1U)
12078 #define S_TCPRXVALID2 12
12079 #define V_TCPRXVALID2(x) ((x) << S_TCPRXVALID2)
12080 #define F_TCPRXVALID2 V_TCPRXVALID2(1U)
12082 #define S_IPRXVALID2 11
12083 #define V_IPRXVALID2(x) ((x) << S_IPRXVALID2)
12084 #define F_IPRXVALID2 V_IPRXVALID2(1U)
12086 #define S_ETHRXVALID2 10
12087 #define V_ETHRXVALID2(x) ((x) << S_ETHRXVALID2)
12088 #define F_ETHRXVALID2 V_ETHRXVALID2(1U)
12090 #define S_CPLRXVALID2 9
12091 #define V_CPLRXVALID2(x) ((x) << S_CPLRXVALID2)
12092 #define F_CPLRXVALID2 V_CPLRXVALID2(1U)
12094 #define S_FSTATIC2 8
12095 #define V_FSTATIC2(x) ((x) << S_FSTATIC2)
12096 #define F_FSTATIC2 V_FSTATIC2(1U)
12098 #define S_ERRORSRDY2 7
12099 #define V_ERRORSRDY2(x) ((x) << S_ERRORSRDY2)
12100 #define F_ERRORSRDY2 V_ERRORSRDY2(1U)
12102 #define S_PLDTXSRDY2 6
12103 #define V_PLDTXSRDY2(x) ((x) << S_PLDTXSRDY2)
12104 #define F_PLDTXSRDY2 V_PLDTXSRDY2(1U)
12107 #define V_DBVLD2(x) ((x) << S_DBVLD2)
12108 #define F_DBVLD2 V_DBVLD2(1U)
12110 #define S_PLDTXVALID2 4
12111 #define V_PLDTXVALID2(x) ((x) << S_PLDTXVALID2)
12112 #define F_PLDTXVALID2 V_PLDTXVALID2(1U)
12114 #define S_ETXVALID2 3
12115 #define V_ETXVALID2(x) ((x) << S_ETXVALID2)
12116 #define F_ETXVALID2 V_ETXVALID2(1U)
12118 #define S_ETXFULL2 2
12119 #define V_ETXFULL2(x) ((x) << S_ETXFULL2)
12120 #define F_ETXFULL2 V_ETXFULL2(1U)
12122 #define S_ERXVALID2 1
12123 #define V_ERXVALID2(x) ((x) << S_ERXVALID2)
12124 #define F_ERXVALID2 V_ERXVALID2(1U)
12126 #define S_ERXFULL2 0
12127 #define V_ERXFULL2(x) ((x) << S_ERXFULL2)
12128 #define F_ERXFULL2 V_ERXFULL2(1U)
12130 #define A_TP_DBG_ESIDE_DISP0 0x136
12132 #define S_RESRDY 31
12133 #define V_RESRDY(x) ((x) << S_RESRDY)
12134 #define F_RESRDY V_RESRDY(1U)
12137 #define M_STATE 0x7U
12138 #define V_STATE(x) ((x) << S_STATE)
12139 #define G_STATE(x) (((x) >> S_STATE) & M_STATE)
12141 #define S_FIFOCPL5RXVALID 27
12142 #define V_FIFOCPL5RXVALID(x) ((x) << S_FIFOCPL5RXVALID)
12143 #define F_FIFOCPL5RXVALID V_FIFOCPL5RXVALID(1U)
12145 #define S_FIFOETHRXVALID 26
12146 #define V_FIFOETHRXVALID(x) ((x) << S_FIFOETHRXVALID)
12147 #define F_FIFOETHRXVALID V_FIFOETHRXVALID(1U)
12149 #define S_FIFOETHRXSOCP 25
12150 #define V_FIFOETHRXSOCP(x) ((x) << S_FIFOETHRXSOCP)
12151 #define F_FIFOETHRXSOCP V_FIFOETHRXSOCP(1U)
12153 #define S_FIFOPLDRXZEROP 24
12154 #define V_FIFOPLDRXZEROP(x) ((x) << S_FIFOPLDRXZEROP)
12155 #define F_FIFOPLDRXZEROP V_FIFOPLDRXZEROP(1U)
12157 #define S_PLDRXVALID 23
12158 #define V_PLDRXVALID(x) ((x) << S_PLDRXVALID)
12159 #define F_PLDRXVALID V_PLDRXVALID(1U)
12161 #define S_FIFOPLDRXZEROP_SRDY 22
12162 #define V_FIFOPLDRXZEROP_SRDY(x) ((x) << S_FIFOPLDRXZEROP_SRDY)
12163 #define F_FIFOPLDRXZEROP_SRDY V_FIFOPLDRXZEROP_SRDY(1U)
12165 #define S_FIFOIPRXVALID 21
12166 #define V_FIFOIPRXVALID(x) ((x) << S_FIFOIPRXVALID)
12167 #define F_FIFOIPRXVALID V_FIFOIPRXVALID(1U)
12169 #define S_FIFOTCPRXVALID 20
12170 #define V_FIFOTCPRXVALID(x) ((x) << S_FIFOTCPRXVALID)
12171 #define F_FIFOTCPRXVALID V_FIFOTCPRXVALID(1U)
12173 #define S_PLDRXCSUMVALID 19
12174 #define V_PLDRXCSUMVALID(x) ((x) << S_PLDRXCSUMVALID)
12175 #define F_PLDRXCSUMVALID V_PLDRXCSUMVALID(1U)
12177 #define S_FIFOIPCSUMSRDY 18
12178 #define V_FIFOIPCSUMSRDY(x) ((x) << S_FIFOIPCSUMSRDY)
12179 #define F_FIFOIPCSUMSRDY V_FIFOIPCSUMSRDY(1U)
12181 #define S_FIFOIPPSEUDOCSUMSRDY 17
12182 #define V_FIFOIPPSEUDOCSUMSRDY(x) ((x) << S_FIFOIPPSEUDOCSUMSRDY)
12183 #define F_FIFOIPPSEUDOCSUMSRDY V_FIFOIPPSEUDOCSUMSRDY(1U)
12185 #define S_FIFOTCPCSUMSRDY 16
12186 #define V_FIFOTCPCSUMSRDY(x) ((x) << S_FIFOTCPCSUMSRDY)
12187 #define F_FIFOTCPCSUMSRDY V_FIFOTCPCSUMSRDY(1U)
12189 #define S_ESTATIC4 12
12190 #define M_ESTATIC4 0xfU
12191 #define V_ESTATIC4(x) ((x) << S_ESTATIC4)
12192 #define G_ESTATIC4(x) (((x) >> S_ESTATIC4) & M_ESTATIC4)
12194 #define S_FIFOCPLSOCPCNT 10
12195 #define M_FIFOCPLSOCPCNT 0x3U
12196 #define V_FIFOCPLSOCPCNT(x) ((x) << S_FIFOCPLSOCPCNT)
12197 #define G_FIFOCPLSOCPCNT(x) (((x) >> S_FIFOCPLSOCPCNT) & M_FIFOCPLSOCPCNT)
12199 #define S_FIFOETHSOCPCNT 8
12200 #define M_FIFOETHSOCPCNT 0x3U
12201 #define V_FIFOETHSOCPCNT(x) ((x) << S_FIFOETHSOCPCNT)
12202 #define G_FIFOETHSOCPCNT(x) (((x) >> S_FIFOETHSOCPCNT) & M_FIFOETHSOCPCNT)
12204 #define S_FIFOIPSOCPCNT 6
12205 #define M_FIFOIPSOCPCNT 0x3U
12206 #define V_FIFOIPSOCPCNT(x) ((x) << S_FIFOIPSOCPCNT)
12207 #define G_FIFOIPSOCPCNT(x) (((x) >> S_FIFOIPSOCPCNT) & M_FIFOIPSOCPCNT)
12209 #define S_FIFOTCPSOCPCNT 4
12210 #define M_FIFOTCPSOCPCNT 0x3U
12211 #define V_FIFOTCPSOCPCNT(x) ((x) << S_FIFOTCPSOCPCNT)
12212 #define G_FIFOTCPSOCPCNT(x) (((x) >> S_FIFOTCPSOCPCNT) & M_FIFOTCPSOCPCNT)
12214 #define S_PLD_RXZEROP_CNT 2
12215 #define M_PLD_RXZEROP_CNT 0x3U
12216 #define V_PLD_RXZEROP_CNT(x) ((x) << S_PLD_RXZEROP_CNT)
12217 #define G_PLD_RXZEROP_CNT(x) (((x) >> S_PLD_RXZEROP_CNT) & M_PLD_RXZEROP_CNT)
12219 #define S_ESTATIC6 1
12220 #define V_ESTATIC6(x) ((x) << S_ESTATIC6)
12221 #define F_ESTATIC6 V_ESTATIC6(1U)
12224 #define V_TXFULL(x) ((x) << S_TXFULL)
12225 #define F_TXFULL V_TXFULL(1U)
12227 #define A_TP_DBG_ESIDE_DISP1 0x137
12228 #define A_TP_MAC_MATCH_MAP0 0x138
12230 #define S_MAPVALUEWR 16
12231 #define M_MAPVALUEWR 0xffU
12232 #define V_MAPVALUEWR(x) ((x) << S_MAPVALUEWR)
12233 #define G_MAPVALUEWR(x) (((x) >> S_MAPVALUEWR) & M_MAPVALUEWR)
12235 #define S_MAPINDEX 2
12236 #define M_MAPINDEX 0x1ffU
12237 #define V_MAPINDEX(x) ((x) << S_MAPINDEX)
12238 #define G_MAPINDEX(x) (((x) >> S_MAPINDEX) & M_MAPINDEX)
12240 #define S_MAPREAD 1
12241 #define V_MAPREAD(x) ((x) << S_MAPREAD)
12242 #define F_MAPREAD V_MAPREAD(1U)
12244 #define S_MAPWRITE 0
12245 #define V_MAPWRITE(x) ((x) << S_MAPWRITE)
12246 #define F_MAPWRITE V_MAPWRITE(1U)
12248 #define A_TP_MAC_MATCH_MAP1 0x139
12250 #define S_MAPVALUERD 0
12251 #define M_MAPVALUERD 0x1ffU
12252 #define V_MAPVALUERD(x) ((x) << S_MAPVALUERD)
12253 #define G_MAPVALUERD(x) (((x) >> S_MAPVALUERD) & M_MAPVALUERD)
12255 #define A_TP_DBG_ESIDE_DISP2 0x13a
12256 #define A_TP_DBG_ESIDE_DISP3 0x13b
12257 #define A_TP_DBG_ESIDE_HDR0 0x13c
12259 #define S_TCPSOPCNT 28
12260 #define M_TCPSOPCNT 0xfU
12261 #define V_TCPSOPCNT(x) ((x) << S_TCPSOPCNT)
12262 #define G_TCPSOPCNT(x) (((x) >> S_TCPSOPCNT) & M_TCPSOPCNT)
12264 #define S_TCPEOPCNT 24
12265 #define M_TCPEOPCNT 0xfU
12266 #define V_TCPEOPCNT(x) ((x) << S_TCPEOPCNT)
12267 #define G_TCPEOPCNT(x) (((x) >> S_TCPEOPCNT) & M_TCPEOPCNT)
12269 #define S_IPSOPCNT 20
12270 #define M_IPSOPCNT 0xfU
12271 #define V_IPSOPCNT(x) ((x) << S_IPSOPCNT)
12272 #define G_IPSOPCNT(x) (((x) >> S_IPSOPCNT) & M_IPSOPCNT)
12274 #define S_IPEOPCNT 16
12275 #define M_IPEOPCNT 0xfU
12276 #define V_IPEOPCNT(x) ((x) << S_IPEOPCNT)
12277 #define G_IPEOPCNT(x) (((x) >> S_IPEOPCNT) & M_IPEOPCNT)
12279 #define S_ETHSOPCNT 12
12280 #define M_ETHSOPCNT 0xfU
12281 #define V_ETHSOPCNT(x) ((x) << S_ETHSOPCNT)
12282 #define G_ETHSOPCNT(x) (((x) >> S_ETHSOPCNT) & M_ETHSOPCNT)
12284 #define S_ETHEOPCNT 8
12285 #define M_ETHEOPCNT 0xfU
12286 #define V_ETHEOPCNT(x) ((x) << S_ETHEOPCNT)
12287 #define G_ETHEOPCNT(x) (((x) >> S_ETHEOPCNT) & M_ETHEOPCNT)
12289 #define S_CPLSOPCNT 4
12290 #define M_CPLSOPCNT 0xfU
12291 #define V_CPLSOPCNT(x) ((x) << S_CPLSOPCNT)
12292 #define G_CPLSOPCNT(x) (((x) >> S_CPLSOPCNT) & M_CPLSOPCNT)
12294 #define S_CPLEOPCNT 0
12295 #define M_CPLEOPCNT 0xfU
12296 #define V_CPLEOPCNT(x) ((x) << S_CPLEOPCNT)
12297 #define G_CPLEOPCNT(x) (((x) >> S_CPLEOPCNT) & M_CPLEOPCNT)
12299 #define A_TP_DBG_ESIDE_HDR1 0x13d
12300 #define A_TP_DBG_ESIDE_HDR2 0x13e
12301 #define A_TP_DBG_ESIDE_HDR3 0x13f
12302 #define A_TP_VLAN_PRI_MAP 0x140
12304 #define S_FRAGMENTATION 9
12305 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
12306 #define F_FRAGMENTATION V_FRAGMENTATION(1U)
12308 #define S_MPSHITTYPE 8
12309 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
12310 #define F_MPSHITTYPE V_MPSHITTYPE(1U)
12312 #define S_MACMATCH 7
12313 #define V_MACMATCH(x) ((x) << S_MACMATCH)
12314 #define F_MACMATCH V_MACMATCH(1U)
12316 #define S_ETHERTYPE 6
12317 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
12318 #define F_ETHERTYPE V_ETHERTYPE(1U)
12320 #define S_PROTOCOL 5
12321 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
12322 #define F_PROTOCOL V_PROTOCOL(1U)
12325 #define V_TOS(x) ((x) << S_TOS)
12326 #define F_TOS V_TOS(1U)
12329 #define V_VLAN(x) ((x) << S_VLAN)
12330 #define F_VLAN V_VLAN(1U)
12332 #define S_VNIC_ID 2
12333 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
12334 #define F_VNIC_ID V_VNIC_ID(1U)
12337 #define V_PORT(x) ((x) << S_PORT)
12338 #define F_PORT V_PORT(1U)
12341 #define V_FCOE(x) ((x) << S_FCOE)
12342 #define F_FCOE V_FCOE(1U)
12344 #define A_TP_INGRESS_CONFIG 0x141
12346 #define S_OPAQUE_TYPE 16
12347 #define M_OPAQUE_TYPE 0xffffU
12348 #define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE)
12349 #define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE)
12351 #define S_OPAQUE_RM 15
12352 #define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM)
12353 #define F_OPAQUE_RM V_OPAQUE_RM(1U)
12355 #define S_OPAQUE_HDR_SIZE 14
12356 #define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE)
12357 #define F_OPAQUE_HDR_SIZE V_OPAQUE_HDR_SIZE(1U)
12359 #define S_OPAQUE_RM_MAC_IN_MAC 13
12360 #define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC)
12361 #define F_OPAQUE_RM_MAC_IN_MAC V_OPAQUE_RM_MAC_IN_MAC(1U)
12363 #define S_FCOE_TARGET 12
12364 #define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET)
12365 #define F_FCOE_TARGET V_FCOE_TARGET(1U)
12368 #define V_VNIC(x) ((x) << S_VNIC)
12369 #define F_VNIC V_VNIC(1U)
12371 #define S_CSUM_HAS_PSEUDO_HDR 10
12372 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
12373 #define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U)
12375 #define S_RM_OVLAN 9
12376 #define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
12377 #define F_RM_OVLAN V_RM_OVLAN(1U)
12379 #define S_LOOKUPEVERYPKT 8
12380 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
12381 #define F_LOOKUPEVERYPKT V_LOOKUPEVERYPKT(1U)
12383 #define S_IPV6_EXT_HDR_SKIP 0
12384 #define M_IPV6_EXT_HDR_SKIP 0xffU
12385 #define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
12386 #define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
12388 #define A_TP_TX_DROP_CFG_CH2 0x142
12389 #define A_TP_TX_DROP_CFG_CH3 0x143
12390 #define A_TP_EGRESS_CONFIG 0x145
12392 #define S_REWRITEFORCETOSIZE 0
12393 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
12394 #define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U)
12396 #define A_TP_EHDR_CONFIG_LO 0x146
12398 #define S_CPLLIMIT 24
12399 #define M_CPLLIMIT 0xffU
12400 #define V_CPLLIMIT(x) ((x) << S_CPLLIMIT)
12401 #define G_CPLLIMIT(x) (((x) >> S_CPLLIMIT) & M_CPLLIMIT)
12403 #define S_ETHLIMIT 16
12404 #define M_ETHLIMIT 0xffU
12405 #define V_ETHLIMIT(x) ((x) << S_ETHLIMIT)
12406 #define G_ETHLIMIT(x) (((x) >> S_ETHLIMIT) & M_ETHLIMIT)
12408 #define S_IPLIMIT 8
12409 #define M_IPLIMIT 0xffU
12410 #define V_IPLIMIT(x) ((x) << S_IPLIMIT)
12411 #define G_IPLIMIT(x) (((x) >> S_IPLIMIT) & M_IPLIMIT)
12413 #define S_TCPLIMIT 0
12414 #define M_TCPLIMIT 0xffU
12415 #define V_TCPLIMIT(x) ((x) << S_TCPLIMIT)
12416 #define G_TCPLIMIT(x) (((x) >> S_TCPLIMIT) & M_TCPLIMIT)
12418 #define A_TP_EHDR_CONFIG_HI 0x147
12419 #define A_TP_DBG_ESIDE_INT 0x148
12421 #define S_ERXSOP2X 28
12422 #define M_ERXSOP2X 0xfU
12423 #define V_ERXSOP2X(x) ((x) << S_ERXSOP2X)
12424 #define G_ERXSOP2X(x) (((x) >> S_ERXSOP2X) & M_ERXSOP2X)
12426 #define S_ERXEOP2X 24
12427 #define M_ERXEOP2X 0xfU
12428 #define V_ERXEOP2X(x) ((x) << S_ERXEOP2X)
12429 #define G_ERXEOP2X(x) (((x) >> S_ERXEOP2X) & M_ERXEOP2X)
12431 #define S_ERXVALID2X 20
12432 #define M_ERXVALID2X 0xfU
12433 #define V_ERXVALID2X(x) ((x) << S_ERXVALID2X)
12434 #define G_ERXVALID2X(x) (((x) >> S_ERXVALID2X) & M_ERXVALID2X)
12436 #define S_ERXAFULL2X 16
12437 #define M_ERXAFULL2X 0xfU
12438 #define V_ERXAFULL2X(x) ((x) << S_ERXAFULL2X)
12439 #define G_ERXAFULL2X(x) (((x) >> S_ERXAFULL2X) & M_ERXAFULL2X)
12441 #define S_PLD2XTXVALID 12
12442 #define M_PLD2XTXVALID 0xfU
12443 #define V_PLD2XTXVALID(x) ((x) << S_PLD2XTXVALID)
12444 #define G_PLD2XTXVALID(x) (((x) >> S_PLD2XTXVALID) & M_PLD2XTXVALID)
12446 #define S_PLD2XTXAFULL 8
12447 #define M_PLD2XTXAFULL 0xfU
12448 #define V_PLD2XTXAFULL(x) ((x) << S_PLD2XTXAFULL)
12449 #define G_PLD2XTXAFULL(x) (((x) >> S_PLD2XTXAFULL) & M_PLD2XTXAFULL)
12451 #define S_ERRORSRDY 7
12452 #define V_ERRORSRDY(x) ((x) << S_ERRORSRDY)
12453 #define F_ERRORSRDY V_ERRORSRDY(1U)
12455 #define S_ERRORDRDY 6
12456 #define V_ERRORDRDY(x) ((x) << S_ERRORDRDY)
12457 #define F_ERRORDRDY V_ERRORDRDY(1U)
12459 #define S_TCPOPSRDY 5
12460 #define V_TCPOPSRDY(x) ((x) << S_TCPOPSRDY)
12461 #define F_TCPOPSRDY V_TCPOPSRDY(1U)
12463 #define S_TCPOPDRDY 4
12464 #define V_TCPOPDRDY(x) ((x) << S_TCPOPDRDY)
12465 #define F_TCPOPDRDY V_TCPOPDRDY(1U)
12467 #define S_PLDTXSRDY 3
12468 #define V_PLDTXSRDY(x) ((x) << S_PLDTXSRDY)
12469 #define F_PLDTXSRDY V_PLDTXSRDY(1U)
12471 #define S_PLDTXDRDY 2
12472 #define V_PLDTXDRDY(x) ((x) << S_PLDTXDRDY)
12473 #define F_PLDTXDRDY V_PLDTXDRDY(1U)
12475 #define S_TCPOPTTXVALID 1
12476 #define V_TCPOPTTXVALID(x) ((x) << S_TCPOPTTXVALID)
12477 #define F_TCPOPTTXVALID V_TCPOPTTXVALID(1U)
12479 #define S_TCPOPTTXFULL 0
12480 #define V_TCPOPTTXFULL(x) ((x) << S_TCPOPTTXFULL)
12481 #define F_TCPOPTTXFULL V_TCPOPTTXFULL(1U)
12483 #define A_TP_DBG_ESIDE_DEMUX 0x149
12485 #define S_EALLDONE 28
12486 #define M_EALLDONE 0xfU
12487 #define V_EALLDONE(x) ((x) << S_EALLDONE)
12488 #define G_EALLDONE(x) (((x) >> S_EALLDONE) & M_EALLDONE)
12490 #define S_EFIFOPLDDONE 24
12491 #define M_EFIFOPLDDONE 0xfU
12492 #define V_EFIFOPLDDONE(x) ((x) << S_EFIFOPLDDONE)
12493 #define G_EFIFOPLDDONE(x) (((x) >> S_EFIFOPLDDONE) & M_EFIFOPLDDONE)
12495 #define S_EDBDONE 20
12496 #define M_EDBDONE 0xfU
12497 #define V_EDBDONE(x) ((x) << S_EDBDONE)
12498 #define G_EDBDONE(x) (((x) >> S_EDBDONE) & M_EDBDONE)
12500 #define S_EISSFIFODONE 16
12501 #define M_EISSFIFODONE 0xfU
12502 #define V_EISSFIFODONE(x) ((x) << S_EISSFIFODONE)
12503 #define G_EISSFIFODONE(x) (((x) >> S_EISSFIFODONE) & M_EISSFIFODONE)
12505 #define S_EACKERRFIFODONE 12
12506 #define M_EACKERRFIFODONE 0xfU
12507 #define V_EACKERRFIFODONE(x) ((x) << S_EACKERRFIFODONE)
12508 #define G_EACKERRFIFODONE(x) (((x) >> S_EACKERRFIFODONE) & M_EACKERRFIFODONE)
12510 #define S_EFIFOERRORDONE 8
12511 #define M_EFIFOERRORDONE 0xfU
12512 #define V_EFIFOERRORDONE(x) ((x) << S_EFIFOERRORDONE)
12513 #define G_EFIFOERRORDONE(x) (((x) >> S_EFIFOERRORDONE) & M_EFIFOERRORDONE)
12515 #define S_ERXPKTATTRFIFOFDONE 4
12516 #define M_ERXPKTATTRFIFOFDONE 0xfU
12517 #define V_ERXPKTATTRFIFOFDONE(x) ((x) << S_ERXPKTATTRFIFOFDONE)
12518 #define G_ERXPKTATTRFIFOFDONE(x) (((x) >> S_ERXPKTATTRFIFOFDONE) & M_ERXPKTATTRFIFOFDONE)
12520 #define S_ETCPOPDONE 0
12521 #define M_ETCPOPDONE 0xfU
12522 #define V_ETCPOPDONE(x) ((x) << S_ETCPOPDONE)
12523 #define G_ETCPOPDONE(x) (((x) >> S_ETCPOPDONE) & M_ETCPOPDONE)
12525 #define A_TP_DBG_ESIDE_IN0 0x14a
12527 #define S_RXVALID 31
12528 #define V_RXVALID(x) ((x) << S_RXVALID)
12529 #define F_RXVALID V_RXVALID(1U)
12531 #define S_RXFULL 30
12532 #define V_RXFULL(x) ((x) << S_RXFULL)
12533 #define F_RXFULL V_RXFULL(1U)
12535 #define S_RXSOCP 29
12536 #define V_RXSOCP(x) ((x) << S_RXSOCP)
12537 #define F_RXSOCP V_RXSOCP(1U)
12540 #define V_RXEOP(x) ((x) << S_RXEOP)
12541 #define F_RXEOP V_RXEOP(1U)
12543 #define S_RXVALID_I 27
12544 #define V_RXVALID_I(x) ((x) << S_RXVALID_I)
12545 #define F_RXVALID_I V_RXVALID_I(1U)
12547 #define S_RXFULL_I 26
12548 #define V_RXFULL_I(x) ((x) << S_RXFULL_I)
12549 #define F_RXFULL_I V_RXFULL_I(1U)
12551 #define S_RXSOCP_I 25
12552 #define V_RXSOCP_I(x) ((x) << S_RXSOCP_I)
12553 #define F_RXSOCP_I V_RXSOCP_I(1U)
12555 #define S_RXEOP_I 24
12556 #define V_RXEOP_I(x) ((x) << S_RXEOP_I)
12557 #define F_RXEOP_I V_RXEOP_I(1U)
12559 #define S_RXVALID_I2 23
12560 #define V_RXVALID_I2(x) ((x) << S_RXVALID_I2)
12561 #define F_RXVALID_I2 V_RXVALID_I2(1U)
12563 #define S_RXFULL_I2 22
12564 #define V_RXFULL_I2(x) ((x) << S_RXFULL_I2)
12565 #define F_RXFULL_I2 V_RXFULL_I2(1U)
12567 #define S_RXSOCP_I2 21
12568 #define V_RXSOCP_I2(x) ((x) << S_RXSOCP_I2)
12569 #define F_RXSOCP_I2 V_RXSOCP_I2(1U)
12571 #define S_RXEOP_I2 20
12572 #define V_RXEOP_I2(x) ((x) << S_RXEOP_I2)
12573 #define F_RXEOP_I2 V_RXEOP_I2(1U)
12575 #define S_CT_MPA_TXVALID_FIFO 19
12576 #define V_CT_MPA_TXVALID_FIFO(x) ((x) << S_CT_MPA_TXVALID_FIFO)
12577 #define F_CT_MPA_TXVALID_FIFO V_CT_MPA_TXVALID_FIFO(1U)
12579 #define S_CT_MPA_TXFULL_FIFO 18
12580 #define V_CT_MPA_TXFULL_FIFO(x) ((x) << S_CT_MPA_TXFULL_FIFO)
12581 #define F_CT_MPA_TXFULL_FIFO V_CT_MPA_TXFULL_FIFO(1U)
12583 #define S_CT_MPA_TXVALID 17
12584 #define V_CT_MPA_TXVALID(x) ((x) << S_CT_MPA_TXVALID)
12585 #define F_CT_MPA_TXVALID V_CT_MPA_TXVALID(1U)
12587 #define S_CT_MPA_TXFULL 16
12588 #define V_CT_MPA_TXFULL(x) ((x) << S_CT_MPA_TXFULL)
12589 #define F_CT_MPA_TXFULL V_CT_MPA_TXFULL(1U)
12591 #define S_RXVALID_BUF 15
12592 #define V_RXVALID_BUF(x) ((x) << S_RXVALID_BUF)
12593 #define F_RXVALID_BUF V_RXVALID_BUF(1U)
12595 #define S_RXFULL_BUF 14
12596 #define V_RXFULL_BUF(x) ((x) << S_RXFULL_BUF)
12597 #define F_RXFULL_BUF V_RXFULL_BUF(1U)
12599 #define S_PLD_TXVALID 13
12600 #define V_PLD_TXVALID(x) ((x) << S_PLD_TXVALID)
12601 #define F_PLD_TXVALID V_PLD_TXVALID(1U)
12603 #define S_PLD_TXFULL 12
12604 #define V_PLD_TXFULL(x) ((x) << S_PLD_TXFULL)
12605 #define F_PLD_TXFULL V_PLD_TXFULL(1U)
12607 #define S_ISS_FIFO_SRDY 11
12608 #define V_ISS_FIFO_SRDY(x) ((x) << S_ISS_FIFO_SRDY)
12609 #define F_ISS_FIFO_SRDY V_ISS_FIFO_SRDY(1U)
12611 #define S_ISS_FIFO_DRDY 10
12612 #define V_ISS_FIFO_DRDY(x) ((x) << S_ISS_FIFO_DRDY)
12613 #define F_ISS_FIFO_DRDY V_ISS_FIFO_DRDY(1U)
12615 #define S_CT_TCP_OP_ISS_SRDY 9
12616 #define V_CT_TCP_OP_ISS_SRDY(x) ((x) << S_CT_TCP_OP_ISS_SRDY)
12617 #define F_CT_TCP_OP_ISS_SRDY V_CT_TCP_OP_ISS_SRDY(1U)
12619 #define S_CT_TCP_OP_ISS_DRDY 8
12620 #define V_CT_TCP_OP_ISS_DRDY(x) ((x) << S_CT_TCP_OP_ISS_DRDY)
12621 #define F_CT_TCP_OP_ISS_DRDY V_CT_TCP_OP_ISS_DRDY(1U)
12623 #define S_P2CSUMERROR_SRDY 7
12624 #define V_P2CSUMERROR_SRDY(x) ((x) << S_P2CSUMERROR_SRDY)
12625 #define F_P2CSUMERROR_SRDY V_P2CSUMERROR_SRDY(1U)
12627 #define S_P2CSUMERROR_DRDY 6
12628 #define V_P2CSUMERROR_DRDY(x) ((x) << S_P2CSUMERROR_DRDY)
12629 #define F_P2CSUMERROR_DRDY V_P2CSUMERROR_DRDY(1U)
12631 #define S_FIFO_ERROR_SRDY 5
12632 #define V_FIFO_ERROR_SRDY(x) ((x) << S_FIFO_ERROR_SRDY)
12633 #define F_FIFO_ERROR_SRDY V_FIFO_ERROR_SRDY(1U)
12635 #define S_FIFO_ERROR_DRDY 4
12636 #define V_FIFO_ERROR_DRDY(x) ((x) << S_FIFO_ERROR_DRDY)
12637 #define F_FIFO_ERROR_DRDY V_FIFO_ERROR_DRDY(1U)
12639 #define S_PLD_SRDY 3
12640 #define V_PLD_SRDY(x) ((x) << S_PLD_SRDY)
12641 #define F_PLD_SRDY V_PLD_SRDY(1U)
12643 #define S_PLD_DRDY 2
12644 #define V_PLD_DRDY(x) ((x) << S_PLD_DRDY)
12645 #define F_PLD_DRDY V_PLD_DRDY(1U)
12647 #define S_RX_PKT_ATTR_SRDY 1
12648 #define V_RX_PKT_ATTR_SRDY(x) ((x) << S_RX_PKT_ATTR_SRDY)
12649 #define F_RX_PKT_ATTR_SRDY V_RX_PKT_ATTR_SRDY(1U)
12651 #define S_RX_PKT_ATTR_DRDY 0
12652 #define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY)
12653 #define F_RX_PKT_ATTR_DRDY V_RX_PKT_ATTR_DRDY(1U)
12655 #define A_TP_DBG_ESIDE_IN1 0x14b
12656 #define A_TP_DBG_ESIDE_IN2 0x14c
12657 #define A_TP_DBG_ESIDE_IN3 0x14d
12658 #define A_TP_DBG_ESIDE_FRM 0x14e
12660 #define S_ERX2XERROR 28
12661 #define M_ERX2XERROR 0xfU
12662 #define V_ERX2XERROR(x) ((x) << S_ERX2XERROR)
12663 #define G_ERX2XERROR(x) (((x) >> S_ERX2XERROR) & M_ERX2XERROR)
12665 #define S_EPLDTX2XERROR 24
12666 #define M_EPLDTX2XERROR 0xfU
12667 #define V_EPLDTX2XERROR(x) ((x) << S_EPLDTX2XERROR)
12668 #define G_EPLDTX2XERROR(x) (((x) >> S_EPLDTX2XERROR) & M_EPLDTX2XERROR)
12670 #define S_ETXERROR 20
12671 #define M_ETXERROR 0xfU
12672 #define V_ETXERROR(x) ((x) << S_ETXERROR)
12673 #define G_ETXERROR(x) (((x) >> S_ETXERROR) & M_ETXERROR)
12675 #define S_EPLDRXERROR 16
12676 #define M_EPLDRXERROR 0xfU
12677 #define V_EPLDRXERROR(x) ((x) << S_EPLDRXERROR)
12678 #define G_EPLDRXERROR(x) (((x) >> S_EPLDRXERROR) & M_EPLDRXERROR)
12680 #define S_ERXSIZEERROR3 12
12681 #define M_ERXSIZEERROR3 0xfU
12682 #define V_ERXSIZEERROR3(x) ((x) << S_ERXSIZEERROR3)
12683 #define G_ERXSIZEERROR3(x) (((x) >> S_ERXSIZEERROR3) & M_ERXSIZEERROR3)
12685 #define S_ERXSIZEERROR2 8
12686 #define M_ERXSIZEERROR2 0xfU
12687 #define V_ERXSIZEERROR2(x) ((x) << S_ERXSIZEERROR2)
12688 #define G_ERXSIZEERROR2(x) (((x) >> S_ERXSIZEERROR2) & M_ERXSIZEERROR2)
12690 #define S_ERXSIZEERROR1 4
12691 #define M_ERXSIZEERROR1 0xfU
12692 #define V_ERXSIZEERROR1(x) ((x) << S_ERXSIZEERROR1)
12693 #define G_ERXSIZEERROR1(x) (((x) >> S_ERXSIZEERROR1) & M_ERXSIZEERROR1)
12695 #define S_ERXSIZEERROR0 0
12696 #define M_ERXSIZEERROR0 0xfU
12697 #define V_ERXSIZEERROR0(x) ((x) << S_ERXSIZEERROR0)
12698 #define G_ERXSIZEERROR0(x) (((x) >> S_ERXSIZEERROR0) & M_ERXSIZEERROR0)
12700 #define A_TP_DBG_ESIDE_DRP 0x14f
12702 #define S_RXDROP3 24
12703 #define M_RXDROP3 0xffU
12704 #define V_RXDROP3(x) ((x) << S_RXDROP3)
12705 #define G_RXDROP3(x) (((x) >> S_RXDROP3) & M_RXDROP3)
12707 #define S_RXDROP2 16
12708 #define M_RXDROP2 0xffU
12709 #define V_RXDROP2(x) ((x) << S_RXDROP2)
12710 #define G_RXDROP2(x) (((x) >> S_RXDROP2) & M_RXDROP2)
12712 #define S_RXDROP1 8
12713 #define M_RXDROP1 0xffU
12714 #define V_RXDROP1(x) ((x) << S_RXDROP1)
12715 #define G_RXDROP1(x) (((x) >> S_RXDROP1) & M_RXDROP1)
12717 #define S_RXDROP0 0
12718 #define M_RXDROP0 0xffU
12719 #define V_RXDROP0(x) ((x) << S_RXDROP0)
12720 #define G_RXDROP0(x) (((x) >> S_RXDROP0) & M_RXDROP0)
12722 #define A_TP_DBG_ESIDE_TX 0x150
12724 #define S_ETXVALID 4
12725 #define M_ETXVALID 0xfU
12726 #define V_ETXVALID(x) ((x) << S_ETXVALID)
12727 #define G_ETXVALID(x) (((x) >> S_ETXVALID) & M_ETXVALID)
12729 #define S_ETXFULL 0
12730 #define M_ETXFULL 0xfU
12731 #define V_ETXFULL(x) ((x) << S_ETXFULL)
12732 #define G_ETXFULL(x) (((x) >> S_ETXFULL) & M_ETXFULL)
12734 #define A_TP_ESIDE_SVID_MASK 0x151
12735 #define A_TP_ESIDE_DVID_MASK 0x152
12736 #define A_TP_ESIDE_ALIGN_MASK 0x153
12738 #define S_USE_LOOP_BIT 24
12739 #define V_USE_LOOP_BIT(x) ((x) << S_USE_LOOP_BIT)
12740 #define F_USE_LOOP_BIT V_USE_LOOP_BIT(1U)
12742 #define S_LOOP_OFFSET 16
12743 #define M_LOOP_OFFSET 0xffU
12744 #define V_LOOP_OFFSET(x) ((x) << S_LOOP_OFFSET)
12745 #define G_LOOP_OFFSET(x) (((x) >> S_LOOP_OFFSET) & M_LOOP_OFFSET)
12747 #define S_DVID_ID_OFFSET 8
12748 #define M_DVID_ID_OFFSET 0xffU
12749 #define V_DVID_ID_OFFSET(x) ((x) << S_DVID_ID_OFFSET)
12750 #define G_DVID_ID_OFFSET(x) (((x) >> S_DVID_ID_OFFSET) & M_DVID_ID_OFFSET)
12752 #define S_SVID_ID_OFFSET 0
12753 #define M_SVID_ID_OFFSET 0xffU
12754 #define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET)
12755 #define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET)
12757 #define A_TP_DBG_CSIDE_RX0 0x230
12759 #define S_CRXSOPCNT 28
12760 #define M_CRXSOPCNT 0xfU
12761 #define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT)
12762 #define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT)
12764 #define S_CRXEOPCNT 24
12765 #define M_CRXEOPCNT 0xfU
12766 #define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT)
12767 #define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT)
12769 #define S_CRXPLDSOPCNT 20
12770 #define M_CRXPLDSOPCNT 0xfU
12771 #define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT)
12772 #define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT)
12774 #define S_CRXPLDEOPCNT 16
12775 #define M_CRXPLDEOPCNT 0xfU
12776 #define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT)
12777 #define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT)
12779 #define S_CRXARBSOPCNT 12
12780 #define M_CRXARBSOPCNT 0xfU
12781 #define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT)
12782 #define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT)
12784 #define S_CRXARBEOPCNT 8
12785 #define M_CRXARBEOPCNT 0xfU
12786 #define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT)
12787 #define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT)
12789 #define S_CRXCPLSOPCNT 4
12790 #define M_CRXCPLSOPCNT 0xfU
12791 #define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT)
12792 #define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT)
12794 #define S_CRXCPLEOPCNT 0
12795 #define M_CRXCPLEOPCNT 0xfU
12796 #define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT)
12797 #define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT)
12799 #define A_TP_DBG_CSIDE_RX1 0x231
12800 #define A_TP_DBG_CSIDE_RX2 0x232
12801 #define A_TP_DBG_CSIDE_RX3 0x233
12802 #define A_TP_DBG_CSIDE_TX0 0x234
12804 #define S_TXSOPCNT 28
12805 #define M_TXSOPCNT 0xfU
12806 #define V_TXSOPCNT(x) ((x) << S_TXSOPCNT)
12807 #define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT)
12809 #define S_TXEOPCNT 24
12810 #define M_TXEOPCNT 0xfU
12811 #define V_TXEOPCNT(x) ((x) << S_TXEOPCNT)
12812 #define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT)
12814 #define S_TXPLDSOPCNT 20
12815 #define M_TXPLDSOPCNT 0xfU
12816 #define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT)
12817 #define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT)
12819 #define S_TXPLDEOPCNT 16
12820 #define M_TXPLDEOPCNT 0xfU
12821 #define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT)
12822 #define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT)
12824 #define S_TXARBSOPCNT 12
12825 #define M_TXARBSOPCNT 0xfU
12826 #define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT)
12827 #define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT)
12829 #define S_TXARBEOPCNT 8
12830 #define M_TXARBEOPCNT 0xfU
12831 #define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT)
12832 #define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT)
12834 #define S_TXCPLSOPCNT 4
12835 #define M_TXCPLSOPCNT 0xfU
12836 #define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT)
12837 #define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT)
12839 #define S_TXCPLEOPCNT 0
12840 #define M_TXCPLEOPCNT 0xfU
12841 #define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT)
12842 #define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT)
12844 #define A_TP_DBG_CSIDE_TX1 0x235
12845 #define A_TP_DBG_CSIDE_TX2 0x236
12846 #define A_TP_DBG_CSIDE_TX3 0x237
12847 #define A_TP_DBG_CSIDE_FIFO0 0x238
12849 #define S_PLD_RXZEROP_SRDY1 31
12850 #define V_PLD_RXZEROP_SRDY1(x) ((x) << S_PLD_RXZEROP_SRDY1)
12851 #define F_PLD_RXZEROP_SRDY1 V_PLD_RXZEROP_SRDY1(1U)
12853 #define S_PLD_RXZEROP_DRDY1 30
12854 #define V_PLD_RXZEROP_DRDY1(x) ((x) << S_PLD_RXZEROP_DRDY1)
12855 #define F_PLD_RXZEROP_DRDY1 V_PLD_RXZEROP_DRDY1(1U)
12857 #define S_PLD_TXZEROP_SRDY1 29
12858 #define V_PLD_TXZEROP_SRDY1(x) ((x) << S_PLD_TXZEROP_SRDY1)
12859 #define F_PLD_TXZEROP_SRDY1 V_PLD_TXZEROP_SRDY1(1U)
12861 #define S_PLD_TXZEROP_DRDY1 28
12862 #define V_PLD_TXZEROP_DRDY1(x) ((x) << S_PLD_TXZEROP_DRDY1)
12863 #define F_PLD_TXZEROP_DRDY1 V_PLD_TXZEROP_DRDY1(1U)
12865 #define S_PLD_TX_SRDY1 27
12866 #define V_PLD_TX_SRDY1(x) ((x) << S_PLD_TX_SRDY1)
12867 #define F_PLD_TX_SRDY1 V_PLD_TX_SRDY1(1U)
12869 #define S_PLD_TX_DRDY1 26
12870 #define V_PLD_TX_DRDY1(x) ((x) << S_PLD_TX_DRDY1)
12871 #define F_PLD_TX_DRDY1 V_PLD_TX_DRDY1(1U)
12873 #define S_ERROR_SRDY1 25
12874 #define V_ERROR_SRDY1(x) ((x) << S_ERROR_SRDY1)
12875 #define F_ERROR_SRDY1 V_ERROR_SRDY1(1U)
12877 #define S_ERROR_DRDY1 24
12878 #define V_ERROR_DRDY1(x) ((x) << S_ERROR_DRDY1)
12879 #define F_ERROR_DRDY1 V_ERROR_DRDY1(1U)
12881 #define S_DB_VLD1 23
12882 #define V_DB_VLD1(x) ((x) << S_DB_VLD1)
12883 #define F_DB_VLD1 V_DB_VLD1(1U)
12885 #define S_DB_GT1 22
12886 #define V_DB_GT1(x) ((x) << S_DB_GT1)
12887 #define F_DB_GT1 V_DB_GT1(1U)
12889 #define S_TXVALID1 21
12890 #define V_TXVALID1(x) ((x) << S_TXVALID1)
12891 #define F_TXVALID1 V_TXVALID1(1U)
12893 #define S_TXFULL1 20
12894 #define V_TXFULL1(x) ((x) << S_TXFULL1)
12895 #define F_TXFULL1 V_TXFULL1(1U)
12897 #define S_PLD_TXVALID1 19
12898 #define V_PLD_TXVALID1(x) ((x) << S_PLD_TXVALID1)
12899 #define F_PLD_TXVALID1 V_PLD_TXVALID1(1U)
12901 #define S_PLD_TXFULL1 18
12902 #define V_PLD_TXFULL1(x) ((x) << S_PLD_TXFULL1)
12903 #define F_PLD_TXFULL1 V_PLD_TXFULL1(1U)
12905 #define S_CPL5_TXVALID1 17
12906 #define V_CPL5_TXVALID1(x) ((x) << S_CPL5_TXVALID1)
12907 #define F_CPL5_TXVALID1 V_CPL5_TXVALID1(1U)
12909 #define S_CPL5_TXFULL1 16
12910 #define V_CPL5_TXFULL1(x) ((x) << S_CPL5_TXFULL1)
12911 #define F_CPL5_TXFULL1 V_CPL5_TXFULL1(1U)
12913 #define S_PLD_RXZEROP_SRDY0 15
12914 #define V_PLD_RXZEROP_SRDY0(x) ((x) << S_PLD_RXZEROP_SRDY0)
12915 #define F_PLD_RXZEROP_SRDY0 V_PLD_RXZEROP_SRDY0(1U)
12917 #define S_PLD_RXZEROP_DRDY0 14
12918 #define V_PLD_RXZEROP_DRDY0(x) ((x) << S_PLD_RXZEROP_DRDY0)
12919 #define F_PLD_RXZEROP_DRDY0 V_PLD_RXZEROP_DRDY0(1U)
12921 #define S_PLD_TXZEROP_SRDY0 13
12922 #define V_PLD_TXZEROP_SRDY0(x) ((x) << S_PLD_TXZEROP_SRDY0)
12923 #define F_PLD_TXZEROP_SRDY0 V_PLD_TXZEROP_SRDY0(1U)
12925 #define S_PLD_TXZEROP_DRDY0 12
12926 #define V_PLD_TXZEROP_DRDY0(x) ((x) << S_PLD_TXZEROP_DRDY0)
12927 #define F_PLD_TXZEROP_DRDY0 V_PLD_TXZEROP_DRDY0(1U)
12929 #define S_PLD_TX_SRDY0 11
12930 #define V_PLD_TX_SRDY0(x) ((x) << S_PLD_TX_SRDY0)
12931 #define F_PLD_TX_SRDY0 V_PLD_TX_SRDY0(1U)
12933 #define S_PLD_TX_DRDY0 10
12934 #define V_PLD_TX_DRDY0(x) ((x) << S_PLD_TX_DRDY0)
12935 #define F_PLD_TX_DRDY0 V_PLD_TX_DRDY0(1U)
12937 #define S_ERROR_SRDY0 9
12938 #define V_ERROR_SRDY0(x) ((x) << S_ERROR_SRDY0)
12939 #define F_ERROR_SRDY0 V_ERROR_SRDY0(1U)
12941 #define S_ERROR_DRDY0 8
12942 #define V_ERROR_DRDY0(x) ((x) << S_ERROR_DRDY0)
12943 #define F_ERROR_DRDY0 V_ERROR_DRDY0(1U)
12945 #define S_DB_VLD0 7
12946 #define V_DB_VLD0(x) ((x) << S_DB_VLD0)
12947 #define F_DB_VLD0 V_DB_VLD0(1U)
12950 #define V_DB_GT0(x) ((x) << S_DB_GT0)
12951 #define F_DB_GT0 V_DB_GT0(1U)
12953 #define S_TXVALID0 5
12954 #define V_TXVALID0(x) ((x) << S_TXVALID0)
12955 #define F_TXVALID0 V_TXVALID0(1U)
12957 #define S_TXFULL0 4
12958 #define V_TXFULL0(x) ((x) << S_TXFULL0)
12959 #define F_TXFULL0 V_TXFULL0(1U)
12961 #define S_PLD_TXVALID0 3
12962 #define V_PLD_TXVALID0(x) ((x) << S_PLD_TXVALID0)
12963 #define F_PLD_TXVALID0 V_PLD_TXVALID0(1U)
12965 #define S_PLD_TXFULL0 2
12966 #define V_PLD_TXFULL0(x) ((x) << S_PLD_TXFULL0)
12967 #define F_PLD_TXFULL0 V_PLD_TXFULL0(1U)
12969 #define S_CPL5_TXVALID0 1
12970 #define V_CPL5_TXVALID0(x) ((x) << S_CPL5_TXVALID0)
12971 #define F_CPL5_TXVALID0 V_CPL5_TXVALID0(1U)
12973 #define S_CPL5_TXFULL0 0
12974 #define V_CPL5_TXFULL0(x) ((x) << S_CPL5_TXFULL0)
12975 #define F_CPL5_TXFULL0 V_CPL5_TXFULL0(1U)
12977 #define A_TP_DBG_CSIDE_FIFO1 0x239
12979 #define S_PLD_RXZEROP_SRDY3 31
12980 #define V_PLD_RXZEROP_SRDY3(x) ((x) << S_PLD_RXZEROP_SRDY3)
12981 #define F_PLD_RXZEROP_SRDY3 V_PLD_RXZEROP_SRDY3(1U)
12983 #define S_PLD_RXZEROP_DRDY3 30
12984 #define V_PLD_RXZEROP_DRDY3(x) ((x) << S_PLD_RXZEROP_DRDY3)
12985 #define F_PLD_RXZEROP_DRDY3 V_PLD_RXZEROP_DRDY3(1U)
12987 #define S_PLD_TXZEROP_SRDY3 29
12988 #define V_PLD_TXZEROP_SRDY3(x) ((x) << S_PLD_TXZEROP_SRDY3)
12989 #define F_PLD_TXZEROP_SRDY3 V_PLD_TXZEROP_SRDY3(1U)
12991 #define S_PLD_TXZEROP_DRDY3 28
12992 #define V_PLD_TXZEROP_DRDY3(x) ((x) << S_PLD_TXZEROP_DRDY3)
12993 #define F_PLD_TXZEROP_DRDY3 V_PLD_TXZEROP_DRDY3(1U)
12995 #define S_PLD_TX_SRDY3 27
12996 #define V_PLD_TX_SRDY3(x) ((x) << S_PLD_TX_SRDY3)
12997 #define F_PLD_TX_SRDY3 V_PLD_TX_SRDY3(1U)
12999 #define S_PLD_TX_DRDY3 26
13000 #define V_PLD_TX_DRDY3(x) ((x) << S_PLD_TX_DRDY3)
13001 #define F_PLD_TX_DRDY3 V_PLD_TX_DRDY3(1U)
13003 #define S_ERROR_SRDY3 25
13004 #define V_ERROR_SRDY3(x) ((x) << S_ERROR_SRDY3)
13005 #define F_ERROR_SRDY3 V_ERROR_SRDY3(1U)
13007 #define S_ERROR_DRDY3 24
13008 #define V_ERROR_DRDY3(x) ((x) << S_ERROR_DRDY3)
13009 #define F_ERROR_DRDY3 V_ERROR_DRDY3(1U)
13011 #define S_DB_VLD3 23
13012 #define V_DB_VLD3(x) ((x) << S_DB_VLD3)
13013 #define F_DB_VLD3 V_DB_VLD3(1U)
13015 #define S_DB_GT3 22
13016 #define V_DB_GT3(x) ((x) << S_DB_GT3)
13017 #define F_DB_GT3 V_DB_GT3(1U)
13019 #define S_TXVALID3 21
13020 #define V_TXVALID3(x) ((x) << S_TXVALID3)
13021 #define F_TXVALID3 V_TXVALID3(1U)
13023 #define S_TXFULL3 20
13024 #define V_TXFULL3(x) ((x) << S_TXFULL3)
13025 #define F_TXFULL3 V_TXFULL3(1U)
13027 #define S_PLD_TXVALID3 19
13028 #define V_PLD_TXVALID3(x) ((x) << S_PLD_TXVALID3)
13029 #define F_PLD_TXVALID3 V_PLD_TXVALID3(1U)
13031 #define S_PLD_TXFULL3 18
13032 #define V_PLD_TXFULL3(x) ((x) << S_PLD_TXFULL3)
13033 #define F_PLD_TXFULL3 V_PLD_TXFULL3(1U)
13035 #define S_CPL5_TXVALID3 17
13036 #define V_CPL5_TXVALID3(x) ((x) << S_CPL5_TXVALID3)
13037 #define F_CPL5_TXVALID3 V_CPL5_TXVALID3(1U)
13039 #define S_CPL5_TXFULL3 16
13040 #define V_CPL5_TXFULL3(x) ((x) << S_CPL5_TXFULL3)
13041 #define F_CPL5_TXFULL3 V_CPL5_TXFULL3(1U)
13043 #define S_PLD_RXZEROP_SRDY2 15
13044 #define V_PLD_RXZEROP_SRDY2(x) ((x) << S_PLD_RXZEROP_SRDY2)
13045 #define F_PLD_RXZEROP_SRDY2 V_PLD_RXZEROP_SRDY2(1U)
13047 #define S_PLD_RXZEROP_DRDY2 14
13048 #define V_PLD_RXZEROP_DRDY2(x) ((x) << S_PLD_RXZEROP_DRDY2)
13049 #define F_PLD_RXZEROP_DRDY2 V_PLD_RXZEROP_DRDY2(1U)
13051 #define S_PLD_TXZEROP_SRDY2 13
13052 #define V_PLD_TXZEROP_SRDY2(x) ((x) << S_PLD_TXZEROP_SRDY2)
13053 #define F_PLD_TXZEROP_SRDY2 V_PLD_TXZEROP_SRDY2(1U)
13055 #define S_PLD_TXZEROP_DRDY2 12
13056 #define V_PLD_TXZEROP_DRDY2(x) ((x) << S_PLD_TXZEROP_DRDY2)
13057 #define F_PLD_TXZEROP_DRDY2 V_PLD_TXZEROP_DRDY2(1U)
13059 #define S_PLD_TX_SRDY2 11
13060 #define V_PLD_TX_SRDY2(x) ((x) << S_PLD_TX_SRDY2)
13061 #define F_PLD_TX_SRDY2 V_PLD_TX_SRDY2(1U)
13063 #define S_PLD_TX_DRDY2 10
13064 #define V_PLD_TX_DRDY2(x) ((x) << S_PLD_TX_DRDY2)
13065 #define F_PLD_TX_DRDY2 V_PLD_TX_DRDY2(1U)
13067 #define S_ERROR_SRDY2 9
13068 #define V_ERROR_SRDY2(x) ((x) << S_ERROR_SRDY2)
13069 #define F_ERROR_SRDY2 V_ERROR_SRDY2(1U)
13071 #define S_ERROR_DRDY2 8
13072 #define V_ERROR_DRDY2(x) ((x) << S_ERROR_DRDY2)
13073 #define F_ERROR_DRDY2 V_ERROR_DRDY2(1U)
13075 #define S_DB_VLD2 7
13076 #define V_DB_VLD2(x) ((x) << S_DB_VLD2)
13077 #define F_DB_VLD2 V_DB_VLD2(1U)
13080 #define V_DB_GT2(x) ((x) << S_DB_GT2)
13081 #define F_DB_GT2 V_DB_GT2(1U)
13083 #define S_TXVALID2 5
13084 #define V_TXVALID2(x) ((x) << S_TXVALID2)
13085 #define F_TXVALID2 V_TXVALID2(1U)
13087 #define S_TXFULL2 4
13088 #define V_TXFULL2(x) ((x) << S_TXFULL2)
13089 #define F_TXFULL2 V_TXFULL2(1U)
13091 #define S_PLD_TXVALID2 3
13092 #define V_PLD_TXVALID2(x) ((x) << S_PLD_TXVALID2)
13093 #define F_PLD_TXVALID2 V_PLD_TXVALID2(1U)
13095 #define S_PLD_TXFULL2 2
13096 #define V_PLD_TXFULL2(x) ((x) << S_PLD_TXFULL2)
13097 #define F_PLD_TXFULL2 V_PLD_TXFULL2(1U)
13099 #define S_CPL5_TXVALID2 1
13100 #define V_CPL5_TXVALID2(x) ((x) << S_CPL5_TXVALID2)
13101 #define F_CPL5_TXVALID2 V_CPL5_TXVALID2(1U)
13103 #define S_CPL5_TXFULL2 0
13104 #define V_CPL5_TXFULL2(x) ((x) << S_CPL5_TXFULL2)
13105 #define F_CPL5_TXFULL2 V_CPL5_TXFULL2(1U)
13107 #define A_TP_DBG_CSIDE_DISP0 0x23a
13109 #define S_CPL5RXVALID 27
13110 #define V_CPL5RXVALID(x) ((x) << S_CPL5RXVALID)
13111 #define F_CPL5RXVALID V_CPL5RXVALID(1U)
13113 #define S_CSTATIC1 26
13114 #define V_CSTATIC1(x) ((x) << S_CSTATIC1)
13115 #define F_CSTATIC1 V_CSTATIC1(1U)
13117 #define S_CSTATIC2 25
13118 #define V_CSTATIC2(x) ((x) << S_CSTATIC2)
13119 #define F_CSTATIC2 V_CSTATIC2(1U)
13121 #define S_PLD_RXZEROP 24
13122 #define V_PLD_RXZEROP(x) ((x) << S_PLD_RXZEROP)
13123 #define F_PLD_RXZEROP V_PLD_RXZEROP(1U)
13125 #define S_DDP_IN_PROGRESS 23
13126 #define V_DDP_IN_PROGRESS(x) ((x) << S_DDP_IN_PROGRESS)
13127 #define F_DDP_IN_PROGRESS V_DDP_IN_PROGRESS(1U)
13129 #define S_PLD_RXZEROP_SRDY 22
13130 #define V_PLD_RXZEROP_SRDY(x) ((x) << S_PLD_RXZEROP_SRDY)
13131 #define F_PLD_RXZEROP_SRDY V_PLD_RXZEROP_SRDY(1U)
13133 #define S_CSTATIC3 21
13134 #define V_CSTATIC3(x) ((x) << S_CSTATIC3)
13135 #define F_CSTATIC3 V_CSTATIC3(1U)
13137 #define S_DDP_DRDY 20
13138 #define V_DDP_DRDY(x) ((x) << S_DDP_DRDY)
13139 #define F_DDP_DRDY V_DDP_DRDY(1U)
13141 #define S_DDP_PRE_STATE 17
13142 #define M_DDP_PRE_STATE 0x7U
13143 #define V_DDP_PRE_STATE(x) ((x) << S_DDP_PRE_STATE)
13144 #define G_DDP_PRE_STATE(x) (((x) >> S_DDP_PRE_STATE) & M_DDP_PRE_STATE)
13146 #define S_DDP_SRDY 16
13147 #define V_DDP_SRDY(x) ((x) << S_DDP_SRDY)
13148 #define F_DDP_SRDY V_DDP_SRDY(1U)
13150 #define S_DDP_MSG_CODE 12
13151 #define M_DDP_MSG_CODE 0xfU
13152 #define V_DDP_MSG_CODE(x) ((x) << S_DDP_MSG_CODE)
13153 #define G_DDP_MSG_CODE(x) (((x) >> S_DDP_MSG_CODE) & M_DDP_MSG_CODE)
13155 #define S_CPL5_SOCP_CNT 10
13156 #define M_CPL5_SOCP_CNT 0x3U
13157 #define V_CPL5_SOCP_CNT(x) ((x) << S_CPL5_SOCP_CNT)
13158 #define G_CPL5_SOCP_CNT(x) (((x) >> S_CPL5_SOCP_CNT) & M_CPL5_SOCP_CNT)
13160 #define S_CSTATIC4 4
13161 #define M_CSTATIC4 0x3fU
13162 #define V_CSTATIC4(x) ((x) << S_CSTATIC4)
13163 #define G_CSTATIC4(x) (((x) >> S_CSTATIC4) & M_CSTATIC4)
13165 #define S_CMD_SEL 1
13166 #define V_CMD_SEL(x) ((x) << S_CMD_SEL)
13167 #define F_CMD_SEL V_CMD_SEL(1U)
13169 #define A_TP_DBG_CSIDE_DISP1 0x23b
13170 #define A_TP_DBG_CSIDE_DDP0 0x23c
13172 #define S_DDPMSGLATEST7 28
13173 #define M_DDPMSGLATEST7 0xfU
13174 #define V_DDPMSGLATEST7(x) ((x) << S_DDPMSGLATEST7)
13175 #define G_DDPMSGLATEST7(x) (((x) >> S_DDPMSGLATEST7) & M_DDPMSGLATEST7)
13177 #define S_DDPMSGLATEST6 24
13178 #define M_DDPMSGLATEST6 0xfU
13179 #define V_DDPMSGLATEST6(x) ((x) << S_DDPMSGLATEST6)
13180 #define G_DDPMSGLATEST6(x) (((x) >> S_DDPMSGLATEST6) & M_DDPMSGLATEST6)
13182 #define S_DDPMSGLATEST5 20
13183 #define M_DDPMSGLATEST5 0xfU
13184 #define V_DDPMSGLATEST5(x) ((x) << S_DDPMSGLATEST5)
13185 #define G_DDPMSGLATEST5(x) (((x) >> S_DDPMSGLATEST5) & M_DDPMSGLATEST5)
13187 #define S_DDPMSGLATEST4 16
13188 #define M_DDPMSGLATEST4 0xfU
13189 #define V_DDPMSGLATEST4(x) ((x) << S_DDPMSGLATEST4)
13190 #define G_DDPMSGLATEST4(x) (((x) >> S_DDPMSGLATEST4) & M_DDPMSGLATEST4)
13192 #define S_DDPMSGLATEST3 12
13193 #define M_DDPMSGLATEST3 0xfU
13194 #define V_DDPMSGLATEST3(x) ((x) << S_DDPMSGLATEST3)
13195 #define G_DDPMSGLATEST3(x) (((x) >> S_DDPMSGLATEST3) & M_DDPMSGLATEST3)
13197 #define S_DDPMSGLATEST2 8
13198 #define M_DDPMSGLATEST2 0xfU
13199 #define V_DDPMSGLATEST2(x) ((x) << S_DDPMSGLATEST2)
13200 #define G_DDPMSGLATEST2(x) (((x) >> S_DDPMSGLATEST2) & M_DDPMSGLATEST2)
13202 #define S_DDPMSGLATEST1 4
13203 #define M_DDPMSGLATEST1 0xfU
13204 #define V_DDPMSGLATEST1(x) ((x) << S_DDPMSGLATEST1)
13205 #define G_DDPMSGLATEST1(x) (((x) >> S_DDPMSGLATEST1) & M_DDPMSGLATEST1)
13207 #define S_DDPMSGLATEST0 0
13208 #define M_DDPMSGLATEST0 0xfU
13209 #define V_DDPMSGLATEST0(x) ((x) << S_DDPMSGLATEST0)
13210 #define G_DDPMSGLATEST0(x) (((x) >> S_DDPMSGLATEST0) & M_DDPMSGLATEST0)
13212 #define A_TP_DBG_CSIDE_DDP1 0x23d
13213 #define A_TP_DBG_CSIDE_FRM 0x23e
13215 #define S_CRX2XERROR 28
13216 #define M_CRX2XERROR 0xfU
13217 #define V_CRX2XERROR(x) ((x) << S_CRX2XERROR)
13218 #define G_CRX2XERROR(x) (((x) >> S_CRX2XERROR) & M_CRX2XERROR)
13220 #define S_CPLDTX2XERROR 24
13221 #define M_CPLDTX2XERROR 0xfU
13222 #define V_CPLDTX2XERROR(x) ((x) << S_CPLDTX2XERROR)
13223 #define G_CPLDTX2XERROR(x) (((x) >> S_CPLDTX2XERROR) & M_CPLDTX2XERROR)
13225 #define S_CTXERROR 22
13226 #define M_CTXERROR 0x3U
13227 #define V_CTXERROR(x) ((x) << S_CTXERROR)
13228 #define G_CTXERROR(x) (((x) >> S_CTXERROR) & M_CTXERROR)
13230 #define S_CPLDRXERROR 20
13231 #define M_CPLDRXERROR 0x3U
13232 #define V_CPLDRXERROR(x) ((x) << S_CPLDRXERROR)
13233 #define G_CPLDRXERROR(x) (((x) >> S_CPLDRXERROR) & M_CPLDRXERROR)
13235 #define S_CPLRXERROR 18
13236 #define M_CPLRXERROR 0x3U
13237 #define V_CPLRXERROR(x) ((x) << S_CPLRXERROR)
13238 #define G_CPLRXERROR(x) (((x) >> S_CPLRXERROR) & M_CPLRXERROR)
13240 #define S_CPLTXERROR 16
13241 #define M_CPLTXERROR 0x3U
13242 #define V_CPLTXERROR(x) ((x) << S_CPLTXERROR)
13243 #define G_CPLTXERROR(x) (((x) >> S_CPLTXERROR) & M_CPLTXERROR)
13245 #define S_CPRSERROR 0
13246 #define M_CPRSERROR 0xfU
13247 #define V_CPRSERROR(x) ((x) << S_CPRSERROR)
13248 #define G_CPRSERROR(x) (((x) >> S_CPRSERROR) & M_CPRSERROR)
13250 #define A_TP_DBG_CSIDE_INT 0x23f
13252 #define S_CRXVALID2X 28
13253 #define M_CRXVALID2X 0xfU
13254 #define V_CRXVALID2X(x) ((x) << S_CRXVALID2X)
13255 #define G_CRXVALID2X(x) (((x) >> S_CRXVALID2X) & M_CRXVALID2X)
13257 #define S_CRXAFULL2X 24
13258 #define M_CRXAFULL2X 0xfU
13259 #define V_CRXAFULL2X(x) ((x) << S_CRXAFULL2X)
13260 #define G_CRXAFULL2X(x) (((x) >> S_CRXAFULL2X) & M_CRXAFULL2X)
13262 #define S_CTXVALID2X 22
13263 #define M_CTXVALID2X 0x3U
13264 #define V_CTXVALID2X(x) ((x) << S_CTXVALID2X)
13265 #define G_CTXVALID2X(x) (((x) >> S_CTXVALID2X) & M_CTXVALID2X)
13267 #define S_CTXAFULL2X 20
13268 #define M_CTXAFULL2X 0x3U
13269 #define V_CTXAFULL2X(x) ((x) << S_CTXAFULL2X)
13270 #define G_CTXAFULL2X(x) (((x) >> S_CTXAFULL2X) & M_CTXAFULL2X)
13272 #define S_PLD2X_RXVALID 18
13273 #define M_PLD2X_RXVALID 0x3U
13274 #define V_PLD2X_RXVALID(x) ((x) << S_PLD2X_RXVALID)
13275 #define G_PLD2X_RXVALID(x) (((x) >> S_PLD2X_RXVALID) & M_PLD2X_RXVALID)
13277 #define S_PLD2X_RXAFULL 16
13278 #define M_PLD2X_RXAFULL 0x3U
13279 #define V_PLD2X_RXAFULL(x) ((x) << S_PLD2X_RXAFULL)
13280 #define G_PLD2X_RXAFULL(x) (((x) >> S_PLD2X_RXAFULL) & M_PLD2X_RXAFULL)
13282 #define S_CSIDE_DDP_VALID 14
13283 #define M_CSIDE_DDP_VALID 0x3U
13284 #define V_CSIDE_DDP_VALID(x) ((x) << S_CSIDE_DDP_VALID)
13285 #define G_CSIDE_DDP_VALID(x) (((x) >> S_CSIDE_DDP_VALID) & M_CSIDE_DDP_VALID)
13287 #define S_DDP_AFULL 12
13288 #define M_DDP_AFULL 0x3U
13289 #define V_DDP_AFULL(x) ((x) << S_DDP_AFULL)
13290 #define G_DDP_AFULL(x) (((x) >> S_DDP_AFULL) & M_DDP_AFULL)
13292 #define S_TRC_RXVALID 11
13293 #define V_TRC_RXVALID(x) ((x) << S_TRC_RXVALID)
13294 #define F_TRC_RXVALID V_TRC_RXVALID(1U)
13296 #define S_TRC_RXFULL 10
13297 #define V_TRC_RXFULL(x) ((x) << S_TRC_RXFULL)
13298 #define F_TRC_RXFULL V_TRC_RXFULL(1U)
13300 #define S_CPL5_TXVALID 9
13301 #define V_CPL5_TXVALID(x) ((x) << S_CPL5_TXVALID)
13302 #define F_CPL5_TXVALID V_CPL5_TXVALID(1U)
13304 #define S_CPL5_TXFULL 8
13305 #define V_CPL5_TXFULL(x) ((x) << S_CPL5_TXFULL)
13306 #define F_CPL5_TXFULL V_CPL5_TXFULL(1U)
13308 #define S_PLD2X_TXVALID 4
13309 #define M_PLD2X_TXVALID 0xfU
13310 #define V_PLD2X_TXVALID(x) ((x) << S_PLD2X_TXVALID)
13311 #define G_PLD2X_TXVALID(x) (((x) >> S_PLD2X_TXVALID) & M_PLD2X_TXVALID)
13313 #define S_PLD2X_TXAFULL 0
13314 #define M_PLD2X_TXAFULL 0xfU
13315 #define V_PLD2X_TXAFULL(x) ((x) << S_PLD2X_TXAFULL)
13316 #define G_PLD2X_TXAFULL(x) (((x) >> S_PLD2X_TXAFULL) & M_PLD2X_TXAFULL)
13318 #define A_TP_CHDR_CONFIG 0x240
13320 #define S_CH1HIGH 24
13321 #define M_CH1HIGH 0xffU
13322 #define V_CH1HIGH(x) ((x) << S_CH1HIGH)
13323 #define G_CH1HIGH(x) (((x) >> S_CH1HIGH) & M_CH1HIGH)
13325 #define S_CH1LOW 16
13326 #define M_CH1LOW 0xffU
13327 #define V_CH1LOW(x) ((x) << S_CH1LOW)
13328 #define G_CH1LOW(x) (((x) >> S_CH1LOW) & M_CH1LOW)
13330 #define S_CH0HIGH 8
13331 #define M_CH0HIGH 0xffU
13332 #define V_CH0HIGH(x) ((x) << S_CH0HIGH)
13333 #define G_CH0HIGH(x) (((x) >> S_CH0HIGH) & M_CH0HIGH)
13336 #define M_CH0LOW 0xffU
13337 #define V_CH0LOW(x) ((x) << S_CH0LOW)
13338 #define G_CH0LOW(x) (((x) >> S_CH0LOW) & M_CH0LOW)
13340 #define A_TP_UTRN_CONFIG 0x241
13342 #define S_CH2FIFOLIMIT 16
13343 #define M_CH2FIFOLIMIT 0xffU
13344 #define V_CH2FIFOLIMIT(x) ((x) << S_CH2FIFOLIMIT)
13345 #define G_CH2FIFOLIMIT(x) (((x) >> S_CH2FIFOLIMIT) & M_CH2FIFOLIMIT)
13347 #define S_CH1FIFOLIMIT 8
13348 #define M_CH1FIFOLIMIT 0xffU
13349 #define V_CH1FIFOLIMIT(x) ((x) << S_CH1FIFOLIMIT)
13350 #define G_CH1FIFOLIMIT(x) (((x) >> S_CH1FIFOLIMIT) & M_CH1FIFOLIMIT)
13352 #define S_CH0FIFOLIMIT 0
13353 #define M_CH0FIFOLIMIT 0xffU
13354 #define V_CH0FIFOLIMIT(x) ((x) << S_CH0FIFOLIMIT)
13355 #define G_CH0FIFOLIMIT(x) (((x) >> S_CH0FIFOLIMIT) & M_CH0FIFOLIMIT)
13357 #define A_TP_CDSP_CONFIG 0x242
13359 #define S_WRITEZEROEN 4
13360 #define V_WRITEZEROEN(x) ((x) << S_WRITEZEROEN)
13361 #define F_WRITEZEROEN V_WRITEZEROEN(1U)
13363 #define S_WRITEZEROOP 0
13364 #define M_WRITEZEROOP 0xfU
13365 #define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP)
13366 #define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP)
13368 #define A_TP_TRC_CONFIG 0x244
13371 #define V_TRCRR(x) ((x) << S_TRCRR)
13372 #define F_TRCRR V_TRCRR(1U)
13375 #define V_TRCCH(x) ((x) << S_TRCCH)
13376 #define F_TRCCH V_TRCCH(1U)
13378 #define A_TP_TAG_CONFIG 0x245
13380 #define S_ETAGTYPE 16
13381 #define M_ETAGTYPE 0xffffU
13382 #define V_ETAGTYPE(x) ((x) << S_ETAGTYPE)
13383 #define G_ETAGTYPE(x) (((x) >> S_ETAGTYPE) & M_ETAGTYPE)
13385 #define A_TP_DBG_CSIDE_PRS 0x246
13387 #define S_CPRSSTATE3 24
13388 #define M_CPRSSTATE3 0x7U
13389 #define V_CPRSSTATE3(x) ((x) << S_CPRSSTATE3)
13390 #define G_CPRSSTATE3(x) (((x) >> S_CPRSSTATE3) & M_CPRSSTATE3)
13392 #define S_CPRSSTATE2 16
13393 #define M_CPRSSTATE2 0x7U
13394 #define V_CPRSSTATE2(x) ((x) << S_CPRSSTATE2)
13395 #define G_CPRSSTATE2(x) (((x) >> S_CPRSSTATE2) & M_CPRSSTATE2)
13397 #define S_CPRSSTATE1 8
13398 #define M_CPRSSTATE1 0x7U
13399 #define V_CPRSSTATE1(x) ((x) << S_CPRSSTATE1)
13400 #define G_CPRSSTATE1(x) (((x) >> S_CPRSSTATE1) & M_CPRSSTATE1)
13402 #define S_CPRSSTATE0 0
13403 #define M_CPRSSTATE0 0x7U
13404 #define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0)
13405 #define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0)
13407 #define A_TP_DBG_CSIDE_DEMUX 0x247
13409 #define S_CALLDONE 28
13410 #define M_CALLDONE 0xfU
13411 #define V_CALLDONE(x) ((x) << S_CALLDONE)
13412 #define G_CALLDONE(x) (((x) >> S_CALLDONE) & M_CALLDONE)
13414 #define S_CTCPL5DONE 24
13415 #define M_CTCPL5DONE 0xfU
13416 #define V_CTCPL5DONE(x) ((x) << S_CTCPL5DONE)
13417 #define G_CTCPL5DONE(x) (((x) >> S_CTCPL5DONE) & M_CTCPL5DONE)
13419 #define S_CTXZEROPDONE 20
13420 #define M_CTXZEROPDONE 0xfU
13421 #define V_CTXZEROPDONE(x) ((x) << S_CTXZEROPDONE)
13422 #define G_CTXZEROPDONE(x) (((x) >> S_CTXZEROPDONE) & M_CTXZEROPDONE)
13424 #define S_CPLDDONE 16
13425 #define M_CPLDDONE 0xfU
13426 #define V_CPLDDONE(x) ((x) << S_CPLDDONE)
13427 #define G_CPLDDONE(x) (((x) >> S_CPLDDONE) & M_CPLDDONE)
13429 #define S_CTTCPOPDONE 12
13430 #define M_CTTCPOPDONE 0xfU
13431 #define V_CTTCPOPDONE(x) ((x) << S_CTTCPOPDONE)
13432 #define G_CTTCPOPDONE(x) (((x) >> S_CTTCPOPDONE) & M_CTTCPOPDONE)
13434 #define S_CDBDONE 8
13435 #define M_CDBDONE 0xfU
13436 #define V_CDBDONE(x) ((x) << S_CDBDONE)
13437 #define G_CDBDONE(x) (((x) >> S_CDBDONE) & M_CDBDONE)
13439 #define S_CISSFIFODONE 4
13440 #define M_CISSFIFODONE 0xfU
13441 #define V_CISSFIFODONE(x) ((x) << S_CISSFIFODONE)
13442 #define G_CISSFIFODONE(x) (((x) >> S_CISSFIFODONE) & M_CISSFIFODONE)
13444 #define S_CTXPKTCSUMDONE 0
13445 #define M_CTXPKTCSUMDONE 0xfU
13446 #define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE)
13447 #define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE)
13449 #define A_TP_FIFO_CONFIG 0x8c0
13451 #define S_CH1_OUTPUT 27
13452 #define M_CH1_OUTPUT 0x1fU
13453 #define V_CH1_OUTPUT(x) ((x) << S_CH1_OUTPUT)
13454 #define G_CH1_OUTPUT(x) (((x) >> S_CH1_OUTPUT) & M_CH1_OUTPUT)
13456 #define S_CH2_OUTPUT 22
13457 #define M_CH2_OUTPUT 0x1fU
13458 #define V_CH2_OUTPUT(x) ((x) << S_CH2_OUTPUT)
13459 #define G_CH2_OUTPUT(x) (((x) >> S_CH2_OUTPUT) & M_CH2_OUTPUT)
13461 #define S_STROBE1 16
13462 #define V_STROBE1(x) ((x) << S_STROBE1)
13463 #define F_STROBE1 V_STROBE1(1U)
13465 #define S_CH1_INPUT 11
13466 #define M_CH1_INPUT 0x1fU
13467 #define V_CH1_INPUT(x) ((x) << S_CH1_INPUT)
13468 #define G_CH1_INPUT(x) (((x) >> S_CH1_INPUT) & M_CH1_INPUT)
13470 #define S_CH2_INPUT 6
13471 #define M_CH2_INPUT 0x1fU
13472 #define V_CH2_INPUT(x) ((x) << S_CH2_INPUT)
13473 #define G_CH2_INPUT(x) (((x) >> S_CH2_INPUT) & M_CH2_INPUT)
13475 #define S_CH3_INPUT 1
13476 #define M_CH3_INPUT 0x1fU
13477 #define V_CH3_INPUT(x) ((x) << S_CH3_INPUT)
13478 #define G_CH3_INPUT(x) (((x) >> S_CH3_INPUT) & M_CH3_INPUT)
13480 #define S_STROBE0 0
13481 #define V_STROBE0(x) ((x) << S_STROBE0)
13482 #define F_STROBE0 V_STROBE0(1U)
13484 #define A_TP_MIB_MAC_IN_ERR_0 0x0
13485 #define A_TP_MIB_MAC_IN_ERR_1 0x1
13486 #define A_TP_MIB_MAC_IN_ERR_2 0x2
13487 #define A_TP_MIB_MAC_IN_ERR_3 0x3
13488 #define A_TP_MIB_HDR_IN_ERR_0 0x4
13489 #define A_TP_MIB_HDR_IN_ERR_1 0x5
13490 #define A_TP_MIB_HDR_IN_ERR_2 0x6
13491 #define A_TP_MIB_HDR_IN_ERR_3 0x7
13492 #define A_TP_MIB_TCP_IN_ERR_0 0x8
13493 #define A_TP_MIB_TCP_IN_ERR_1 0x9
13494 #define A_TP_MIB_TCP_IN_ERR_2 0xa
13495 #define A_TP_MIB_TCP_IN_ERR_3 0xb
13496 #define A_TP_MIB_TCP_OUT_RST 0xc
13497 #define A_TP_MIB_TCP_IN_SEG_HI 0x10
13498 #define A_TP_MIB_TCP_IN_SEG_LO 0x11
13499 #define A_TP_MIB_TCP_OUT_SEG_HI 0x12
13500 #define A_TP_MIB_TCP_OUT_SEG_LO 0x13
13501 #define A_TP_MIB_TCP_RXT_SEG_HI 0x14
13502 #define A_TP_MIB_TCP_RXT_SEG_LO 0x15
13503 #define A_TP_MIB_TNL_CNG_DROP_0 0x18
13504 #define A_TP_MIB_TNL_CNG_DROP_1 0x19
13505 #define A_TP_MIB_TNL_CNG_DROP_2 0x1a
13506 #define A_TP_MIB_TNL_CNG_DROP_3 0x1b
13507 #define A_TP_MIB_OFD_CHN_DROP_0 0x1c
13508 #define A_TP_MIB_OFD_CHN_DROP_1 0x1d
13509 #define A_TP_MIB_OFD_CHN_DROP_2 0x1e
13510 #define A_TP_MIB_OFD_CHN_DROP_3 0x1f
13511 #define A_TP_MIB_TNL_OUT_PKT_0 0x20
13512 #define A_TP_MIB_TNL_OUT_PKT_1 0x21
13513 #define A_TP_MIB_TNL_OUT_PKT_2 0x22
13514 #define A_TP_MIB_TNL_OUT_PKT_3 0x23
13515 #define A_TP_MIB_TNL_IN_PKT_0 0x24
13516 #define A_TP_MIB_TNL_IN_PKT_1 0x25
13517 #define A_TP_MIB_TNL_IN_PKT_2 0x26
13518 #define A_TP_MIB_TNL_IN_PKT_3 0x27
13519 #define A_TP_MIB_TCP_V6IN_ERR_0 0x28
13520 #define A_TP_MIB_TCP_V6IN_ERR_1 0x29
13521 #define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
13522 #define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
13523 #define A_TP_MIB_TCP_V6OUT_RST 0x2c
13524 #define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
13525 #define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
13526 #define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
13527 #define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
13528 #define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
13529 #define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
13530 #define A_TP_MIB_OFD_ARP_DROP 0x36
13531 #define A_TP_MIB_OFD_DFR_DROP 0x37
13532 #define A_TP_MIB_CPL_IN_REQ_0 0x38
13533 #define A_TP_MIB_CPL_IN_REQ_1 0x39
13534 #define A_TP_MIB_CPL_IN_REQ_2 0x3a
13535 #define A_TP_MIB_CPL_IN_REQ_3 0x3b
13536 #define A_TP_MIB_CPL_OUT_RSP_0 0x3c
13537 #define A_TP_MIB_CPL_OUT_RSP_1 0x3d
13538 #define A_TP_MIB_CPL_OUT_RSP_2 0x3e
13539 #define A_TP_MIB_CPL_OUT_RSP_3 0x3f
13540 #define A_TP_MIB_TNL_LPBK_0 0x40
13541 #define A_TP_MIB_TNL_LPBK_1 0x41
13542 #define A_TP_MIB_TNL_LPBK_2 0x42
13543 #define A_TP_MIB_TNL_LPBK_3 0x43
13544 #define A_TP_MIB_TNL_DROP_0 0x44
13545 #define A_TP_MIB_TNL_DROP_1 0x45
13546 #define A_TP_MIB_TNL_DROP_2 0x46
13547 #define A_TP_MIB_TNL_DROP_3 0x47
13548 #define A_TP_MIB_FCOE_DDP_0 0x48
13549 #define A_TP_MIB_FCOE_DDP_1 0x49
13550 #define A_TP_MIB_FCOE_DDP_2 0x4a
13551 #define A_TP_MIB_FCOE_DDP_3 0x4b
13552 #define A_TP_MIB_FCOE_DROP_0 0x4c
13553 #define A_TP_MIB_FCOE_DROP_1 0x4d
13554 #define A_TP_MIB_FCOE_DROP_2 0x4e
13555 #define A_TP_MIB_FCOE_DROP_3 0x4f
13556 #define A_TP_MIB_FCOE_BYTE_0_HI 0x50
13557 #define A_TP_MIB_FCOE_BYTE_0_LO 0x51
13558 #define A_TP_MIB_FCOE_BYTE_1_HI 0x52
13559 #define A_TP_MIB_FCOE_BYTE_1_LO 0x53
13560 #define A_TP_MIB_FCOE_BYTE_2_HI 0x54
13561 #define A_TP_MIB_FCOE_BYTE_2_LO 0x55
13562 #define A_TP_MIB_FCOE_BYTE_3_HI 0x56
13563 #define A_TP_MIB_FCOE_BYTE_3_LO 0x57
13564 #define A_TP_MIB_OFD_VLN_DROP_0 0x58
13565 #define A_TP_MIB_OFD_VLN_DROP_1 0x59
13566 #define A_TP_MIB_OFD_VLN_DROP_2 0x5a
13567 #define A_TP_MIB_OFD_VLN_DROP_3 0x5b
13568 #define A_TP_MIB_USM_PKTS 0x5c
13569 #define A_TP_MIB_USM_DROP 0x5d
13570 #define A_TP_MIB_USM_BYTES_HI 0x5e
13571 #define A_TP_MIB_USM_BYTES_LO 0x5f
13572 #define A_TP_MIB_TID_DEL 0x60
13573 #define A_TP_MIB_TID_INV 0x61
13574 #define A_TP_MIB_TID_ACT 0x62
13575 #define A_TP_MIB_TID_PAS 0x63
13576 #define A_TP_MIB_RQE_DFR_MOD 0x64
13577 #define A_TP_MIB_RQE_DFR_PKT 0x65
13578 #define A_TP_MIB_CPL_OUT_ERR_0 0x68
13579 #define A_TP_MIB_CPL_OUT_ERR_1 0x69
13580 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a
13581 #define A_TP_MIB_CPL_OUT_ERR_3 0x6b
13583 /* registers for module ULP_TX */
13584 #define ULP_TX_BASE_ADDR 0x8dc0
13586 #define A_ULP_TX_CONFIG 0x8dc0
13588 #define S_STAG_MIX_ENABLE 2
13589 #define V_STAG_MIX_ENABLE(x) ((x) << S_STAG_MIX_ENABLE)
13590 #define F_STAG_MIX_ENABLE V_STAG_MIX_ENABLE(1U)
13592 #define S_STAGF_FIX_DISABLE 1
13593 #define V_STAGF_FIX_DISABLE(x) ((x) << S_STAGF_FIX_DISABLE)
13594 #define F_STAGF_FIX_DISABLE V_STAGF_FIX_DISABLE(1U)
13596 #define S_EXTRA_TAG_INSERTION_ENABLE 0
13597 #define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE)
13598 #define F_EXTRA_TAG_INSERTION_ENABLE V_EXTRA_TAG_INSERTION_ENABLE(1U)
13600 #define A_ULP_TX_PERR_INJECT 0x8dc4
13601 #define A_ULP_TX_INT_ENABLE 0x8dc8
13603 #define S_PBL_BOUND_ERR_CH3 31
13604 #define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3)
13605 #define F_PBL_BOUND_ERR_CH3 V_PBL_BOUND_ERR_CH3(1U)
13607 #define S_PBL_BOUND_ERR_CH2 30
13608 #define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2)
13609 #define F_PBL_BOUND_ERR_CH2 V_PBL_BOUND_ERR_CH2(1U)
13611 #define S_PBL_BOUND_ERR_CH1 29
13612 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
13613 #define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U)
13615 #define S_PBL_BOUND_ERR_CH0 28
13616 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
13617 #define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U)
13619 #define S_SGE2ULP_FIFO_PERR_SET3 27
13620 #define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3)
13621 #define F_SGE2ULP_FIFO_PERR_SET3 V_SGE2ULP_FIFO_PERR_SET3(1U)
13623 #define S_SGE2ULP_FIFO_PERR_SET2 26
13624 #define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2)
13625 #define F_SGE2ULP_FIFO_PERR_SET2 V_SGE2ULP_FIFO_PERR_SET2(1U)
13627 #define S_SGE2ULP_FIFO_PERR_SET1 25
13628 #define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1)
13629 #define F_SGE2ULP_FIFO_PERR_SET1 V_SGE2ULP_FIFO_PERR_SET1(1U)
13631 #define S_SGE2ULP_FIFO_PERR_SET0 24
13632 #define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0)
13633 #define F_SGE2ULP_FIFO_PERR_SET0 V_SGE2ULP_FIFO_PERR_SET0(1U)
13635 #define S_CIM2ULP_FIFO_PERR_SET3 23
13636 #define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3)
13637 #define F_CIM2ULP_FIFO_PERR_SET3 V_CIM2ULP_FIFO_PERR_SET3(1U)
13639 #define S_CIM2ULP_FIFO_PERR_SET2 22
13640 #define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2)
13641 #define F_CIM2ULP_FIFO_PERR_SET2 V_CIM2ULP_FIFO_PERR_SET2(1U)
13643 #define S_CIM2ULP_FIFO_PERR_SET1 21
13644 #define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1)
13645 #define F_CIM2ULP_FIFO_PERR_SET1 V_CIM2ULP_FIFO_PERR_SET1(1U)
13647 #define S_CIM2ULP_FIFO_PERR_SET0 20
13648 #define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0)
13649 #define F_CIM2ULP_FIFO_PERR_SET0 V_CIM2ULP_FIFO_PERR_SET0(1U)
13651 #define S_CQE_FIFO_PERR_SET3 19
13652 #define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3)
13653 #define F_CQE_FIFO_PERR_SET3 V_CQE_FIFO_PERR_SET3(1U)
13655 #define S_CQE_FIFO_PERR_SET2 18
13656 #define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2)
13657 #define F_CQE_FIFO_PERR_SET2 V_CQE_FIFO_PERR_SET2(1U)
13659 #define S_CQE_FIFO_PERR_SET1 17
13660 #define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1)
13661 #define F_CQE_FIFO_PERR_SET1 V_CQE_FIFO_PERR_SET1(1U)
13663 #define S_CQE_FIFO_PERR_SET0 16
13664 #define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0)
13665 #define F_CQE_FIFO_PERR_SET0 V_CQE_FIFO_PERR_SET0(1U)
13667 #define S_PBL_FIFO_PERR_SET3 15
13668 #define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3)
13669 #define F_PBL_FIFO_PERR_SET3 V_PBL_FIFO_PERR_SET3(1U)
13671 #define S_PBL_FIFO_PERR_SET2 14
13672 #define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2)
13673 #define F_PBL_FIFO_PERR_SET2 V_PBL_FIFO_PERR_SET2(1U)
13675 #define S_PBL_FIFO_PERR_SET1 13
13676 #define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1)
13677 #define F_PBL_FIFO_PERR_SET1 V_PBL_FIFO_PERR_SET1(1U)
13679 #define S_PBL_FIFO_PERR_SET0 12
13680 #define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0)
13681 #define F_PBL_FIFO_PERR_SET0 V_PBL_FIFO_PERR_SET0(1U)
13683 #define S_CMD_FIFO_PERR_SET3 11
13684 #define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3)
13685 #define F_CMD_FIFO_PERR_SET3 V_CMD_FIFO_PERR_SET3(1U)
13687 #define S_CMD_FIFO_PERR_SET2 10
13688 #define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2)
13689 #define F_CMD_FIFO_PERR_SET2 V_CMD_FIFO_PERR_SET2(1U)
13691 #define S_CMD_FIFO_PERR_SET1 9
13692 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
13693 #define F_CMD_FIFO_PERR_SET1 V_CMD_FIFO_PERR_SET1(1U)
13695 #define S_CMD_FIFO_PERR_SET0 8
13696 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
13697 #define F_CMD_FIFO_PERR_SET0 V_CMD_FIFO_PERR_SET0(1U)
13699 #define S_LSO_HDR_SRAM_PERR_SET3 7
13700 #define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3)
13701 #define F_LSO_HDR_SRAM_PERR_SET3 V_LSO_HDR_SRAM_PERR_SET3(1U)
13703 #define S_LSO_HDR_SRAM_PERR_SET2 6
13704 #define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2)
13705 #define F_LSO_HDR_SRAM_PERR_SET2 V_LSO_HDR_SRAM_PERR_SET2(1U)
13707 #define S_LSO_HDR_SRAM_PERR_SET1 5
13708 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
13709 #define F_LSO_HDR_SRAM_PERR_SET1 V_LSO_HDR_SRAM_PERR_SET1(1U)
13711 #define S_LSO_HDR_SRAM_PERR_SET0 4
13712 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
13713 #define F_LSO_HDR_SRAM_PERR_SET0 V_LSO_HDR_SRAM_PERR_SET0(1U)
13715 #define S_IMM_DATA_PERR_SET_CH3 3
13716 #define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3)
13717 #define F_IMM_DATA_PERR_SET_CH3 V_IMM_DATA_PERR_SET_CH3(1U)
13719 #define S_IMM_DATA_PERR_SET_CH2 2
13720 #define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2)
13721 #define F_IMM_DATA_PERR_SET_CH2 V_IMM_DATA_PERR_SET_CH2(1U)
13723 #define S_IMM_DATA_PERR_SET_CH1 1
13724 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
13725 #define F_IMM_DATA_PERR_SET_CH1 V_IMM_DATA_PERR_SET_CH1(1U)
13727 #define S_IMM_DATA_PERR_SET_CH0 0
13728 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
13729 #define F_IMM_DATA_PERR_SET_CH0 V_IMM_DATA_PERR_SET_CH0(1U)
13731 #define A_ULP_TX_INT_CAUSE 0x8dcc
13732 #define A_ULP_TX_PERR_ENABLE 0x8dd0
13733 #define A_ULP_TX_TPT_LLIMIT 0x8dd4
13734 #define A_ULP_TX_TPT_ULIMIT 0x8dd8
13735 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
13736 #define A_ULP_TX_PBL_ULIMIT 0x8de0
13737 #define A_ULP_TX_CPL_ERR_OFFSET 0x8de4
13738 #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
13739 #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
13740 #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
13741 #define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4
13742 #define A_ULP_TX_CPL_PACK_SIZE1 0x8df8
13744 #define S_CH3SIZE1 24
13745 #define M_CH3SIZE1 0xffU
13746 #define V_CH3SIZE1(x) ((x) << S_CH3SIZE1)
13747 #define G_CH3SIZE1(x) (((x) >> S_CH3SIZE1) & M_CH3SIZE1)
13749 #define S_CH2SIZE1 16
13750 #define M_CH2SIZE1 0xffU
13751 #define V_CH2SIZE1(x) ((x) << S_CH2SIZE1)
13752 #define G_CH2SIZE1(x) (((x) >> S_CH2SIZE1) & M_CH2SIZE1)
13754 #define S_CH1SIZE1 8
13755 #define M_CH1SIZE1 0xffU
13756 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
13757 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
13759 #define S_CH0SIZE1 0
13760 #define M_CH0SIZE1 0xffU
13761 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
13762 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
13764 #define A_ULP_TX_CPL_PACK_SIZE2 0x8dfc
13766 #define S_CH3SIZE2 24
13767 #define M_CH3SIZE2 0xffU
13768 #define V_CH3SIZE2(x) ((x) << S_CH3SIZE2)
13769 #define G_CH3SIZE2(x) (((x) >> S_CH3SIZE2) & M_CH3SIZE2)
13771 #define S_CH2SIZE2 16
13772 #define M_CH2SIZE2 0xffU
13773 #define V_CH2SIZE2(x) ((x) << S_CH2SIZE2)
13774 #define G_CH2SIZE2(x) (((x) >> S_CH2SIZE2) & M_CH2SIZE2)
13776 #define S_CH1SIZE2 8
13777 #define M_CH1SIZE2 0xffU
13778 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
13779 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
13781 #define S_CH0SIZE2 0
13782 #define M_CH0SIZE2 0xffU
13783 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
13784 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
13786 #define A_ULP_TX_ERR_MSG2CIM 0x8e00
13787 #define A_ULP_TX_ERR_TABLE_BASE 0x8e04
13788 #define A_ULP_TX_ERR_CNT_CH0 0x8e10
13790 #define S_ERR_CNT0 0
13791 #define M_ERR_CNT0 0xfffffU
13792 #define V_ERR_CNT0(x) ((x) << S_ERR_CNT0)
13793 #define G_ERR_CNT0(x) (((x) >> S_ERR_CNT0) & M_ERR_CNT0)
13795 #define A_ULP_TX_ERR_CNT_CH1 0x8e14
13797 #define S_ERR_CNT1 0
13798 #define M_ERR_CNT1 0xfffffU
13799 #define V_ERR_CNT1(x) ((x) << S_ERR_CNT1)
13800 #define G_ERR_CNT1(x) (((x) >> S_ERR_CNT1) & M_ERR_CNT1)
13802 #define A_ULP_TX_ERR_CNT_CH2 0x8e18
13804 #define S_ERR_CNT2 0
13805 #define M_ERR_CNT2 0xfffffU
13806 #define V_ERR_CNT2(x) ((x) << S_ERR_CNT2)
13807 #define G_ERR_CNT2(x) (((x) >> S_ERR_CNT2) & M_ERR_CNT2)
13809 #define A_ULP_TX_ERR_CNT_CH3 0x8e1c
13811 #define S_ERR_CNT3 0
13812 #define M_ERR_CNT3 0xfffffU
13813 #define V_ERR_CNT3(x) ((x) << S_ERR_CNT3)
13814 #define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3)
13816 #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
13817 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
13818 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
13819 #define A_ULP_TX_FPGA_CMD_0 0x8e3c
13820 #define A_ULP_TX_FPGA_CMD_1 0x8e40
13821 #define A_ULP_TX_FPGA_CMD_2 0x8e44
13822 #define A_ULP_TX_FPGA_CMD_3 0x8e48
13823 #define A_ULP_TX_FPGA_CMD_4 0x8e4c
13824 #define A_ULP_TX_FPGA_CMD_5 0x8e50
13825 #define A_ULP_TX_FPGA_CMD_6 0x8e54
13826 #define A_ULP_TX_FPGA_CMD_7 0x8e58
13827 #define A_ULP_TX_FPGA_CMD_8 0x8e5c
13828 #define A_ULP_TX_FPGA_CMD_9 0x8e60
13829 #define A_ULP_TX_FPGA_CMD_10 0x8e64
13830 #define A_ULP_TX_FPGA_CMD_11 0x8e68
13831 #define A_ULP_TX_FPGA_CMD_12 0x8e6c
13832 #define A_ULP_TX_FPGA_CMD_13 0x8e70
13833 #define A_ULP_TX_FPGA_CMD_14 0x8e74
13834 #define A_ULP_TX_FPGA_CMD_15 0x8e78
13835 #define A_ULP_TX_SE_CNT_ERR 0x8ea0
13837 #define S_ERR_CH3 12
13838 #define M_ERR_CH3 0xfU
13839 #define V_ERR_CH3(x) ((x) << S_ERR_CH3)
13840 #define G_ERR_CH3(x) (((x) >> S_ERR_CH3) & M_ERR_CH3)
13842 #define S_ERR_CH2 8
13843 #define M_ERR_CH2 0xfU
13844 #define V_ERR_CH2(x) ((x) << S_ERR_CH2)
13845 #define G_ERR_CH2(x) (((x) >> S_ERR_CH2) & M_ERR_CH2)
13847 #define S_ERR_CH1 4
13848 #define M_ERR_CH1 0xfU
13849 #define V_ERR_CH1(x) ((x) << S_ERR_CH1)
13850 #define G_ERR_CH1(x) (((x) >> S_ERR_CH1) & M_ERR_CH1)
13852 #define S_ERR_CH0 0
13853 #define M_ERR_CH0 0xfU
13854 #define V_ERR_CH0(x) ((x) << S_ERR_CH0)
13855 #define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0)
13857 #define A_ULP_TX_SE_CNT_CLR 0x8ea4
13859 #define S_CLR_DROP 16
13860 #define M_CLR_DROP 0xfU
13861 #define V_CLR_DROP(x) ((x) << S_CLR_DROP)
13862 #define G_CLR_DROP(x) (((x) >> S_CLR_DROP) & M_CLR_DROP)
13864 #define S_CLR_CH3 12
13865 #define M_CLR_CH3 0xfU
13866 #define V_CLR_CH3(x) ((x) << S_CLR_CH3)
13867 #define G_CLR_CH3(x) (((x) >> S_CLR_CH3) & M_CLR_CH3)
13869 #define S_CLR_CH2 8
13870 #define M_CLR_CH2 0xfU
13871 #define V_CLR_CH2(x) ((x) << S_CLR_CH2)
13872 #define G_CLR_CH2(x) (((x) >> S_CLR_CH2) & M_CLR_CH2)
13874 #define S_CLR_CH1 4
13875 #define M_CLR_CH1 0xfU
13876 #define V_CLR_CH1(x) ((x) << S_CLR_CH1)
13877 #define G_CLR_CH1(x) (((x) >> S_CLR_CH1) & M_CLR_CH1)
13879 #define S_CLR_CH0 0
13880 #define M_CLR_CH0 0xfU
13881 #define V_CLR_CH0(x) ((x) << S_CLR_CH0)
13882 #define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0)
13884 #define A_ULP_TX_SE_CNT_CH0 0x8ea8
13886 #define S_SOP_CNT_ULP2TP 28
13887 #define M_SOP_CNT_ULP2TP 0xfU
13888 #define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP)
13889 #define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP)
13891 #define S_EOP_CNT_ULP2TP 24
13892 #define M_EOP_CNT_ULP2TP 0xfU
13893 #define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP)
13894 #define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP)
13896 #define S_SOP_CNT_LSO_IN 20
13897 #define M_SOP_CNT_LSO_IN 0xfU
13898 #define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN)
13899 #define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN)
13901 #define S_EOP_CNT_LSO_IN 16
13902 #define M_EOP_CNT_LSO_IN 0xfU
13903 #define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN)
13904 #define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN)
13906 #define S_SOP_CNT_ALG_IN 12
13907 #define M_SOP_CNT_ALG_IN 0xfU
13908 #define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN)
13909 #define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN)
13911 #define S_EOP_CNT_ALG_IN 8
13912 #define M_EOP_CNT_ALG_IN 0xfU
13913 #define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN)
13914 #define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN)
13916 #define S_SOP_CNT_CIM2ULP 4
13917 #define M_SOP_CNT_CIM2ULP 0xfU
13918 #define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP)
13919 #define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP)
13921 #define S_EOP_CNT_CIM2ULP 0
13922 #define M_EOP_CNT_CIM2ULP 0xfU
13923 #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
13924 #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)
13926 #define A_ULP_TX_SE_CNT_CH1 0x8eac
13927 #define A_ULP_TX_SE_CNT_CH2 0x8eb0
13928 #define A_ULP_TX_SE_CNT_CH3 0x8eb4
13929 #define A_ULP_TX_DROP_CNT 0x8eb8
13931 #define S_DROP_CH3 12
13932 #define M_DROP_CH3 0xfU
13933 #define V_DROP_CH3(x) ((x) << S_DROP_CH3)
13934 #define G_DROP_CH3(x) (((x) >> S_DROP_CH3) & M_DROP_CH3)
13936 #define S_DROP_CH2 8
13937 #define M_DROP_CH2 0xfU
13938 #define V_DROP_CH2(x) ((x) << S_DROP_CH2)
13939 #define G_DROP_CH2(x) (((x) >> S_DROP_CH2) & M_DROP_CH2)
13941 #define S_DROP_CH1 4
13942 #define M_DROP_CH1 0xfU
13943 #define V_DROP_CH1(x) ((x) << S_DROP_CH1)
13944 #define G_DROP_CH1(x) (((x) >> S_DROP_CH1) & M_DROP_CH1)
13946 #define S_DROP_CH0 0
13947 #define M_DROP_CH0 0xfU
13948 #define V_DROP_CH0(x) ((x) << S_DROP_CH0)
13949 #define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0)
13951 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
13952 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
13953 #define A_ULP_TX_LA_WRPTR_0 0x8ec8
13954 #define A_ULP_TX_LA_RESERVED_0 0x8ecc
13955 #define A_ULP_TX_LA_RDPTR_1 0x8ed0
13956 #define A_ULP_TX_LA_RDDATA_1 0x8ed4
13957 #define A_ULP_TX_LA_WRPTR_1 0x8ed8
13958 #define A_ULP_TX_LA_RESERVED_1 0x8edc
13959 #define A_ULP_TX_LA_RDPTR_2 0x8ee0
13960 #define A_ULP_TX_LA_RDDATA_2 0x8ee4
13961 #define A_ULP_TX_LA_WRPTR_2 0x8ee8
13962 #define A_ULP_TX_LA_RESERVED_2 0x8eec
13963 #define A_ULP_TX_LA_RDPTR_3 0x8ef0
13964 #define A_ULP_TX_LA_RDDATA_3 0x8ef4
13965 #define A_ULP_TX_LA_WRPTR_3 0x8ef8
13966 #define A_ULP_TX_LA_RESERVED_3 0x8efc
13967 #define A_ULP_TX_LA_RDPTR_4 0x8f00
13968 #define A_ULP_TX_LA_RDDATA_4 0x8f04
13969 #define A_ULP_TX_LA_WRPTR_4 0x8f08
13970 #define A_ULP_TX_LA_RESERVED_4 0x8f0c
13971 #define A_ULP_TX_LA_RDPTR_5 0x8f10
13972 #define A_ULP_TX_LA_RDDATA_5 0x8f14
13973 #define A_ULP_TX_LA_WRPTR_5 0x8f18
13974 #define A_ULP_TX_LA_RESERVED_5 0x8f1c
13975 #define A_ULP_TX_LA_RDPTR_6 0x8f20
13976 #define A_ULP_TX_LA_RDDATA_6 0x8f24
13977 #define A_ULP_TX_LA_WRPTR_6 0x8f28
13978 #define A_ULP_TX_LA_RESERVED_6 0x8f2c
13979 #define A_ULP_TX_LA_RDPTR_7 0x8f30
13980 #define A_ULP_TX_LA_RDDATA_7 0x8f34
13981 #define A_ULP_TX_LA_WRPTR_7 0x8f38
13982 #define A_ULP_TX_LA_RESERVED_7 0x8f3c
13983 #define A_ULP_TX_LA_RDPTR_8 0x8f40
13984 #define A_ULP_TX_LA_RDDATA_8 0x8f44
13985 #define A_ULP_TX_LA_WRPTR_8 0x8f48
13986 #define A_ULP_TX_LA_RESERVED_8 0x8f4c
13987 #define A_ULP_TX_LA_RDPTR_9 0x8f50
13988 #define A_ULP_TX_LA_RDDATA_9 0x8f54
13989 #define A_ULP_TX_LA_WRPTR_9 0x8f58
13990 #define A_ULP_TX_LA_RESERVED_9 0x8f5c
13991 #define A_ULP_TX_LA_RDPTR_10 0x8f60
13992 #define A_ULP_TX_LA_RDDATA_10 0x8f64
13993 #define A_ULP_TX_LA_WRPTR_10 0x8f68
13994 #define A_ULP_TX_LA_RESERVED_10 0x8f6c
13996 /* registers for module PM_RX */
13997 #define PM_RX_BASE_ADDR 0x8fc0
13999 #define A_PM_RX_CFG 0x8fc0
14000 #define A_PM_RX_MODE 0x8fc4
14002 #define S_RX_USE_BUNDLE_LEN 4
14003 #define V_RX_USE_BUNDLE_LEN(x) ((x) << S_RX_USE_BUNDLE_LEN)
14004 #define F_RX_USE_BUNDLE_LEN V_RX_USE_BUNDLE_LEN(1U)
14006 #define S_STAT_TO_CH 3
14007 #define V_STAT_TO_CH(x) ((x) << S_STAT_TO_CH)
14008 #define F_STAT_TO_CH V_STAT_TO_CH(1U)
14010 #define S_STAT_FROM_CH 1
14011 #define M_STAT_FROM_CH 0x3U
14012 #define V_STAT_FROM_CH(x) ((x) << S_STAT_FROM_CH)
14013 #define G_STAT_FROM_CH(x) (((x) >> S_STAT_FROM_CH) & M_STAT_FROM_CH)
14015 #define S_PREFETCH_ENABLE 0
14016 #define V_PREFETCH_ENABLE(x) ((x) << S_PREFETCH_ENABLE)
14017 #define F_PREFETCH_ENABLE V_PREFETCH_ENABLE(1U)
14019 #define A_PM_RX_STAT_CONFIG 0x8fc8
14020 #define A_PM_RX_STAT_COUNT 0x8fcc
14021 #define A_PM_RX_STAT_LSB 0x8fd0
14022 #define A_PM_RX_STAT_MSB 0x8fd4
14023 #define A_PM_RX_INT_ENABLE 0x8fd8
14025 #define S_ZERO_E_CMD_ERROR 22
14026 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
14027 #define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U)
14029 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 21
14030 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
14031 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
14033 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 20
14034 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
14035 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
14037 #define S_IESPI2_FIFO2X_RX_FRAMING_ERROR 19
14038 #define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
14039 #define F_IESPI2_FIFO2X_RX_FRAMING_ERROR V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U)
14041 #define S_IESPI3_FIFO2X_RX_FRAMING_ERROR 18
14042 #define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
14043 #define F_IESPI3_FIFO2X_RX_FRAMING_ERROR V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U)
14045 #define S_IESPI0_RX_FRAMING_ERROR 17
14046 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
14047 #define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U)
14049 #define S_IESPI1_RX_FRAMING_ERROR 16
14050 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
14051 #define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U)
14053 #define S_IESPI2_RX_FRAMING_ERROR 15
14054 #define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR)
14055 #define F_IESPI2_RX_FRAMING_ERROR V_IESPI2_RX_FRAMING_ERROR(1U)
14057 #define S_IESPI3_RX_FRAMING_ERROR 14
14058 #define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR)
14059 #define F_IESPI3_RX_FRAMING_ERROR V_IESPI3_RX_FRAMING_ERROR(1U)
14061 #define S_IESPI0_TX_FRAMING_ERROR 13
14062 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
14063 #define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U)
14065 #define S_IESPI1_TX_FRAMING_ERROR 12
14066 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
14067 #define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U)
14069 #define S_IESPI2_TX_FRAMING_ERROR 11
14070 #define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR)
14071 #define F_IESPI2_TX_FRAMING_ERROR V_IESPI2_TX_FRAMING_ERROR(1U)
14073 #define S_IESPI3_TX_FRAMING_ERROR 10
14074 #define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR)
14075 #define F_IESPI3_TX_FRAMING_ERROR V_IESPI3_TX_FRAMING_ERROR(1U)
14077 #define S_OCSPI0_RX_FRAMING_ERROR 9
14078 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
14079 #define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U)
14081 #define S_OCSPI1_RX_FRAMING_ERROR 8
14082 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
14083 #define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U)
14085 #define S_OCSPI0_TX_FRAMING_ERROR 7
14086 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
14087 #define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U)
14089 #define S_OCSPI1_TX_FRAMING_ERROR 6
14090 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
14091 #define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U)
14093 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 5
14094 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
14095 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
14097 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 4
14098 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
14099 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
14101 #define S_OCSPI_PAR_ERROR 3
14102 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
14103 #define F_OCSPI_PAR_ERROR V_OCSPI_PAR_ERROR(1U)
14105 #define S_DB_OPTIONS_PAR_ERROR 2
14106 #define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR)
14107 #define F_DB_OPTIONS_PAR_ERROR V_DB_OPTIONS_PAR_ERROR(1U)
14109 #define S_IESPI_PAR_ERROR 1
14110 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
14111 #define F_IESPI_PAR_ERROR V_IESPI_PAR_ERROR(1U)
14113 #define S_E_PCMD_PAR_ERROR 0
14114 #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
14115 #define F_E_PCMD_PAR_ERROR V_E_PCMD_PAR_ERROR(1U)
14117 #define A_PM_RX_INT_CAUSE 0x8fdc
14119 /* registers for module PM_TX */
14120 #define PM_TX_BASE_ADDR 0x8fe0
14122 #define A_PM_TX_CFG 0x8fe0
14124 #define S_CH3_OUTPUT 17
14125 #define M_CH3_OUTPUT 0x1fU
14126 #define V_CH3_OUTPUT(x) ((x) << S_CH3_OUTPUT)
14127 #define G_CH3_OUTPUT(x) (((x) >> S_CH3_OUTPUT) & M_CH3_OUTPUT)
14129 #define A_PM_TX_MODE 0x8fe4
14131 #define S_CONG_THRESH3 25
14132 #define M_CONG_THRESH3 0x7fU
14133 #define V_CONG_THRESH3(x) ((x) << S_CONG_THRESH3)
14134 #define G_CONG_THRESH3(x) (((x) >> S_CONG_THRESH3) & M_CONG_THRESH3)
14136 #define S_CONG_THRESH2 18
14137 #define M_CONG_THRESH2 0x7fU
14138 #define V_CONG_THRESH2(x) ((x) << S_CONG_THRESH2)
14139 #define G_CONG_THRESH2(x) (((x) >> S_CONG_THRESH2) & M_CONG_THRESH2)
14141 #define S_CONG_THRESH1 11
14142 #define M_CONG_THRESH1 0x7fU
14143 #define V_CONG_THRESH1(x) ((x) << S_CONG_THRESH1)
14144 #define G_CONG_THRESH1(x) (((x) >> S_CONG_THRESH1) & M_CONG_THRESH1)
14146 #define S_CONG_THRESH0 4
14147 #define M_CONG_THRESH0 0x7fU
14148 #define V_CONG_THRESH0(x) ((x) << S_CONG_THRESH0)
14149 #define G_CONG_THRESH0(x) (((x) >> S_CONG_THRESH0) & M_CONG_THRESH0)
14151 #define S_TX_USE_BUNDLE_LEN 3
14152 #define V_TX_USE_BUNDLE_LEN(x) ((x) << S_TX_USE_BUNDLE_LEN)
14153 #define F_TX_USE_BUNDLE_LEN V_TX_USE_BUNDLE_LEN(1U)
14155 #define S_STAT_CHANNEL 1
14156 #define M_STAT_CHANNEL 0x3U
14157 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
14158 #define G_STAT_CHANNEL(x) (((x) >> S_STAT_CHANNEL) & M_STAT_CHANNEL)
14160 #define A_PM_TX_STAT_CONFIG 0x8fe8
14161 #define A_PM_TX_STAT_COUNT 0x8fec
14162 #define A_PM_TX_STAT_LSB 0x8ff0
14163 #define A_PM_TX_STAT_MSB 0x8ff4
14164 #define A_PM_TX_INT_ENABLE 0x8ff8
14166 #define S_PCMD_LEN_OVFL0 31
14167 #define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0)
14168 #define F_PCMD_LEN_OVFL0 V_PCMD_LEN_OVFL0(1U)
14170 #define S_PCMD_LEN_OVFL1 30
14171 #define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1)
14172 #define F_PCMD_LEN_OVFL1 V_PCMD_LEN_OVFL1(1U)
14174 #define S_PCMD_LEN_OVFL2 29
14175 #define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2)
14176 #define F_PCMD_LEN_OVFL2 V_PCMD_LEN_OVFL2(1U)
14178 #define S_ZERO_C_CMD_ERRO 28
14179 #define V_ZERO_C_CMD_ERRO(x) ((x) << S_ZERO_C_CMD_ERRO)
14180 #define F_ZERO_C_CMD_ERRO V_ZERO_C_CMD_ERRO(1U)
14182 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 27
14183 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
14184 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
14186 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 26
14187 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
14188 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
14190 #define S_ICSPI2_FIFO2X_RX_FRAMING_ERROR 25
14191 #define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
14192 #define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
14194 #define S_ICSPI3_FIFO2X_RX_FRAMING_ERROR 24
14195 #define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
14196 #define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
14198 #define S_ICSPI0_RX_FRAMING_ERROR 23
14199 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
14200 #define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U)
14202 #define S_ICSPI1_RX_FRAMING_ERROR 22
14203 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
14204 #define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U)
14206 #define S_ICSPI2_RX_FRAMING_ERROR 21
14207 #define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR)
14208 #define F_ICSPI2_RX_FRAMING_ERROR V_ICSPI2_RX_FRAMING_ERROR(1U)
14210 #define S_ICSPI3_RX_FRAMING_ERROR 20
14211 #define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR)
14212 #define F_ICSPI3_RX_FRAMING_ERROR V_ICSPI3_RX_FRAMING_ERROR(1U)
14214 #define S_ICSPI0_TX_FRAMING_ERROR 19
14215 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
14216 #define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U)
14218 #define S_ICSPI1_TX_FRAMING_ERROR 18
14219 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
14220 #define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U)
14222 #define S_ICSPI2_TX_FRAMING_ERROR 17
14223 #define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR)
14224 #define F_ICSPI2_TX_FRAMING_ERROR V_ICSPI2_TX_FRAMING_ERROR(1U)
14226 #define S_ICSPI3_TX_FRAMING_ERROR 16
14227 #define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR)
14228 #define F_ICSPI3_TX_FRAMING_ERROR V_ICSPI3_TX_FRAMING_ERROR(1U)
14230 #define S_OESPI0_RX_FRAMING_ERROR 15
14231 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
14232 #define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U)
14234 #define S_OESPI1_RX_FRAMING_ERROR 14
14235 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
14236 #define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U)
14238 #define S_OESPI2_RX_FRAMING_ERROR 13
14239 #define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR)
14240 #define F_OESPI2_RX_FRAMING_ERROR V_OESPI2_RX_FRAMING_ERROR(1U)
14242 #define S_OESPI3_RX_FRAMING_ERROR 12
14243 #define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR)
14244 #define F_OESPI3_RX_FRAMING_ERROR V_OESPI3_RX_FRAMING_ERROR(1U)
14246 #define S_OESPI0_TX_FRAMING_ERROR 11
14247 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
14248 #define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U)
14250 #define S_OESPI1_TX_FRAMING_ERROR 10
14251 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
14252 #define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U)
14254 #define S_OESPI2_TX_FRAMING_ERROR 9
14255 #define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR)
14256 #define F_OESPI2_TX_FRAMING_ERROR V_OESPI2_TX_FRAMING_ERROR(1U)
14258 #define S_OESPI3_TX_FRAMING_ERROR 8
14259 #define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR)
14260 #define F_OESPI3_TX_FRAMING_ERROR V_OESPI3_TX_FRAMING_ERROR(1U)
14262 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7
14263 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
14264 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
14266 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6
14267 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
14268 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
14270 #define S_OESPI2_OFIFO2X_TX_FRAMING_ERROR 5
14271 #define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
14272 #define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
14274 #define S_OESPI3_OFIFO2X_TX_FRAMING_ERROR 4
14275 #define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
14276 #define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
14278 #define S_OESPI_PAR_ERROR 3
14279 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
14280 #define F_OESPI_PAR_ERROR V_OESPI_PAR_ERROR(1U)
14282 #define S_ICSPI_PAR_ERROR 1
14283 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
14284 #define F_ICSPI_PAR_ERROR V_ICSPI_PAR_ERROR(1U)
14286 #define S_C_PCMD_PAR_ERROR 0
14287 #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
14288 #define F_C_PCMD_PAR_ERROR V_C_PCMD_PAR_ERROR(1U)
14290 #define A_PM_TX_INT_CAUSE 0x8ffc
14292 #define S_ZERO_C_CMD_ERROR 28
14293 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
14294 #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U)
14296 /* registers for module MPS */
14297 #define MPS_BASE_ADDR 0x9000
14299 #define A_MPS_PORT_CTL 0x0
14301 #define S_LPBKEN 31
14302 #define V_LPBKEN(x) ((x) << S_LPBKEN)
14303 #define F_LPBKEN V_LPBKEN(1U)
14305 #define S_PORTTXEN 30
14306 #define V_PORTTXEN(x) ((x) << S_PORTTXEN)
14307 #define F_PORTTXEN V_PORTTXEN(1U)
14309 #define S_PORTRXEN 29
14310 #define V_PORTRXEN(x) ((x) << S_PORTRXEN)
14311 #define F_PORTRXEN V_PORTRXEN(1U)
14314 #define V_PPPEN(x) ((x) << S_PPPEN)
14315 #define F_PPPEN V_PPPEN(1U)
14317 #define S_FCSSTRIPEN 27
14318 #define V_FCSSTRIPEN(x) ((x) << S_FCSSTRIPEN)
14319 #define F_FCSSTRIPEN V_FCSSTRIPEN(1U)
14321 #define S_PPPANDPAUSE 26
14322 #define V_PPPANDPAUSE(x) ((x) << S_PPPANDPAUSE)
14323 #define F_PPPANDPAUSE V_PPPANDPAUSE(1U)
14325 #define S_PRIOPPPENMAP 16
14326 #define M_PRIOPPPENMAP 0xffU
14327 #define V_PRIOPPPENMAP(x) ((x) << S_PRIOPPPENMAP)
14328 #define G_PRIOPPPENMAP(x) (((x) >> S_PRIOPPPENMAP) & M_PRIOPPPENMAP)
14330 #define A_MPS_VF_CTL 0x0
14331 #define A_MPS_PORT_PAUSE_CTL 0x4
14333 #define S_TIMEUNIT 0
14334 #define M_TIMEUNIT 0xffffU
14335 #define V_TIMEUNIT(x) ((x) << S_TIMEUNIT)
14336 #define G_TIMEUNIT(x) (((x) >> S_TIMEUNIT) & M_TIMEUNIT)
14338 #define A_MPS_PORT_TX_PAUSE_CTL 0x8
14340 #define S_REGSENDOFF 24
14341 #define M_REGSENDOFF 0xffU
14342 #define V_REGSENDOFF(x) ((x) << S_REGSENDOFF)
14343 #define G_REGSENDOFF(x) (((x) >> S_REGSENDOFF) & M_REGSENDOFF)
14345 #define S_REGSENDON 16
14346 #define M_REGSENDON 0xffU
14347 #define V_REGSENDON(x) ((x) << S_REGSENDON)
14348 #define G_REGSENDON(x) (((x) >> S_REGSENDON) & M_REGSENDON)
14350 #define S_SGESENDEN 8
14351 #define M_SGESENDEN 0xffU
14352 #define V_SGESENDEN(x) ((x) << S_SGESENDEN)
14353 #define G_SGESENDEN(x) (((x) >> S_SGESENDEN) & M_SGESENDEN)
14355 #define S_RXSENDEN 0
14356 #define M_RXSENDEN 0xffU
14357 #define V_RXSENDEN(x) ((x) << S_RXSENDEN)
14358 #define G_RXSENDEN(x) (((x) >> S_RXSENDEN) & M_RXSENDEN)
14360 #define A_MPS_PORT_TX_PAUSE_CTL2 0xc
14362 #define S_XOFFDISABLE 0
14363 #define V_XOFFDISABLE(x) ((x) << S_XOFFDISABLE)
14364 #define F_XOFFDISABLE V_XOFFDISABLE(1U)
14366 #define A_MPS_PORT_RX_PAUSE_CTL 0x10
14368 #define S_REGHALTON 8
14369 #define M_REGHALTON 0xffU
14370 #define V_REGHALTON(x) ((x) << S_REGHALTON)
14371 #define G_REGHALTON(x) (((x) >> S_REGHALTON) & M_REGHALTON)
14373 #define S_RXHALTEN 0
14374 #define M_RXHALTEN 0xffU
14375 #define V_RXHALTEN(x) ((x) << S_RXHALTEN)
14376 #define G_RXHALTEN(x) (((x) >> S_RXHALTEN) & M_RXHALTEN)
14378 #define A_MPS_PORT_TX_PAUSE_STATUS 0x14
14380 #define S_REGSENDING 16
14381 #define M_REGSENDING 0xffU
14382 #define V_REGSENDING(x) ((x) << S_REGSENDING)
14383 #define G_REGSENDING(x) (((x) >> S_REGSENDING) & M_REGSENDING)
14385 #define S_SGESENDING 8
14386 #define M_SGESENDING 0xffU
14387 #define V_SGESENDING(x) ((x) << S_SGESENDING)
14388 #define G_SGESENDING(x) (((x) >> S_SGESENDING) & M_SGESENDING)
14390 #define S_RXSENDING 0
14391 #define M_RXSENDING 0xffU
14392 #define V_RXSENDING(x) ((x) << S_RXSENDING)
14393 #define G_RXSENDING(x) (((x) >> S_RXSENDING) & M_RXSENDING)
14395 #define A_MPS_PORT_RX_PAUSE_STATUS 0x18
14397 #define S_REGHALTED 8
14398 #define M_REGHALTED 0xffU
14399 #define V_REGHALTED(x) ((x) << S_REGHALTED)
14400 #define G_REGHALTED(x) (((x) >> S_REGHALTED) & M_REGHALTED)
14402 #define S_RXHALTED 0
14403 #define M_RXHALTED 0xffU
14404 #define V_RXHALTED(x) ((x) << S_RXHALTED)
14405 #define G_RXHALTED(x) (((x) >> S_RXHALTED) & M_RXHALTED)
14407 #define A_MPS_PORT_TX_PAUSE_DEST_L 0x1c
14408 #define A_MPS_PORT_TX_PAUSE_DEST_H 0x20
14411 #define M_ADDR 0xffffU
14412 #define V_ADDR(x) ((x) << S_ADDR)
14413 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
14415 #define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24
14416 #define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28
14417 #define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c
14420 #define M_PRTY7 0x3U
14421 #define V_PRTY7(x) ((x) << S_PRTY7)
14422 #define G_PRTY7(x) (((x) >> S_PRTY7) & M_PRTY7)
14425 #define M_PRTY6 0x3U
14426 #define V_PRTY6(x) ((x) << S_PRTY6)
14427 #define G_PRTY6(x) (((x) >> S_PRTY6) & M_PRTY6)
14430 #define M_PRTY5 0x3U
14431 #define V_PRTY5(x) ((x) << S_PRTY5)
14432 #define G_PRTY5(x) (((x) >> S_PRTY5) & M_PRTY5)
14435 #define M_PRTY4 0x3U
14436 #define V_PRTY4(x) ((x) << S_PRTY4)
14437 #define G_PRTY4(x) (((x) >> S_PRTY4) & M_PRTY4)
14440 #define M_PRTY3 0x3U
14441 #define V_PRTY3(x) ((x) << S_PRTY3)
14442 #define G_PRTY3(x) (((x) >> S_PRTY3) & M_PRTY3)
14445 #define M_PRTY2 0x3U
14446 #define V_PRTY2(x) ((x) << S_PRTY2)
14447 #define G_PRTY2(x) (((x) >> S_PRTY2) & M_PRTY2)
14450 #define M_PRTY1 0x3U
14451 #define V_PRTY1(x) ((x) << S_PRTY1)
14452 #define G_PRTY1(x) (((x) >> S_PRTY1) & M_PRTY1)
14455 #define M_PRTY0 0x3U
14456 #define V_PRTY0(x) ((x) << S_PRTY0)
14457 #define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0)
14459 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
14460 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
14461 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
14462 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
14463 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
14464 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
14465 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
14466 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
14467 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
14468 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
14469 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
14470 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
14471 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
14472 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
14473 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
14474 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
14475 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
14476 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
14477 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
14478 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
14479 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
14480 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
14481 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
14482 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
14483 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
14484 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
14485 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
14486 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
14487 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
14488 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
14489 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
14490 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
14491 #define A_MPS_PORT_RX_CTL 0x100
14493 #define S_NO_RPLCT_M 20
14494 #define V_NO_RPLCT_M(x) ((x) << S_NO_RPLCT_M)
14495 #define F_NO_RPLCT_M V_NO_RPLCT_M(1U)
14497 #define S_RPLCT_SEL_L 18
14498 #define M_RPLCT_SEL_L 0x3U
14499 #define V_RPLCT_SEL_L(x) ((x) << S_RPLCT_SEL_L)
14500 #define G_RPLCT_SEL_L(x) (((x) >> S_RPLCT_SEL_L) & M_RPLCT_SEL_L)
14502 #define S_FLTR_VLAN_SEL 17
14503 #define V_FLTR_VLAN_SEL(x) ((x) << S_FLTR_VLAN_SEL)
14504 #define F_FLTR_VLAN_SEL V_FLTR_VLAN_SEL(1U)
14506 #define S_PRIO_VLAN_SEL 16
14507 #define V_PRIO_VLAN_SEL(x) ((x) << S_PRIO_VLAN_SEL)
14508 #define F_PRIO_VLAN_SEL V_PRIO_VLAN_SEL(1U)
14510 #define S_CHK_8023_LEN_M 15
14511 #define V_CHK_8023_LEN_M(x) ((x) << S_CHK_8023_LEN_M)
14512 #define F_CHK_8023_LEN_M V_CHK_8023_LEN_M(1U)
14514 #define S_CHK_8023_LEN_L 14
14515 #define V_CHK_8023_LEN_L(x) ((x) << S_CHK_8023_LEN_L)
14516 #define F_CHK_8023_LEN_L V_CHK_8023_LEN_L(1U)
14518 #define S_NIV_DROP 13
14519 #define V_NIV_DROP(x) ((x) << S_NIV_DROP)
14520 #define F_NIV_DROP V_NIV_DROP(1U)
14522 #define S_NOV_DROP 12
14523 #define V_NOV_DROP(x) ((x) << S_NOV_DROP)
14524 #define F_NOV_DROP V_NOV_DROP(1U)
14526 #define S_CLS_PRT 11
14527 #define V_CLS_PRT(x) ((x) << S_CLS_PRT)
14528 #define F_CLS_PRT V_CLS_PRT(1U)
14530 #define S_RX_QFC_EN 10
14531 #define V_RX_QFC_EN(x) ((x) << S_RX_QFC_EN)
14532 #define F_RX_QFC_EN V_RX_QFC_EN(1U)
14534 #define S_QFC_FWD_UP 9
14535 #define V_QFC_FWD_UP(x) ((x) << S_QFC_FWD_UP)
14536 #define F_QFC_FWD_UP V_QFC_FWD_UP(1U)
14538 #define S_PPP_FWD_UP 8
14539 #define V_PPP_FWD_UP(x) ((x) << S_PPP_FWD_UP)
14540 #define F_PPP_FWD_UP V_PPP_FWD_UP(1U)
14542 #define S_PAUSE_FWD_UP 7
14543 #define V_PAUSE_FWD_UP(x) ((x) << S_PAUSE_FWD_UP)
14544 #define F_PAUSE_FWD_UP V_PAUSE_FWD_UP(1U)
14546 #define S_LPBK_BP 6
14547 #define V_LPBK_BP(x) ((x) << S_LPBK_BP)
14548 #define F_LPBK_BP V_LPBK_BP(1U)
14550 #define S_PASS_NO_MATCH 5
14551 #define V_PASS_NO_MATCH(x) ((x) << S_PASS_NO_MATCH)
14552 #define F_PASS_NO_MATCH V_PASS_NO_MATCH(1U)
14554 #define S_IVLAN_EN 4
14555 #define V_IVLAN_EN(x) ((x) << S_IVLAN_EN)
14556 #define F_IVLAN_EN V_IVLAN_EN(1U)
14558 #define S_OVLAN_EN3 3
14559 #define V_OVLAN_EN3(x) ((x) << S_OVLAN_EN3)
14560 #define F_OVLAN_EN3 V_OVLAN_EN3(1U)
14562 #define S_OVLAN_EN2 2
14563 #define V_OVLAN_EN2(x) ((x) << S_OVLAN_EN2)
14564 #define F_OVLAN_EN2 V_OVLAN_EN2(1U)
14566 #define S_OVLAN_EN1 1
14567 #define V_OVLAN_EN1(x) ((x) << S_OVLAN_EN1)
14568 #define F_OVLAN_EN1 V_OVLAN_EN1(1U)
14570 #define S_OVLAN_EN0 0
14571 #define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0)
14572 #define F_OVLAN_EN0 V_OVLAN_EN0(1U)
14574 #define A_MPS_PORT_RX_MTU 0x104
14575 #define A_MPS_PORT_RX_PF_MAP 0x108
14576 #define A_MPS_PORT_RX_VF_MAP0 0x10c
14577 #define A_MPS_PORT_RX_VF_MAP1 0x110
14578 #define A_MPS_PORT_RX_VF_MAP2 0x114
14579 #define A_MPS_PORT_RX_VF_MAP3 0x118
14580 #define A_MPS_PORT_RX_IVLAN 0x11c
14582 #define S_IVLAN_ETYPE 0
14583 #define M_IVLAN_ETYPE 0xffffU
14584 #define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE)
14585 #define G_IVLAN_ETYPE(x) (((x) >> S_IVLAN_ETYPE) & M_IVLAN_ETYPE)
14587 #define A_MPS_PORT_RX_OVLAN0 0x120
14589 #define S_OVLAN_MASK 16
14590 #define M_OVLAN_MASK 0xffffU
14591 #define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK)
14592 #define G_OVLAN_MASK(x) (((x) >> S_OVLAN_MASK) & M_OVLAN_MASK)
14594 #define S_OVLAN_ETYPE 0
14595 #define M_OVLAN_ETYPE 0xffffU
14596 #define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE)
14597 #define G_OVLAN_ETYPE(x) (((x) >> S_OVLAN_ETYPE) & M_OVLAN_ETYPE)
14599 #define A_MPS_PORT_RX_OVLAN1 0x124
14600 #define A_MPS_PORT_RX_OVLAN2 0x128
14601 #define A_MPS_PORT_RX_OVLAN3 0x12c
14602 #define A_MPS_PORT_RX_RSS_HASH 0x130
14603 #define A_MPS_PORT_RX_RSS_CONTROL 0x134
14605 #define S_RSS_CTRL 16
14606 #define M_RSS_CTRL 0xffU
14607 #define V_RSS_CTRL(x) ((x) << S_RSS_CTRL)
14608 #define G_RSS_CTRL(x) (((x) >> S_RSS_CTRL) & M_RSS_CTRL)
14610 #define S_QUE_NUM 0
14611 #define M_QUE_NUM 0xffffU
14612 #define V_QUE_NUM(x) ((x) << S_QUE_NUM)
14613 #define G_QUE_NUM(x) (((x) >> S_QUE_NUM) & M_QUE_NUM)
14615 #define A_MPS_PORT_RX_CTL1 0x138
14617 #define S_FIXED_PFVF_MAC 13
14618 #define V_FIXED_PFVF_MAC(x) ((x) << S_FIXED_PFVF_MAC)
14619 #define F_FIXED_PFVF_MAC V_FIXED_PFVF_MAC(1U)
14621 #define S_FIXED_PFVF_LPBK 12
14622 #define V_FIXED_PFVF_LPBK(x) ((x) << S_FIXED_PFVF_LPBK)
14623 #define F_FIXED_PFVF_LPBK V_FIXED_PFVF_LPBK(1U)
14625 #define S_FIXED_PFVF_LPBK_OV 11
14626 #define V_FIXED_PFVF_LPBK_OV(x) ((x) << S_FIXED_PFVF_LPBK_OV)
14627 #define F_FIXED_PFVF_LPBK_OV V_FIXED_PFVF_LPBK_OV(1U)
14629 #define S_FIXED_PF 8
14630 #define M_FIXED_PF 0x7U
14631 #define V_FIXED_PF(x) ((x) << S_FIXED_PF)
14632 #define G_FIXED_PF(x) (((x) >> S_FIXED_PF) & M_FIXED_PF)
14634 #define S_FIXED_VF_VLD 7
14635 #define V_FIXED_VF_VLD(x) ((x) << S_FIXED_VF_VLD)
14636 #define F_FIXED_VF_VLD V_FIXED_VF_VLD(1U)
14638 #define S_FIXED_VF 0
14639 #define M_FIXED_VF 0x7fU
14640 #define V_FIXED_VF(x) ((x) << S_FIXED_VF)
14641 #define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF)
14643 #define A_MPS_PORT_RX_SPARE 0x13c
14644 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
14647 #define M_CREDIT 0xffffU
14648 #define V_CREDIT(x) ((x) << S_CREDIT)
14649 #define G_CREDIT(x) (((x) >> S_CREDIT) & M_CREDIT)
14651 #define A_MPS_PORT_TX_MAC_RELOAD_CH1 0x194
14652 #define A_MPS_PORT_TX_MAC_RELOAD_CH2 0x198
14653 #define A_MPS_PORT_TX_MAC_RELOAD_CH3 0x19c
14654 #define A_MPS_PORT_TX_MAC_RELOAD_CH4 0x1a0
14655 #define A_MPS_PORT_TX_LPBK_RELOAD_CH0 0x1a8
14656 #define A_MPS_PORT_TX_LPBK_RELOAD_CH1 0x1ac
14657 #define A_MPS_PORT_TX_LPBK_RELOAD_CH2 0x1b0
14658 #define A_MPS_PORT_TX_LPBK_RELOAD_CH3 0x1b4
14659 #define A_MPS_PORT_TX_LPBK_RELOAD_CH4 0x1b8
14660 #define A_MPS_PORT_TX_FIFO_CTL 0x1c4
14663 #define M_FIFOTH 0x1ffU
14664 #define V_FIFOTH(x) ((x) << S_FIFOTH)
14665 #define G_FIFOTH(x) (((x) >> S_FIFOTH) & M_FIFOTH)
14668 #define V_FIFOEN(x) ((x) << S_FIFOEN)
14669 #define F_FIFOEN V_FIFOEN(1U)
14671 #define S_MAXPKTCNT 0
14672 #define M_MAXPKTCNT 0xfU
14673 #define V_MAXPKTCNT(x) ((x) << S_MAXPKTCNT)
14674 #define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT)
14676 #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
14677 #define A_MPS_PORT_CLS_HASH_SRAM 0x200
14680 #define V_VALID(x) ((x) << S_VALID)
14681 #define F_VALID V_VALID(1U)
14683 #define S_HASHPORTMAP 16
14684 #define M_HASHPORTMAP 0xfU
14685 #define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP)
14686 #define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP)
14688 #define S_MULTILISTEN 15
14689 #define V_MULTILISTEN(x) ((x) << S_MULTILISTEN)
14690 #define F_MULTILISTEN V_MULTILISTEN(1U)
14692 #define S_PRIORITY 12
14693 #define M_PRIORITY 0x7U
14694 #define V_PRIORITY(x) ((x) << S_PRIORITY)
14695 #define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY)
14697 #define S_REPLICATE 11
14698 #define V_REPLICATE(x) ((x) << S_REPLICATE)
14699 #define F_REPLICATE V_REPLICATE(1U)
14703 #define V_PF(x) ((x) << S_PF)
14704 #define G_PF(x) (((x) >> S_PF) & M_PF)
14706 #define S_VF_VALID 7
14707 #define V_VF_VALID(x) ((x) << S_VF_VALID)
14708 #define F_VF_VALID V_VF_VALID(1U)
14712 #define V_VF(x) ((x) << S_VF)
14713 #define G_VF(x) (((x) >> S_VF) & M_VF)
14715 #define A_MPS_PF_CTL 0x2c0
14718 #define V_TXEN(x) ((x) << S_TXEN)
14719 #define F_TXEN V_TXEN(1U)
14722 #define V_RXEN(x) ((x) << S_RXEN)
14723 #define F_RXEN V_RXEN(1U)
14725 #define A_MPS_PF_TX_QINQ_VLAN 0x2e0
14727 #define S_PROTOCOLID 16
14728 #define M_PROTOCOLID 0xffffU
14729 #define V_PROTOCOLID(x) ((x) << S_PROTOCOLID)
14730 #define G_PROTOCOLID(x) (((x) >> S_PROTOCOLID) & M_PROTOCOLID)
14732 #define S_VLAN_PRIO 13
14733 #define M_VLAN_PRIO 0x7U
14734 #define V_VLAN_PRIO(x) ((x) << S_VLAN_PRIO)
14735 #define G_VLAN_PRIO(x) (((x) >> S_VLAN_PRIO) & M_VLAN_PRIO)
14738 #define V_CFI(x) ((x) << S_CFI)
14739 #define F_CFI V_CFI(1U)
14742 #define M_TAG 0xfffU
14743 #define V_TAG(x) ((x) << S_TAG)
14744 #define G_TAG(x) (((x) >> S_TAG) & M_TAG)
14746 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300
14747 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304
14748 #define A_MPS_PORT_CLS_HASH_CTL 0x304
14750 #define S_UNICASTENABLE 31
14751 #define V_UNICASTENABLE(x) ((x) << S_UNICASTENABLE)
14752 #define F_UNICASTENABLE V_UNICASTENABLE(1U)
14754 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_L 0x308
14755 #define A_MPS_PORT_CLS_PROMISCUOUS_CTL 0x308
14757 #define S_PROMISCEN 31
14758 #define V_PROMISCEN(x) ((x) << S_PROMISCEN)
14759 #define F_PROMISCEN V_PROMISCEN(1U)
14761 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
14762 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
14763 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
14764 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310
14766 #define S_MATCHBOTH 17
14767 #define V_MATCHBOTH(x) ((x) << S_MATCHBOTH)
14768 #define F_MATCHBOTH V_MATCHBOTH(1U)
14770 #define S_BMC_VLD 16
14771 #define V_BMC_VLD(x) ((x) << S_BMC_VLD)
14772 #define F_BMC_VLD V_BMC_VLD(1U)
14774 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
14775 #define A_MPS_PORT_CLS_BMC_VLAN 0x314
14777 #define S_BMC_VLAN_SEL 13
14778 #define V_BMC_VLAN_SEL(x) ((x) << S_BMC_VLAN_SEL)
14779 #define F_BMC_VLAN_SEL V_BMC_VLAN_SEL(1U)
14781 #define S_VLAN_VLD 12
14782 #define V_VLAN_VLD(x) ((x) << S_VLAN_VLD)
14783 #define F_VLAN_VLD V_VLAN_VLD(1U)
14785 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318
14786 #define A_MPS_PORT_CLS_CTL 0x318
14788 #define S_PF_VLAN_SEL 0
14789 #define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL)
14790 #define F_PF_VLAN_SEL V_PF_VLAN_SEL(1U)
14792 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
14793 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
14794 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
14795 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
14796 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
14797 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330
14798 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334
14799 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338
14800 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c
14801 #define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340
14802 #define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344
14803 #define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348
14804 #define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c
14805 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350
14806 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_H 0x354
14807 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_L 0x358
14808 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_H 0x35c
14809 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_L 0x360
14810 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_H 0x364
14811 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_L 0x368
14812 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_H 0x36c
14813 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_L 0x370
14814 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_H 0x374
14815 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378
14816 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c
14817 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380
14818 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384
14819 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
14820 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
14821 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
14822 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
14823 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
14824 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
14825 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
14826 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
14827 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
14828 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
14829 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
14830 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
14831 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
14832 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
14833 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
14834 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
14835 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
14836 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
14837 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
14838 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
14839 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
14840 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
14841 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
14842 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
14843 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
14844 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
14845 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
14846 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
14847 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
14848 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
14849 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
14850 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
14851 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
14852 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
14853 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
14854 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
14855 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
14856 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
14857 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
14858 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
14859 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
14860 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
14861 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
14862 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
14863 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
14864 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
14865 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
14866 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
14867 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
14868 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
14869 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
14870 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
14871 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
14872 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
14873 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
14874 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
14875 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
14876 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
14877 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
14878 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
14879 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
14880 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
14881 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
14882 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
14883 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
14884 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
14885 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
14886 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
14887 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
14888 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
14889 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
14890 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
14891 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
14892 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
14893 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
14894 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
14895 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
14896 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
14897 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
14898 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
14899 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
14900 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
14901 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
14902 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
14903 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
14904 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
14905 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
14906 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
14907 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
14908 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
14909 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
14910 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
14911 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
14912 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
14913 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
14914 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
14915 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
14916 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
14917 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
14918 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
14919 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
14920 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
14921 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
14922 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
14923 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
14924 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
14925 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
14926 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
14927 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
14928 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
14929 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
14930 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
14931 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
14932 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
14933 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
14934 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
14935 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
14936 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
14937 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
14938 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
14939 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
14940 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
14941 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
14942 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
14943 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
14944 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
14945 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
14946 #define A_MPS_CMN_CTL 0x9000
14948 #define S_DETECT8023 3
14949 #define V_DETECT8023(x) ((x) << S_DETECT8023)
14950 #define F_DETECT8023 V_DETECT8023(1U)
14952 #define S_VFDIRECTACCESS 2
14953 #define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS)
14954 #define F_VFDIRECTACCESS V_VFDIRECTACCESS(1U)
14956 #define S_NUMPORTS 0
14957 #define M_NUMPORTS 0x3U
14958 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
14959 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
14961 #define A_MPS_INT_ENABLE 0x9004
14963 #define S_STATINTENB 5
14964 #define V_STATINTENB(x) ((x) << S_STATINTENB)
14965 #define F_STATINTENB V_STATINTENB(1U)
14967 #define S_TXINTENB 4
14968 #define V_TXINTENB(x) ((x) << S_TXINTENB)
14969 #define F_TXINTENB V_TXINTENB(1U)
14971 #define S_RXINTENB 3
14972 #define V_RXINTENB(x) ((x) << S_RXINTENB)
14973 #define F_RXINTENB V_RXINTENB(1U)
14975 #define S_TRCINTENB 2
14976 #define V_TRCINTENB(x) ((x) << S_TRCINTENB)
14977 #define F_TRCINTENB V_TRCINTENB(1U)
14979 #define S_CLSINTENB 1
14980 #define V_CLSINTENB(x) ((x) << S_CLSINTENB)
14981 #define F_CLSINTENB V_CLSINTENB(1U)
14983 #define S_PLINTENB 0
14984 #define V_PLINTENB(x) ((x) << S_PLINTENB)
14985 #define F_PLINTENB V_PLINTENB(1U)
14987 #define A_MPS_INT_CAUSE 0x9008
14989 #define S_STATINT 5
14990 #define V_STATINT(x) ((x) << S_STATINT)
14991 #define F_STATINT V_STATINT(1U)
14994 #define V_TXINT(x) ((x) << S_TXINT)
14995 #define F_TXINT V_TXINT(1U)
14998 #define V_RXINT(x) ((x) << S_RXINT)
14999 #define F_RXINT V_RXINT(1U)
15002 #define V_TRCINT(x) ((x) << S_TRCINT)
15003 #define F_TRCINT V_TRCINT(1U)
15006 #define V_CLSINT(x) ((x) << S_CLSINT)
15007 #define F_CLSINT V_CLSINT(1U)
15010 #define V_PLINT(x) ((x) << S_PLINT)
15011 #define F_PLINT V_PLINT(1U)
15013 #define A_MPS_VF_TX_CTL_31_0 0x9010
15014 #define A_MPS_VF_TX_CTL_63_32 0x9014
15015 #define A_MPS_VF_TX_CTL_95_64 0x9018
15016 #define A_MPS_VF_TX_CTL_127_96 0x901c
15017 #define A_MPS_VF_RX_CTL_31_0 0x9020
15018 #define A_MPS_VF_RX_CTL_63_32 0x9024
15019 #define A_MPS_VF_RX_CTL_95_64 0x9028
15020 #define A_MPS_VF_RX_CTL_127_96 0x902c
15021 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP0 0x9030
15024 #define M_VALUE 0xffffU
15025 #define V_VALUE(x) ((x) << S_VALUE)
15026 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
15028 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP1 0x9034
15029 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP2 0x9038
15030 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP3 0x903c
15031 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP0 0x9040
15032 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP1 0x9044
15033 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP2 0x9048
15034 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP3 0x904c
15035 #define A_MPS_TP_CSIDE_MUX_CTL_P0 0x9050
15038 #define M_WEIGHT 0xfffU
15039 #define V_WEIGHT(x) ((x) << S_WEIGHT)
15040 #define G_WEIGHT(x) (((x) >> S_WEIGHT) & M_WEIGHT)
15042 #define A_MPS_TP_CSIDE_MUX_CTL_P1 0x9054
15043 #define A_MPS_WOL_CTL_MODE 0x9058
15045 #define S_WOL_MODE 0
15046 #define V_WOL_MODE(x) ((x) << S_WOL_MODE)
15047 #define F_WOL_MODE V_WOL_MODE(1U)
15049 #define A_MPS_FPGA_DEBUG 0x9060
15051 #define S_LPBK_EN 8
15052 #define V_LPBK_EN(x) ((x) << S_LPBK_EN)
15053 #define F_LPBK_EN V_LPBK_EN(1U)
15055 #define S_CH_MAP3 6
15056 #define M_CH_MAP3 0x3U
15057 #define V_CH_MAP3(x) ((x) << S_CH_MAP3)
15058 #define G_CH_MAP3(x) (((x) >> S_CH_MAP3) & M_CH_MAP3)
15060 #define S_CH_MAP2 4
15061 #define M_CH_MAP2 0x3U
15062 #define V_CH_MAP2(x) ((x) << S_CH_MAP2)
15063 #define G_CH_MAP2(x) (((x) >> S_CH_MAP2) & M_CH_MAP2)
15065 #define S_CH_MAP1 2
15066 #define M_CH_MAP1 0x3U
15067 #define V_CH_MAP1(x) ((x) << S_CH_MAP1)
15068 #define G_CH_MAP1(x) (((x) >> S_CH_MAP1) & M_CH_MAP1)
15070 #define S_CH_MAP0 0
15071 #define M_CH_MAP0 0x3U
15072 #define V_CH_MAP0(x) ((x) << S_CH_MAP0)
15073 #define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0)
15075 #define A_MPS_DEBUG_CTL 0x9068
15077 #define S_DBGMODECTL_H 11
15078 #define V_DBGMODECTL_H(x) ((x) << S_DBGMODECTL_H)
15079 #define F_DBGMODECTL_H V_DBGMODECTL_H(1U)
15081 #define S_DBGSEL_H 6
15082 #define M_DBGSEL_H 0x1fU
15083 #define V_DBGSEL_H(x) ((x) << S_DBGSEL_H)
15084 #define G_DBGSEL_H(x) (((x) >> S_DBGSEL_H) & M_DBGSEL_H)
15086 #define S_DBGMODECTL_L 5
15087 #define V_DBGMODECTL_L(x) ((x) << S_DBGMODECTL_L)
15088 #define F_DBGMODECTL_L V_DBGMODECTL_L(1U)
15090 #define S_DBGSEL_L 0
15091 #define M_DBGSEL_L 0x1fU
15092 #define V_DBGSEL_L(x) ((x) << S_DBGSEL_L)
15093 #define G_DBGSEL_L(x) (((x) >> S_DBGSEL_L) & M_DBGSEL_L)
15095 #define A_MPS_DEBUG_DATA_REG_L 0x906c
15096 #define A_MPS_DEBUG_DATA_REG_H 0x9070
15097 #define A_MPS_TOP_SPARE 0x9074
15099 #define S_TOPSPARE 12
15100 #define M_TOPSPARE 0xfffffU
15101 #define V_TOPSPARE(x) ((x) << S_TOPSPARE)
15102 #define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE)
15104 #define S_CHIKN_14463 8
15105 #define M_CHIKN_14463 0xfU
15106 #define V_CHIKN_14463(x) ((x) << S_CHIKN_14463)
15107 #define G_CHIKN_14463(x) (((x) >> S_CHIKN_14463) & M_CHIKN_14463)
15109 #define S_OVLANSELLPBK3 7
15110 #define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3)
15111 #define F_OVLANSELLPBK3 V_OVLANSELLPBK3(1U)
15113 #define S_OVLANSELLPBK2 6
15114 #define V_OVLANSELLPBK2(x) ((x) << S_OVLANSELLPBK2)
15115 #define F_OVLANSELLPBK2 V_OVLANSELLPBK2(1U)
15117 #define S_OVLANSELLPBK1 5
15118 #define V_OVLANSELLPBK1(x) ((x) << S_OVLANSELLPBK1)
15119 #define F_OVLANSELLPBK1 V_OVLANSELLPBK1(1U)
15121 #define S_OVLANSELLPBK0 4
15122 #define V_OVLANSELLPBK0(x) ((x) << S_OVLANSELLPBK0)
15123 #define F_OVLANSELLPBK0 V_OVLANSELLPBK0(1U)
15125 #define S_OVLANSELMAC3 3
15126 #define V_OVLANSELMAC3(x) ((x) << S_OVLANSELMAC3)
15127 #define F_OVLANSELMAC3 V_OVLANSELMAC3(1U)
15129 #define S_OVLANSELMAC2 2
15130 #define V_OVLANSELMAC2(x) ((x) << S_OVLANSELMAC2)
15131 #define F_OVLANSELMAC2 V_OVLANSELMAC2(1U)
15133 #define S_OVLANSELMAC1 1
15134 #define V_OVLANSELMAC1(x) ((x) << S_OVLANSELMAC1)
15135 #define F_OVLANSELMAC1 V_OVLANSELMAC1(1U)
15137 #define S_OVLANSELMAC0 0
15138 #define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0)
15139 #define F_OVLANSELMAC0 V_OVLANSELMAC0(1U)
15141 #define A_MPS_BUILD_REVISION 0x90fc
15142 #define A_MPS_TX_PRTY_SEL 0x9400
15144 #define S_CH4_PRTY 20
15145 #define M_CH4_PRTY 0x7U
15146 #define V_CH4_PRTY(x) ((x) << S_CH4_PRTY)
15147 #define G_CH4_PRTY(x) (((x) >> S_CH4_PRTY) & M_CH4_PRTY)
15149 #define S_CH3_PRTY 16
15150 #define M_CH3_PRTY 0x7U
15151 #define V_CH3_PRTY(x) ((x) << S_CH3_PRTY)
15152 #define G_CH3_PRTY(x) (((x) >> S_CH3_PRTY) & M_CH3_PRTY)
15154 #define S_CH2_PRTY 12
15155 #define M_CH2_PRTY 0x7U
15156 #define V_CH2_PRTY(x) ((x) << S_CH2_PRTY)
15157 #define G_CH2_PRTY(x) (((x) >> S_CH2_PRTY) & M_CH2_PRTY)
15159 #define S_CH1_PRTY 8
15160 #define M_CH1_PRTY 0x7U
15161 #define V_CH1_PRTY(x) ((x) << S_CH1_PRTY)
15162 #define G_CH1_PRTY(x) (((x) >> S_CH1_PRTY) & M_CH1_PRTY)
15164 #define S_CH0_PRTY 4
15165 #define M_CH0_PRTY 0x7U
15166 #define V_CH0_PRTY(x) ((x) << S_CH0_PRTY)
15167 #define G_CH0_PRTY(x) (((x) >> S_CH0_PRTY) & M_CH0_PRTY)
15169 #define S_TP_SOURCE 2
15170 #define M_TP_SOURCE 0x3U
15171 #define V_TP_SOURCE(x) ((x) << S_TP_SOURCE)
15172 #define G_TP_SOURCE(x) (((x) >> S_TP_SOURCE) & M_TP_SOURCE)
15174 #define S_NCSI_SOURCE 0
15175 #define M_NCSI_SOURCE 0x3U
15176 #define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE)
15177 #define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE)
15179 #define A_MPS_TX_INT_ENABLE 0x9404
15181 #define S_PORTERR 16
15182 #define V_PORTERR(x) ((x) << S_PORTERR)
15183 #define F_PORTERR V_PORTERR(1U)
15185 #define S_FRMERR 15
15186 #define V_FRMERR(x) ((x) << S_FRMERR)
15187 #define F_FRMERR V_FRMERR(1U)
15189 #define S_SECNTERR 14
15190 #define V_SECNTERR(x) ((x) << S_SECNTERR)
15191 #define F_SECNTERR V_SECNTERR(1U)
15193 #define S_BUBBLE 13
15194 #define V_BUBBLE(x) ((x) << S_BUBBLE)
15195 #define F_BUBBLE V_BUBBLE(1U)
15197 #define S_TXDESCFIFO 9
15198 #define M_TXDESCFIFO 0xfU
15199 #define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO)
15200 #define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO)
15202 #define S_TXDATAFIFO 5
15203 #define M_TXDATAFIFO 0xfU
15204 #define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO)
15205 #define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO)
15207 #define S_NCSIFIFO 4
15208 #define V_NCSIFIFO(x) ((x) << S_NCSIFIFO)
15209 #define F_NCSIFIFO V_NCSIFIFO(1U)
15212 #define M_TPFIFO 0xfU
15213 #define V_TPFIFO(x) ((x) << S_TPFIFO)
15214 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
15216 #define A_MPS_TX_INT_CAUSE 0x9408
15217 #define A_MPS_TX_PERR_ENABLE 0x9410
15218 #define A_MPS_TX_PERR_INJECT 0x9414
15220 #define S_MPSTXMEMSEL 1
15221 #define M_MPSTXMEMSEL 0x1fU
15222 #define V_MPSTXMEMSEL(x) ((x) << S_MPSTXMEMSEL)
15223 #define G_MPSTXMEMSEL(x) (((x) >> S_MPSTXMEMSEL) & M_MPSTXMEMSEL)
15225 #define A_MPS_TX_SE_CNT_TP01 0x9418
15226 #define A_MPS_TX_SE_CNT_TP23 0x941c
15227 #define A_MPS_TX_SE_CNT_MAC01 0x9420
15228 #define A_MPS_TX_SE_CNT_MAC23 0x9424
15229 #define A_MPS_TX_SECNT_SPI_BUBBLE_ERR 0x9428
15231 #define S_BUBBLEERR 16
15232 #define M_BUBBLEERR 0xffU
15233 #define V_BUBBLEERR(x) ((x) << S_BUBBLEERR)
15234 #define G_BUBBLEERR(x) (((x) >> S_BUBBLEERR) & M_BUBBLEERR)
15237 #define M_SPI 0xffU
15238 #define V_SPI(x) ((x) << S_SPI)
15239 #define G_SPI(x) (((x) >> S_SPI) & M_SPI)
15242 #define M_SECNT 0xffU
15243 #define V_SECNT(x) ((x) << S_SECNT)
15244 #define G_SECNT(x) (((x) >> S_SECNT) & M_SECNT)
15246 #define A_MPS_TX_SECNT_BUBBLE_CLR 0x942c
15248 #define S_BUBBLECLR 8
15249 #define M_BUBBLECLR 0xffU
15250 #define V_BUBBLECLR(x) ((x) << S_BUBBLECLR)
15251 #define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR)
15253 #define A_MPS_TX_PORT_ERR 0x9430
15255 #define S_LPBKPT3 7
15256 #define V_LPBKPT3(x) ((x) << S_LPBKPT3)
15257 #define F_LPBKPT3 V_LPBKPT3(1U)
15259 #define S_LPBKPT2 6
15260 #define V_LPBKPT2(x) ((x) << S_LPBKPT2)
15261 #define F_LPBKPT2 V_LPBKPT2(1U)
15263 #define S_LPBKPT1 5
15264 #define V_LPBKPT1(x) ((x) << S_LPBKPT1)
15265 #define F_LPBKPT1 V_LPBKPT1(1U)
15267 #define S_LPBKPT0 4
15268 #define V_LPBKPT0(x) ((x) << S_LPBKPT0)
15269 #define F_LPBKPT0 V_LPBKPT0(1U)
15272 #define V_PT3(x) ((x) << S_PT3)
15273 #define F_PT3 V_PT3(1U)
15276 #define V_PT2(x) ((x) << S_PT2)
15277 #define F_PT2 V_PT2(1U)
15280 #define V_PT1(x) ((x) << S_PT1)
15281 #define F_PT1 V_PT1(1U)
15284 #define V_PT0(x) ((x) << S_PT0)
15285 #define F_PT0 V_PT0(1U)
15287 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH0 0x9434
15290 #define V_BPEN(x) ((x) << S_BPEN)
15291 #define F_BPEN V_BPEN(1U)
15294 #define V_DROPEN(x) ((x) << S_DROPEN)
15295 #define F_DROPEN V_DROPEN(1U)
15297 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH1 0x9438
15298 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH2 0x943c
15299 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH3 0x9440
15300 #define A_MPS_TX_DEBUG_REG_TP2TX_10 0x9444
15302 #define S_SOPCH1 31
15303 #define V_SOPCH1(x) ((x) << S_SOPCH1)
15304 #define F_SOPCH1 V_SOPCH1(1U)
15306 #define S_EOPCH1 30
15307 #define V_EOPCH1(x) ((x) << S_EOPCH1)
15308 #define F_EOPCH1 V_EOPCH1(1U)
15310 #define S_SIZECH1 27
15311 #define M_SIZECH1 0x7U
15312 #define V_SIZECH1(x) ((x) << S_SIZECH1)
15313 #define G_SIZECH1(x) (((x) >> S_SIZECH1) & M_SIZECH1)
15315 #define S_ERRCH1 26
15316 #define V_ERRCH1(x) ((x) << S_ERRCH1)
15317 #define F_ERRCH1 V_ERRCH1(1U)
15319 #define S_FULLCH1 25
15320 #define V_FULLCH1(x) ((x) << S_FULLCH1)
15321 #define F_FULLCH1 V_FULLCH1(1U)
15323 #define S_VALIDCH1 24
15324 #define V_VALIDCH1(x) ((x) << S_VALIDCH1)
15325 #define F_VALIDCH1 V_VALIDCH1(1U)
15327 #define S_DATACH1 16
15328 #define M_DATACH1 0xffU
15329 #define V_DATACH1(x) ((x) << S_DATACH1)
15330 #define G_DATACH1(x) (((x) >> S_DATACH1) & M_DATACH1)
15332 #define S_SOPCH0 15
15333 #define V_SOPCH0(x) ((x) << S_SOPCH0)
15334 #define F_SOPCH0 V_SOPCH0(1U)
15336 #define S_EOPCH0 14
15337 #define V_EOPCH0(x) ((x) << S_EOPCH0)
15338 #define F_EOPCH0 V_EOPCH0(1U)
15340 #define S_SIZECH0 11
15341 #define M_SIZECH0 0x7U
15342 #define V_SIZECH0(x) ((x) << S_SIZECH0)
15343 #define G_SIZECH0(x) (((x) >> S_SIZECH0) & M_SIZECH0)
15345 #define S_ERRCH0 10
15346 #define V_ERRCH0(x) ((x) << S_ERRCH0)
15347 #define F_ERRCH0 V_ERRCH0(1U)
15349 #define S_FULLCH0 9
15350 #define V_FULLCH0(x) ((x) << S_FULLCH0)
15351 #define F_FULLCH0 V_FULLCH0(1U)
15353 #define S_VALIDCH0 8
15354 #define V_VALIDCH0(x) ((x) << S_VALIDCH0)
15355 #define F_VALIDCH0 V_VALIDCH0(1U)
15357 #define S_DATACH0 0
15358 #define M_DATACH0 0xffU
15359 #define V_DATACH0(x) ((x) << S_DATACH0)
15360 #define G_DATACH0(x) (((x) >> S_DATACH0) & M_DATACH0)
15362 #define A_MPS_TX_DEBUG_REG_TP2TX_32 0x9448
15364 #define S_SOPCH3 31
15365 #define V_SOPCH3(x) ((x) << S_SOPCH3)
15366 #define F_SOPCH3 V_SOPCH3(1U)
15368 #define S_EOPCH3 30
15369 #define V_EOPCH3(x) ((x) << S_EOPCH3)
15370 #define F_EOPCH3 V_EOPCH3(1U)
15372 #define S_SIZECH3 27
15373 #define M_SIZECH3 0x7U
15374 #define V_SIZECH3(x) ((x) << S_SIZECH3)
15375 #define G_SIZECH3(x) (((x) >> S_SIZECH3) & M_SIZECH3)
15377 #define S_ERRCH3 26
15378 #define V_ERRCH3(x) ((x) << S_ERRCH3)
15379 #define F_ERRCH3 V_ERRCH3(1U)
15381 #define S_FULLCH3 25
15382 #define V_FULLCH3(x) ((x) << S_FULLCH3)
15383 #define F_FULLCH3 V_FULLCH3(1U)
15385 #define S_VALIDCH3 24
15386 #define V_VALIDCH3(x) ((x) << S_VALIDCH3)
15387 #define F_VALIDCH3 V_VALIDCH3(1U)
15389 #define S_DATACH3 16
15390 #define M_DATACH3 0xffU
15391 #define V_DATACH3(x) ((x) << S_DATACH3)
15392 #define G_DATACH3(x) (((x) >> S_DATACH3) & M_DATACH3)
15394 #define S_SOPCH2 15
15395 #define V_SOPCH2(x) ((x) << S_SOPCH2)
15396 #define F_SOPCH2 V_SOPCH2(1U)
15398 #define S_EOPCH2 14
15399 #define V_EOPCH2(x) ((x) << S_EOPCH2)
15400 #define F_EOPCH2 V_EOPCH2(1U)
15402 #define S_SIZECH2 11
15403 #define M_SIZECH2 0x7U
15404 #define V_SIZECH2(x) ((x) << S_SIZECH2)
15405 #define G_SIZECH2(x) (((x) >> S_SIZECH2) & M_SIZECH2)
15407 #define S_ERRCH2 10
15408 #define V_ERRCH2(x) ((x) << S_ERRCH2)
15409 #define F_ERRCH2 V_ERRCH2(1U)
15411 #define S_FULLCH2 9
15412 #define V_FULLCH2(x) ((x) << S_FULLCH2)
15413 #define F_FULLCH2 V_FULLCH2(1U)
15415 #define S_VALIDCH2 8
15416 #define V_VALIDCH2(x) ((x) << S_VALIDCH2)
15417 #define F_VALIDCH2 V_VALIDCH2(1U)
15419 #define S_DATACH2 0
15420 #define M_DATACH2 0xffU
15421 #define V_DATACH2(x) ((x) << S_DATACH2)
15422 #define G_DATACH2(x) (((x) >> S_DATACH2) & M_DATACH2)
15424 #define A_MPS_TX_DEBUG_REG_TX2MAC_10 0x944c
15426 #define S_SOPPT1 31
15427 #define V_SOPPT1(x) ((x) << S_SOPPT1)
15428 #define F_SOPPT1 V_SOPPT1(1U)
15430 #define S_EOPPT1 30
15431 #define V_EOPPT1(x) ((x) << S_EOPPT1)
15432 #define F_EOPPT1 V_EOPPT1(1U)
15434 #define S_SIZEPT1 27
15435 #define M_SIZEPT1 0x7U
15436 #define V_SIZEPT1(x) ((x) << S_SIZEPT1)
15437 #define G_SIZEPT1(x) (((x) >> S_SIZEPT1) & M_SIZEPT1)
15439 #define S_ERRPT1 26
15440 #define V_ERRPT1(x) ((x) << S_ERRPT1)
15441 #define F_ERRPT1 V_ERRPT1(1U)
15443 #define S_FULLPT1 25
15444 #define V_FULLPT1(x) ((x) << S_FULLPT1)
15445 #define F_FULLPT1 V_FULLPT1(1U)
15447 #define S_VALIDPT1 24
15448 #define V_VALIDPT1(x) ((x) << S_VALIDPT1)
15449 #define F_VALIDPT1 V_VALIDPT1(1U)
15451 #define S_DATAPT1 16
15452 #define M_DATAPT1 0xffU
15453 #define V_DATAPT1(x) ((x) << S_DATAPT1)
15454 #define G_DATAPT1(x) (((x) >> S_DATAPT1) & M_DATAPT1)
15456 #define S_SOPPT0 15
15457 #define V_SOPPT0(x) ((x) << S_SOPPT0)
15458 #define F_SOPPT0 V_SOPPT0(1U)
15460 #define S_EOPPT0 14
15461 #define V_EOPPT0(x) ((x) << S_EOPPT0)
15462 #define F_EOPPT0 V_EOPPT0(1U)
15464 #define S_SIZEPT0 11
15465 #define M_SIZEPT0 0x7U
15466 #define V_SIZEPT0(x) ((x) << S_SIZEPT0)
15467 #define G_SIZEPT0(x) (((x) >> S_SIZEPT0) & M_SIZEPT0)
15469 #define S_ERRPT0 10
15470 #define V_ERRPT0(x) ((x) << S_ERRPT0)
15471 #define F_ERRPT0 V_ERRPT0(1U)
15473 #define S_FULLPT0 9
15474 #define V_FULLPT0(x) ((x) << S_FULLPT0)
15475 #define F_FULLPT0 V_FULLPT0(1U)
15477 #define S_VALIDPT0 8
15478 #define V_VALIDPT0(x) ((x) << S_VALIDPT0)
15479 #define F_VALIDPT0 V_VALIDPT0(1U)
15481 #define S_DATAPT0 0
15482 #define M_DATAPT0 0xffU
15483 #define V_DATAPT0(x) ((x) << S_DATAPT0)
15484 #define G_DATAPT0(x) (((x) >> S_DATAPT0) & M_DATAPT0)
15486 #define A_MPS_TX_DEBUG_REG_TX2MAC_32 0x9450
15488 #define S_SOPPT3 31
15489 #define V_SOPPT3(x) ((x) << S_SOPPT3)
15490 #define F_SOPPT3 V_SOPPT3(1U)
15492 #define S_EOPPT3 30
15493 #define V_EOPPT3(x) ((x) << S_EOPPT3)
15494 #define F_EOPPT3 V_EOPPT3(1U)
15496 #define S_SIZEPT3 27
15497 #define M_SIZEPT3 0x7U
15498 #define V_SIZEPT3(x) ((x) << S_SIZEPT3)
15499 #define G_SIZEPT3(x) (((x) >> S_SIZEPT3) & M_SIZEPT3)
15501 #define S_ERRPT3 26
15502 #define V_ERRPT3(x) ((x) << S_ERRPT3)
15503 #define F_ERRPT3 V_ERRPT3(1U)
15505 #define S_FULLPT3 25
15506 #define V_FULLPT3(x) ((x) << S_FULLPT3)
15507 #define F_FULLPT3 V_FULLPT3(1U)
15509 #define S_VALIDPT3 24
15510 #define V_VALIDPT3(x) ((x) << S_VALIDPT3)
15511 #define F_VALIDPT3 V_VALIDPT3(1U)
15513 #define S_DATAPT3 16
15514 #define M_DATAPT3 0xffU
15515 #define V_DATAPT3(x) ((x) << S_DATAPT3)
15516 #define G_DATAPT3(x) (((x) >> S_DATAPT3) & M_DATAPT3)
15518 #define S_SOPPT2 15
15519 #define V_SOPPT2(x) ((x) << S_SOPPT2)
15520 #define F_SOPPT2 V_SOPPT2(1U)
15522 #define S_EOPPT2 14
15523 #define V_EOPPT2(x) ((x) << S_EOPPT2)
15524 #define F_EOPPT2 V_EOPPT2(1U)
15526 #define S_SIZEPT2 11
15527 #define M_SIZEPT2 0x7U
15528 #define V_SIZEPT2(x) ((x) << S_SIZEPT2)
15529 #define G_SIZEPT2(x) (((x) >> S_SIZEPT2) & M_SIZEPT2)
15531 #define S_ERRPT2 10
15532 #define V_ERRPT2(x) ((x) << S_ERRPT2)
15533 #define F_ERRPT2 V_ERRPT2(1U)
15535 #define S_FULLPT2 9
15536 #define V_FULLPT2(x) ((x) << S_FULLPT2)
15537 #define F_FULLPT2 V_FULLPT2(1U)
15539 #define S_VALIDPT2 8
15540 #define V_VALIDPT2(x) ((x) << S_VALIDPT2)
15541 #define F_VALIDPT2 V_VALIDPT2(1U)
15543 #define S_DATAPT2 0
15544 #define M_DATAPT2 0xffU
15545 #define V_DATAPT2(x) ((x) << S_DATAPT2)
15546 #define G_DATAPT2(x) (((x) >> S_DATAPT2) & M_DATAPT2)
15548 #define A_MPS_TX_SGE_CH_PAUSE_IGNR 0x9454
15550 #define S_SGEPAUSEIGNR 0
15551 #define M_SGEPAUSEIGNR 0xfU
15552 #define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR)
15553 #define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR)
15555 #define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458
15557 #define S_SUBPRTH 11
15558 #define M_SUBPRTH 0x1fU
15559 #define V_SUBPRTH(x) ((x) << S_SUBPRTH)
15560 #define G_SUBPRTH(x) (((x) >> S_SUBPRTH) & M_SUBPRTH)
15563 #define M_PORTH 0x7U
15564 #define V_PORTH(x) ((x) << S_PORTH)
15565 #define G_PORTH(x) (((x) >> S_PORTH) & M_PORTH)
15567 #define S_SUBPRTL 3
15568 #define M_SUBPRTL 0x1fU
15569 #define V_SUBPRTL(x) ((x) << S_SUBPRTL)
15570 #define G_SUBPRTL(x) (((x) >> S_SUBPRTL) & M_SUBPRTL)
15573 #define M_PORTL 0x7U
15574 #define V_PORTL(x) ((x) << S_PORTL)
15575 #define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL)
15577 #define A_MPS_STAT_CTL 0x9600
15579 #define S_COUNTVFINPF 1
15580 #define V_COUNTVFINPF(x) ((x) << S_COUNTVFINPF)
15581 #define F_COUNTVFINPF V_COUNTVFINPF(1U)
15583 #define S_LPBKERRSTAT 0
15584 #define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT)
15585 #define F_LPBKERRSTAT V_LPBKERRSTAT(1U)
15587 #define A_MPS_STAT_INT_ENABLE 0x9608
15589 #define S_PLREADSYNCERR 0
15590 #define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR)
15591 #define F_PLREADSYNCERR V_PLREADSYNCERR(1U)
15593 #define A_MPS_STAT_INT_CAUSE 0x960c
15594 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM 0x9610
15597 #define V_RXBG(x) ((x) << S_RXBG)
15598 #define F_RXBG V_RXBG(1U)
15601 #define M_RXVF 0x3U
15602 #define V_RXVF(x) ((x) << S_RXVF)
15603 #define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF)
15606 #define M_TXVF 0x3U
15607 #define V_TXVF(x) ((x) << S_TXVF)
15608 #define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF)
15611 #define M_RXPF 0x7U
15612 #define V_RXPF(x) ((x) << S_RXPF)
15613 #define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF)
15616 #define M_TXPF 0x3U
15617 #define V_TXPF(x) ((x) << S_TXPF)
15618 #define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF)
15621 #define M_RXPORT 0xfU
15622 #define V_RXPORT(x) ((x) << S_RXPORT)
15623 #define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT)
15626 #define M_LBPORT 0x7U
15627 #define V_LBPORT(x) ((x) << S_LBPORT)
15628 #define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT)
15631 #define M_TXPORT 0xfU
15632 #define V_TXPORT(x) ((x) << S_TXPORT)
15633 #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)
15635 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
15636 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
15637 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
15641 #define V_TX(x) ((x) << S_TX)
15642 #define G_TX(x) (((x) >> S_TX) & M_TX)
15644 #define S_TXPAUSEFIFO 8
15645 #define M_TXPAUSEFIFO 0xfU
15646 #define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO)
15647 #define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO)
15650 #define M_DROP 0xffU
15651 #define V_DROP(x) ((x) << S_DROP)
15652 #define G_DROP(x) (((x) >> S_DROP) & M_DROP)
15654 #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
15655 #define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624
15656 #define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628
15658 #define S_PAUSEFIFO 20
15659 #define M_PAUSEFIFO 0xfU
15660 #define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO)
15661 #define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO)
15664 #define M_LPBK 0xfU
15665 #define V_LPBK(x) ((x) << S_LPBK)
15666 #define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK)
15670 #define V_NQ(x) ((x) << S_NQ)
15671 #define G_NQ(x) (((x) >> S_NQ) & M_NQ)
15675 #define V_PV(x) ((x) << S_PV)
15676 #define G_PV(x) (((x) >> S_PV) & M_PV)
15680 #define V_MAC(x) ((x) << S_MAC)
15681 #define G_MAC(x) (((x) >> S_MAC) & M_MAC)
15683 #define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
15684 #define A_MPS_STAT_PERR_ENABLE_RX_FIFO 0x9630
15685 #define A_MPS_STAT_PERR_INJECT 0x9634
15687 #define S_STATMEMSEL 1
15688 #define M_STATMEMSEL 0x7fU
15689 #define V_STATMEMSEL(x) ((x) << S_STATMEMSEL)
15690 #define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL)
15692 #define A_MPS_STAT_DEBUG_SUB_SEL 0x9638
15693 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
15694 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
15695 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
15696 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
15697 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
15698 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
15699 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
15700 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
15701 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
15702 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
15703 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
15704 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
15705 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
15706 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
15707 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
15708 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
15709 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
15710 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
15711 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
15712 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
15713 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
15714 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
15715 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
15716 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
15717 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
15718 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
15719 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
15720 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
15721 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
15722 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
15723 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
15724 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
15725 #define A_MPS_TRC_CFG 0x9800
15727 #define S_TRCFIFOEMPTY 4
15728 #define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY)
15729 #define F_TRCFIFOEMPTY V_TRCFIFOEMPTY(1U)
15731 #define S_TRCIGNOREDROPINPUT 3
15732 #define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT)
15733 #define F_TRCIGNOREDROPINPUT V_TRCIGNOREDROPINPUT(1U)
15735 #define S_TRCKEEPDUPLICATES 2
15736 #define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES)
15737 #define F_TRCKEEPDUPLICATES V_TRCKEEPDUPLICATES(1U)
15740 #define V_TRCEN(x) ((x) << S_TRCEN)
15741 #define F_TRCEN V_TRCEN(1U)
15743 #define S_TRCMULTIFILTER 0
15744 #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
15745 #define F_TRCMULTIFILTER V_TRCMULTIFILTER(1U)
15747 #define A_MPS_TRC_RSS_HASH 0x9804
15748 #define A_MPS_TRC_RSS_CONTROL 0x9808
15750 #define S_RSSCONTROL 16
15751 #define M_RSSCONTROL 0xffU
15752 #define V_RSSCONTROL(x) ((x) << S_RSSCONTROL)
15753 #define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL)
15755 #define S_QUEUENUMBER 0
15756 #define M_QUEUENUMBER 0xffffU
15757 #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
15758 #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)
15760 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
15762 #define S_TFINVERTMATCH 24
15763 #define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH)
15764 #define F_TFINVERTMATCH V_TFINVERTMATCH(1U)
15766 #define S_TFPKTTOOLARGE 23
15767 #define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE)
15768 #define F_TFPKTTOOLARGE V_TFPKTTOOLARGE(1U)
15771 #define V_TFEN(x) ((x) << S_TFEN)
15772 #define F_TFEN V_TFEN(1U)
15774 #define S_TFPORT 18
15775 #define M_TFPORT 0xfU
15776 #define V_TFPORT(x) ((x) << S_TFPORT)
15777 #define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT)
15779 #define S_TFDROP 17
15780 #define V_TFDROP(x) ((x) << S_TFDROP)
15781 #define F_TFDROP V_TFDROP(1U)
15783 #define S_TFSOPEOPERR 16
15784 #define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR)
15785 #define F_TFSOPEOPERR V_TFSOPEOPERR(1U)
15787 #define S_TFLENGTH 8
15788 #define M_TFLENGTH 0x1fU
15789 #define V_TFLENGTH(x) ((x) << S_TFLENGTH)
15790 #define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH)
15792 #define S_TFOFFSET 0
15793 #define M_TFOFFSET 0x1fU
15794 #define V_TFOFFSET(x) ((x) << S_TFOFFSET)
15795 #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)
15797 #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
15799 #define S_TFMINPKTSIZE 16
15800 #define M_TFMINPKTSIZE 0x1ffU
15801 #define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE)
15802 #define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE)
15804 #define S_TFCAPTUREMAX 0
15805 #define M_TFCAPTUREMAX 0x3fffU
15806 #define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX)
15807 #define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX)
15809 #define A_MPS_TRC_FILTER_RUNT_CTL 0x9830
15811 #define S_TFRUNTSIZE 0
15812 #define M_TFRUNTSIZE 0x3fU
15813 #define V_TFRUNTSIZE(x) ((x) << S_TFRUNTSIZE)
15814 #define G_TFRUNTSIZE(x) (((x) >> S_TFRUNTSIZE) & M_TFRUNTSIZE)
15816 #define A_MPS_TRC_FILTER_DROP 0x9840
15818 #define S_TFDROPINPCOUNT 16
15819 #define M_TFDROPINPCOUNT 0xffffU
15820 #define V_TFDROPINPCOUNT(x) ((x) << S_TFDROPINPCOUNT)
15821 #define G_TFDROPINPCOUNT(x) (((x) >> S_TFDROPINPCOUNT) & M_TFDROPINPCOUNT)
15823 #define S_TFDROPBUFFERCOUNT 0
15824 #define M_TFDROPBUFFERCOUNT 0xffffU
15825 #define V_TFDROPBUFFERCOUNT(x) ((x) << S_TFDROPBUFFERCOUNT)
15826 #define G_TFDROPBUFFERCOUNT(x) (((x) >> S_TFDROPBUFFERCOUNT) & M_TFDROPBUFFERCOUNT)
15828 #define A_MPS_TRC_PERR_INJECT 0x9850
15830 #define S_TRCMEMSEL 1
15831 #define M_TRCMEMSEL 0xfU
15832 #define V_TRCMEMSEL(x) ((x) << S_TRCMEMSEL)
15833 #define G_TRCMEMSEL(x) (((x) >> S_TRCMEMSEL) & M_TRCMEMSEL)
15835 #define A_MPS_TRC_PERR_ENABLE 0x9854
15837 #define S_MISCPERR 8
15838 #define V_MISCPERR(x) ((x) << S_MISCPERR)
15839 #define F_MISCPERR V_MISCPERR(1U)
15841 #define S_PKTFIFO 4
15842 #define M_PKTFIFO 0xfU
15843 #define V_PKTFIFO(x) ((x) << S_PKTFIFO)
15844 #define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO)
15846 #define S_FILTMEM 0
15847 #define M_FILTMEM 0xfU
15848 #define V_FILTMEM(x) ((x) << S_FILTMEM)
15849 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
15851 #define A_MPS_TRC_INT_ENABLE 0x9858
15853 #define S_TRCPLERRENB 9
15854 #define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB)
15855 #define F_TRCPLERRENB V_TRCPLERRENB(1U)
15857 #define A_MPS_TRC_INT_CAUSE 0x985c
15858 #define A_MPS_TRC_TIMESTAMP_L 0x9860
15859 #define A_MPS_TRC_TIMESTAMP_H 0x9864
15860 #define A_MPS_TRC_FILTER0_MATCH 0x9c00
15861 #define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
15862 #define A_MPS_TRC_FILTER1_MATCH 0x9d00
15863 #define A_MPS_TRC_FILTER1_DONT_CARE 0x9d80
15864 #define A_MPS_TRC_FILTER2_MATCH 0x9e00
15865 #define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80
15866 #define A_MPS_TRC_FILTER3_MATCH 0x9f00
15867 #define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80
15868 #define A_MPS_CLS_CTL 0xd000
15870 #define S_MEMWRITEFAULT 4
15871 #define V_MEMWRITEFAULT(x) ((x) << S_MEMWRITEFAULT)
15872 #define F_MEMWRITEFAULT V_MEMWRITEFAULT(1U)
15874 #define S_MEMWRITEWAITING 3
15875 #define V_MEMWRITEWAITING(x) ((x) << S_MEMWRITEWAITING)
15876 #define F_MEMWRITEWAITING V_MEMWRITEWAITING(1U)
15878 #define S_CIMNOPROMISCUOUS 2
15879 #define V_CIMNOPROMISCUOUS(x) ((x) << S_CIMNOPROMISCUOUS)
15880 #define F_CIMNOPROMISCUOUS V_CIMNOPROMISCUOUS(1U)
15882 #define S_HYPERVISORONLY 1
15883 #define V_HYPERVISORONLY(x) ((x) << S_HYPERVISORONLY)
15884 #define F_HYPERVISORONLY V_HYPERVISORONLY(1U)
15886 #define S_VLANCLSEN 0
15887 #define V_VLANCLSEN(x) ((x) << S_VLANCLSEN)
15888 #define F_VLANCLSEN V_VLANCLSEN(1U)
15890 #define A_MPS_CLS_ARB_WEIGHT 0xd004
15892 #define S_PLWEIGHT 16
15893 #define M_PLWEIGHT 0x1fU
15894 #define V_PLWEIGHT(x) ((x) << S_PLWEIGHT)
15895 #define G_PLWEIGHT(x) (((x) >> S_PLWEIGHT) & M_PLWEIGHT)
15897 #define S_CIMWEIGHT 8
15898 #define M_CIMWEIGHT 0x1fU
15899 #define V_CIMWEIGHT(x) ((x) << S_CIMWEIGHT)
15900 #define G_CIMWEIGHT(x) (((x) >> S_CIMWEIGHT) & M_CIMWEIGHT)
15902 #define S_LPBKWEIGHT 0
15903 #define M_LPBKWEIGHT 0x1fU
15904 #define V_LPBKWEIGHT(x) ((x) << S_LPBKWEIGHT)
15905 #define G_LPBKWEIGHT(x) (((x) >> S_LPBKWEIGHT) & M_LPBKWEIGHT)
15907 #define A_MPS_CLS_BMC_MAC_ADDR_L 0xd010
15908 #define A_MPS_CLS_BMC_MAC_ADDR_H 0xd014
15909 #define A_MPS_CLS_BMC_VLAN 0xd018
15910 #define A_MPS_CLS_PERR_INJECT 0xd01c
15912 #define S_CLS_MEMSEL 1
15913 #define M_CLS_MEMSEL 0x3U
15914 #define V_CLS_MEMSEL(x) ((x) << S_CLS_MEMSEL)
15915 #define G_CLS_MEMSEL(x) (((x) >> S_CLS_MEMSEL) & M_CLS_MEMSEL)
15917 #define A_MPS_CLS_PERR_ENABLE 0xd020
15919 #define S_HASHSRAM 2
15920 #define V_HASHSRAM(x) ((x) << S_HASHSRAM)
15921 #define F_HASHSRAM V_HASHSRAM(1U)
15923 #define S_MATCHTCAM 1
15924 #define V_MATCHTCAM(x) ((x) << S_MATCHTCAM)
15925 #define F_MATCHTCAM V_MATCHTCAM(1U)
15927 #define S_MATCHSRAM 0
15928 #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
15929 #define F_MATCHSRAM V_MATCHSRAM(1U)
15931 #define A_MPS_CLS_INT_ENABLE 0xd024
15933 #define S_PLERRENB 3
15934 #define V_PLERRENB(x) ((x) << S_PLERRENB)
15935 #define F_PLERRENB V_PLERRENB(1U)
15937 #define A_MPS_CLS_INT_CAUSE 0xd028
15938 #define A_MPS_CLS_PL_TEST_DATA_L 0xd02c
15939 #define A_MPS_CLS_PL_TEST_DATA_H 0xd030
15940 #define A_MPS_CLS_PL_TEST_RES_DATA 0xd034
15942 #define S_CLS_PRIORITY 24
15943 #define M_CLS_PRIORITY 0x7U
15944 #define V_CLS_PRIORITY(x) ((x) << S_CLS_PRIORITY)
15945 #define G_CLS_PRIORITY(x) (((x) >> S_CLS_PRIORITY) & M_CLS_PRIORITY)
15947 #define S_CLS_REPLICATE 23
15948 #define V_CLS_REPLICATE(x) ((x) << S_CLS_REPLICATE)
15949 #define F_CLS_REPLICATE V_CLS_REPLICATE(1U)
15951 #define S_CLS_INDEX 14
15952 #define M_CLS_INDEX 0x1ffU
15953 #define V_CLS_INDEX(x) ((x) << S_CLS_INDEX)
15954 #define G_CLS_INDEX(x) (((x) >> S_CLS_INDEX) & M_CLS_INDEX)
15957 #define M_CLS_VF 0x7fU
15958 #define V_CLS_VF(x) ((x) << S_CLS_VF)
15959 #define G_CLS_VF(x) (((x) >> S_CLS_VF) & M_CLS_VF)
15961 #define S_CLS_VF_VLD 6
15962 #define V_CLS_VF_VLD(x) ((x) << S_CLS_VF_VLD)
15963 #define F_CLS_VF_VLD V_CLS_VF_VLD(1U)
15966 #define M_CLS_PF 0x7U
15967 #define V_CLS_PF(x) ((x) << S_CLS_PF)
15968 #define G_CLS_PF(x) (((x) >> S_CLS_PF) & M_CLS_PF)
15970 #define S_CLS_MATCH 0
15971 #define M_CLS_MATCH 0x7U
15972 #define V_CLS_MATCH(x) ((x) << S_CLS_MATCH)
15973 #define G_CLS_MATCH(x) (((x) >> S_CLS_MATCH) & M_CLS_MATCH)
15975 #define A_MPS_CLS_PL_TEST_CTL 0xd038
15977 #define S_PLTESTCTL 0
15978 #define V_PLTESTCTL(x) ((x) << S_PLTESTCTL)
15979 #define F_PLTESTCTL V_PLTESTCTL(1U)
15981 #define A_MPS_CLS_PORT_BMC_CTL 0xd03c
15983 #define S_PRTBMCCTL 0
15984 #define V_PRTBMCCTL(x) ((x) << S_PRTBMCCTL)
15985 #define F_PRTBMCCTL V_PRTBMCCTL(1U)
15987 #define A_MPS_CLS_VLAN_TABLE 0xdfc0
15989 #define S_VLAN_MASK 16
15990 #define M_VLAN_MASK 0xfffU
15991 #define V_VLAN_MASK(x) ((x) << S_VLAN_MASK)
15992 #define G_VLAN_MASK(x) (((x) >> S_VLAN_MASK) & M_VLAN_MASK)
15994 #define S_VLANPF 13
15995 #define M_VLANPF 0x7U
15996 #define V_VLANPF(x) ((x) << S_VLANPF)
15997 #define G_VLANPF(x) (((x) >> S_VLANPF) & M_VLANPF)
15999 #define S_VLAN_VALID 12
16000 #define V_VLAN_VALID(x) ((x) << S_VLAN_VALID)
16001 #define F_VLAN_VALID V_VLAN_VALID(1U)
16003 #define A_MPS_CLS_SRAM_L 0xe000
16005 #define S_MULTILISTEN3 28
16006 #define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3)
16007 #define F_MULTILISTEN3 V_MULTILISTEN3(1U)
16009 #define S_MULTILISTEN2 27
16010 #define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2)
16011 #define F_MULTILISTEN2 V_MULTILISTEN2(1U)
16013 #define S_MULTILISTEN1 26
16014 #define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1)
16015 #define F_MULTILISTEN1 V_MULTILISTEN1(1U)
16017 #define S_MULTILISTEN0 25
16018 #define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0)
16019 #define F_MULTILISTEN0 V_MULTILISTEN0(1U)
16021 #define S_SRAM_PRIO3 22
16022 #define M_SRAM_PRIO3 0x7U
16023 #define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3)
16024 #define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3)
16026 #define S_SRAM_PRIO2 19
16027 #define M_SRAM_PRIO2 0x7U
16028 #define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2)
16029 #define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2)
16031 #define S_SRAM_PRIO1 16
16032 #define M_SRAM_PRIO1 0x7U
16033 #define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1)
16034 #define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1)
16036 #define S_SRAM_PRIO0 13
16037 #define M_SRAM_PRIO0 0x7U
16038 #define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0)
16039 #define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0)
16041 #define S_SRAM_VLD 12
16042 #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
16043 #define F_SRAM_VLD V_SRAM_VLD(1U)
16045 #define A_MPS_CLS_SRAM_H 0xe004
16047 #define S_MACPARITY1 9
16048 #define V_MACPARITY1(x) ((x) << S_MACPARITY1)
16049 #define F_MACPARITY1 V_MACPARITY1(1U)
16051 #define S_MACPARITY0 8
16052 #define V_MACPARITY0(x) ((x) << S_MACPARITY0)
16053 #define F_MACPARITY0 V_MACPARITY0(1U)
16055 #define S_MACPARITYMASKSIZE 4
16056 #define M_MACPARITYMASKSIZE 0xfU
16057 #define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE)
16058 #define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)
16060 #define S_PORTMAP 0
16061 #define M_PORTMAP 0xfU
16062 #define V_PORTMAP(x) ((x) << S_PORTMAP)
16063 #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
16065 #define A_MPS_CLS_TCAM_Y_L 0xf000
16066 #define A_MPS_CLS_TCAM_Y_H 0xf004
16069 #define M_TCAMYH 0xffffU
16070 #define V_TCAMYH(x) ((x) << S_TCAMYH)
16071 #define G_TCAMYH(x) (((x) >> S_TCAMYH) & M_TCAMYH)
16073 #define A_MPS_CLS_TCAM_X_L 0xf008
16074 #define A_MPS_CLS_TCAM_X_H 0xf00c
16077 #define M_TCAMXH 0xffffU
16078 #define V_TCAMXH(x) ((x) << S_TCAMXH)
16079 #define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH)
16081 #define A_MPS_RX_CTL 0x11000
16083 #define S_FILT_VLAN_SEL 17
16084 #define V_FILT_VLAN_SEL(x) ((x) << S_FILT_VLAN_SEL)
16085 #define F_FILT_VLAN_SEL V_FILT_VLAN_SEL(1U)
16087 #define S_CBA_EN 16
16088 #define V_CBA_EN(x) ((x) << S_CBA_EN)
16089 #define F_CBA_EN V_CBA_EN(1U)
16091 #define S_BLK_SNDR 12
16092 #define M_BLK_SNDR 0xfU
16093 #define V_BLK_SNDR(x) ((x) << S_BLK_SNDR)
16094 #define G_BLK_SNDR(x) (((x) >> S_BLK_SNDR) & M_BLK_SNDR)
16097 #define M_CMPRS 0xfU
16098 #define V_CMPRS(x) ((x) << S_CMPRS)
16099 #define G_CMPRS(x) (((x) >> S_CMPRS) & M_CMPRS)
16102 #define M_SNF 0xffU
16103 #define V_SNF(x) ((x) << S_SNF)
16104 #define G_SNF(x) (((x) >> S_SNF) & M_SNF)
16106 #define A_MPS_RX_PORT_MUX_CTL 0x11004
16108 #define S_CTL_P3 12
16109 #define M_CTL_P3 0xfU
16110 #define V_CTL_P3(x) ((x) << S_CTL_P3)
16111 #define G_CTL_P3(x) (((x) >> S_CTL_P3) & M_CTL_P3)
16114 #define M_CTL_P2 0xfU
16115 #define V_CTL_P2(x) ((x) << S_CTL_P2)
16116 #define G_CTL_P2(x) (((x) >> S_CTL_P2) & M_CTL_P2)
16119 #define M_CTL_P1 0xfU
16120 #define V_CTL_P1(x) ((x) << S_CTL_P1)
16121 #define G_CTL_P1(x) (((x) >> S_CTL_P1) & M_CTL_P1)
16124 #define M_CTL_P0 0xfU
16125 #define V_CTL_P0(x) ((x) << S_CTL_P0)
16126 #define G_CTL_P0(x) (((x) >> S_CTL_P0) & M_CTL_P0)
16128 #define A_MPS_RX_PG_FL 0x11008
16131 #define V_RST(x) ((x) << S_RST)
16132 #define F_RST V_RST(1U)
16135 #define M_CNT 0xffffU
16136 #define V_CNT(x) ((x) << S_CNT)
16137 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
16139 #define A_MPS_RX_PKT_FL 0x1100c
16140 #define A_MPS_RX_PG_RSV0 0x11010
16142 #define S_CLR_INTR 31
16143 #define V_CLR_INTR(x) ((x) << S_CLR_INTR)
16144 #define F_CLR_INTR V_CLR_INTR(1U)
16146 #define S_SET_INTR 30
16147 #define V_SET_INTR(x) ((x) << S_SET_INTR)
16148 #define F_SET_INTR V_SET_INTR(1U)
16151 #define M_USED 0x7ffU
16152 #define V_USED(x) ((x) << S_USED)
16153 #define G_USED(x) (((x) >> S_USED) & M_USED)
16156 #define M_ALLOC 0x7ffU
16157 #define V_ALLOC(x) ((x) << S_ALLOC)
16158 #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)
16160 #define A_MPS_RX_PG_RSV1 0x11014
16161 #define A_MPS_RX_PG_RSV2 0x11018
16162 #define A_MPS_RX_PG_RSV3 0x1101c
16163 #define A_MPS_RX_PG_RSV4 0x11020
16164 #define A_MPS_RX_PG_RSV5 0x11024
16165 #define A_MPS_RX_PG_RSV6 0x11028
16166 #define A_MPS_RX_PG_RSV7 0x1102c
16167 #define A_MPS_RX_PG_SHR_BG0 0x11030
16170 #define V_EN(x) ((x) << S_EN)
16171 #define F_EN V_EN(1U)
16174 #define V_SEL(x) ((x) << S_SEL)
16175 #define F_SEL V_SEL(1U)
16178 #define M_MAX 0x7ffU
16179 #define V_MAX(x) ((x) << S_MAX)
16180 #define G_MAX(x) (((x) >> S_MAX) & M_MAX)
16183 #define M_BORW 0x7ffU
16184 #define V_BORW(x) ((x) << S_BORW)
16185 #define G_BORW(x) (((x) >> S_BORW) & M_BORW)
16187 #define A_MPS_RX_PG_SHR_BG1 0x11034
16188 #define A_MPS_RX_PG_SHR_BG2 0x11038
16189 #define A_MPS_RX_PG_SHR_BG3 0x1103c
16190 #define A_MPS_RX_PG_SHR0 0x11040
16193 #define M_QUOTA 0x7ffU
16194 #define V_QUOTA(x) ((x) << S_QUOTA)
16195 #define G_QUOTA(x) (((x) >> S_QUOTA) & M_QUOTA)
16197 #define S_SHR_USED 0
16198 #define M_SHR_USED 0x7ffU
16199 #define V_SHR_USED(x) ((x) << S_SHR_USED)
16200 #define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED)
16202 #define A_MPS_RX_PG_SHR1 0x11044
16203 #define A_MPS_RX_PG_HYST_BG0 0x11048
16206 #define M_TH 0x7ffU
16207 #define V_TH(x) ((x) << S_TH)
16208 #define G_TH(x) (((x) >> S_TH) & M_TH)
16210 #define A_MPS_RX_PG_HYST_BG1 0x1104c
16211 #define A_MPS_RX_PG_HYST_BG2 0x11050
16212 #define A_MPS_RX_PG_HYST_BG3 0x11054
16213 #define A_MPS_RX_OCH_CTL 0x11058
16215 #define S_DROP_WT 27
16216 #define M_DROP_WT 0x1fU
16217 #define V_DROP_WT(x) ((x) << S_DROP_WT)
16218 #define G_DROP_WT(x) (((x) >> S_DROP_WT) & M_DROP_WT)
16220 #define S_TRUNC_WT 22
16221 #define M_TRUNC_WT 0x1fU
16222 #define V_TRUNC_WT(x) ((x) << S_TRUNC_WT)
16223 #define G_TRUNC_WT(x) (((x) >> S_TRUNC_WT) & M_TRUNC_WT)
16225 #define S_OCH_DRAIN 13
16226 #define M_OCH_DRAIN 0x1fU
16227 #define V_OCH_DRAIN(x) ((x) << S_OCH_DRAIN)
16228 #define G_OCH_DRAIN(x) (((x) >> S_OCH_DRAIN) & M_OCH_DRAIN)
16230 #define S_OCH_DROP 8
16231 #define M_OCH_DROP 0x1fU
16232 #define V_OCH_DROP(x) ((x) << S_OCH_DROP)
16233 #define G_OCH_DROP(x) (((x) >> S_OCH_DROP) & M_OCH_DROP)
16236 #define M_STOP 0x1fU
16237 #define V_STOP(x) ((x) << S_STOP)
16238 #define G_STOP(x) (((x) >> S_STOP) & M_STOP)
16240 #define A_MPS_RX_LPBK_BP0 0x1105c
16243 #define M_THRESH 0x7ffU
16244 #define V_THRESH(x) ((x) << S_THRESH)
16245 #define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH)
16247 #define A_MPS_RX_LPBK_BP1 0x11060
16248 #define A_MPS_RX_LPBK_BP2 0x11064
16249 #define A_MPS_RX_LPBK_BP3 0x11068
16250 #define A_MPS_RX_PORT_GAP 0x1106c
16253 #define M_GAP 0xfffffU
16254 #define V_GAP(x) ((x) << S_GAP)
16255 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
16257 #define A_MPS_RX_CHMN_CNT 0x11070
16258 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
16261 #define V_FF(x) ((x) << S_FF)
16262 #define F_FF V_FF(1U)
16265 #define V_PGMO(x) ((x) << S_PGMO)
16266 #define F_PGMO V_PGMO(1U)
16269 #define V_PGME(x) ((x) << S_PGME)
16270 #define F_PGME V_PGME(1U)
16273 #define V_CHMN(x) ((x) << S_CHMN)
16274 #define F_CHMN V_CHMN(1U)
16277 #define V_RPLC(x) ((x) << S_RPLC)
16278 #define F_RPLC V_RPLC(1U)
16281 #define V_ATRB(x) ((x) << S_ATRB)
16282 #define F_ATRB V_ATRB(1U)
16285 #define V_PSMX(x) ((x) << S_PSMX)
16286 #define F_PSMX V_PSMX(1U)
16289 #define V_PGLL(x) ((x) << S_PGLL)
16290 #define F_PGLL V_PGLL(1U)
16293 #define V_PGFL(x) ((x) << S_PGFL)
16294 #define F_PGFL V_PGFL(1U)
16297 #define V_PKTQ(x) ((x) << S_PKTQ)
16298 #define F_PKTQ V_PKTQ(1U)
16301 #define V_PKFL(x) ((x) << S_PKFL)
16302 #define F_PKFL V_PKFL(1U)
16305 #define V_PPM3(x) ((x) << S_PPM3)
16306 #define F_PPM3 V_PPM3(1U)
16309 #define V_PPM2(x) ((x) << S_PPM2)
16310 #define F_PPM2 V_PPM2(1U)
16313 #define V_PPM1(x) ((x) << S_PPM1)
16314 #define F_PPM1 V_PPM1(1U)
16317 #define V_PPM0(x) ((x) << S_PPM0)
16318 #define F_PPM0 V_PPM0(1U)
16321 #define V_SPMX(x) ((x) << S_SPMX)
16322 #define F_SPMX V_SPMX(1U)
16325 #define V_CDL3(x) ((x) << S_CDL3)
16326 #define F_CDL3 V_CDL3(1U)
16329 #define V_CDL2(x) ((x) << S_CDL2)
16330 #define F_CDL2 V_CDL2(1U)
16333 #define V_CDL1(x) ((x) << S_CDL1)
16334 #define F_CDL1 V_CDL1(1U)
16337 #define V_CDL0(x) ((x) << S_CDL0)
16338 #define F_CDL0 V_CDL0(1U)
16341 #define V_CDM3(x) ((x) << S_CDM3)
16342 #define F_CDM3 V_CDM3(1U)
16345 #define V_CDM2(x) ((x) << S_CDM2)
16346 #define F_CDM2 V_CDM2(1U)
16349 #define V_CDM1(x) ((x) << S_CDM1)
16350 #define F_CDM1 V_CDM1(1U)
16353 #define V_CDM0(x) ((x) << S_CDM0)
16354 #define F_CDM0 V_CDM0(1U)
16356 #define A_MPS_RX_PERR_INT_ENABLE 0x11078
16357 #define A_MPS_RX_PERR_ENABLE 0x1107c
16358 #define A_MPS_RX_PERR_INJECT 0x11080
16359 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
16361 #define S_INT_ERR_INT 8
16362 #define M_INT_ERR_INT 0x1fU
16363 #define V_INT_ERR_INT(x) ((x) << S_INT_ERR_INT)
16364 #define G_INT_ERR_INT(x) (((x) >> S_INT_ERR_INT) & M_INT_ERR_INT)
16366 #define S_PG_TH_INT7 7
16367 #define V_PG_TH_INT7(x) ((x) << S_PG_TH_INT7)
16368 #define F_PG_TH_INT7 V_PG_TH_INT7(1U)
16370 #define S_PG_TH_INT6 6
16371 #define V_PG_TH_INT6(x) ((x) << S_PG_TH_INT6)
16372 #define F_PG_TH_INT6 V_PG_TH_INT6(1U)
16374 #define S_PG_TH_INT5 5
16375 #define V_PG_TH_INT5(x) ((x) << S_PG_TH_INT5)
16376 #define F_PG_TH_INT5 V_PG_TH_INT5(1U)
16378 #define S_PG_TH_INT4 4
16379 #define V_PG_TH_INT4(x) ((x) << S_PG_TH_INT4)
16380 #define F_PG_TH_INT4 V_PG_TH_INT4(1U)
16382 #define S_PG_TH_INT3 3
16383 #define V_PG_TH_INT3(x) ((x) << S_PG_TH_INT3)
16384 #define F_PG_TH_INT3 V_PG_TH_INT3(1U)
16386 #define S_PG_TH_INT2 2
16387 #define V_PG_TH_INT2(x) ((x) << S_PG_TH_INT2)
16388 #define F_PG_TH_INT2 V_PG_TH_INT2(1U)
16390 #define S_PG_TH_INT1 1
16391 #define V_PG_TH_INT1(x) ((x) << S_PG_TH_INT1)
16392 #define F_PG_TH_INT1 V_PG_TH_INT1(1U)
16394 #define S_PG_TH_INT0 0
16395 #define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0)
16396 #define F_PG_TH_INT0 V_PG_TH_INT0(1U)
16398 #define A_MPS_RX_FUNC_INT_ENABLE 0x11088
16399 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
16401 #define S_TH_HIGH 16
16402 #define M_TH_HIGH 0xffffU
16403 #define V_TH_HIGH(x) ((x) << S_TH_HIGH)
16404 #define G_TH_HIGH(x) (((x) >> S_TH_HIGH) & M_TH_HIGH)
16407 #define M_TH_LOW 0xffffU
16408 #define V_TH_LOW(x) ((x) << S_TH_LOW)
16409 #define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW)
16411 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
16412 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
16413 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
16414 #define A_MPS_RX_PPP_ATRB 0x1109c
16417 #define M_ETYPE 0xffffU
16418 #define V_ETYPE(x) ((x) << S_ETYPE)
16419 #define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE)
16422 #define M_OPCODE 0xffffU
16423 #define V_OPCODE(x) ((x) << S_OPCODE)
16424 #define G_OPCODE(x) (((x) >> S_OPCODE) & M_OPCODE)
16426 #define A_MPS_RX_QFC0_ATRB 0x110a0
16429 #define M_DA 0xffffU
16430 #define V_DA(x) ((x) << S_DA)
16431 #define G_DA(x) (((x) >> S_DA) & M_DA)
16433 #define A_MPS_RX_QFC1_ATRB 0x110a4
16434 #define A_MPS_RX_PT_ARB0 0x110a8
16436 #define S_LPBK_WT 16
16437 #define M_LPBK_WT 0x3fffU
16438 #define V_LPBK_WT(x) ((x) << S_LPBK_WT)
16439 #define G_LPBK_WT(x) (((x) >> S_LPBK_WT) & M_LPBK_WT)
16442 #define M_MAC_WT 0x3fffU
16443 #define V_MAC_WT(x) ((x) << S_MAC_WT)
16444 #define G_MAC_WT(x) (((x) >> S_MAC_WT) & M_MAC_WT)
16446 #define A_MPS_RX_PT_ARB1 0x110ac
16447 #define A_MPS_RX_PT_ARB2 0x110b0
16448 #define A_MPS_RX_PT_ARB3 0x110b4
16449 #define A_MPS_RX_PT_ARB4 0x110b8
16450 #define A_MPS_PF_OUT_EN 0x110bc
16453 #define M_OUTEN 0xffU
16454 #define V_OUTEN(x) ((x) << S_OUTEN)
16455 #define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN)
16457 #define A_MPS_BMC_MTU 0x110c0
16460 #define M_MTU 0x3fffU
16461 #define V_MTU(x) ((x) << S_MTU)
16462 #define G_MTU(x) (((x) >> S_MTU) & M_MTU)
16464 #define A_MPS_BMC_PKT_CNT 0x110c4
16465 #define A_MPS_BMC_BYTE_CNT 0x110c8
16466 #define A_MPS_PFVF_ATRB_CTL 0x110cc
16468 #define S_RD_WRN 31
16469 #define V_RD_WRN(x) ((x) << S_RD_WRN)
16470 #define F_RD_WRN V_RD_WRN(1U)
16473 #define M_PFVF 0xffU
16474 #define V_PFVF(x) ((x) << S_PFVF)
16475 #define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF)
16477 #define A_MPS_PFVF_ATRB 0x110d0
16479 #define S_ATTR_PF 28
16480 #define M_ATTR_PF 0x7U
16481 #define V_ATTR_PF(x) ((x) << S_ATTR_PF)
16482 #define G_ATTR_PF(x) (((x) >> S_ATTR_PF) & M_ATTR_PF)
16485 #define V_OFF(x) ((x) << S_OFF)
16486 #define F_OFF V_OFF(1U)
16488 #define S_NV_DROP 17
16489 #define V_NV_DROP(x) ((x) << S_NV_DROP)
16490 #define F_NV_DROP V_NV_DROP(1U)
16492 #define S_ATTR_MODE 16
16493 #define V_ATTR_MODE(x) ((x) << S_ATTR_MODE)
16494 #define F_ATTR_MODE V_ATTR_MODE(1U)
16496 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4
16498 #define S_VLAN_EN 16
16499 #define V_VLAN_EN(x) ((x) << S_VLAN_EN)
16500 #define F_VLAN_EN V_VLAN_EN(1U)
16502 #define S_VLAN_ID 0
16503 #define M_VLAN_ID 0xfffU
16504 #define V_VLAN_ID(x) ((x) << S_VLAN_ID)
16505 #define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID)
16507 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8
16508 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc
16509 #define A_MPS_PFVF_ATRB_FLTR3 0x110e0
16510 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4
16511 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8
16512 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec
16513 #define A_MPS_PFVF_ATRB_FLTR7 0x110f0
16514 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4
16515 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8
16516 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc
16517 #define A_MPS_PFVF_ATRB_FLTR11 0x11100
16518 #define A_MPS_PFVF_ATRB_FLTR12 0x11104
16519 #define A_MPS_PFVF_ATRB_FLTR13 0x11108
16520 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c
16521 #define A_MPS_PFVF_ATRB_FLTR15 0x11110
16522 #define A_MPS_RPLC_MAP_CTL 0x11114
16524 #define S_RPLC_MAP_ADDR 0
16525 #define M_RPLC_MAP_ADDR 0x3ffU
16526 #define V_RPLC_MAP_ADDR(x) ((x) << S_RPLC_MAP_ADDR)
16527 #define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR)
16529 #define A_MPS_PF_RPLCT_MAP 0x11118
16532 #define M_PF_EN 0xffU
16533 #define V_PF_EN(x) ((x) << S_PF_EN)
16534 #define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN)
16536 #define A_MPS_VF_RPLCT_MAP0 0x1111c
16537 #define A_MPS_VF_RPLCT_MAP1 0x11120
16538 #define A_MPS_VF_RPLCT_MAP2 0x11124
16539 #define A_MPS_VF_RPLCT_MAP3 0x11128
16540 #define A_MPS_MEM_DBG_CTL 0x1112c
16543 #define V_PKD(x) ((x) << S_PKD)
16544 #define F_PKD V_PKD(1U)
16547 #define V_PGD(x) ((x) << S_PGD)
16548 #define F_PGD V_PGD(1U)
16550 #define A_MPS_PKD_MEM_DATA0 0x11130
16551 #define A_MPS_PKD_MEM_DATA1 0x11134
16552 #define A_MPS_PKD_MEM_DATA2 0x11138
16553 #define A_MPS_PGD_MEM_DATA 0x1113c
16554 #define A_MPS_RX_SE_CNT_ERR 0x11140
16556 #define S_RX_SE_ERRMAP 0
16557 #define M_RX_SE_ERRMAP 0xfffffU
16558 #define V_RX_SE_ERRMAP(x) ((x) << S_RX_SE_ERRMAP)
16559 #define G_RX_SE_ERRMAP(x) (((x) >> S_RX_SE_ERRMAP) & M_RX_SE_ERRMAP)
16561 #define A_MPS_RX_SE_CNT_CLR 0x11144
16562 #define A_MPS_RX_SE_CNT_IN0 0x11148
16564 #define S_SOP_CNT_PM 24
16565 #define M_SOP_CNT_PM 0xffU
16566 #define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM)
16567 #define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM)
16569 #define S_EOP_CNT_PM 16
16570 #define M_EOP_CNT_PM 0xffU
16571 #define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM)
16572 #define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM)
16574 #define S_SOP_CNT_IN 8
16575 #define M_SOP_CNT_IN 0xffU
16576 #define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN)
16577 #define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN)
16579 #define S_EOP_CNT_IN 0
16580 #define M_EOP_CNT_IN 0xffU
16581 #define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN)
16582 #define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN)
16584 #define A_MPS_RX_SE_CNT_IN1 0x1114c
16585 #define A_MPS_RX_SE_CNT_IN2 0x11150
16586 #define A_MPS_RX_SE_CNT_IN3 0x11154
16587 #define A_MPS_RX_SE_CNT_IN4 0x11158
16588 #define A_MPS_RX_SE_CNT_IN5 0x1115c
16589 #define A_MPS_RX_SE_CNT_IN6 0x11160
16590 #define A_MPS_RX_SE_CNT_IN7 0x11164
16591 #define A_MPS_RX_SE_CNT_OUT01 0x11168
16593 #define S_SOP_CNT_1 24
16594 #define M_SOP_CNT_1 0xffU
16595 #define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1)
16596 #define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1)
16598 #define S_EOP_CNT_1 16
16599 #define M_EOP_CNT_1 0xffU
16600 #define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1)
16601 #define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1)
16603 #define S_SOP_CNT_0 8
16604 #define M_SOP_CNT_0 0xffU
16605 #define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0)
16606 #define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0)
16608 #define S_EOP_CNT_0 0
16609 #define M_EOP_CNT_0 0xffU
16610 #define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0)
16611 #define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0)
16613 #define A_MPS_RX_SE_CNT_OUT23 0x1116c
16615 #define S_SOP_CNT_3 24
16616 #define M_SOP_CNT_3 0xffU
16617 #define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3)
16618 #define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3)
16620 #define S_EOP_CNT_3 16
16621 #define M_EOP_CNT_3 0xffU
16622 #define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3)
16623 #define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3)
16625 #define S_SOP_CNT_2 8
16626 #define M_SOP_CNT_2 0xffU
16627 #define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2)
16628 #define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2)
16630 #define S_EOP_CNT_2 0
16631 #define M_EOP_CNT_2 0xffU
16632 #define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2)
16633 #define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2)
16635 #define A_MPS_RX_SPI_ERR 0x11170
16637 #define S_LENERR 21
16638 #define M_LENERR 0xfU
16639 #define V_LENERR(x) ((x) << S_LENERR)
16640 #define G_LENERR(x) (((x) >> S_LENERR) & M_LENERR)
16643 #define M_SPIERR 0x1fffffU
16644 #define V_SPIERR(x) ((x) << S_SPIERR)
16645 #define G_SPIERR(x) (((x) >> S_SPIERR) & M_SPIERR)
16647 #define A_MPS_RX_IN_BUS_STATE 0x11174
16650 #define M_ST3 0xffU
16651 #define V_ST3(x) ((x) << S_ST3)
16652 #define G_ST3(x) (((x) >> S_ST3) & M_ST3)
16655 #define M_ST2 0xffU
16656 #define V_ST2(x) ((x) << S_ST2)
16657 #define G_ST2(x) (((x) >> S_ST2) & M_ST2)
16660 #define M_ST1 0xffU
16661 #define V_ST1(x) ((x) << S_ST1)
16662 #define G_ST1(x) (((x) >> S_ST1) & M_ST1)
16665 #define M_ST0 0xffU
16666 #define V_ST0(x) ((x) << S_ST0)
16667 #define G_ST0(x) (((x) >> S_ST0) & M_ST0)
16669 #define A_MPS_RX_OUT_BUS_STATE 0x11178
16671 #define S_ST_NCSI 23
16672 #define M_ST_NCSI 0x1ffU
16673 #define V_ST_NCSI(x) ((x) << S_ST_NCSI)
16674 #define G_ST_NCSI(x) (((x) >> S_ST_NCSI) & M_ST_NCSI)
16677 #define M_ST_TP 0x7fffffU
16678 #define V_ST_TP(x) ((x) << S_ST_TP)
16679 #define G_ST_TP(x) (((x) >> S_ST_TP) & M_ST_TP)
16681 #define A_MPS_RX_DBG_CTL 0x1117c
16683 #define S_OUT_DBG_CHNL 8
16684 #define M_OUT_DBG_CHNL 0x7U
16685 #define V_OUT_DBG_CHNL(x) ((x) << S_OUT_DBG_CHNL)
16686 #define G_OUT_DBG_CHNL(x) (((x) >> S_OUT_DBG_CHNL) & M_OUT_DBG_CHNL)
16688 #define S_DBG_PKD_QSEL 7
16689 #define V_DBG_PKD_QSEL(x) ((x) << S_DBG_PKD_QSEL)
16690 #define F_DBG_PKD_QSEL V_DBG_PKD_QSEL(1U)
16692 #define S_DBG_CDS_INV 6
16693 #define V_DBG_CDS_INV(x) ((x) << S_DBG_CDS_INV)
16694 #define F_DBG_CDS_INV V_DBG_CDS_INV(1U)
16696 #define S_IN_DBG_PORT 3
16697 #define M_IN_DBG_PORT 0x7U
16698 #define V_IN_DBG_PORT(x) ((x) << S_IN_DBG_PORT)
16699 #define G_IN_DBG_PORT(x) (((x) >> S_IN_DBG_PORT) & M_IN_DBG_PORT)
16701 #define S_IN_DBG_CHNL 0
16702 #define M_IN_DBG_CHNL 0x7U
16703 #define V_IN_DBG_CHNL(x) ((x) << S_IN_DBG_CHNL)
16704 #define G_IN_DBG_CHNL(x) (((x) >> S_IN_DBG_CHNL) & M_IN_DBG_CHNL)
16706 #define A_MPS_RX_CLS_DROP_CNT0 0x11180
16708 #define S_LPBK_CNT0 16
16709 #define M_LPBK_CNT0 0xffffU
16710 #define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0)
16711 #define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0)
16713 #define S_MAC_CNT0 0
16714 #define M_MAC_CNT0 0xffffU
16715 #define V_MAC_CNT0(x) ((x) << S_MAC_CNT0)
16716 #define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0)
16718 #define A_MPS_RX_CLS_DROP_CNT1 0x11184
16720 #define S_LPBK_CNT1 16
16721 #define M_LPBK_CNT1 0xffffU
16722 #define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1)
16723 #define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1)
16725 #define S_MAC_CNT1 0
16726 #define M_MAC_CNT1 0xffffU
16727 #define V_MAC_CNT1(x) ((x) << S_MAC_CNT1)
16728 #define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1)
16730 #define A_MPS_RX_CLS_DROP_CNT2 0x11188
16732 #define S_LPBK_CNT2 16
16733 #define M_LPBK_CNT2 0xffffU
16734 #define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2)
16735 #define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2)
16737 #define S_MAC_CNT2 0
16738 #define M_MAC_CNT2 0xffffU
16739 #define V_MAC_CNT2(x) ((x) << S_MAC_CNT2)
16740 #define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2)
16742 #define A_MPS_RX_CLS_DROP_CNT3 0x1118c
16744 #define S_LPBK_CNT3 16
16745 #define M_LPBK_CNT3 0xffffU
16746 #define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3)
16747 #define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3)
16749 #define S_MAC_CNT3 0
16750 #define M_MAC_CNT3 0xffffU
16751 #define V_MAC_CNT3(x) ((x) << S_MAC_CNT3)
16752 #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)
16754 #define A_MPS_RX_SPARE 0x11190
16756 /* registers for module CPL_SWITCH */
16757 #define CPL_SWITCH_BASE_ADDR 0x19040
16759 #define A_CPL_SWITCH_CNTRL 0x19040
16761 #define S_CPL_PKT_TID 8
16762 #define M_CPL_PKT_TID 0xffffffU
16763 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
16764 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
16766 #define S_CIM_TRUNCATE_ENABLE 5
16767 #define V_CIM_TRUNCATE_ENABLE(x) ((x) << S_CIM_TRUNCATE_ENABLE)
16768 #define F_CIM_TRUNCATE_ENABLE V_CIM_TRUNCATE_ENABLE(1U)
16770 #define S_CIM_TO_UP_FULL_SIZE 4
16771 #define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
16772 #define F_CIM_TO_UP_FULL_SIZE V_CIM_TO_UP_FULL_SIZE(1U)
16774 #define S_CPU_NO_ENABLE 3
16775 #define V_CPU_NO_ENABLE(x) ((x) << S_CPU_NO_ENABLE)
16776 #define F_CPU_NO_ENABLE V_CPU_NO_ENABLE(1U)
16778 #define S_SWITCH_TABLE_ENABLE 2
16779 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
16780 #define F_SWITCH_TABLE_ENABLE V_SWITCH_TABLE_ENABLE(1U)
16782 #define S_SGE_ENABLE 1
16783 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
16784 #define F_SGE_ENABLE V_SGE_ENABLE(1U)
16786 #define S_CIM_ENABLE 0
16787 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
16788 #define F_CIM_ENABLE V_CIM_ENABLE(1U)
16790 #define A_CPL_SWITCH_TBL_IDX 0x19044
16792 #define S_SWITCH_TBL_IDX 0
16793 #define M_SWITCH_TBL_IDX 0xfU
16794 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
16795 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
16797 #define A_CPL_SWITCH_TBL_DATA 0x19048
16798 #define A_CPL_SWITCH_ZERO_ERROR 0x1904c
16800 #define S_ZERO_CMD_CH1 8
16801 #define M_ZERO_CMD_CH1 0xffU
16802 #define V_ZERO_CMD_CH1(x) ((x) << S_ZERO_CMD_CH1)
16803 #define G_ZERO_CMD_CH1(x) (((x) >> S_ZERO_CMD_CH1) & M_ZERO_CMD_CH1)
16805 #define S_ZERO_CMD_CH0 0
16806 #define M_ZERO_CMD_CH0 0xffU
16807 #define V_ZERO_CMD_CH0(x) ((x) << S_ZERO_CMD_CH0)
16808 #define G_ZERO_CMD_CH0(x) (((x) >> S_ZERO_CMD_CH0) & M_ZERO_CMD_CH0)
16810 #define A_CPL_INTR_ENABLE 0x19050
16812 #define S_CIM_OP_MAP_PERR 5
16813 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
16814 #define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U)
16816 #define S_CIM_OVFL_ERROR 4
16817 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
16818 #define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U)
16820 #define S_TP_FRAMING_ERROR 3
16821 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
16822 #define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U)
16824 #define S_SGE_FRAMING_ERROR 2
16825 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
16826 #define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U)
16828 #define S_CIM_FRAMING_ERROR 1
16829 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
16830 #define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U)
16832 #define S_ZERO_SWITCH_ERROR 0
16833 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
16834 #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U)
16836 #define A_CPL_INTR_CAUSE 0x19054
16837 #define A_CPL_MAP_TBL_IDX 0x19058
16839 #define S_MAP_TBL_IDX 0
16840 #define M_MAP_TBL_IDX 0xffU
16841 #define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX)
16842 #define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX)
16844 #define A_CPL_MAP_TBL_DATA 0x1905c
16846 #define S_MAP_TBL_DATA 0
16847 #define M_MAP_TBL_DATA 0xffU
16848 #define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA)
16849 #define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA)
16851 /* registers for module SMB */
16852 #define SMB_BASE_ADDR 0x19060
16854 #define A_SMB_GLOBAL_TIME_CFG 0x19060
16856 #define S_MACROCNTCFG 8
16857 #define M_MACROCNTCFG 0x1fU
16858 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
16859 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
16861 #define S_MICROCNTCFG 0
16862 #define M_MICROCNTCFG 0xffU
16863 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
16864 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
16866 #define A_SMB_MST_TIMEOUT_CFG 0x19064
16868 #define S_MSTTIMEOUTCFG 0
16869 #define M_MSTTIMEOUTCFG 0xffffffU
16870 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
16871 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
16873 #define A_SMB_MST_CTL_CFG 0x19068
16875 #define S_MSTFIFODBG 31
16876 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
16877 #define F_MSTFIFODBG V_MSTFIFODBG(1U)
16879 #define S_MSTFIFODBGCLR 30
16880 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
16881 #define F_MSTFIFODBGCLR V_MSTFIFODBGCLR(1U)
16883 #define S_MSTRXBYTECFG 12
16884 #define M_MSTRXBYTECFG 0x3fU
16885 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
16886 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
16888 #define S_MSTTXBYTECFG 6
16889 #define M_MSTTXBYTECFG 0x3fU
16890 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
16891 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
16893 #define S_MSTRESET 1
16894 #define V_MSTRESET(x) ((x) << S_MSTRESET)
16895 #define F_MSTRESET V_MSTRESET(1U)
16897 #define S_MSTCTLEN 0
16898 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
16899 #define F_MSTCTLEN V_MSTCTLEN(1U)
16901 #define A_SMB_MST_CTL_STS 0x1906c
16903 #define S_MSTRXBYTECNT 12
16904 #define M_MSTRXBYTECNT 0x3fU
16905 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
16906 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
16908 #define S_MSTTXBYTECNT 6
16909 #define M_MSTTXBYTECNT 0x3fU
16910 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
16911 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
16913 #define S_MSTBUSYSTS 0
16914 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
16915 #define F_MSTBUSYSTS V_MSTBUSYSTS(1U)
16917 #define A_SMB_MST_TX_FIFO_RDWR 0x19070
16918 #define A_SMB_MST_RX_FIFO_RDWR 0x19074
16919 #define A_SMB_SLV_TIMEOUT_CFG 0x19078
16921 #define S_SLVTIMEOUTCFG 0
16922 #define M_SLVTIMEOUTCFG 0xffffffU
16923 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
16924 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
16926 #define A_SMB_SLV_CTL_CFG 0x1907c
16928 #define S_SLVFIFODBG 31
16929 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
16930 #define F_SLVFIFODBG V_SLVFIFODBG(1U)
16932 #define S_SLVFIFODBGCLR 30
16933 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
16934 #define F_SLVFIFODBGCLR V_SLVFIFODBGCLR(1U)
16936 #define S_SLVCRCOUTBITINV 21
16937 #define V_SLVCRCOUTBITINV(x) ((x) << S_SLVCRCOUTBITINV)
16938 #define F_SLVCRCOUTBITINV V_SLVCRCOUTBITINV(1U)
16940 #define S_SLVCRCOUTBITREV 20
16941 #define V_SLVCRCOUTBITREV(x) ((x) << S_SLVCRCOUTBITREV)
16942 #define F_SLVCRCOUTBITREV V_SLVCRCOUTBITREV(1U)
16944 #define S_SLVCRCINBITREV 19
16945 #define V_SLVCRCINBITREV(x) ((x) << S_SLVCRCINBITREV)
16946 #define F_SLVCRCINBITREV V_SLVCRCINBITREV(1U)
16948 #define S_SLVCRCPRESET 11
16949 #define M_SLVCRCPRESET 0xffU
16950 #define V_SLVCRCPRESET(x) ((x) << S_SLVCRCPRESET)
16951 #define G_SLVCRCPRESET(x) (((x) >> S_SLVCRCPRESET) & M_SLVCRCPRESET)
16953 #define S_SLVADDRCFG 4
16954 #define M_SLVADDRCFG 0x7fU
16955 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
16956 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
16958 #define S_SLVALRTSET 2
16959 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
16960 #define F_SLVALRTSET V_SLVALRTSET(1U)
16962 #define S_SLVRESET 1
16963 #define V_SLVRESET(x) ((x) << S_SLVRESET)
16964 #define F_SLVRESET V_SLVRESET(1U)
16966 #define S_SLVCTLEN 0
16967 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
16968 #define F_SLVCTLEN V_SLVCTLEN(1U)
16970 #define A_SMB_SLV_CTL_STS 0x19080
16972 #define S_SLVFIFOTXCNT 12
16973 #define M_SLVFIFOTXCNT 0x3fU
16974 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
16975 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
16977 #define S_SLVFIFOCNT 6
16978 #define M_SLVFIFOCNT 0x3fU
16979 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
16980 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
16982 #define S_SLVALRTSTS 2
16983 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
16984 #define F_SLVALRTSTS V_SLVALRTSTS(1U)
16986 #define S_SLVBUSYSTS 0
16987 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
16988 #define F_SLVBUSYSTS V_SLVBUSYSTS(1U)
16990 #define A_SMB_SLV_FIFO_RDWR 0x19084
16991 #define A_SMB_INT_ENABLE 0x1908c
16993 #define S_MSTTXFIFOPAREN 21
16994 #define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN)
16995 #define F_MSTTXFIFOPAREN V_MSTTXFIFOPAREN(1U)
16997 #define S_MSTRXFIFOPAREN 20
16998 #define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN)
16999 #define F_MSTRXFIFOPAREN V_MSTRXFIFOPAREN(1U)
17001 #define S_SLVFIFOPAREN 19
17002 #define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN)
17003 #define F_SLVFIFOPAREN V_SLVFIFOPAREN(1U)
17005 #define S_SLVUNEXPBUSSTOPEN 18
17006 #define V_SLVUNEXPBUSSTOPEN(x) ((x) << S_SLVUNEXPBUSSTOPEN)
17007 #define F_SLVUNEXPBUSSTOPEN V_SLVUNEXPBUSSTOPEN(1U)
17009 #define S_SLVUNEXPBUSSTARTEN 17
17010 #define V_SLVUNEXPBUSSTARTEN(x) ((x) << S_SLVUNEXPBUSSTARTEN)
17011 #define F_SLVUNEXPBUSSTARTEN V_SLVUNEXPBUSSTARTEN(1U)
17013 #define S_SLVCOMMANDCODEINVEN 16
17014 #define V_SLVCOMMANDCODEINVEN(x) ((x) << S_SLVCOMMANDCODEINVEN)
17015 #define F_SLVCOMMANDCODEINVEN V_SLVCOMMANDCODEINVEN(1U)
17017 #define S_SLVBYTECNTERREN 15
17018 #define V_SLVBYTECNTERREN(x) ((x) << S_SLVBYTECNTERREN)
17019 #define F_SLVBYTECNTERREN V_SLVBYTECNTERREN(1U)
17021 #define S_SLVUNEXPACKMSTEN 14
17022 #define V_SLVUNEXPACKMSTEN(x) ((x) << S_SLVUNEXPACKMSTEN)
17023 #define F_SLVUNEXPACKMSTEN V_SLVUNEXPACKMSTEN(1U)
17025 #define S_SLVUNEXPNACKMSTEN 13
17026 #define V_SLVUNEXPNACKMSTEN(x) ((x) << S_SLVUNEXPNACKMSTEN)
17027 #define F_SLVUNEXPNACKMSTEN V_SLVUNEXPNACKMSTEN(1U)
17029 #define S_SLVNOBUSSTOPEN 12
17030 #define V_SLVNOBUSSTOPEN(x) ((x) << S_SLVNOBUSSTOPEN)
17031 #define F_SLVNOBUSSTOPEN V_SLVNOBUSSTOPEN(1U)
17033 #define S_SLVNOREPSTARTEN 11
17034 #define V_SLVNOREPSTARTEN(x) ((x) << S_SLVNOREPSTARTEN)
17035 #define F_SLVNOREPSTARTEN V_SLVNOREPSTARTEN(1U)
17037 #define S_SLVRXADDRINTEN 10
17038 #define V_SLVRXADDRINTEN(x) ((x) << S_SLVRXADDRINTEN)
17039 #define F_SLVRXADDRINTEN V_SLVRXADDRINTEN(1U)
17041 #define S_SLVRXPECERRINTEN 9
17042 #define V_SLVRXPECERRINTEN(x) ((x) << S_SLVRXPECERRINTEN)
17043 #define F_SLVRXPECERRINTEN V_SLVRXPECERRINTEN(1U)
17045 #define S_SLVPREPTOARPINTEN 8
17046 #define V_SLVPREPTOARPINTEN(x) ((x) << S_SLVPREPTOARPINTEN)
17047 #define F_SLVPREPTOARPINTEN V_SLVPREPTOARPINTEN(1U)
17049 #define S_SLVTIMEOUTINTEN 7
17050 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
17051 #define F_SLVTIMEOUTINTEN V_SLVTIMEOUTINTEN(1U)
17053 #define S_SLVERRINTEN 6
17054 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
17055 #define F_SLVERRINTEN V_SLVERRINTEN(1U)
17057 #define S_SLVDONEINTEN 5
17058 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
17059 #define F_SLVDONEINTEN V_SLVDONEINTEN(1U)
17061 #define S_SLVRXRDYINTEN 4
17062 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
17063 #define F_SLVRXRDYINTEN V_SLVRXRDYINTEN(1U)
17065 #define S_MSTTIMEOUTINTEN 3
17066 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
17067 #define F_MSTTIMEOUTINTEN V_MSTTIMEOUTINTEN(1U)
17069 #define S_MSTNACKINTEN 2
17070 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
17071 #define F_MSTNACKINTEN V_MSTNACKINTEN(1U)
17073 #define S_MSTLOSTARBINTEN 1
17074 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
17075 #define F_MSTLOSTARBINTEN V_MSTLOSTARBINTEN(1U)
17077 #define S_MSTDONEINTEN 0
17078 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
17079 #define F_MSTDONEINTEN V_MSTDONEINTEN(1U)
17081 #define A_SMB_INT_CAUSE 0x19090
17083 #define S_MSTTXFIFOPARINT 21
17084 #define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT)
17085 #define F_MSTTXFIFOPARINT V_MSTTXFIFOPARINT(1U)
17087 #define S_MSTRXFIFOPARINT 20
17088 #define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT)
17089 #define F_MSTRXFIFOPARINT V_MSTRXFIFOPARINT(1U)
17091 #define S_SLVFIFOPARINT 19
17092 #define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT)
17093 #define F_SLVFIFOPARINT V_SLVFIFOPARINT(1U)
17095 #define S_SLVUNEXPBUSSTOPINT 18
17096 #define V_SLVUNEXPBUSSTOPINT(x) ((x) << S_SLVUNEXPBUSSTOPINT)
17097 #define F_SLVUNEXPBUSSTOPINT V_SLVUNEXPBUSSTOPINT(1U)
17099 #define S_SLVUNEXPBUSSTARTINT 17
17100 #define V_SLVUNEXPBUSSTARTINT(x) ((x) << S_SLVUNEXPBUSSTARTINT)
17101 #define F_SLVUNEXPBUSSTARTINT V_SLVUNEXPBUSSTARTINT(1U)
17103 #define S_SLVCOMMANDCODEINVINT 16
17104 #define V_SLVCOMMANDCODEINVINT(x) ((x) << S_SLVCOMMANDCODEINVINT)
17105 #define F_SLVCOMMANDCODEINVINT V_SLVCOMMANDCODEINVINT(1U)
17107 #define S_SLVBYTECNTERRINT 15
17108 #define V_SLVBYTECNTERRINT(x) ((x) << S_SLVBYTECNTERRINT)
17109 #define F_SLVBYTECNTERRINT V_SLVBYTECNTERRINT(1U)
17111 #define S_SLVUNEXPACKMSTINT 14
17112 #define V_SLVUNEXPACKMSTINT(x) ((x) << S_SLVUNEXPACKMSTINT)
17113 #define F_SLVUNEXPACKMSTINT V_SLVUNEXPACKMSTINT(1U)
17115 #define S_SLVUNEXPNACKMSTINT 13
17116 #define V_SLVUNEXPNACKMSTINT(x) ((x) << S_SLVUNEXPNACKMSTINT)
17117 #define F_SLVUNEXPNACKMSTINT V_SLVUNEXPNACKMSTINT(1U)
17119 #define S_SLVNOBUSSTOPINT 12
17120 #define V_SLVNOBUSSTOPINT(x) ((x) << S_SLVNOBUSSTOPINT)
17121 #define F_SLVNOBUSSTOPINT V_SLVNOBUSSTOPINT(1U)
17123 #define S_SLVNOREPSTARTINT 11
17124 #define V_SLVNOREPSTARTINT(x) ((x) << S_SLVNOREPSTARTINT)
17125 #define F_SLVNOREPSTARTINT V_SLVNOREPSTARTINT(1U)
17127 #define S_SLVRXADDRINT 10
17128 #define V_SLVRXADDRINT(x) ((x) << S_SLVRXADDRINT)
17129 #define F_SLVRXADDRINT V_SLVRXADDRINT(1U)
17131 #define S_SLVRXPECERRINT 9
17132 #define V_SLVRXPECERRINT(x) ((x) << S_SLVRXPECERRINT)
17133 #define F_SLVRXPECERRINT V_SLVRXPECERRINT(1U)
17135 #define S_SLVPREPTOARPINT 8
17136 #define V_SLVPREPTOARPINT(x) ((x) << S_SLVPREPTOARPINT)
17137 #define F_SLVPREPTOARPINT V_SLVPREPTOARPINT(1U)
17139 #define S_SLVTIMEOUTINT 7
17140 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
17141 #define F_SLVTIMEOUTINT V_SLVTIMEOUTINT(1U)
17143 #define S_SLVERRINT 6
17144 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
17145 #define F_SLVERRINT V_SLVERRINT(1U)
17147 #define S_SLVDONEINT 5
17148 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
17149 #define F_SLVDONEINT V_SLVDONEINT(1U)
17151 #define S_SLVRXRDYINT 4
17152 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
17153 #define F_SLVRXRDYINT V_SLVRXRDYINT(1U)
17155 #define S_MSTTIMEOUTINT 3
17156 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
17157 #define F_MSTTIMEOUTINT V_MSTTIMEOUTINT(1U)
17159 #define S_MSTNACKINT 2
17160 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
17161 #define F_MSTNACKINT V_MSTNACKINT(1U)
17163 #define S_MSTLOSTARBINT 1
17164 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
17165 #define F_MSTLOSTARBINT V_MSTLOSTARBINT(1U)
17167 #define S_MSTDONEINT 0
17168 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
17169 #define F_MSTDONEINT V_MSTDONEINT(1U)
17171 #define A_SMB_DEBUG_DATA 0x19094
17173 #define S_DEBUGDATAH 16
17174 #define M_DEBUGDATAH 0xffffU
17175 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
17176 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
17178 #define S_DEBUGDATAL 0
17179 #define M_DEBUGDATAL 0xffffU
17180 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
17181 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
17183 #define A_SMB_PERR_EN 0x19098
17185 #define S_MSTTXFIFOPERREN 2
17186 #define V_MSTTXFIFOPERREN(x) ((x) << S_MSTTXFIFOPERREN)
17187 #define F_MSTTXFIFOPERREN V_MSTTXFIFOPERREN(1U)
17189 #define S_MSTRXFIFOPERREN 1
17190 #define V_MSTRXFIFOPERREN(x) ((x) << S_MSTRXFIFOPERREN)
17191 #define F_MSTRXFIFOPERREN V_MSTRXFIFOPERREN(1U)
17193 #define S_SLVFIFOPERREN 0
17194 #define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN)
17195 #define F_SLVFIFOPERREN V_SLVFIFOPERREN(1U)
17197 #define A_SMB_PERR_INJ 0x1909c
17199 #define S_MSTTXINJDATAERR 3
17200 #define V_MSTTXINJDATAERR(x) ((x) << S_MSTTXINJDATAERR)
17201 #define F_MSTTXINJDATAERR V_MSTTXINJDATAERR(1U)
17203 #define S_MSTRXINJDATAERR 2
17204 #define V_MSTRXINJDATAERR(x) ((x) << S_MSTRXINJDATAERR)
17205 #define F_MSTRXINJDATAERR V_MSTRXINJDATAERR(1U)
17207 #define S_SLVINJDATAERR 1
17208 #define V_SLVINJDATAERR(x) ((x) << S_SLVINJDATAERR)
17209 #define F_SLVINJDATAERR V_SLVINJDATAERR(1U)
17211 #define S_FIFOINJDATAERREN 0
17212 #define V_FIFOINJDATAERREN(x) ((x) << S_FIFOINJDATAERREN)
17213 #define F_FIFOINJDATAERREN V_FIFOINJDATAERREN(1U)
17215 #define A_SMB_SLV_ARP_CTL 0x190a0
17217 #define S_ARPCOMMANDCODE 2
17218 #define M_ARPCOMMANDCODE 0xffU
17219 #define V_ARPCOMMANDCODE(x) ((x) << S_ARPCOMMANDCODE)
17220 #define G_ARPCOMMANDCODE(x) (((x) >> S_ARPCOMMANDCODE) & M_ARPCOMMANDCODE)
17222 #define S_ARPADDRRES 1
17223 #define V_ARPADDRRES(x) ((x) << S_ARPADDRRES)
17224 #define F_ARPADDRRES V_ARPADDRRES(1U)
17226 #define S_ARPADDRVAL 0
17227 #define V_ARPADDRVAL(x) ((x) << S_ARPADDRVAL)
17228 #define F_ARPADDRVAL V_ARPADDRVAL(1U)
17230 #define A_SMB_ARP_UDID0 0x190a4
17231 #define A_SMB_ARP_UDID1 0x190a8
17233 #define S_SUBSYSTEMVENDORID 16
17234 #define M_SUBSYSTEMVENDORID 0xffffU
17235 #define V_SUBSYSTEMVENDORID(x) ((x) << S_SUBSYSTEMVENDORID)
17236 #define G_SUBSYSTEMVENDORID(x) (((x) >> S_SUBSYSTEMVENDORID) & M_SUBSYSTEMVENDORID)
17238 #define S_SUBSYSTEMDEVICEID 0
17239 #define M_SUBSYSTEMDEVICEID 0xffffU
17240 #define V_SUBSYSTEMDEVICEID(x) ((x) << S_SUBSYSTEMDEVICEID)
17241 #define G_SUBSYSTEMDEVICEID(x) (((x) >> S_SUBSYSTEMDEVICEID) & M_SUBSYSTEMDEVICEID)
17243 #define A_SMB_ARP_UDID2 0x190ac
17245 #define S_DEVICEID 16
17246 #define M_DEVICEID 0xffffU
17247 #define V_DEVICEID(x) ((x) << S_DEVICEID)
17248 #define G_DEVICEID(x) (((x) >> S_DEVICEID) & M_DEVICEID)
17250 #define S_INTERFACE 0
17251 #define M_INTERFACE 0xffffU
17252 #define V_INTERFACE(x) ((x) << S_INTERFACE)
17253 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
17255 #define A_SMB_ARP_UDID3 0x190b0
17257 #define S_DEVICECAP 24
17258 #define M_DEVICECAP 0xffU
17259 #define V_DEVICECAP(x) ((x) << S_DEVICECAP)
17260 #define G_DEVICECAP(x) (((x) >> S_DEVICECAP) & M_DEVICECAP)
17262 #define S_VERSIONID 16
17263 #define M_VERSIONID 0xffU
17264 #define V_VERSIONID(x) ((x) << S_VERSIONID)
17265 #define G_VERSIONID(x) (((x) >> S_VERSIONID) & M_VERSIONID)
17267 #define S_VENDORID 0
17268 #define M_VENDORID 0xffffU
17269 #define V_VENDORID(x) ((x) << S_VENDORID)
17270 #define G_VENDORID(x) (((x) >> S_VENDORID) & M_VENDORID)
17272 #define A_SMB_SLV_AUX_ADDR0 0x190b4
17274 #define S_AUXADDR0VAL 6
17275 #define V_AUXADDR0VAL(x) ((x) << S_AUXADDR0VAL)
17276 #define F_AUXADDR0VAL V_AUXADDR0VAL(1U)
17278 #define S_AUXADDR0 0
17279 #define M_AUXADDR0 0x3fU
17280 #define V_AUXADDR0(x) ((x) << S_AUXADDR0)
17281 #define G_AUXADDR0(x) (((x) >> S_AUXADDR0) & M_AUXADDR0)
17283 #define A_SMB_SLV_AUX_ADDR1 0x190b8
17285 #define S_AUXADDR1VAL 6
17286 #define V_AUXADDR1VAL(x) ((x) << S_AUXADDR1VAL)
17287 #define F_AUXADDR1VAL V_AUXADDR1VAL(1U)
17289 #define S_AUXADDR1 0
17290 #define M_AUXADDR1 0x3fU
17291 #define V_AUXADDR1(x) ((x) << S_AUXADDR1)
17292 #define G_AUXADDR1(x) (((x) >> S_AUXADDR1) & M_AUXADDR1)
17294 #define A_SMB_SLV_AUX_ADDR2 0x190bc
17296 #define S_AUXADDR2VAL 6
17297 #define V_AUXADDR2VAL(x) ((x) << S_AUXADDR2VAL)
17298 #define F_AUXADDR2VAL V_AUXADDR2VAL(1U)
17300 #define S_AUXADDR2 0
17301 #define M_AUXADDR2 0x3fU
17302 #define V_AUXADDR2(x) ((x) << S_AUXADDR2)
17303 #define G_AUXADDR2(x) (((x) >> S_AUXADDR2) & M_AUXADDR2)
17305 #define A_SMB_SLV_AUX_ADDR3 0x190c0
17307 #define S_AUXADDR3VAL 6
17308 #define V_AUXADDR3VAL(x) ((x) << S_AUXADDR3VAL)
17309 #define F_AUXADDR3VAL V_AUXADDR3VAL(1U)
17311 #define S_AUXADDR3 0
17312 #define M_AUXADDR3 0x3fU
17313 #define V_AUXADDR3(x) ((x) << S_AUXADDR3)
17314 #define G_AUXADDR3(x) (((x) >> S_AUXADDR3) & M_AUXADDR3)
17316 #define A_SMB_COMMAND_CODE0 0x190c4
17318 #define S_SMBUSCOMMANDCODE0 0
17319 #define M_SMBUSCOMMANDCODE0 0xffU
17320 #define V_SMBUSCOMMANDCODE0(x) ((x) << S_SMBUSCOMMANDCODE0)
17321 #define G_SMBUSCOMMANDCODE0(x) (((x) >> S_SMBUSCOMMANDCODE0) & M_SMBUSCOMMANDCODE0)
17323 #define A_SMB_COMMAND_CODE1 0x190c8
17325 #define S_SMBUSCOMMANDCODE1 0
17326 #define M_SMBUSCOMMANDCODE1 0xffU
17327 #define V_SMBUSCOMMANDCODE1(x) ((x) << S_SMBUSCOMMANDCODE1)
17328 #define G_SMBUSCOMMANDCODE1(x) (((x) >> S_SMBUSCOMMANDCODE1) & M_SMBUSCOMMANDCODE1)
17330 #define A_SMB_COMMAND_CODE2 0x190cc
17332 #define S_SMBUSCOMMANDCODE2 0
17333 #define M_SMBUSCOMMANDCODE2 0xffU
17334 #define V_SMBUSCOMMANDCODE2(x) ((x) << S_SMBUSCOMMANDCODE2)
17335 #define G_SMBUSCOMMANDCODE2(x) (((x) >> S_SMBUSCOMMANDCODE2) & M_SMBUSCOMMANDCODE2)
17337 #define A_SMB_COMMAND_CODE3 0x190d0
17339 #define S_SMBUSCOMMANDCODE3 0
17340 #define M_SMBUSCOMMANDCODE3 0xffU
17341 #define V_SMBUSCOMMANDCODE3(x) ((x) << S_SMBUSCOMMANDCODE3)
17342 #define G_SMBUSCOMMANDCODE3(x) (((x) >> S_SMBUSCOMMANDCODE3) & M_SMBUSCOMMANDCODE3)
17344 #define A_SMB_COMMAND_CODE4 0x190d4
17346 #define S_SMBUSCOMMANDCODE4 0
17347 #define M_SMBUSCOMMANDCODE4 0xffU
17348 #define V_SMBUSCOMMANDCODE4(x) ((x) << S_SMBUSCOMMANDCODE4)
17349 #define G_SMBUSCOMMANDCODE4(x) (((x) >> S_SMBUSCOMMANDCODE4) & M_SMBUSCOMMANDCODE4)
17351 #define A_SMB_COMMAND_CODE5 0x190d8
17353 #define S_SMBUSCOMMANDCODE5 0
17354 #define M_SMBUSCOMMANDCODE5 0xffU
17355 #define V_SMBUSCOMMANDCODE5(x) ((x) << S_SMBUSCOMMANDCODE5)
17356 #define G_SMBUSCOMMANDCODE5(x) (((x) >> S_SMBUSCOMMANDCODE5) & M_SMBUSCOMMANDCODE5)
17358 #define A_SMB_COMMAND_CODE6 0x190dc
17360 #define S_SMBUSCOMMANDCODE6 0
17361 #define M_SMBUSCOMMANDCODE6 0xffU
17362 #define V_SMBUSCOMMANDCODE6(x) ((x) << S_SMBUSCOMMANDCODE6)
17363 #define G_SMBUSCOMMANDCODE6(x) (((x) >> S_SMBUSCOMMANDCODE6) & M_SMBUSCOMMANDCODE6)
17365 #define A_SMB_COMMAND_CODE7 0x190e0
17367 #define S_SMBUSCOMMANDCODE7 0
17368 #define M_SMBUSCOMMANDCODE7 0xffU
17369 #define V_SMBUSCOMMANDCODE7(x) ((x) << S_SMBUSCOMMANDCODE7)
17370 #define G_SMBUSCOMMANDCODE7(x) (((x) >> S_SMBUSCOMMANDCODE7) & M_SMBUSCOMMANDCODE7)
17372 #define A_SMB_MICRO_CNT_CLK_CFG 0x190e4
17374 #define S_MACROCNTCLKCFG 8
17375 #define M_MACROCNTCLKCFG 0x1fU
17376 #define V_MACROCNTCLKCFG(x) ((x) << S_MACROCNTCLKCFG)
17377 #define G_MACROCNTCLKCFG(x) (((x) >> S_MACROCNTCLKCFG) & M_MACROCNTCLKCFG)
17379 #define S_MICROCNTCLKCFG 0
17380 #define M_MICROCNTCLKCFG 0xffU
17381 #define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG)
17382 #define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG)
17384 /* registers for module I2CM */
17385 #define I2CM_BASE_ADDR 0x190f0
17387 #define A_I2CM_CFG 0x190f0
17389 #define S_I2C_CLKDIV 0
17390 #define M_I2C_CLKDIV 0xfffU
17391 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
17392 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
17394 #define A_I2CM_DATA 0x190f4
17396 #define S_I2C_DATA 0
17397 #define M_I2C_DATA 0xffU
17398 #define V_I2C_DATA(x) ((x) << S_I2C_DATA)
17399 #define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
17401 #define A_I2CM_OP 0x190f8
17403 #define S_I2C_ACK 30
17404 #define V_I2C_ACK(x) ((x) << S_I2C_ACK)
17405 #define F_I2C_ACK V_I2C_ACK(1U)
17407 #define S_I2C_CONT 1
17408 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
17409 #define F_I2C_CONT V_I2C_CONT(1U)
17412 #define V_OP(x) ((x) << S_OP)
17413 #define F_OP V_OP(1U)
17415 /* registers for module MI */
17416 #define MI_BASE_ADDR 0x19100
17418 #define A_MI_CFG 0x19100
17421 #define V_T4_ST(x) ((x) << S_T4_ST)
17422 #define F_T4_ST V_T4_ST(1U)
17425 #define M_CLKDIV 0xffU
17426 #define V_CLKDIV(x) ((x) << S_CLKDIV)
17427 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
17431 #define V_ST(x) ((x) << S_ST)
17432 #define G_ST(x) (((x) >> S_ST) & M_ST)
17435 #define V_PREEN(x) ((x) << S_PREEN)
17436 #define F_PREEN V_PREEN(1U)
17439 #define V_MDIINV(x) ((x) << S_MDIINV)
17440 #define F_MDIINV V_MDIINV(1U)
17442 #define S_MDIO_1P2V_SEL 0
17443 #define V_MDIO_1P2V_SEL(x) ((x) << S_MDIO_1P2V_SEL)
17444 #define F_MDIO_1P2V_SEL V_MDIO_1P2V_SEL(1U)
17446 #define A_MI_ADDR 0x19104
17448 #define S_PHYADDR 5
17449 #define M_PHYADDR 0x1fU
17450 #define V_PHYADDR(x) ((x) << S_PHYADDR)
17451 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
17453 #define S_REGADDR 0
17454 #define M_REGADDR 0x1fU
17455 #define V_REGADDR(x) ((x) << S_REGADDR)
17456 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
17458 #define A_MI_DATA 0x19108
17460 #define S_MDIDATA 0
17461 #define M_MDIDATA 0xffffU
17462 #define V_MDIDATA(x) ((x) << S_MDIDATA)
17463 #define G_MDIDATA(x) (((x) >> S_MDIDATA) & M_MDIDATA)
17465 #define A_MI_OP 0x1910c
17468 #define V_INC(x) ((x) << S_INC)
17469 #define F_INC V_INC(1U)
17472 #define M_MDIOP 0x3U
17473 #define V_MDIOP(x) ((x) << S_MDIOP)
17474 #define G_MDIOP(x) (((x) >> S_MDIOP) & M_MDIOP)
17476 /* registers for module UART */
17477 #define UART_BASE_ADDR 0x19110
17479 #define A_UART_CONFIG 0x19110
17481 #define S_STOPBITS 22
17482 #define M_STOPBITS 0x3U
17483 #define V_STOPBITS(x) ((x) << S_STOPBITS)
17484 #define G_STOPBITS(x) (((x) >> S_STOPBITS) & M_STOPBITS)
17486 #define S_PARITY 20
17487 #define M_PARITY 0x3U
17488 #define V_PARITY(x) ((x) << S_PARITY)
17489 #define G_PARITY(x) (((x) >> S_PARITY) & M_PARITY)
17491 #define S_DATABITS 16
17492 #define M_DATABITS 0xfU
17493 #define V_DATABITS(x) ((x) << S_DATABITS)
17494 #define G_DATABITS(x) (((x) >> S_DATABITS) & M_DATABITS)
17496 #define S_UART_CLKDIV 0
17497 #define M_UART_CLKDIV 0xfffU
17498 #define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV)
17499 #define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV)
17501 /* registers for module PMU */
17502 #define PMU_BASE_ADDR 0x19120
17504 #define A_PMU_PART_CG_PWRMODE 0x19120
17506 #define S_TPPARTCGEN 14
17507 #define V_TPPARTCGEN(x) ((x) << S_TPPARTCGEN)
17508 #define F_TPPARTCGEN V_TPPARTCGEN(1U)
17510 #define S_PDPPARTCGEN 13
17511 #define V_PDPPARTCGEN(x) ((x) << S_PDPPARTCGEN)
17512 #define F_PDPPARTCGEN V_PDPPARTCGEN(1U)
17514 #define S_PCIEPARTCGEN 12
17515 #define V_PCIEPARTCGEN(x) ((x) << S_PCIEPARTCGEN)
17516 #define F_PCIEPARTCGEN V_PCIEPARTCGEN(1U)
17518 #define S_EDC1PARTCGEN 11
17519 #define V_EDC1PARTCGEN(x) ((x) << S_EDC1PARTCGEN)
17520 #define F_EDC1PARTCGEN V_EDC1PARTCGEN(1U)
17522 #define S_MCPARTCGEN 10
17523 #define V_MCPARTCGEN(x) ((x) << S_MCPARTCGEN)
17524 #define F_MCPARTCGEN V_MCPARTCGEN(1U)
17526 #define S_EDC0PARTCGEN 9
17527 #define V_EDC0PARTCGEN(x) ((x) << S_EDC0PARTCGEN)
17528 #define F_EDC0PARTCGEN V_EDC0PARTCGEN(1U)
17530 #define S_LEPARTCGEN 8
17531 #define V_LEPARTCGEN(x) ((x) << S_LEPARTCGEN)
17532 #define F_LEPARTCGEN V_LEPARTCGEN(1U)
17534 #define S_INITPOWERMODE 0
17535 #define M_INITPOWERMODE 0x3U
17536 #define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE)
17537 #define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE)
17539 #define A_PMU_SLEEPMODE_WAKEUP 0x19124
17541 #define S_HWWAKEUPEN 5
17542 #define V_HWWAKEUPEN(x) ((x) << S_HWWAKEUPEN)
17543 #define F_HWWAKEUPEN V_HWWAKEUPEN(1U)
17545 #define S_PORT3SLEEPMODE 4
17546 #define V_PORT3SLEEPMODE(x) ((x) << S_PORT3SLEEPMODE)
17547 #define F_PORT3SLEEPMODE V_PORT3SLEEPMODE(1U)
17549 #define S_PORT2SLEEPMODE 3
17550 #define V_PORT2SLEEPMODE(x) ((x) << S_PORT2SLEEPMODE)
17551 #define F_PORT2SLEEPMODE V_PORT2SLEEPMODE(1U)
17553 #define S_PORT1SLEEPMODE 2
17554 #define V_PORT1SLEEPMODE(x) ((x) << S_PORT1SLEEPMODE)
17555 #define F_PORT1SLEEPMODE V_PORT1SLEEPMODE(1U)
17557 #define S_PORT0SLEEPMODE 1
17558 #define V_PORT0SLEEPMODE(x) ((x) << S_PORT0SLEEPMODE)
17559 #define F_PORT0SLEEPMODE V_PORT0SLEEPMODE(1U)
17562 #define V_WAKEUP(x) ((x) << S_WAKEUP)
17563 #define F_WAKEUP V_WAKEUP(1U)
17565 /* registers for module ULP_RX */
17566 #define ULP_RX_BASE_ADDR 0x19150
17568 #define A_ULP_RX_CTL 0x19150
17570 #define S_PCMD1THRESHOLD 24
17571 #define M_PCMD1THRESHOLD 0xffU
17572 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
17573 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
17575 #define S_PCMD0THRESHOLD 16
17576 #define M_PCMD0THRESHOLD 0xffU
17577 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
17578 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
17580 #define S_DISABLE_0B_STAG_ERR 14
17581 #define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR)
17582 #define F_DISABLE_0B_STAG_ERR V_DISABLE_0B_STAG_ERR(1U)
17584 #define S_RDMA_0B_WR_OPCODE 10
17585 #define M_RDMA_0B_WR_OPCODE 0xfU
17586 #define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE)
17587 #define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)
17589 #define S_RDMA_0B_WR_PASS 9
17590 #define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS)
17591 #define F_RDMA_0B_WR_PASS V_RDMA_0B_WR_PASS(1U)
17593 #define S_STAG_RQE 8
17594 #define V_STAG_RQE(x) ((x) << S_STAG_RQE)
17595 #define F_STAG_RQE V_STAG_RQE(1U)
17597 #define S_RDMA_STATE_EN 7
17598 #define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN)
17599 #define F_RDMA_STATE_EN V_RDMA_STATE_EN(1U)
17601 #define S_CRC1_EN 6
17602 #define V_CRC1_EN(x) ((x) << S_CRC1_EN)
17603 #define F_CRC1_EN V_CRC1_EN(1U)
17605 #define S_RDMA_0B_WR_CQE 5
17606 #define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE)
17607 #define F_RDMA_0B_WR_CQE V_RDMA_0B_WR_CQE(1U)
17609 #define S_PCIE_ATRB_EN 4
17610 #define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN)
17611 #define F_PCIE_ATRB_EN V_PCIE_ATRB_EN(1U)
17613 #define S_RDMA_PERMISSIVE_MODE 3
17614 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
17615 #define F_RDMA_PERMISSIVE_MODE V_RDMA_PERMISSIVE_MODE(1U)
17617 #define S_PAGEPODME 2
17618 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
17619 #define F_PAGEPODME V_PAGEPODME(1U)
17621 #define S_ISCSITAGTCB 1
17622 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
17623 #define F_ISCSITAGTCB V_ISCSITAGTCB(1U)
17625 #define S_TDDPTAGTCB 0
17626 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
17627 #define F_TDDPTAGTCB V_TDDPTAGTCB(1U)
17629 #define A_ULP_RX_INT_ENABLE 0x19154
17631 #define S_ENABLE_CTX_1 24
17632 #define V_ENABLE_CTX_1(x) ((x) << S_ENABLE_CTX_1)
17633 #define F_ENABLE_CTX_1 V_ENABLE_CTX_1(1U)
17635 #define S_ENABLE_CTX_0 23
17636 #define V_ENABLE_CTX_0(x) ((x) << S_ENABLE_CTX_0)
17637 #define F_ENABLE_CTX_0 V_ENABLE_CTX_0(1U)
17639 #define S_ENABLE_FF 22
17640 #define V_ENABLE_FF(x) ((x) << S_ENABLE_FF)
17641 #define F_ENABLE_FF V_ENABLE_FF(1U)
17643 #define S_ENABLE_APF_1 21
17644 #define V_ENABLE_APF_1(x) ((x) << S_ENABLE_APF_1)
17645 #define F_ENABLE_APF_1 V_ENABLE_APF_1(1U)
17647 #define S_ENABLE_APF_0 20
17648 #define V_ENABLE_APF_0(x) ((x) << S_ENABLE_APF_0)
17649 #define F_ENABLE_APF_0 V_ENABLE_APF_0(1U)
17651 #define S_ENABLE_AF_1 19
17652 #define V_ENABLE_AF_1(x) ((x) << S_ENABLE_AF_1)
17653 #define F_ENABLE_AF_1 V_ENABLE_AF_1(1U)
17655 #define S_ENABLE_AF_0 18
17656 #define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0)
17657 #define F_ENABLE_AF_0 V_ENABLE_AF_0(1U)
17659 #define S_ENABLE_PCMDF_1 17
17660 #define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1)
17661 #define F_ENABLE_PCMDF_1 V_ENABLE_PCMDF_1(1U)
17663 #define S_ENABLE_MPARC_1 16
17664 #define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1)
17665 #define F_ENABLE_MPARC_1 V_ENABLE_MPARC_1(1U)
17667 #define S_ENABLE_MPARF_1 15
17668 #define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1)
17669 #define F_ENABLE_MPARF_1 V_ENABLE_MPARF_1(1U)
17671 #define S_ENABLE_DDPCF_1 14
17672 #define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1)
17673 #define F_ENABLE_DDPCF_1 V_ENABLE_DDPCF_1(1U)
17675 #define S_ENABLE_TPTCF_1 13
17676 #define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1)
17677 #define F_ENABLE_TPTCF_1 V_ENABLE_TPTCF_1(1U)
17679 #define S_ENABLE_PCMDF_0 12
17680 #define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0)
17681 #define F_ENABLE_PCMDF_0 V_ENABLE_PCMDF_0(1U)
17683 #define S_ENABLE_MPARC_0 11
17684 #define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0)
17685 #define F_ENABLE_MPARC_0 V_ENABLE_MPARC_0(1U)
17687 #define S_ENABLE_MPARF_0 10
17688 #define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0)
17689 #define F_ENABLE_MPARF_0 V_ENABLE_MPARF_0(1U)
17691 #define S_ENABLE_DDPCF_0 9
17692 #define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0)
17693 #define F_ENABLE_DDPCF_0 V_ENABLE_DDPCF_0(1U)
17695 #define S_ENABLE_TPTCF_0 8
17696 #define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0)
17697 #define F_ENABLE_TPTCF_0 V_ENABLE_TPTCF_0(1U)
17699 #define S_ENABLE_DDPDF_1 7
17700 #define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1)
17701 #define F_ENABLE_DDPDF_1 V_ENABLE_DDPDF_1(1U)
17703 #define S_ENABLE_DDPMF_1 6
17704 #define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1)
17705 #define F_ENABLE_DDPMF_1 V_ENABLE_DDPMF_1(1U)
17707 #define S_ENABLE_MEMRF_1 5
17708 #define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1)
17709 #define F_ENABLE_MEMRF_1 V_ENABLE_MEMRF_1(1U)
17711 #define S_ENABLE_PRSDF_1 4
17712 #define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1)
17713 #define F_ENABLE_PRSDF_1 V_ENABLE_PRSDF_1(1U)
17715 #define S_ENABLE_DDPDF_0 3
17716 #define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0)
17717 #define F_ENABLE_DDPDF_0 V_ENABLE_DDPDF_0(1U)
17719 #define S_ENABLE_DDPMF_0 2
17720 #define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0)
17721 #define F_ENABLE_DDPMF_0 V_ENABLE_DDPMF_0(1U)
17723 #define S_ENABLE_MEMRF_0 1
17724 #define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0)
17725 #define F_ENABLE_MEMRF_0 V_ENABLE_MEMRF_0(1U)
17727 #define S_ENABLE_PRSDF_0 0
17728 #define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0)
17729 #define F_ENABLE_PRSDF_0 V_ENABLE_PRSDF_0(1U)
17731 #define A_ULP_RX_INT_CAUSE 0x19158
17733 #define S_CAUSE_CTX_1 24
17734 #define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1)
17735 #define F_CAUSE_CTX_1 V_CAUSE_CTX_1(1U)
17737 #define S_CAUSE_CTX_0 23
17738 #define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0)
17739 #define F_CAUSE_CTX_0 V_CAUSE_CTX_0(1U)
17741 #define S_CAUSE_FF 22
17742 #define V_CAUSE_FF(x) ((x) << S_CAUSE_FF)
17743 #define F_CAUSE_FF V_CAUSE_FF(1U)
17745 #define S_CAUSE_APF_1 21
17746 #define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1)
17747 #define F_CAUSE_APF_1 V_CAUSE_APF_1(1U)
17749 #define S_CAUSE_APF_0 20
17750 #define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0)
17751 #define F_CAUSE_APF_0 V_CAUSE_APF_0(1U)
17753 #define S_CAUSE_AF_1 19
17754 #define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1)
17755 #define F_CAUSE_AF_1 V_CAUSE_AF_1(1U)
17757 #define S_CAUSE_AF_0 18
17758 #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
17759 #define F_CAUSE_AF_0 V_CAUSE_AF_0(1U)
17761 #define S_CAUSE_PCMDF_1 17
17762 #define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
17763 #define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U)
17765 #define S_CAUSE_MPARC_1 16
17766 #define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
17767 #define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U)
17769 #define S_CAUSE_MPARF_1 15
17770 #define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
17771 #define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U)
17773 #define S_CAUSE_DDPCF_1 14
17774 #define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
17775 #define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U)
17777 #define S_CAUSE_TPTCF_1 13
17778 #define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
17779 #define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U)
17781 #define S_CAUSE_PCMDF_0 12
17782 #define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
17783 #define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U)
17785 #define S_CAUSE_MPARC_0 11
17786 #define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
17787 #define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U)
17789 #define S_CAUSE_MPARF_0 10
17790 #define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
17791 #define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U)
17793 #define S_CAUSE_DDPCF_0 9
17794 #define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
17795 #define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U)
17797 #define S_CAUSE_TPTCF_0 8
17798 #define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
17799 #define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U)
17801 #define S_CAUSE_DDPDF_1 7
17802 #define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
17803 #define F_CAUSE_DDPDF_1 V_CAUSE_DDPDF_1(1U)
17805 #define S_CAUSE_DDPMF_1 6
17806 #define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
17807 #define F_CAUSE_DDPMF_1 V_CAUSE_DDPMF_1(1U)
17809 #define S_CAUSE_MEMRF_1 5
17810 #define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
17811 #define F_CAUSE_MEMRF_1 V_CAUSE_MEMRF_1(1U)
17813 #define S_CAUSE_PRSDF_1 4
17814 #define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
17815 #define F_CAUSE_PRSDF_1 V_CAUSE_PRSDF_1(1U)
17817 #define S_CAUSE_DDPDF_0 3
17818 #define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
17819 #define F_CAUSE_DDPDF_0 V_CAUSE_DDPDF_0(1U)
17821 #define S_CAUSE_DDPMF_0 2
17822 #define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
17823 #define F_CAUSE_DDPMF_0 V_CAUSE_DDPMF_0(1U)
17825 #define S_CAUSE_MEMRF_0 1
17826 #define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
17827 #define F_CAUSE_MEMRF_0 V_CAUSE_MEMRF_0(1U)
17829 #define S_CAUSE_PRSDF_0 0
17830 #define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
17831 #define F_CAUSE_PRSDF_0 V_CAUSE_PRSDF_0(1U)
17833 #define A_ULP_RX_ISCSI_LLIMIT 0x1915c
17835 #define S_ISCSILLIMIT 6
17836 #define M_ISCSILLIMIT 0x3ffffffU
17837 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
17838 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
17840 #define A_ULP_RX_ISCSI_ULIMIT 0x19160
17842 #define S_ISCSIULIMIT 6
17843 #define M_ISCSIULIMIT 0x3ffffffU
17844 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
17845 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
17847 #define A_ULP_RX_ISCSI_TAGMASK 0x19164
17849 #define S_ISCSITAGMASK 6
17850 #define M_ISCSITAGMASK 0x3ffffffU
17851 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
17852 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
17854 #define A_ULP_RX_ISCSI_PSZ 0x19168
17857 #define M_HPZ3 0xfU
17858 #define V_HPZ3(x) ((x) << S_HPZ3)
17859 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
17862 #define M_HPZ2 0xfU
17863 #define V_HPZ2(x) ((x) << S_HPZ2)
17864 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
17867 #define M_HPZ1 0xfU
17868 #define V_HPZ1(x) ((x) << S_HPZ1)
17869 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
17872 #define M_HPZ0 0xfU
17873 #define V_HPZ0(x) ((x) << S_HPZ0)
17874 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
17876 #define A_ULP_RX_TDDP_LLIMIT 0x1916c
17878 #define S_TDDPLLIMIT 6
17879 #define M_TDDPLLIMIT 0x3ffffffU
17880 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
17881 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
17883 #define A_ULP_RX_TDDP_ULIMIT 0x19170
17885 #define S_TDDPULIMIT 6
17886 #define M_TDDPULIMIT 0x3ffffffU
17887 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
17888 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
17890 #define A_ULP_RX_TDDP_TAGMASK 0x19174
17892 #define S_TDDPTAGMASK 6
17893 #define M_TDDPTAGMASK 0x3ffffffU
17894 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
17895 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
17897 #define A_ULP_RX_TDDP_PSZ 0x19178
17898 #define A_ULP_RX_STAG_LLIMIT 0x1917c
17899 #define A_ULP_RX_STAG_ULIMIT 0x19180
17900 #define A_ULP_RX_RQ_LLIMIT 0x19184
17901 #define A_ULP_RX_RQ_ULIMIT 0x19188
17902 #define A_ULP_RX_PBL_LLIMIT 0x1918c
17903 #define A_ULP_RX_PBL_ULIMIT 0x19190
17904 #define A_ULP_RX_CTX_BASE 0x19194
17905 #define A_ULP_RX_PERR_ENABLE 0x1919c
17906 #define A_ULP_RX_PERR_INJECT 0x191a0
17907 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4
17908 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8
17909 #define A_ULP_RX_CTX_ACC_CH0 0x191ac
17912 #define V_REQ(x) ((x) << S_REQ)
17913 #define F_REQ V_REQ(1U)
17916 #define V_WB(x) ((x) << S_WB)
17917 #define F_WB V_WB(1U)
17919 #define S_ULPRX_TID 0
17920 #define M_ULPRX_TID 0xfffffU
17921 #define V_ULPRX_TID(x) ((x) << S_ULPRX_TID)
17922 #define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID)
17924 #define A_ULP_RX_CTX_ACC_CH1 0x191b0
17925 #define A_ULP_RX_SE_CNT_ERR 0x191d0
17926 #define A_ULP_RX_SE_CNT_CLR 0x191d4
17928 #define S_CLRCHAN0 4
17929 #define M_CLRCHAN0 0xfU
17930 #define V_CLRCHAN0(x) ((x) << S_CLRCHAN0)
17931 #define G_CLRCHAN0(x) (((x) >> S_CLRCHAN0) & M_CLRCHAN0)
17933 #define S_CLRCHAN1 0
17934 #define M_CLRCHAN1 0xfU
17935 #define V_CLRCHAN1(x) ((x) << S_CLRCHAN1)
17936 #define G_CLRCHAN1(x) (((x) >> S_CLRCHAN1) & M_CLRCHAN1)
17938 #define A_ULP_RX_SE_CNT_CH0 0x191d8
17940 #define S_SOP_CNT_OUT0 28
17941 #define M_SOP_CNT_OUT0 0xfU
17942 #define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0)
17943 #define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0)
17945 #define S_EOP_CNT_OUT0 24
17946 #define M_EOP_CNT_OUT0 0xfU
17947 #define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0)
17948 #define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0)
17950 #define S_SOP_CNT_AL0 20
17951 #define M_SOP_CNT_AL0 0xfU
17952 #define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0)
17953 #define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0)
17955 #define S_EOP_CNT_AL0 16
17956 #define M_EOP_CNT_AL0 0xfU
17957 #define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0)
17958 #define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0)
17960 #define S_SOP_CNT_MR0 12
17961 #define M_SOP_CNT_MR0 0xfU
17962 #define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0)
17963 #define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0)
17965 #define S_EOP_CNT_MR0 8
17966 #define M_EOP_CNT_MR0 0xfU
17967 #define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0)
17968 #define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0)
17970 #define S_SOP_CNT_IN0 4
17971 #define M_SOP_CNT_IN0 0xfU
17972 #define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0)
17973 #define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0)
17975 #define S_EOP_CNT_IN0 0
17976 #define M_EOP_CNT_IN0 0xfU
17977 #define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0)
17978 #define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0)
17980 #define A_ULP_RX_SE_CNT_CH1 0x191dc
17982 #define S_SOP_CNT_OUT1 28
17983 #define M_SOP_CNT_OUT1 0xfU
17984 #define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1)
17985 #define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1)
17987 #define S_EOP_CNT_OUT1 24
17988 #define M_EOP_CNT_OUT1 0xfU
17989 #define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1)
17990 #define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1)
17992 #define S_SOP_CNT_AL1 20
17993 #define M_SOP_CNT_AL1 0xfU
17994 #define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1)
17995 #define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1)
17997 #define S_EOP_CNT_AL1 16
17998 #define M_EOP_CNT_AL1 0xfU
17999 #define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1)
18000 #define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1)
18002 #define S_SOP_CNT_MR1 12
18003 #define M_SOP_CNT_MR1 0xfU
18004 #define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1)
18005 #define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1)
18007 #define S_EOP_CNT_MR1 8
18008 #define M_EOP_CNT_MR1 0xfU
18009 #define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1)
18010 #define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1)
18012 #define S_SOP_CNT_IN1 4
18013 #define M_SOP_CNT_IN1 0xfU
18014 #define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1)
18015 #define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1)
18017 #define S_EOP_CNT_IN1 0
18018 #define M_EOP_CNT_IN1 0xfU
18019 #define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1)
18020 #define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1)
18022 #define A_ULP_RX_DBG_CTL 0x191e0
18024 #define S_EN_DBG_H 17
18025 #define V_EN_DBG_H(x) ((x) << S_EN_DBG_H)
18026 #define F_EN_DBG_H V_EN_DBG_H(1U)
18028 #define S_EN_DBG_L 16
18029 #define V_EN_DBG_L(x) ((x) << S_EN_DBG_L)
18030 #define F_EN_DBG_L V_EN_DBG_L(1U)
18033 #define M_SEL_H 0xffU
18034 #define V_SEL_H(x) ((x) << S_SEL_H)
18035 #define G_SEL_H(x) (((x) >> S_SEL_H) & M_SEL_H)
18038 #define M_SEL_L 0xffU
18039 #define V_SEL_L(x) ((x) << S_SEL_L)
18040 #define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L)
18042 #define A_ULP_RX_DBG_DATAH 0x191e4
18043 #define A_ULP_RX_DBG_DATAL 0x191e8
18044 #define A_ULP_RX_LA_CHNL 0x19238
18046 #define S_CHNL_SEL 0
18047 #define V_CHNL_SEL(x) ((x) << S_CHNL_SEL)
18048 #define F_CHNL_SEL V_CHNL_SEL(1U)
18050 #define A_ULP_RX_LA_CTL 0x1923c
18052 #define S_TRC_SEL 0
18053 #define V_TRC_SEL(x) ((x) << S_TRC_SEL)
18054 #define F_TRC_SEL V_TRC_SEL(1U)
18056 #define A_ULP_RX_LA_RDPTR 0x19240
18059 #define M_RD_PTR 0x1ffU
18060 #define V_RD_PTR(x) ((x) << S_RD_PTR)
18061 #define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR)
18063 #define A_ULP_RX_LA_RDDATA 0x19244
18064 #define A_ULP_RX_LA_WRPTR 0x19248
18067 #define M_WR_PTR 0x1ffU
18068 #define V_WR_PTR(x) ((x) << S_WR_PTR)
18069 #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)
18071 #define A_ULP_RX_LA_RESERVED 0x1924c
18073 /* registers for module SF */
18074 #define SF_BASE_ADDR 0x193f8
18076 #define A_SF_DATA 0x193f8
18077 #define A_SF_OP 0x193fc
18079 #define S_SF_LOCK 4
18080 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
18081 #define F_SF_LOCK V_SF_LOCK(1U)
18084 #define V_CONT(x) ((x) << S_CONT)
18085 #define F_CONT V_CONT(1U)
18087 #define S_BYTECNT 1
18088 #define M_BYTECNT 0x3U
18089 #define V_BYTECNT(x) ((x) << S_BYTECNT)
18090 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
18092 /* registers for module PL */
18093 #define PL_BASE_ADDR 0x19400
18095 #define A_PL_VF_WHOAMI 0x0
18097 #define S_PORTXMAP 24
18098 #define M_PORTXMAP 0x7U
18099 #define V_PORTXMAP(x) ((x) << S_PORTXMAP)
18100 #define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP)
18102 #define S_SOURCEBUS 16
18103 #define M_SOURCEBUS 0x3U
18104 #define V_SOURCEBUS(x) ((x) << S_SOURCEBUS)
18105 #define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS)
18107 #define S_SOURCEPF 8
18108 #define M_SOURCEPF 0x7U
18109 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
18110 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
18113 #define V_ISVF(x) ((x) << S_ISVF)
18114 #define F_ISVF V_ISVF(1U)
18117 #define M_VFID 0x7fU
18118 #define V_VFID(x) ((x) << S_VFID)
18119 #define G_VFID(x) (((x) >> S_VFID) & M_VFID)
18121 #define A_PL_PF_INT_CAUSE 0x3c0
18124 #define V_PFSW(x) ((x) << S_PFSW)
18125 #define F_PFSW V_PFSW(1U)
18128 #define V_PFSGE(x) ((x) << S_PFSGE)
18129 #define F_PFSGE V_PFSGE(1U)
18132 #define V_PFCIM(x) ((x) << S_PFCIM)
18133 #define F_PFCIM V_PFCIM(1U)
18136 #define V_PFMPS(x) ((x) << S_PFMPS)
18137 #define F_PFMPS V_PFMPS(1U)
18139 #define A_PL_PF_INT_ENABLE 0x3c4
18140 #define A_PL_PF_CTL 0x3c8
18143 #define V_SWINT(x) ((x) << S_SWINT)
18144 #define F_SWINT V_SWINT(1U)
18146 #define A_PL_WHOAMI 0x19400
18147 #define A_PL_PERR_CAUSE 0x19404
18150 #define V_UART(x) ((x) << S_UART)
18151 #define F_UART V_UART(1U)
18153 #define S_ULP_TX 27
18154 #define V_ULP_TX(x) ((x) << S_ULP_TX)
18155 #define F_ULP_TX V_ULP_TX(1U)
18158 #define V_SGE(x) ((x) << S_SGE)
18159 #define F_SGE V_SGE(1U)
18162 #define V_HMA(x) ((x) << S_HMA)
18163 #define F_HMA V_HMA(1U)
18165 #define S_CPL_SWITCH 24
18166 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
18167 #define F_CPL_SWITCH V_CPL_SWITCH(1U)
18169 #define S_ULP_RX 23
18170 #define V_ULP_RX(x) ((x) << S_ULP_RX)
18171 #define F_ULP_RX V_ULP_RX(1U)
18174 #define V_PM_RX(x) ((x) << S_PM_RX)
18175 #define F_PM_RX V_PM_RX(1U)
18178 #define V_PM_TX(x) ((x) << S_PM_TX)
18179 #define F_PM_TX V_PM_TX(1U)
18182 #define V_MA(x) ((x) << S_MA)
18183 #define F_MA V_MA(1U)
18186 #define V_TP(x) ((x) << S_TP)
18187 #define F_TP V_TP(1U)
18190 #define V_LE(x) ((x) << S_LE)
18191 #define F_LE V_LE(1U)
18194 #define V_EDC1(x) ((x) << S_EDC1)
18195 #define F_EDC1 V_EDC1(1U)
18198 #define V_EDC0(x) ((x) << S_EDC0)
18199 #define F_EDC0 V_EDC0(1U)
18202 #define V_MC(x) ((x) << S_MC)
18203 #define F_MC V_MC(1U)
18206 #define V_PCIE(x) ((x) << S_PCIE)
18207 #define F_PCIE V_PCIE(1U)
18210 #define V_PMU(x) ((x) << S_PMU)
18211 #define F_PMU V_PMU(1U)
18213 #define S_XGMAC_KR1 12
18214 #define V_XGMAC_KR1(x) ((x) << S_XGMAC_KR1)
18215 #define F_XGMAC_KR1 V_XGMAC_KR1(1U)
18217 #define S_XGMAC_KR0 11
18218 #define V_XGMAC_KR0(x) ((x) << S_XGMAC_KR0)
18219 #define F_XGMAC_KR0 V_XGMAC_KR0(1U)
18221 #define S_XGMAC1 10
18222 #define V_XGMAC1(x) ((x) << S_XGMAC1)
18223 #define F_XGMAC1 V_XGMAC1(1U)
18226 #define V_XGMAC0(x) ((x) << S_XGMAC0)
18227 #define F_XGMAC0 V_XGMAC0(1U)
18230 #define V_SMB(x) ((x) << S_SMB)
18231 #define F_SMB V_SMB(1U)
18234 #define V_SF(x) ((x) << S_SF)
18235 #define F_SF V_SF(1U)
18238 #define V_PL(x) ((x) << S_PL)
18239 #define F_PL V_PL(1U)
18242 #define V_NCSI(x) ((x) << S_NCSI)
18243 #define F_NCSI V_NCSI(1U)
18246 #define V_MPS(x) ((x) << S_MPS)
18247 #define F_MPS V_MPS(1U)
18250 #define V_MI(x) ((x) << S_MI)
18251 #define F_MI V_MI(1U)
18254 #define V_DBG(x) ((x) << S_DBG)
18255 #define F_DBG V_DBG(1U)
18258 #define V_I2CM(x) ((x) << S_I2CM)
18259 #define F_I2CM V_I2CM(1U)
18262 #define V_CIM(x) ((x) << S_CIM)
18263 #define F_CIM V_CIM(1U)
18265 #define A_PL_PERR_ENABLE 0x19408
18266 #define A_PL_INT_CAUSE 0x1940c
18269 #define V_FLR(x) ((x) << S_FLR)
18270 #define F_FLR V_FLR(1U)
18272 #define S_SW_CIM 29
18273 #define V_SW_CIM(x) ((x) << S_SW_CIM)
18274 #define F_SW_CIM V_SW_CIM(1U)
18276 #define A_PL_INT_ENABLE 0x19410
18277 #define A_PL_INT_MAP0 0x19414
18279 #define S_MAPNCSI 16
18280 #define M_MAPNCSI 0x1ffU
18281 #define V_MAPNCSI(x) ((x) << S_MAPNCSI)
18282 #define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI)
18284 #define S_MAPDEFAULT 0
18285 #define M_MAPDEFAULT 0x1ffU
18286 #define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT)
18287 #define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT)
18289 #define A_PL_INT_MAP1 0x19418
18291 #define S_MAPXGMAC1 16
18292 #define M_MAPXGMAC1 0x1ffU
18293 #define V_MAPXGMAC1(x) ((x) << S_MAPXGMAC1)
18294 #define G_MAPXGMAC1(x) (((x) >> S_MAPXGMAC1) & M_MAPXGMAC1)
18296 #define S_MAPXGMAC0 0
18297 #define M_MAPXGMAC0 0x1ffU
18298 #define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0)
18299 #define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0)
18301 #define A_PL_INT_MAP2 0x1941c
18303 #define S_MAPXGMAC_KR1 16
18304 #define M_MAPXGMAC_KR1 0x1ffU
18305 #define V_MAPXGMAC_KR1(x) ((x) << S_MAPXGMAC_KR1)
18306 #define G_MAPXGMAC_KR1(x) (((x) >> S_MAPXGMAC_KR1) & M_MAPXGMAC_KR1)
18308 #define S_MAPXGMAC_KR0 0
18309 #define M_MAPXGMAC_KR0 0x1ffU
18310 #define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0)
18311 #define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0)
18313 #define A_PL_INT_MAP3 0x19420
18316 #define M_MAPMI 0x1ffU
18317 #define V_MAPMI(x) ((x) << S_MAPMI)
18318 #define G_MAPMI(x) (((x) >> S_MAPMI) & M_MAPMI)
18321 #define M_MAPSMB 0x1ffU
18322 #define V_MAPSMB(x) ((x) << S_MAPSMB)
18323 #define G_MAPSMB(x) (((x) >> S_MAPSMB) & M_MAPSMB)
18325 #define A_PL_INT_MAP4 0x19424
18327 #define S_MAPDBG 16
18328 #define M_MAPDBG 0x1ffU
18329 #define V_MAPDBG(x) ((x) << S_MAPDBG)
18330 #define G_MAPDBG(x) (((x) >> S_MAPDBG) & M_MAPDBG)
18332 #define S_MAPI2CM 0
18333 #define M_MAPI2CM 0x1ffU
18334 #define V_MAPI2CM(x) ((x) << S_MAPI2CM)
18335 #define G_MAPI2CM(x) (((x) >> S_MAPI2CM) & M_MAPI2CM)
18337 #define A_PL_RST 0x19428
18339 #define S_FATALPERREN 3
18340 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
18341 #define F_FATALPERREN V_FATALPERREN(1U)
18343 #define S_SWINTCIM 2
18344 #define V_SWINTCIM(x) ((x) << S_SWINTCIM)
18345 #define F_SWINTCIM V_SWINTCIM(1U)
18348 #define V_PIORST(x) ((x) << S_PIORST)
18349 #define F_PIORST V_PIORST(1U)
18351 #define S_PIORSTMODE 0
18352 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
18353 #define F_PIORSTMODE V_PIORSTMODE(1U)
18355 #define A_PL_PL_PERR_INJECT 0x1942c
18357 #define S_PL_MEMSEL 1
18358 #define V_PL_MEMSEL(x) ((x) << S_PL_MEMSEL)
18359 #define F_PL_MEMSEL V_PL_MEMSEL(1U)
18361 #define A_PL_PL_INT_CAUSE 0x19430
18363 #define S_PF_ENABLEERR 5
18364 #define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR)
18365 #define F_PF_ENABLEERR V_PF_ENABLEERR(1U)
18367 #define S_FATALPERR 4
18368 #define V_FATALPERR(x) ((x) << S_FATALPERR)
18369 #define F_FATALPERR V_FATALPERR(1U)
18371 #define S_INVALIDACCESS 3
18372 #define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS)
18373 #define F_INVALIDACCESS V_INVALIDACCESS(1U)
18375 #define S_TIMEOUT 2
18376 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
18377 #define F_TIMEOUT V_TIMEOUT(1U)
18380 #define V_PLERR(x) ((x) << S_PLERR)
18381 #define F_PLERR V_PLERR(1U)
18383 #define S_PERRVFID 0
18384 #define V_PERRVFID(x) ((x) << S_PERRVFID)
18385 #define F_PERRVFID V_PERRVFID(1U)
18387 #define A_PL_PL_INT_ENABLE 0x19434
18388 #define A_PL_PL_PERR_ENABLE 0x19438
18389 #define A_PL_REV 0x1943c
18393 #define V_REV(x) ((x) << S_REV)
18394 #define G_REV(x) (((x) >> S_REV) & M_REV)
18396 #define A_PL_SEMAPHORE_CTL 0x1944c
18398 #define S_LOCKSTATUS 16
18399 #define M_LOCKSTATUS 0xffU
18400 #define V_LOCKSTATUS(x) ((x) << S_LOCKSTATUS)
18401 #define G_LOCKSTATUS(x) (((x) >> S_LOCKSTATUS) & M_LOCKSTATUS)
18403 #define S_OWNEROVERRIDE 8
18404 #define V_OWNEROVERRIDE(x) ((x) << S_OWNEROVERRIDE)
18405 #define F_OWNEROVERRIDE V_OWNEROVERRIDE(1U)
18407 #define S_ENABLEPF 0
18408 #define M_ENABLEPF 0xffU
18409 #define V_ENABLEPF(x) ((x) << S_ENABLEPF)
18410 #define G_ENABLEPF(x) (((x) >> S_ENABLEPF) & M_ENABLEPF)
18412 #define A_PL_SEMAPHORE_LOCK 0x19450
18414 #define S_SEMLOCK 31
18415 #define V_SEMLOCK(x) ((x) << S_SEMLOCK)
18416 #define F_SEMLOCK V_SEMLOCK(1U)
18418 #define S_SEMSRCBUS 3
18419 #define M_SEMSRCBUS 0x3U
18420 #define V_SEMSRCBUS(x) ((x) << S_SEMSRCBUS)
18421 #define G_SEMSRCBUS(x) (((x) >> S_SEMSRCBUS) & M_SEMSRCBUS)
18423 #define S_SEMSRCPF 0
18424 #define M_SEMSRCPF 0x7U
18425 #define V_SEMSRCPF(x) ((x) << S_SEMSRCPF)
18426 #define G_SEMSRCPF(x) (((x) >> S_SEMSRCPF) & M_SEMSRCPF)
18428 #define A_PL_PF_ENABLE 0x19470
18430 #define S_PF_ENABLE 0
18431 #define M_PF_ENABLE 0xffU
18432 #define V_PF_ENABLE(x) ((x) << S_PF_ENABLE)
18433 #define G_PF_ENABLE(x) (((x) >> S_PF_ENABLE) & M_PF_ENABLE)
18435 #define A_PL_PORTX_MAP 0x19474
18438 #define M_MAP7 0x7U
18439 #define V_MAP7(x) ((x) << S_MAP7)
18440 #define G_MAP7(x) (((x) >> S_MAP7) & M_MAP7)
18443 #define M_MAP6 0x7U
18444 #define V_MAP6(x) ((x) << S_MAP6)
18445 #define G_MAP6(x) (((x) >> S_MAP6) & M_MAP6)
18448 #define M_MAP5 0x7U
18449 #define V_MAP5(x) ((x) << S_MAP5)
18450 #define G_MAP5(x) (((x) >> S_MAP5) & M_MAP5)
18453 #define M_MAP4 0x7U
18454 #define V_MAP4(x) ((x) << S_MAP4)
18455 #define G_MAP4(x) (((x) >> S_MAP4) & M_MAP4)
18458 #define M_MAP3 0x7U
18459 #define V_MAP3(x) ((x) << S_MAP3)
18460 #define G_MAP3(x) (((x) >> S_MAP3) & M_MAP3)
18463 #define M_MAP2 0x7U
18464 #define V_MAP2(x) ((x) << S_MAP2)
18465 #define G_MAP2(x) (((x) >> S_MAP2) & M_MAP2)
18468 #define M_MAP1 0x7U
18469 #define V_MAP1(x) ((x) << S_MAP1)
18470 #define G_MAP1(x) (((x) >> S_MAP1) & M_MAP1)
18473 #define M_MAP0 0x7U
18474 #define V_MAP0(x) ((x) << S_MAP0)
18475 #define G_MAP0(x) (((x) >> S_MAP0) & M_MAP0)
18477 #define A_PL_VF_SLICE_L 0x19490
18479 #define S_LIMITADDR 16
18480 #define M_LIMITADDR 0x3ffU
18481 #define V_LIMITADDR(x) ((x) << S_LIMITADDR)
18482 #define G_LIMITADDR(x) (((x) >> S_LIMITADDR) & M_LIMITADDR)
18484 #define S_SLICEBASEADDR 0
18485 #define M_SLICEBASEADDR 0x3ffU
18486 #define V_SLICEBASEADDR(x) ((x) << S_SLICEBASEADDR)
18487 #define G_SLICEBASEADDR(x) (((x) >> S_SLICEBASEADDR) & M_SLICEBASEADDR)
18489 #define A_PL_VF_SLICE_H 0x19494
18491 #define S_MODINDX 16
18492 #define M_MODINDX 0x7U
18493 #define V_MODINDX(x) ((x) << S_MODINDX)
18494 #define G_MODINDX(x) (((x) >> S_MODINDX) & M_MODINDX)
18496 #define S_MODOFFSET 0
18497 #define M_MODOFFSET 0x3ffU
18498 #define V_MODOFFSET(x) ((x) << S_MODOFFSET)
18499 #define G_MODOFFSET(x) (((x) >> S_MODOFFSET) & M_MODOFFSET)
18501 #define A_PL_FLR_VF_STATUS 0x194d0
18502 #define A_PL_FLR_PF_STATUS 0x194e0
18505 #define M_FLR_PF 0xffU
18506 #define V_FLR_PF(x) ((x) << S_FLR_PF)
18507 #define G_FLR_PF(x) (((x) >> S_FLR_PF) & M_FLR_PF)
18509 #define A_PL_TIMEOUT_CTL 0x194f0
18511 #define S_PL_TIMEOUT 0
18512 #define M_PL_TIMEOUT 0xffffU
18513 #define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT)
18514 #define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT)
18516 #define A_PL_TIMEOUT_STATUS0 0x194f4
18518 #define S_PL_TOADDR 2
18519 #define M_PL_TOADDR 0xfffffffU
18520 #define V_PL_TOADDR(x) ((x) << S_PL_TOADDR)
18521 #define G_PL_TOADDR(x) (((x) >> S_PL_TOADDR) & M_PL_TOADDR)
18523 #define A_PL_TIMEOUT_STATUS1 0x194f8
18525 #define S_PL_TOVALID 31
18526 #define V_PL_TOVALID(x) ((x) << S_PL_TOVALID)
18527 #define F_PL_TOVALID V_PL_TOVALID(1U)
18530 #define V_WRITE(x) ((x) << S_WRITE)
18531 #define F_WRITE V_WRITE(1U)
18533 #define S_PL_TOBUS 20
18534 #define M_PL_TOBUS 0x3U
18535 #define V_PL_TOBUS(x) ((x) << S_PL_TOBUS)
18536 #define G_PL_TOBUS(x) (((x) >> S_PL_TOBUS) & M_PL_TOBUS)
18539 #define V_RGN(x) ((x) << S_RGN)
18540 #define F_RGN V_RGN(1U)
18542 #define S_PL_TOPF 16
18543 #define M_PL_TOPF 0x7U
18544 #define V_PL_TOPF(x) ((x) << S_PL_TOPF)
18545 #define G_PL_TOPF(x) (((x) >> S_PL_TOPF) & M_PL_TOPF)
18547 #define S_PL_TORID 0
18548 #define M_PL_TORID 0xffffU
18549 #define V_PL_TORID(x) ((x) << S_PL_TORID)
18550 #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)
18552 #define A_PL_VFID_MAP 0x19800
18554 #define S_VFID_VLD 7
18555 #define V_VFID_VLD(x) ((x) << S_VFID_VLD)
18556 #define F_VFID_VLD V_VFID_VLD(1U)
18558 /* registers for module LE */
18559 #define LE_BASE_ADDR 0x19c00
18561 #define A_LE_BUF_CONFIG 0x19c00
18562 #define A_LE_DB_CONFIG 0x19c04
18564 #define S_TCAMCMDOVLAPEN 21
18565 #define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN)
18566 #define F_TCAMCMDOVLAPEN V_TCAMCMDOVLAPEN(1U)
18568 #define S_HASHEN 20
18569 #define V_HASHEN(x) ((x) << S_HASHEN)
18570 #define F_HASHEN V_HASHEN(1U)
18572 #define S_ASBOTHSRCHEN 18
18573 #define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN)
18574 #define F_ASBOTHSRCHEN V_ASBOTHSRCHEN(1U)
18576 #define S_ASLIPCOMPEN 17
18577 #define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN)
18578 #define F_ASLIPCOMPEN V_ASLIPCOMPEN(1U)
18581 #define V_BUILD(x) ((x) << S_BUILD)
18582 #define F_BUILD V_BUILD(1U)
18584 #define S_FILTEREN 11
18585 #define V_FILTEREN(x) ((x) << S_FILTEREN)
18586 #define F_FILTEREN V_FILTEREN(1U)
18588 #define S_SYNMODE 7
18589 #define M_SYNMODE 0x3U
18590 #define V_SYNMODE(x) ((x) << S_SYNMODE)
18591 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
18593 #define S_LEBUSEN 5
18594 #define V_LEBUSEN(x) ((x) << S_LEBUSEN)
18595 #define F_LEBUSEN V_LEBUSEN(1U)
18597 #define S_ELOOKDUMEN 4
18598 #define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN)
18599 #define F_ELOOKDUMEN V_ELOOKDUMEN(1U)
18601 #define S_IPV4ONLYEN 3
18602 #define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN)
18603 #define F_IPV4ONLYEN V_IPV4ONLYEN(1U)
18605 #define S_MOSTCMDOEN 2
18606 #define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN)
18607 #define F_MOSTCMDOEN V_MOSTCMDOEN(1U)
18609 #define S_DELACTSYNOEN 1
18610 #define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN)
18611 #define F_DELACTSYNOEN V_DELACTSYNOEN(1U)
18613 #define S_CMDOVERLAPDIS 0
18614 #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
18615 #define F_CMDOVERLAPDIS V_CMDOVERLAPDIS(1U)
18617 #define A_LE_MISC 0x19c08
18619 #define S_CMPUNVAIL 0
18620 #define M_CMPUNVAIL 0xfU
18621 #define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL)
18622 #define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL)
18624 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
18627 #define M_RTINDX 0x3fU
18628 #define V_RTINDX(x) ((x) << S_RTINDX)
18629 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
18631 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
18634 #define M_FTINDX 0x3fU
18635 #define V_FTINDX(x) ((x) << S_FTINDX)
18636 #define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)
18638 #define A_LE_DB_SERVER_INDEX 0x19c18
18641 #define M_SRINDX 0x3fU
18642 #define V_SRINDX(x) ((x) << S_SRINDX)
18643 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
18645 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
18647 #define S_CLIPTINDX 7
18648 #define M_CLIPTINDX 0x3fU
18649 #define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
18650 #define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)
18652 #define A_LE_DB_ACT_CNT_IPV4 0x19c20
18654 #define S_ACTCNTIPV4 0
18655 #define M_ACTCNTIPV4 0xfffffU
18656 #define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4)
18657 #define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4)
18659 #define A_LE_DB_ACT_CNT_IPV6 0x19c24
18661 #define S_ACTCNTIPV6 0
18662 #define M_ACTCNTIPV6 0xfffffU
18663 #define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6)
18664 #define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6)
18666 #define A_LE_DB_HASH_CONFIG 0x19c28
18668 #define S_HASHTIDSIZE 16
18669 #define M_HASHTIDSIZE 0x3fU
18670 #define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE)
18671 #define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE)
18673 #define S_HASHSIZE 0
18674 #define M_HASHSIZE 0x3fU
18675 #define V_HASHSIZE(x) ((x) << S_HASHSIZE)
18676 #define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)
18678 #define A_LE_DB_HASH_TABLE_BASE 0x19c2c
18679 #define A_LE_DB_HASH_TID_BASE 0x19c30
18680 #define A_LE_DB_SIZE 0x19c34
18681 #define A_LE_DB_INT_ENABLE 0x19c38
18683 #define S_MSGSEL 27
18684 #define M_MSGSEL 0x1fU
18685 #define V_MSGSEL(x) ((x) << S_MSGSEL)
18686 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
18688 #define S_REQQPARERR 16
18689 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
18690 #define F_REQQPARERR V_REQQPARERR(1U)
18692 #define S_UNKNOWNCMD 15
18693 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
18694 #define F_UNKNOWNCMD V_UNKNOWNCMD(1U)
18696 #define S_DROPFILTERHIT 13
18697 #define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT)
18698 #define F_DROPFILTERHIT V_DROPFILTERHIT(1U)
18700 #define S_FILTERHIT 12
18701 #define V_FILTERHIT(x) ((x) << S_FILTERHIT)
18702 #define F_FILTERHIT V_FILTERHIT(1U)
18704 #define S_SYNCOOKIEOFF 11
18705 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
18706 #define F_SYNCOOKIEOFF V_SYNCOOKIEOFF(1U)
18708 #define S_SYNCOOKIEBAD 10
18709 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
18710 #define F_SYNCOOKIEBAD V_SYNCOOKIEBAD(1U)
18712 #define S_SYNCOOKIE 9
18713 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
18714 #define F_SYNCOOKIE V_SYNCOOKIE(1U)
18716 #define S_NFASRCHFAIL 8
18717 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
18718 #define F_NFASRCHFAIL V_NFASRCHFAIL(1U)
18720 #define S_ACTRGNFULL 7
18721 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
18722 #define F_ACTRGNFULL V_ACTRGNFULL(1U)
18724 #define S_PARITYERR 6
18725 #define V_PARITYERR(x) ((x) << S_PARITYERR)
18726 #define F_PARITYERR V_PARITYERR(1U)
18728 #define S_LIPMISS 5
18729 #define V_LIPMISS(x) ((x) << S_LIPMISS)
18730 #define F_LIPMISS V_LIPMISS(1U)
18733 #define V_LIP0(x) ((x) << S_LIP0)
18734 #define F_LIP0 V_LIP0(1U)
18737 #define V_MISS(x) ((x) << S_MISS)
18738 #define F_MISS V_MISS(1U)
18740 #define S_ROUTINGHIT 2
18741 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
18742 #define F_ROUTINGHIT V_ROUTINGHIT(1U)
18744 #define S_ACTIVEHIT 1
18745 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
18746 #define F_ACTIVEHIT V_ACTIVEHIT(1U)
18748 #define S_SERVERHIT 0
18749 #define V_SERVERHIT(x) ((x) << S_SERVERHIT)
18750 #define F_SERVERHIT V_SERVERHIT(1U)
18752 #define A_LE_DB_INT_CAUSE 0x19c3c
18753 #define A_LE_DB_INT_TID 0x19c40
18756 #define M_INTTID 0xfffffU
18757 #define V_INTTID(x) ((x) << S_INTTID)
18758 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
18760 #define A_LE_DB_INT_PTID 0x19c44
18762 #define S_INTPTID 0
18763 #define M_INTPTID 0xfffffU
18764 #define V_INTPTID(x) ((x) << S_INTPTID)
18765 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
18767 #define A_LE_DB_INT_INDEX 0x19c48
18769 #define S_INTINDEX 0
18770 #define M_INTINDEX 0xfffffU
18771 #define V_INTINDEX(x) ((x) << S_INTINDEX)
18772 #define G_INTINDEX(x) (((x) >> S_INTINDEX) & M_INTINDEX)
18774 #define A_LE_DB_INT_CMD 0x19c4c
18777 #define M_INTCMD 0xfU
18778 #define V_INTCMD(x) ((x) << S_INTCMD)
18779 #define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD)
18781 #define A_LE_DB_MASK_IPV4 0x19c50
18782 #define A_LE_DB_MASK_IPV6 0x19ca0
18783 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
18784 #define A_LE_DB_DBGI_CONFIG 0x19cf0
18786 #define S_DBGICMDPERR 31
18787 #define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR)
18788 #define F_DBGICMDPERR V_DBGICMDPERR(1U)
18790 #define S_DBGICMDRANGE 22
18791 #define M_DBGICMDRANGE 0x7U
18792 #define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE)
18793 #define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE)
18795 #define S_DBGICMDMSKTYPE 21
18796 #define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE)
18797 #define F_DBGICMDMSKTYPE V_DBGICMDMSKTYPE(1U)
18799 #define S_DBGICMDSEARCH 20
18800 #define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH)
18801 #define F_DBGICMDSEARCH V_DBGICMDSEARCH(1U)
18803 #define S_DBGICMDREAD 19
18804 #define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD)
18805 #define F_DBGICMDREAD V_DBGICMDREAD(1U)
18807 #define S_DBGICMDLEARN 18
18808 #define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN)
18809 #define F_DBGICMDLEARN V_DBGICMDLEARN(1U)
18811 #define S_DBGICMDERASE 17
18812 #define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE)
18813 #define F_DBGICMDERASE V_DBGICMDERASE(1U)
18815 #define S_DBGICMDIPV6 16
18816 #define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6)
18817 #define F_DBGICMDIPV6 V_DBGICMDIPV6(1U)
18819 #define S_DBGICMDTYPE 13
18820 #define M_DBGICMDTYPE 0x7U
18821 #define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE)
18822 #define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE)
18824 #define S_DBGICMDACKERR 12
18825 #define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR)
18826 #define F_DBGICMDACKERR V_DBGICMDACKERR(1U)
18828 #define S_DBGICMDBUSY 3
18829 #define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY)
18830 #define F_DBGICMDBUSY V_DBGICMDBUSY(1U)
18832 #define S_DBGICMDSTRT 2
18833 #define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT)
18834 #define F_DBGICMDSTRT V_DBGICMDSTRT(1U)
18836 #define S_DBGICMDMODE 0
18837 #define M_DBGICMDMODE 0x3U
18838 #define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
18839 #define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)
18841 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
18843 #define S_DBGICMD 20
18844 #define M_DBGICMD 0xfU
18845 #define V_DBGICMD(x) ((x) << S_DBGICMD)
18846 #define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD)
18848 #define S_DBGITINDEX 0
18849 #define M_DBGITINDEX 0xfffffU
18850 #define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
18851 #define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)
18853 #define A_LE_PERR_ENABLE 0x19cf8
18855 #define S_REQQUEUE 1
18856 #define V_REQQUEUE(x) ((x) << S_REQQUEUE)
18857 #define F_REQQUEUE V_REQQUEUE(1U)
18860 #define V_TCAM(x) ((x) << S_TCAM)
18861 #define F_TCAM V_TCAM(1U)
18863 #define A_LE_SPARE 0x19cfc
18864 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
18865 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
18866 #define A_LE_DB_DBGI_RSP_STATUS 0x19d94
18868 #define S_DBGIRSPINDEX 12
18869 #define M_DBGIRSPINDEX 0xfffffU
18870 #define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX)
18871 #define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX)
18873 #define S_DBGIRSPMSG 8
18874 #define M_DBGIRSPMSG 0xfU
18875 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
18876 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
18878 #define S_DBGIRSPMSGVLD 7
18879 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
18880 #define F_DBGIRSPMSGVLD V_DBGIRSPMSGVLD(1U)
18882 #define S_DBGIRSPMHIT 2
18883 #define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT)
18884 #define F_DBGIRSPMHIT V_DBGIRSPMHIT(1U)
18886 #define S_DBGIRSPHIT 1
18887 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
18888 #define F_DBGIRSPHIT V_DBGIRSPHIT(1U)
18890 #define S_DBGIRSPVALID 0
18891 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
18892 #define F_DBGIRSPVALID V_DBGIRSPVALID(1U)
18894 #define A_LE_DB_DBGI_RSP_DATA 0x19da0
18895 #define A_LE_DB_DBGI_RSP_LAST_CMD 0x19de4
18897 #define S_LASTCMDB 16
18898 #define M_LASTCMDB 0x7ffU
18899 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
18900 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
18902 #define S_LASTCMDA 0
18903 #define M_LASTCMDA 0x7ffU
18904 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
18905 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
18907 #define A_LE_DB_DROP_FILTER_ENTRY 0x19de8
18909 #define S_DROPFILTEREN 31
18910 #define V_DROPFILTEREN(x) ((x) << S_DROPFILTEREN)
18911 #define F_DROPFILTEREN V_DROPFILTEREN(1U)
18913 #define S_DROPFILTERCLEAR 17
18914 #define V_DROPFILTERCLEAR(x) ((x) << S_DROPFILTERCLEAR)
18915 #define F_DROPFILTERCLEAR V_DROPFILTERCLEAR(1U)
18917 #define S_DROPFILTERSET 16
18918 #define V_DROPFILTERSET(x) ((x) << S_DROPFILTERSET)
18919 #define F_DROPFILTERSET V_DROPFILTERSET(1U)
18921 #define S_DROPFILTERFIDX 0
18922 #define M_DROPFILTERFIDX 0x1fffU
18923 #define V_DROPFILTERFIDX(x) ((x) << S_DROPFILTERFIDX)
18924 #define G_DROPFILTERFIDX(x) (((x) >> S_DROPFILTERFIDX) & M_DROPFILTERFIDX)
18926 #define A_LE_DB_PTID_SVRBASE 0x19df0
18928 #define S_SVRBASE_ADDR 2
18929 #define M_SVRBASE_ADDR 0x3ffffU
18930 #define V_SVRBASE_ADDR(x) ((x) << S_SVRBASE_ADDR)
18931 #define G_SVRBASE_ADDR(x) (((x) >> S_SVRBASE_ADDR) & M_SVRBASE_ADDR)
18933 #define A_LE_DB_FTID_FLTRBASE 0x19df4
18935 #define S_FLTRBASE_ADDR 2
18936 #define M_FLTRBASE_ADDR 0x3ffffU
18937 #define V_FLTRBASE_ADDR(x) ((x) << S_FLTRBASE_ADDR)
18938 #define G_FLTRBASE_ADDR(x) (((x) >> S_FLTRBASE_ADDR) & M_FLTRBASE_ADDR)
18940 #define A_LE_DB_TID_HASHBASE 0x19df8
18942 #define S_HASHBASE_ADDR 2
18943 #define M_HASHBASE_ADDR 0xfffffU
18944 #define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
18945 #define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)
18947 #define A_LE_PERR_INJECT 0x19dfc
18949 #define S_LEMEMSEL 1
18950 #define M_LEMEMSEL 0x7U
18951 #define V_LEMEMSEL(x) ((x) << S_LEMEMSEL)
18952 #define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL)
18954 #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
18955 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
18956 #define A_LE_HASH_MASK_GEN_IPV4 0x19ea0
18957 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
18958 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
18959 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
18960 #define A_LE_DEBUG_LA_CONFIG 0x19f20
18961 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24
18962 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
18963 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
18964 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
18966 /* registers for module NCSI */
18967 #define NCSI_BASE_ADDR 0x1a000
18969 #define A_NCSI_PORT_CFGREG 0x1a000
18971 #define S_WIREEN 28
18972 #define M_WIREEN 0xfU
18973 #define V_WIREEN(x) ((x) << S_WIREEN)
18974 #define G_WIREEN(x) (((x) >> S_WIREEN) & M_WIREEN)
18976 #define S_STRP_CRC 24
18977 #define M_STRP_CRC 0xfU
18978 #define V_STRP_CRC(x) ((x) << S_STRP_CRC)
18979 #define G_STRP_CRC(x) (((x) >> S_STRP_CRC) & M_STRP_CRC)
18981 #define S_RX_HALT 22
18982 #define V_RX_HALT(x) ((x) << S_RX_HALT)
18983 #define F_RX_HALT V_RX_HALT(1U)
18985 #define S_FLUSH_RX_FIFO 21
18986 #define V_FLUSH_RX_FIFO(x) ((x) << S_FLUSH_RX_FIFO)
18987 #define F_FLUSH_RX_FIFO V_FLUSH_RX_FIFO(1U)
18989 #define S_HW_ARB_EN 20
18990 #define V_HW_ARB_EN(x) ((x) << S_HW_ARB_EN)
18991 #define F_HW_ARB_EN V_HW_ARB_EN(1U)
18993 #define S_SOFT_PKG_SEL 19
18994 #define V_SOFT_PKG_SEL(x) ((x) << S_SOFT_PKG_SEL)
18995 #define F_SOFT_PKG_SEL V_SOFT_PKG_SEL(1U)
18997 #define S_ERR_DISCARD_EN 18
18998 #define V_ERR_DISCARD_EN(x) ((x) << S_ERR_DISCARD_EN)
18999 #define F_ERR_DISCARD_EN V_ERR_DISCARD_EN(1U)
19001 #define S_MAX_PKT_SIZE 4
19002 #define M_MAX_PKT_SIZE 0x3fffU
19003 #define V_MAX_PKT_SIZE(x) ((x) << S_MAX_PKT_SIZE)
19004 #define G_MAX_PKT_SIZE(x) (((x) >> S_MAX_PKT_SIZE) & M_MAX_PKT_SIZE)
19006 #define S_RX_BYTE_SWAP 3
19007 #define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP)
19008 #define F_RX_BYTE_SWAP V_RX_BYTE_SWAP(1U)
19010 #define S_TX_BYTE_SWAP 2
19011 #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
19012 #define F_TX_BYTE_SWAP V_TX_BYTE_SWAP(1U)
19014 #define A_NCSI_RST_CTRL 0x1a004
19016 #define S_MAC_REF_RST 2
19017 #define V_MAC_REF_RST(x) ((x) << S_MAC_REF_RST)
19018 #define F_MAC_REF_RST V_MAC_REF_RST(1U)
19020 #define S_MAC_RX_RST 1
19021 #define V_MAC_RX_RST(x) ((x) << S_MAC_RX_RST)
19022 #define F_MAC_RX_RST V_MAC_RX_RST(1U)
19024 #define S_MAC_TX_RST 0
19025 #define V_MAC_TX_RST(x) ((x) << S_MAC_TX_RST)
19026 #define F_MAC_TX_RST V_MAC_TX_RST(1U)
19028 #define A_NCSI_CH0_SADDR_LOW 0x1a010
19029 #define A_NCSI_CH0_SADDR_HIGH 0x1a014
19031 #define S_CHO_SADDR_EN 31
19032 #define V_CHO_SADDR_EN(x) ((x) << S_CHO_SADDR_EN)
19033 #define F_CHO_SADDR_EN V_CHO_SADDR_EN(1U)
19035 #define S_CH0_SADDR_HIGH 0
19036 #define M_CH0_SADDR_HIGH 0xffffU
19037 #define V_CH0_SADDR_HIGH(x) ((x) << S_CH0_SADDR_HIGH)
19038 #define G_CH0_SADDR_HIGH(x) (((x) >> S_CH0_SADDR_HIGH) & M_CH0_SADDR_HIGH)
19040 #define A_NCSI_CH1_SADDR_LOW 0x1a018
19041 #define A_NCSI_CH1_SADDR_HIGH 0x1a01c
19043 #define S_CH1_SADDR_EN 31
19044 #define V_CH1_SADDR_EN(x) ((x) << S_CH1_SADDR_EN)
19045 #define F_CH1_SADDR_EN V_CH1_SADDR_EN(1U)
19047 #define S_CH1_SADDR_HIGH 0
19048 #define M_CH1_SADDR_HIGH 0xffffU
19049 #define V_CH1_SADDR_HIGH(x) ((x) << S_CH1_SADDR_HIGH)
19050 #define G_CH1_SADDR_HIGH(x) (((x) >> S_CH1_SADDR_HIGH) & M_CH1_SADDR_HIGH)
19052 #define A_NCSI_CH2_SADDR_LOW 0x1a020
19053 #define A_NCSI_CH2_SADDR_HIGH 0x1a024
19055 #define S_CH2_SADDR_EN 31
19056 #define V_CH2_SADDR_EN(x) ((x) << S_CH2_SADDR_EN)
19057 #define F_CH2_SADDR_EN V_CH2_SADDR_EN(1U)
19059 #define S_CH2_SADDR_HIGH 0
19060 #define M_CH2_SADDR_HIGH 0xffffU
19061 #define V_CH2_SADDR_HIGH(x) ((x) << S_CH2_SADDR_HIGH)
19062 #define G_CH2_SADDR_HIGH(x) (((x) >> S_CH2_SADDR_HIGH) & M_CH2_SADDR_HIGH)
19064 #define A_NCSI_CH3_SADDR_LOW 0x1a028
19065 #define A_NCSI_CH3_SADDR_HIGH 0x1a02c
19067 #define S_CH3_SADDR_EN 31
19068 #define V_CH3_SADDR_EN(x) ((x) << S_CH3_SADDR_EN)
19069 #define F_CH3_SADDR_EN V_CH3_SADDR_EN(1U)
19071 #define S_CH3_SADDR_HIGH 0
19072 #define M_CH3_SADDR_HIGH 0xffffU
19073 #define V_CH3_SADDR_HIGH(x) ((x) << S_CH3_SADDR_HIGH)
19074 #define G_CH3_SADDR_HIGH(x) (((x) >> S_CH3_SADDR_HIGH) & M_CH3_SADDR_HIGH)
19076 #define A_NCSI_WORK_REQHDR_0 0x1a030
19077 #define A_NCSI_WORK_REQHDR_1 0x1a034
19078 #define A_NCSI_WORK_REQHDR_2 0x1a038
19079 #define A_NCSI_WORK_REQHDR_3 0x1a03c
19080 #define A_NCSI_MPS_HDR_LO 0x1a040
19081 #define A_NCSI_MPS_HDR_HI 0x1a044
19082 #define A_NCSI_CTL 0x1a048
19084 #define S_STRIP_OVLAN 3
19085 #define V_STRIP_OVLAN(x) ((x) << S_STRIP_OVLAN)
19086 #define F_STRIP_OVLAN V_STRIP_OVLAN(1U)
19088 #define S_BMC_DROP_NON_BC 2
19089 #define V_BMC_DROP_NON_BC(x) ((x) << S_BMC_DROP_NON_BC)
19090 #define F_BMC_DROP_NON_BC V_BMC_DROP_NON_BC(1U)
19092 #define S_BMC_RX_FWD_ALL 1
19093 #define V_BMC_RX_FWD_ALL(x) ((x) << S_BMC_RX_FWD_ALL)
19094 #define F_BMC_RX_FWD_ALL V_BMC_RX_FWD_ALL(1U)
19096 #define S_FWD_BMC 0
19097 #define V_FWD_BMC(x) ((x) << S_FWD_BMC)
19098 #define F_FWD_BMC V_FWD_BMC(1U)
19100 #define A_NCSI_NCSI_ETYPE 0x1a04c
19102 #define S_NCSI_ETHERTYPE 0
19103 #define M_NCSI_ETHERTYPE 0xffffU
19104 #define V_NCSI_ETHERTYPE(x) ((x) << S_NCSI_ETHERTYPE)
19105 #define G_NCSI_ETHERTYPE(x) (((x) >> S_NCSI_ETHERTYPE) & M_NCSI_ETHERTYPE)
19107 #define A_NCSI_RX_FIFO_CNT 0x1a050
19109 #define S_NCSI_RXFIFO_CNT 0
19110 #define M_NCSI_RXFIFO_CNT 0x7ffU
19111 #define V_NCSI_RXFIFO_CNT(x) ((x) << S_NCSI_RXFIFO_CNT)
19112 #define G_NCSI_RXFIFO_CNT(x) (((x) >> S_NCSI_RXFIFO_CNT) & M_NCSI_RXFIFO_CNT)
19114 #define A_NCSI_RX_ERR_CNT 0x1a054
19115 #define A_NCSI_RX_OF_CNT 0x1a058
19116 #define A_NCSI_RX_MS_CNT 0x1a05c
19117 #define A_NCSI_RX_IE_CNT 0x1a060
19118 #define A_NCSI_MPS_DEMUX_CNT 0x1a064
19120 #define S_MPS2CIM_CNT 16
19121 #define M_MPS2CIM_CNT 0x1ffU
19122 #define V_MPS2CIM_CNT(x) ((x) << S_MPS2CIM_CNT)
19123 #define G_MPS2CIM_CNT(x) (((x) >> S_MPS2CIM_CNT) & M_MPS2CIM_CNT)
19125 #define S_MPS2BMC_CNT 0
19126 #define M_MPS2BMC_CNT 0x1ffU
19127 #define V_MPS2BMC_CNT(x) ((x) << S_MPS2BMC_CNT)
19128 #define G_MPS2BMC_CNT(x) (((x) >> S_MPS2BMC_CNT) & M_MPS2BMC_CNT)
19130 #define A_NCSI_CIM_DEMUX_CNT 0x1a068
19132 #define S_CIM2MPS_CNT 16
19133 #define M_CIM2MPS_CNT 0x1ffU
19134 #define V_CIM2MPS_CNT(x) ((x) << S_CIM2MPS_CNT)
19135 #define G_CIM2MPS_CNT(x) (((x) >> S_CIM2MPS_CNT) & M_CIM2MPS_CNT)
19137 #define S_CIM2BMC_CNT 0
19138 #define M_CIM2BMC_CNT 0x1ffU
19139 #define V_CIM2BMC_CNT(x) ((x) << S_CIM2BMC_CNT)
19140 #define G_CIM2BMC_CNT(x) (((x) >> S_CIM2BMC_CNT) & M_CIM2BMC_CNT)
19142 #define A_NCSI_TX_FIFO_CNT 0x1a06c
19144 #define S_TX_FIFO_CNT 0
19145 #define M_TX_FIFO_CNT 0x3ffU
19146 #define V_TX_FIFO_CNT(x) ((x) << S_TX_FIFO_CNT)
19147 #define G_TX_FIFO_CNT(x) (((x) >> S_TX_FIFO_CNT) & M_TX_FIFO_CNT)
19149 #define A_NCSI_SE_CNT_CTL 0x1a0b0
19151 #define S_SE_CNT_CLR 0
19152 #define M_SE_CNT_CLR 0xfU
19153 #define V_SE_CNT_CLR(x) ((x) << S_SE_CNT_CLR)
19154 #define G_SE_CNT_CLR(x) (((x) >> S_SE_CNT_CLR) & M_SE_CNT_CLR)
19156 #define A_NCSI_SE_CNT_MPS 0x1a0b4
19158 #define S_NC2MPS_SOP_CNT 24
19159 #define M_NC2MPS_SOP_CNT 0xffU
19160 #define V_NC2MPS_SOP_CNT(x) ((x) << S_NC2MPS_SOP_CNT)
19161 #define G_NC2MPS_SOP_CNT(x) (((x) >> S_NC2MPS_SOP_CNT) & M_NC2MPS_SOP_CNT)
19163 #define S_NC2MPS_EOP_CNT 16
19164 #define M_NC2MPS_EOP_CNT 0x3fU
19165 #define V_NC2MPS_EOP_CNT(x) ((x) << S_NC2MPS_EOP_CNT)
19166 #define G_NC2MPS_EOP_CNT(x) (((x) >> S_NC2MPS_EOP_CNT) & M_NC2MPS_EOP_CNT)
19168 #define S_MPS2NC_SOP_CNT 8
19169 #define M_MPS2NC_SOP_CNT 0xffU
19170 #define V_MPS2NC_SOP_CNT(x) ((x) << S_MPS2NC_SOP_CNT)
19171 #define G_MPS2NC_SOP_CNT(x) (((x) >> S_MPS2NC_SOP_CNT) & M_MPS2NC_SOP_CNT)
19173 #define S_MPS2NC_EOP_CNT 0
19174 #define M_MPS2NC_EOP_CNT 0xffU
19175 #define V_MPS2NC_EOP_CNT(x) ((x) << S_MPS2NC_EOP_CNT)
19176 #define G_MPS2NC_EOP_CNT(x) (((x) >> S_MPS2NC_EOP_CNT) & M_MPS2NC_EOP_CNT)
19178 #define A_NCSI_SE_CNT_CIM 0x1a0b8
19180 #define S_NC2CIM_SOP_CNT 24
19181 #define M_NC2CIM_SOP_CNT 0xffU
19182 #define V_NC2CIM_SOP_CNT(x) ((x) << S_NC2CIM_SOP_CNT)
19183 #define G_NC2CIM_SOP_CNT(x) (((x) >> S_NC2CIM_SOP_CNT) & M_NC2CIM_SOP_CNT)
19185 #define S_NC2CIM_EOP_CNT 16
19186 #define M_NC2CIM_EOP_CNT 0x3fU
19187 #define V_NC2CIM_EOP_CNT(x) ((x) << S_NC2CIM_EOP_CNT)
19188 #define G_NC2CIM_EOP_CNT(x) (((x) >> S_NC2CIM_EOP_CNT) & M_NC2CIM_EOP_CNT)
19190 #define S_CIM2NC_SOP_CNT 8
19191 #define M_CIM2NC_SOP_CNT 0xffU
19192 #define V_CIM2NC_SOP_CNT(x) ((x) << S_CIM2NC_SOP_CNT)
19193 #define G_CIM2NC_SOP_CNT(x) (((x) >> S_CIM2NC_SOP_CNT) & M_CIM2NC_SOP_CNT)
19195 #define S_CIM2NC_EOP_CNT 0
19196 #define M_CIM2NC_EOP_CNT 0xffU
19197 #define V_CIM2NC_EOP_CNT(x) ((x) << S_CIM2NC_EOP_CNT)
19198 #define G_CIM2NC_EOP_CNT(x) (((x) >> S_CIM2NC_EOP_CNT) & M_CIM2NC_EOP_CNT)
19200 #define A_NCSI_BUS_DEBUG 0x1a0bc
19202 #define S_SOP_CNT_ERR 12
19203 #define M_SOP_CNT_ERR 0xfU
19204 #define V_SOP_CNT_ERR(x) ((x) << S_SOP_CNT_ERR)
19205 #define G_SOP_CNT_ERR(x) (((x) >> S_SOP_CNT_ERR) & M_SOP_CNT_ERR)
19207 #define S_BUS_STATE_MPS_OUT 6
19208 #define M_BUS_STATE_MPS_OUT 0x3U
19209 #define V_BUS_STATE_MPS_OUT(x) ((x) << S_BUS_STATE_MPS_OUT)
19210 #define G_BUS_STATE_MPS_OUT(x) (((x) >> S_BUS_STATE_MPS_OUT) & M_BUS_STATE_MPS_OUT)
19212 #define S_BUS_STATE_MPS_IN 4
19213 #define M_BUS_STATE_MPS_IN 0x3U
19214 #define V_BUS_STATE_MPS_IN(x) ((x) << S_BUS_STATE_MPS_IN)
19215 #define G_BUS_STATE_MPS_IN(x) (((x) >> S_BUS_STATE_MPS_IN) & M_BUS_STATE_MPS_IN)
19217 #define S_BUS_STATE_CIM_OUT 2
19218 #define M_BUS_STATE_CIM_OUT 0x3U
19219 #define V_BUS_STATE_CIM_OUT(x) ((x) << S_BUS_STATE_CIM_OUT)
19220 #define G_BUS_STATE_CIM_OUT(x) (((x) >> S_BUS_STATE_CIM_OUT) & M_BUS_STATE_CIM_OUT)
19222 #define S_BUS_STATE_CIM_IN 0
19223 #define M_BUS_STATE_CIM_IN 0x3U
19224 #define V_BUS_STATE_CIM_IN(x) ((x) << S_BUS_STATE_CIM_IN)
19225 #define G_BUS_STATE_CIM_IN(x) (((x) >> S_BUS_STATE_CIM_IN) & M_BUS_STATE_CIM_IN)
19227 #define A_NCSI_LA_RDPTR 0x1a0c0
19228 #define A_NCSI_LA_RDDATA 0x1a0c4
19229 #define A_NCSI_LA_WRPTR 0x1a0c8
19230 #define A_NCSI_LA_RESERVED 0x1a0cc
19231 #define A_NCSI_LA_CTL 0x1a0d0
19232 #define A_NCSI_INT_ENABLE 0x1a0d4
19234 #define S_CIM_DM_PRTY_ERR 8
19235 #define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR)
19236 #define F_CIM_DM_PRTY_ERR V_CIM_DM_PRTY_ERR(1U)
19238 #define S_MPS_DM_PRTY_ERR 7
19239 #define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR)
19240 #define F_MPS_DM_PRTY_ERR V_MPS_DM_PRTY_ERR(1U)
19243 #define V_TOKEN(x) ((x) << S_TOKEN)
19244 #define F_TOKEN V_TOKEN(1U)
19246 #define S_ARB_DONE 5
19247 #define V_ARB_DONE(x) ((x) << S_ARB_DONE)
19248 #define F_ARB_DONE V_ARB_DONE(1U)
19250 #define S_ARB_STARTED 4
19251 #define V_ARB_STARTED(x) ((x) << S_ARB_STARTED)
19252 #define F_ARB_STARTED V_ARB_STARTED(1U)
19255 #define V_WOL(x) ((x) << S_WOL)
19256 #define F_WOL V_WOL(1U)
19259 #define V_MACINT(x) ((x) << S_MACINT)
19260 #define F_MACINT V_MACINT(1U)
19262 #define S_TXFIFO_PRTY_ERR 1
19263 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
19264 #define F_TXFIFO_PRTY_ERR V_TXFIFO_PRTY_ERR(1U)
19266 #define S_RXFIFO_PRTY_ERR 0
19267 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
19268 #define F_RXFIFO_PRTY_ERR V_RXFIFO_PRTY_ERR(1U)
19270 #define A_NCSI_INT_CAUSE 0x1a0d8
19271 #define A_NCSI_STATUS 0x1a0dc
19274 #define V_MASTER(x) ((x) << S_MASTER)
19275 #define F_MASTER V_MASTER(1U)
19277 #define S_ARB_STATUS 0
19278 #define V_ARB_STATUS(x) ((x) << S_ARB_STATUS)
19279 #define F_ARB_STATUS V_ARB_STATUS(1U)
19281 #define A_NCSI_PAUSE_CTRL 0x1a0e0
19283 #define S_FORCEPAUSE 0
19284 #define V_FORCEPAUSE(x) ((x) << S_FORCEPAUSE)
19285 #define F_FORCEPAUSE V_FORCEPAUSE(1U)
19287 #define A_NCSI_PAUSE_TIMEOUT 0x1a0e4
19288 #define A_NCSI_PAUSE_WM 0x1a0ec
19290 #define S_PAUSEHWM 16
19291 #define M_PAUSEHWM 0x7ffU
19292 #define V_PAUSEHWM(x) ((x) << S_PAUSEHWM)
19293 #define G_PAUSEHWM(x) (((x) >> S_PAUSEHWM) & M_PAUSEHWM)
19295 #define S_PAUSELWM 0
19296 #define M_PAUSELWM 0x7ffU
19297 #define V_PAUSELWM(x) ((x) << S_PAUSELWM)
19298 #define G_PAUSELWM(x) (((x) >> S_PAUSELWM) & M_PAUSELWM)
19300 #define A_NCSI_DEBUG 0x1a0f0
19302 #define S_DEBUGSEL 0
19303 #define M_DEBUGSEL 0x3fU
19304 #define V_DEBUGSEL(x) ((x) << S_DEBUGSEL)
19305 #define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL)
19307 #define A_NCSI_PERR_INJECT 0x1a0f4
19309 #define S_MCSIMELSEL 1
19310 #define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL)
19311 #define F_MCSIMELSEL V_MCSIMELSEL(1U)
19313 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100
19315 #define S_TXSNDZEROPAUSE 12
19316 #define V_TXSNDZEROPAUSE(x) ((x) << S_TXSNDZEROPAUSE)
19317 #define F_TXSNDZEROPAUSE V_TXSNDZEROPAUSE(1U)
19319 #define S_TXSNDPAUSE 11
19320 #define V_TXSNDPAUSE(x) ((x) << S_TXSNDPAUSE)
19321 #define F_TXSNDPAUSE V_TXSNDPAUSE(1U)
19323 #define S_TXSTOP 10
19324 #define V_TXSTOP(x) ((x) << S_TXSTOP)
19325 #define F_TXSTOP V_TXSTOP(1U)
19327 #define S_TXSTART 9
19328 #define V_TXSTART(x) ((x) << S_TXSTART)
19329 #define F_TXSTART V_TXSTART(1U)
19331 #define S_BACKPRESS 8
19332 #define V_BACKPRESS(x) ((x) << S_BACKPRESS)
19333 #define F_BACKPRESS V_BACKPRESS(1U)
19335 #define S_STATWREN 7
19336 #define V_STATWREN(x) ((x) << S_STATWREN)
19337 #define F_STATWREN V_STATWREN(1U)
19339 #define S_INCRSTAT 6
19340 #define V_INCRSTAT(x) ((x) << S_INCRSTAT)
19341 #define F_INCRSTAT V_INCRSTAT(1U)
19343 #define S_CLEARSTAT 5
19344 #define V_CLEARSTAT(x) ((x) << S_CLEARSTAT)
19345 #define F_CLEARSTAT V_CLEARSTAT(1U)
19347 #define S_ENMGMTPORT 4
19348 #define V_ENMGMTPORT(x) ((x) << S_ENMGMTPORT)
19349 #define F_ENMGMTPORT V_ENMGMTPORT(1U)
19351 #define S_NCSITXEN 3
19352 #define V_NCSITXEN(x) ((x) << S_NCSITXEN)
19353 #define F_NCSITXEN V_NCSITXEN(1U)
19355 #define S_NCSIRXEN 2
19356 #define V_NCSIRXEN(x) ((x) << S_NCSIRXEN)
19357 #define F_NCSIRXEN V_NCSIRXEN(1U)
19359 #define S_LOOPLOCAL 1
19360 #define V_LOOPLOCAL(x) ((x) << S_LOOPLOCAL)
19361 #define F_LOOPLOCAL V_LOOPLOCAL(1U)
19363 #define S_LOOPPHY 0
19364 #define V_LOOPPHY(x) ((x) << S_LOOPPHY)
19365 #define F_LOOPPHY V_LOOPPHY(1U)
19367 #define A_NCSI_MACB_NETWORK_CFG 0x1a104
19369 #define S_PCLKDIV128 22
19370 #define V_PCLKDIV128(x) ((x) << S_PCLKDIV128)
19371 #define F_PCLKDIV128 V_PCLKDIV128(1U)
19373 #define S_COPYPAUSE 21
19374 #define V_COPYPAUSE(x) ((x) << S_COPYPAUSE)
19375 #define F_COPYPAUSE V_COPYPAUSE(1U)
19377 #define S_NONSTDPREOK 20
19378 #define V_NONSTDPREOK(x) ((x) << S_NONSTDPREOK)
19379 #define F_NONSTDPREOK V_NONSTDPREOK(1U)
19382 #define V_NOFCS(x) ((x) << S_NOFCS)
19383 #define F_NOFCS V_NOFCS(1U)
19385 #define S_RXENHALFDUP 18
19386 #define V_RXENHALFDUP(x) ((x) << S_RXENHALFDUP)
19387 #define F_RXENHALFDUP V_RXENHALFDUP(1U)
19389 #define S_NOCOPYFCS 17
19390 #define V_NOCOPYFCS(x) ((x) << S_NOCOPYFCS)
19391 #define F_NOCOPYFCS V_NOCOPYFCS(1U)
19393 #define S_LENCHKEN 16
19394 #define V_LENCHKEN(x) ((x) << S_LENCHKEN)
19395 #define F_LENCHKEN V_LENCHKEN(1U)
19397 #define S_RXBUFOFFSET 14
19398 #define M_RXBUFOFFSET 0x3U
19399 #define V_RXBUFOFFSET(x) ((x) << S_RXBUFOFFSET)
19400 #define G_RXBUFOFFSET(x) (((x) >> S_RXBUFOFFSET) & M_RXBUFOFFSET)
19402 #define S_PAUSEEN 13
19403 #define V_PAUSEEN(x) ((x) << S_PAUSEEN)
19404 #define F_PAUSEEN V_PAUSEEN(1U)
19406 #define S_RETRYTEST 12
19407 #define V_RETRYTEST(x) ((x) << S_RETRYTEST)
19408 #define F_RETRYTEST V_RETRYTEST(1U)
19410 #define S_PCLKDIV 10
19411 #define M_PCLKDIV 0x3U
19412 #define V_PCLKDIV(x) ((x) << S_PCLKDIV)
19413 #define G_PCLKDIV(x) (((x) >> S_PCLKDIV) & M_PCLKDIV)
19415 #define S_EXTCLASS 9
19416 #define V_EXTCLASS(x) ((x) << S_EXTCLASS)
19417 #define F_EXTCLASS V_EXTCLASS(1U)
19419 #define S_EN1536FRAME 8
19420 #define V_EN1536FRAME(x) ((x) << S_EN1536FRAME)
19421 #define F_EN1536FRAME V_EN1536FRAME(1U)
19423 #define S_UCASTHASHEN 7
19424 #define V_UCASTHASHEN(x) ((x) << S_UCASTHASHEN)
19425 #define F_UCASTHASHEN V_UCASTHASHEN(1U)
19427 #define S_MCASTHASHEN 6
19428 #define V_MCASTHASHEN(x) ((x) << S_MCASTHASHEN)
19429 #define F_MCASTHASHEN V_MCASTHASHEN(1U)
19431 #define S_RXBCASTDIS 5
19432 #define V_RXBCASTDIS(x) ((x) << S_RXBCASTDIS)
19433 #define F_RXBCASTDIS V_RXBCASTDIS(1U)
19435 #define S_NCSICOPYALLFRAMES 4
19436 #define V_NCSICOPYALLFRAMES(x) ((x) << S_NCSICOPYALLFRAMES)
19437 #define F_NCSICOPYALLFRAMES V_NCSICOPYALLFRAMES(1U)
19439 #define S_JUMBOEN 3
19440 #define V_JUMBOEN(x) ((x) << S_JUMBOEN)
19441 #define F_JUMBOEN V_JUMBOEN(1U)
19444 #define V_SEREN(x) ((x) << S_SEREN)
19445 #define F_SEREN V_SEREN(1U)
19447 #define S_FULLDUPLEX 1
19448 #define V_FULLDUPLEX(x) ((x) << S_FULLDUPLEX)
19449 #define F_FULLDUPLEX V_FULLDUPLEX(1U)
19452 #define V_SPEED(x) ((x) << S_SPEED)
19453 #define F_SPEED V_SPEED(1U)
19455 #define A_NCSI_MACB_NETWORK_STATUS 0x1a108
19457 #define S_PHYMGMTSTATUS 2
19458 #define V_PHYMGMTSTATUS(x) ((x) << S_PHYMGMTSTATUS)
19459 #define F_PHYMGMTSTATUS V_PHYMGMTSTATUS(1U)
19461 #define S_MDISTATUS 1
19462 #define V_MDISTATUS(x) ((x) << S_MDISTATUS)
19463 #define F_MDISTATUS V_MDISTATUS(1U)
19465 #define S_LINKSTATUS 0
19466 #define V_LINKSTATUS(x) ((x) << S_LINKSTATUS)
19467 #define F_LINKSTATUS V_LINKSTATUS(1U)
19469 #define A_NCSI_MACB_TX_STATUS 0x1a114
19471 #define S_UNDERRUNERR 6
19472 #define V_UNDERRUNERR(x) ((x) << S_UNDERRUNERR)
19473 #define F_UNDERRUNERR V_UNDERRUNERR(1U)
19475 #define S_TXCOMPLETE 5
19476 #define V_TXCOMPLETE(x) ((x) << S_TXCOMPLETE)
19477 #define F_TXCOMPLETE V_TXCOMPLETE(1U)
19479 #define S_BUFFEREXHAUSTED 4
19480 #define V_BUFFEREXHAUSTED(x) ((x) << S_BUFFEREXHAUSTED)
19481 #define F_BUFFEREXHAUSTED V_BUFFEREXHAUSTED(1U)
19483 #define S_TXPROGRESS 3
19484 #define V_TXPROGRESS(x) ((x) << S_TXPROGRESS)
19485 #define F_TXPROGRESS V_TXPROGRESS(1U)
19487 #define S_RETRYLIMIT 2
19488 #define V_RETRYLIMIT(x) ((x) << S_RETRYLIMIT)
19489 #define F_RETRYLIMIT V_RETRYLIMIT(1U)
19491 #define S_COLEVENT 1
19492 #define V_COLEVENT(x) ((x) << S_COLEVENT)
19493 #define F_COLEVENT V_COLEVENT(1U)
19495 #define S_USEDBITREAD 0
19496 #define V_USEDBITREAD(x) ((x) << S_USEDBITREAD)
19497 #define F_USEDBITREAD V_USEDBITREAD(1U)
19499 #define A_NCSI_MACB_RX_BUF_QPTR 0x1a118
19501 #define S_RXBUFQPTR 2
19502 #define M_RXBUFQPTR 0x3fffffffU
19503 #define V_RXBUFQPTR(x) ((x) << S_RXBUFQPTR)
19504 #define G_RXBUFQPTR(x) (((x) >> S_RXBUFQPTR) & M_RXBUFQPTR)
19506 #define A_NCSI_MACB_TX_BUF_QPTR 0x1a11c
19508 #define S_TXBUFQPTR 2
19509 #define M_TXBUFQPTR 0x3fffffffU
19510 #define V_TXBUFQPTR(x) ((x) << S_TXBUFQPTR)
19511 #define G_TXBUFQPTR(x) (((x) >> S_TXBUFQPTR) & M_TXBUFQPTR)
19513 #define A_NCSI_MACB_RX_STATUS 0x1a120
19515 #define S_RXOVERRUNERR 2
19516 #define V_RXOVERRUNERR(x) ((x) << S_RXOVERRUNERR)
19517 #define F_RXOVERRUNERR V_RXOVERRUNERR(1U)
19519 #define S_MACB_FRAMERCVD 1
19520 #define V_MACB_FRAMERCVD(x) ((x) << S_MACB_FRAMERCVD)
19521 #define F_MACB_FRAMERCVD V_MACB_FRAMERCVD(1U)
19523 #define S_NORXBUF 0
19524 #define V_NORXBUF(x) ((x) << S_NORXBUF)
19525 #define F_NORXBUF V_NORXBUF(1U)
19527 #define A_NCSI_MACB_INT_STATUS 0x1a124
19529 #define S_PAUSETIMEZERO 13
19530 #define V_PAUSETIMEZERO(x) ((x) << S_PAUSETIMEZERO)
19531 #define F_PAUSETIMEZERO V_PAUSETIMEZERO(1U)
19533 #define S_PAUSERCVD 12
19534 #define V_PAUSERCVD(x) ((x) << S_PAUSERCVD)
19535 #define F_PAUSERCVD V_PAUSERCVD(1U)
19537 #define S_HRESPNOTOK 11
19538 #define V_HRESPNOTOK(x) ((x) << S_HRESPNOTOK)
19539 #define F_HRESPNOTOK V_HRESPNOTOK(1U)
19541 #define S_RXOVERRUN 10
19542 #define V_RXOVERRUN(x) ((x) << S_RXOVERRUN)
19543 #define F_RXOVERRUN V_RXOVERRUN(1U)
19545 #define S_LINKCHANGE 9
19546 #define V_LINKCHANGE(x) ((x) << S_LINKCHANGE)
19547 #define F_LINKCHANGE V_LINKCHANGE(1U)
19549 #define S_INT_TXCOMPLETE 7
19550 #define V_INT_TXCOMPLETE(x) ((x) << S_INT_TXCOMPLETE)
19551 #define F_INT_TXCOMPLETE V_INT_TXCOMPLETE(1U)
19553 #define S_TXBUFERR 6
19554 #define V_TXBUFERR(x) ((x) << S_TXBUFERR)
19555 #define F_TXBUFERR V_TXBUFERR(1U)
19557 #define S_RETRYLIMITERR 5
19558 #define V_RETRYLIMITERR(x) ((x) << S_RETRYLIMITERR)
19559 #define F_RETRYLIMITERR V_RETRYLIMITERR(1U)
19561 #define S_TXBUFUNDERRUN 4
19562 #define V_TXBUFUNDERRUN(x) ((x) << S_TXBUFUNDERRUN)
19563 #define F_TXBUFUNDERRUN V_TXBUFUNDERRUN(1U)
19565 #define S_TXUSEDBITREAD 3
19566 #define V_TXUSEDBITREAD(x) ((x) << S_TXUSEDBITREAD)
19567 #define F_TXUSEDBITREAD V_TXUSEDBITREAD(1U)
19569 #define S_RXUSEDBITREAD 2
19570 #define V_RXUSEDBITREAD(x) ((x) << S_RXUSEDBITREAD)
19571 #define F_RXUSEDBITREAD V_RXUSEDBITREAD(1U)
19573 #define S_RXCOMPLETE 1
19574 #define V_RXCOMPLETE(x) ((x) << S_RXCOMPLETE)
19575 #define F_RXCOMPLETE V_RXCOMPLETE(1U)
19577 #define S_MGMTFRAMESENT 0
19578 #define V_MGMTFRAMESENT(x) ((x) << S_MGMTFRAMESENT)
19579 #define F_MGMTFRAMESENT V_MGMTFRAMESENT(1U)
19581 #define A_NCSI_MACB_INT_EN 0x1a128
19582 #define A_NCSI_MACB_INT_DIS 0x1a12c
19583 #define A_NCSI_MACB_INT_MASK 0x1a130
19584 #define A_NCSI_MACB_PAUSE_TIME 0x1a138
19586 #define S_PAUSETIME 0
19587 #define M_PAUSETIME 0xffffU
19588 #define V_PAUSETIME(x) ((x) << S_PAUSETIME)
19589 #define G_PAUSETIME(x) (((x) >> S_PAUSETIME) & M_PAUSETIME)
19591 #define A_NCSI_MACB_PAUSE_FRAMES_RCVD 0x1a13c
19593 #define S_PAUSEFRRCVD 0
19594 #define M_PAUSEFRRCVD 0xffffU
19595 #define V_PAUSEFRRCVD(x) ((x) << S_PAUSEFRRCVD)
19596 #define G_PAUSEFRRCVD(x) (((x) >> S_PAUSEFRRCVD) & M_PAUSEFRRCVD)
19598 #define A_NCSI_MACB_TX_FRAMES_OK 0x1a140
19600 #define S_TXFRAMESOK 0
19601 #define M_TXFRAMESOK 0xffffffU
19602 #define V_TXFRAMESOK(x) ((x) << S_TXFRAMESOK)
19603 #define G_TXFRAMESOK(x) (((x) >> S_TXFRAMESOK) & M_TXFRAMESOK)
19605 #define A_NCSI_MACB_SINGLE_COL_FRAMES 0x1a144
19607 #define S_SINGLECOLTXFRAMES 0
19608 #define M_SINGLECOLTXFRAMES 0xffffU
19609 #define V_SINGLECOLTXFRAMES(x) ((x) << S_SINGLECOLTXFRAMES)
19610 #define G_SINGLECOLTXFRAMES(x) (((x) >> S_SINGLECOLTXFRAMES) & M_SINGLECOLTXFRAMES)
19612 #define A_NCSI_MACB_MUL_COL_FRAMES 0x1a148
19614 #define S_MULCOLTXFRAMES 0
19615 #define M_MULCOLTXFRAMES 0xffffU
19616 #define V_MULCOLTXFRAMES(x) ((x) << S_MULCOLTXFRAMES)
19617 #define G_MULCOLTXFRAMES(x) (((x) >> S_MULCOLTXFRAMES) & M_MULCOLTXFRAMES)
19619 #define A_NCSI_MACB_RX_FRAMES_OK 0x1a14c
19621 #define S_RXFRAMESOK 0
19622 #define M_RXFRAMESOK 0xffffffU
19623 #define V_RXFRAMESOK(x) ((x) << S_RXFRAMESOK)
19624 #define G_RXFRAMESOK(x) (((x) >> S_RXFRAMESOK) & M_RXFRAMESOK)
19626 #define A_NCSI_MACB_FCS_ERR 0x1a150
19628 #define S_RXFCSERR 0
19629 #define M_RXFCSERR 0xffU
19630 #define V_RXFCSERR(x) ((x) << S_RXFCSERR)
19631 #define G_RXFCSERR(x) (((x) >> S_RXFCSERR) & M_RXFCSERR)
19633 #define A_NCSI_MACB_ALIGN_ERR 0x1a154
19635 #define S_RXALIGNERR 0
19636 #define M_RXALIGNERR 0xffU
19637 #define V_RXALIGNERR(x) ((x) << S_RXALIGNERR)
19638 #define G_RXALIGNERR(x) (((x) >> S_RXALIGNERR) & M_RXALIGNERR)
19640 #define A_NCSI_MACB_DEF_TX_FRAMES 0x1a158
19642 #define S_TXDEFERREDFRAMES 0
19643 #define M_TXDEFERREDFRAMES 0xffffU
19644 #define V_TXDEFERREDFRAMES(x) ((x) << S_TXDEFERREDFRAMES)
19645 #define G_TXDEFERREDFRAMES(x) (((x) >> S_TXDEFERREDFRAMES) & M_TXDEFERREDFRAMES)
19647 #define A_NCSI_MACB_LATE_COL 0x1a15c
19649 #define S_LATECOLLISIONS 0
19650 #define M_LATECOLLISIONS 0xffffU
19651 #define V_LATECOLLISIONS(x) ((x) << S_LATECOLLISIONS)
19652 #define G_LATECOLLISIONS(x) (((x) >> S_LATECOLLISIONS) & M_LATECOLLISIONS)
19654 #define A_NCSI_MACB_EXCESSIVE_COL 0x1a160
19656 #define S_EXCESSIVECOLLISIONS 0
19657 #define M_EXCESSIVECOLLISIONS 0xffU
19658 #define V_EXCESSIVECOLLISIONS(x) ((x) << S_EXCESSIVECOLLISIONS)
19659 #define G_EXCESSIVECOLLISIONS(x) (((x) >> S_EXCESSIVECOLLISIONS) & M_EXCESSIVECOLLISIONS)
19661 #define A_NCSI_MACB_TX_UNDERRUN_ERR 0x1a164
19663 #define S_TXUNDERRUNERR 0
19664 #define M_TXUNDERRUNERR 0xffU
19665 #define V_TXUNDERRUNERR(x) ((x) << S_TXUNDERRUNERR)
19666 #define G_TXUNDERRUNERR(x) (((x) >> S_TXUNDERRUNERR) & M_TXUNDERRUNERR)
19668 #define A_NCSI_MACB_CARRIER_SENSE_ERR 0x1a168
19670 #define S_CARRIERSENSEERRS 0
19671 #define M_CARRIERSENSEERRS 0xffU
19672 #define V_CARRIERSENSEERRS(x) ((x) << S_CARRIERSENSEERRS)
19673 #define G_CARRIERSENSEERRS(x) (((x) >> S_CARRIERSENSEERRS) & M_CARRIERSENSEERRS)
19675 #define A_NCSI_MACB_RX_RESOURCE_ERR 0x1a16c
19677 #define S_RXRESOURCEERR 0
19678 #define M_RXRESOURCEERR 0xffffU
19679 #define V_RXRESOURCEERR(x) ((x) << S_RXRESOURCEERR)
19680 #define G_RXRESOURCEERR(x) (((x) >> S_RXRESOURCEERR) & M_RXRESOURCEERR)
19682 #define A_NCSI_MACB_RX_OVERRUN_ERR 0x1a170
19684 #define S_RXOVERRUNERRCNT 0
19685 #define M_RXOVERRUNERRCNT 0xffU
19686 #define V_RXOVERRUNERRCNT(x) ((x) << S_RXOVERRUNERRCNT)
19687 #define G_RXOVERRUNERRCNT(x) (((x) >> S_RXOVERRUNERRCNT) & M_RXOVERRUNERRCNT)
19689 #define A_NCSI_MACB_RX_SYMBOL_ERR 0x1a174
19691 #define S_RXSYMBOLERR 0
19692 #define M_RXSYMBOLERR 0xffU
19693 #define V_RXSYMBOLERR(x) ((x) << S_RXSYMBOLERR)
19694 #define G_RXSYMBOLERR(x) (((x) >> S_RXSYMBOLERR) & M_RXSYMBOLERR)
19696 #define A_NCSI_MACB_RX_OVERSIZE_FRAME 0x1a178
19698 #define S_RXOVERSIZEERR 0
19699 #define M_RXOVERSIZEERR 0xffU
19700 #define V_RXOVERSIZEERR(x) ((x) << S_RXOVERSIZEERR)
19701 #define G_RXOVERSIZEERR(x) (((x) >> S_RXOVERSIZEERR) & M_RXOVERSIZEERR)
19703 #define A_NCSI_MACB_RX_JABBER_ERR 0x1a17c
19705 #define S_RXJABBERERR 0
19706 #define M_RXJABBERERR 0xffU
19707 #define V_RXJABBERERR(x) ((x) << S_RXJABBERERR)
19708 #define G_RXJABBERERR(x) (((x) >> S_RXJABBERERR) & M_RXJABBERERR)
19710 #define A_NCSI_MACB_RX_UNDERSIZE_FRAME 0x1a180
19712 #define S_RXUNDERSIZEFR 0
19713 #define M_RXUNDERSIZEFR 0xffU
19714 #define V_RXUNDERSIZEFR(x) ((x) << S_RXUNDERSIZEFR)
19715 #define G_RXUNDERSIZEFR(x) (((x) >> S_RXUNDERSIZEFR) & M_RXUNDERSIZEFR)
19717 #define A_NCSI_MACB_SQE_TEST_ERR 0x1a184
19719 #define S_SQETESTERR 0
19720 #define M_SQETESTERR 0xffU
19721 #define V_SQETESTERR(x) ((x) << S_SQETESTERR)
19722 #define G_SQETESTERR(x) (((x) >> S_SQETESTERR) & M_SQETESTERR)
19724 #define A_NCSI_MACB_LENGTH_ERR 0x1a188
19726 #define S_LENGTHERR 0
19727 #define M_LENGTHERR 0xffU
19728 #define V_LENGTHERR(x) ((x) << S_LENGTHERR)
19729 #define G_LENGTHERR(x) (((x) >> S_LENGTHERR) & M_LENGTHERR)
19731 #define A_NCSI_MACB_TX_PAUSE_FRAMES 0x1a18c
19733 #define S_TXPAUSEFRAMES 0
19734 #define M_TXPAUSEFRAMES 0xffffU
19735 #define V_TXPAUSEFRAMES(x) ((x) << S_TXPAUSEFRAMES)
19736 #define G_TXPAUSEFRAMES(x) (((x) >> S_TXPAUSEFRAMES) & M_TXPAUSEFRAMES)
19738 #define A_NCSI_MACB_HASH_LOW 0x1a190
19739 #define A_NCSI_MACB_HASH_HIGH 0x1a194
19740 #define A_NCSI_MACB_SPECIFIC_1_LOW 0x1a198
19741 #define A_NCSI_MACB_SPECIFIC_1_HIGH 0x1a19c
19743 #define S_MATCHHIGH 0
19744 #define M_MATCHHIGH 0xffffU
19745 #define V_MATCHHIGH(x) ((x) << S_MATCHHIGH)
19746 #define G_MATCHHIGH(x) (((x) >> S_MATCHHIGH) & M_MATCHHIGH)
19748 #define A_NCSI_MACB_SPECIFIC_2_LOW 0x1a1a0
19749 #define A_NCSI_MACB_SPECIFIC_2_HIGH 0x1a1a4
19750 #define A_NCSI_MACB_SPECIFIC_3_LOW 0x1a1a8
19751 #define A_NCSI_MACB_SPECIFIC_3_HIGH 0x1a1ac
19752 #define A_NCSI_MACB_SPECIFIC_4_LOW 0x1a1b0
19753 #define A_NCSI_MACB_SPECIFIC_4_HIGH 0x1a1b4
19754 #define A_NCSI_MACB_TYPE_ID 0x1a1b8
19757 #define M_TYPEID 0xffffU
19758 #define V_TYPEID(x) ((x) << S_TYPEID)
19759 #define G_TYPEID(x) (((x) >> S_TYPEID) & M_TYPEID)
19761 #define A_NCSI_MACB_TX_PAUSE_QUANTUM 0x1a1bc
19763 #define S_TXPAUSEQUANTUM 0
19764 #define M_TXPAUSEQUANTUM 0xffffU
19765 #define V_TXPAUSEQUANTUM(x) ((x) << S_TXPAUSEQUANTUM)
19766 #define G_TXPAUSEQUANTUM(x) (((x) >> S_TXPAUSEQUANTUM) & M_TXPAUSEQUANTUM)
19768 #define A_NCSI_MACB_USER_IO 0x1a1c0
19770 #define S_USERPROGINPUT 16
19771 #define M_USERPROGINPUT 0xffffU
19772 #define V_USERPROGINPUT(x) ((x) << S_USERPROGINPUT)
19773 #define G_USERPROGINPUT(x) (((x) >> S_USERPROGINPUT) & M_USERPROGINPUT)
19775 #define S_USERPROGOUTPUT 0
19776 #define M_USERPROGOUTPUT 0xffffU
19777 #define V_USERPROGOUTPUT(x) ((x) << S_USERPROGOUTPUT)
19778 #define G_USERPROGOUTPUT(x) (((x) >> S_USERPROGOUTPUT) & M_USERPROGOUTPUT)
19780 #define A_NCSI_MACB_WOL_CFG 0x1a1c4
19782 #define S_MCHASHEN 19
19783 #define V_MCHASHEN(x) ((x) << S_MCHASHEN)
19784 #define F_MCHASHEN V_MCHASHEN(1U)
19786 #define S_SPECIFIC1EN 18
19787 #define V_SPECIFIC1EN(x) ((x) << S_SPECIFIC1EN)
19788 #define F_SPECIFIC1EN V_SPECIFIC1EN(1U)
19791 #define V_ARPEN(x) ((x) << S_ARPEN)
19792 #define F_ARPEN V_ARPEN(1U)
19794 #define S_MAGICPKTEN 16
19795 #define V_MAGICPKTEN(x) ((x) << S_MAGICPKTEN)
19796 #define F_MAGICPKTEN V_MAGICPKTEN(1U)
19798 #define S_ARPIPADDR 0
19799 #define M_ARPIPADDR 0xffffU
19800 #define V_ARPIPADDR(x) ((x) << S_ARPIPADDR)
19801 #define G_ARPIPADDR(x) (((x) >> S_ARPIPADDR) & M_ARPIPADDR)
19803 #define A_NCSI_MACB_REV_STATUS 0x1a1fc
19805 #define S_PARTREF 16
19806 #define M_PARTREF 0xffffU
19807 #define V_PARTREF(x) ((x) << S_PARTREF)
19808 #define G_PARTREF(x) (((x) >> S_PARTREF) & M_PARTREF)
19811 #define M_DESREV 0xffffU
19812 #define V_DESREV(x) ((x) << S_DESREV)
19813 #define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV)
19815 /* registers for module XGMAC */
19816 #define XGMAC_BASE_ADDR 0x0
19818 #define A_XGMAC_PORT_CFG 0x1000
19820 #define S_XGMII_CLK_SEL 29
19821 #define M_XGMII_CLK_SEL 0x7U
19822 #define V_XGMII_CLK_SEL(x) ((x) << S_XGMII_CLK_SEL)
19823 #define G_XGMII_CLK_SEL(x) (((x) >> S_XGMII_CLK_SEL) & M_XGMII_CLK_SEL)
19825 #define S_SINKTX 27
19826 #define V_SINKTX(x) ((x) << S_SINKTX)
19827 #define F_SINKTX V_SINKTX(1U)
19829 #define S_SINKTXONLINKDOWN 26
19830 #define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN)
19831 #define F_SINKTXONLINKDOWN V_SINKTXONLINKDOWN(1U)
19833 #define S_XG2G_SPEED_MODE 25
19834 #define V_XG2G_SPEED_MODE(x) ((x) << S_XG2G_SPEED_MODE)
19835 #define F_XG2G_SPEED_MODE V_XG2G_SPEED_MODE(1U)
19837 #define S_LOOPNOFWD 24
19838 #define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD)
19839 #define F_LOOPNOFWD V_LOOPNOFWD(1U)
19841 #define S_XGM_TX_PAUSE_SIZE 23
19842 #define V_XGM_TX_PAUSE_SIZE(x) ((x) << S_XGM_TX_PAUSE_SIZE)
19843 #define F_XGM_TX_PAUSE_SIZE V_XGM_TX_PAUSE_SIZE(1U)
19845 #define S_XGM_TX_PAUSE_FRAME 22
19846 #define V_XGM_TX_PAUSE_FRAME(x) ((x) << S_XGM_TX_PAUSE_FRAME)
19847 #define F_XGM_TX_PAUSE_FRAME V_XGM_TX_PAUSE_FRAME(1U)
19849 #define S_XGM_TX_DISABLE_PRE 21
19850 #define V_XGM_TX_DISABLE_PRE(x) ((x) << S_XGM_TX_DISABLE_PRE)
19851 #define F_XGM_TX_DISABLE_PRE V_XGM_TX_DISABLE_PRE(1U)
19853 #define S_XGM_TX_DISABLE_CRC 20
19854 #define V_XGM_TX_DISABLE_CRC(x) ((x) << S_XGM_TX_DISABLE_CRC)
19855 #define F_XGM_TX_DISABLE_CRC V_XGM_TX_DISABLE_CRC(1U)
19857 #define S_SMUX_RX_LOOP 19
19858 #define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP)
19859 #define F_SMUX_RX_LOOP V_SMUX_RX_LOOP(1U)
19861 #define S_RX_LANE_SWAP 18
19862 #define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP)
19863 #define F_RX_LANE_SWAP V_RX_LANE_SWAP(1U)
19865 #define S_TX_LANE_SWAP 17
19866 #define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP)
19867 #define F_TX_LANE_SWAP V_TX_LANE_SWAP(1U)
19869 #define S_SIGNAL_DET 14
19870 #define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET)
19871 #define F_SIGNAL_DET V_SIGNAL_DET(1U)
19873 #define S_PMUX_RX_LOOP 13
19874 #define V_PMUX_RX_LOOP(x) ((x) << S_PMUX_RX_LOOP)
19875 #define F_PMUX_RX_LOOP V_PMUX_RX_LOOP(1U)
19877 #define S_PMUX_TX_LOOP 12
19878 #define V_PMUX_TX_LOOP(x) ((x) << S_PMUX_TX_LOOP)
19879 #define F_PMUX_TX_LOOP V_PMUX_TX_LOOP(1U)
19881 #define S_XGM_RX_SEL 10
19882 #define M_XGM_RX_SEL 0x3U
19883 #define V_XGM_RX_SEL(x) ((x) << S_XGM_RX_SEL)
19884 #define G_XGM_RX_SEL(x) (((x) >> S_XGM_RX_SEL) & M_XGM_RX_SEL)
19886 #define S_PCS_TX_SEL 8
19887 #define M_PCS_TX_SEL 0x3U
19888 #define V_PCS_TX_SEL(x) ((x) << S_PCS_TX_SEL)
19889 #define G_PCS_TX_SEL(x) (((x) >> S_PCS_TX_SEL) & M_PCS_TX_SEL)
19891 #define S_XAUI20_REM_PRE 5
19892 #define V_XAUI20_REM_PRE(x) ((x) << S_XAUI20_REM_PRE)
19893 #define F_XAUI20_REM_PRE V_XAUI20_REM_PRE(1U)
19895 #define S_XAUI20_XGMII_SEL 4
19896 #define V_XAUI20_XGMII_SEL(x) ((x) << S_XAUI20_XGMII_SEL)
19897 #define F_XAUI20_XGMII_SEL V_XAUI20_XGMII_SEL(1U)
19899 #define S_PORT_SEL 0
19900 #define V_PORT_SEL(x) ((x) << S_PORT_SEL)
19901 #define F_PORT_SEL V_PORT_SEL(1U)
19903 #define A_XGMAC_PORT_RESET_CTRL 0x1004
19905 #define S_AUXEXT_RESET 10
19906 #define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET)
19907 #define F_AUXEXT_RESET V_AUXEXT_RESET(1U)
19909 #define S_TXFIFO_RESET 9
19910 #define V_TXFIFO_RESET(x) ((x) << S_TXFIFO_RESET)
19911 #define F_TXFIFO_RESET V_TXFIFO_RESET(1U)
19913 #define S_RXFIFO_RESET 8
19914 #define V_RXFIFO_RESET(x) ((x) << S_RXFIFO_RESET)
19915 #define F_RXFIFO_RESET V_RXFIFO_RESET(1U)
19917 #define S_BEAN_RESET 7
19918 #define V_BEAN_RESET(x) ((x) << S_BEAN_RESET)
19919 #define F_BEAN_RESET V_BEAN_RESET(1U)
19921 #define S_XAUI_RESET 6
19922 #define V_XAUI_RESET(x) ((x) << S_XAUI_RESET)
19923 #define F_XAUI_RESET V_XAUI_RESET(1U)
19925 #define S_AE_RESET 5
19926 #define V_AE_RESET(x) ((x) << S_AE_RESET)
19927 #define F_AE_RESET V_AE_RESET(1U)
19929 #define S_XGM_RESET 4
19930 #define V_XGM_RESET(x) ((x) << S_XGM_RESET)
19931 #define F_XGM_RESET V_XGM_RESET(1U)
19933 #define S_XG2G_RESET 3
19934 #define V_XG2G_RESET(x) ((x) << S_XG2G_RESET)
19935 #define F_XG2G_RESET V_XG2G_RESET(1U)
19937 #define S_WOL_RESET 2
19938 #define V_WOL_RESET(x) ((x) << S_WOL_RESET)
19939 #define F_WOL_RESET V_WOL_RESET(1U)
19941 #define S_XFI_PCS_RESET 1
19942 #define V_XFI_PCS_RESET(x) ((x) << S_XFI_PCS_RESET)
19943 #define F_XFI_PCS_RESET V_XFI_PCS_RESET(1U)
19945 #define S_HSS_RESET 0
19946 #define V_HSS_RESET(x) ((x) << S_HSS_RESET)
19947 #define F_HSS_RESET V_HSS_RESET(1U)
19949 #define A_XGMAC_PORT_LED_CFG 0x1008
19951 #define S_LED1_CFG 5
19952 #define M_LED1_CFG 0x7U
19953 #define V_LED1_CFG(x) ((x) << S_LED1_CFG)
19954 #define G_LED1_CFG(x) (((x) >> S_LED1_CFG) & M_LED1_CFG)
19956 #define S_LED1_POLARITY_INV 4
19957 #define V_LED1_POLARITY_INV(x) ((x) << S_LED1_POLARITY_INV)
19958 #define F_LED1_POLARITY_INV V_LED1_POLARITY_INV(1U)
19960 #define S_LED0_CFG 1
19961 #define M_LED0_CFG 0x7U
19962 #define V_LED0_CFG(x) ((x) << S_LED0_CFG)
19963 #define G_LED0_CFG(x) (((x) >> S_LED0_CFG) & M_LED0_CFG)
19965 #define S_LED0_POLARITY_INV 0
19966 #define V_LED0_POLARITY_INV(x) ((x) << S_LED0_POLARITY_INV)
19967 #define F_LED0_POLARITY_INV V_LED0_POLARITY_INV(1U)
19969 #define A_XGMAC_PORT_LED_COUNTHI 0x100c
19971 #define S_LED_COUNT_HI 0
19972 #define M_LED_COUNT_HI 0x1ffffffU
19973 #define V_LED_COUNT_HI(x) ((x) << S_LED_COUNT_HI)
19974 #define G_LED_COUNT_HI(x) (((x) >> S_LED_COUNT_HI) & M_LED_COUNT_HI)
19976 #define A_XGMAC_PORT_LED_COUNTLO 0x1010
19978 #define S_LED_COUNT_LO 0
19979 #define M_LED_COUNT_LO 0x1ffffffU
19980 #define V_LED_COUNT_LO(x) ((x) << S_LED_COUNT_LO)
19981 #define G_LED_COUNT_LO(x) (((x) >> S_LED_COUNT_LO) & M_LED_COUNT_LO)
19983 #define A_XGMAC_PORT_DEBUG_CFG 0x1014
19985 #define S_TESTCLK_SEL 0
19986 #define M_TESTCLK_SEL 0xfU
19987 #define V_TESTCLK_SEL(x) ((x) << S_TESTCLK_SEL)
19988 #define G_TESTCLK_SEL(x) (((x) >> S_TESTCLK_SEL) & M_TESTCLK_SEL)
19990 #define A_XGMAC_PORT_CFG2 0x1018
19992 #define S_RX_POLARITY_INV 28
19993 #define M_RX_POLARITY_INV 0xfU
19994 #define V_RX_POLARITY_INV(x) ((x) << S_RX_POLARITY_INV)
19995 #define G_RX_POLARITY_INV(x) (((x) >> S_RX_POLARITY_INV) & M_RX_POLARITY_INV)
19997 #define S_TX_POLARITY_INV 24
19998 #define M_TX_POLARITY_INV 0xfU
19999 #define V_TX_POLARITY_INV(x) ((x) << S_TX_POLARITY_INV)
20000 #define G_TX_POLARITY_INV(x) (((x) >> S_TX_POLARITY_INV) & M_TX_POLARITY_INV)
20002 #define S_INSTANCENUM 22
20003 #define M_INSTANCENUM 0x3U
20004 #define V_INSTANCENUM(x) ((x) << S_INSTANCENUM)
20005 #define G_INSTANCENUM(x) (((x) >> S_INSTANCENUM) & M_INSTANCENUM)
20007 #define S_STOPONPERR 21
20008 #define V_STOPONPERR(x) ((x) << S_STOPONPERR)
20009 #define F_STOPONPERR V_STOPONPERR(1U)
20011 #define S_MACTXEN 20
20012 #define V_MACTXEN(x) ((x) << S_MACTXEN)
20013 #define F_MACTXEN V_MACTXEN(1U)
20015 #define S_MACRXEN 19
20016 #define V_MACRXEN(x) ((x) << S_MACRXEN)
20017 #define F_MACRXEN V_MACRXEN(1U)
20020 #define V_PATEN(x) ((x) << S_PATEN)
20021 #define F_PATEN V_PATEN(1U)
20023 #define S_MAGICEN 17
20024 #define V_MAGICEN(x) ((x) << S_MAGICEN)
20025 #define F_MAGICEN V_MAGICEN(1U)
20028 #define M_TX_IPG 0x1fffU
20029 #define V_TX_IPG(x) ((x) << S_TX_IPG)
20030 #define G_TX_IPG(x) (((x) >> S_TX_IPG) & M_TX_IPG)
20032 #define S_AEC_PMA_TX_READY 1
20033 #define V_AEC_PMA_TX_READY(x) ((x) << S_AEC_PMA_TX_READY)
20034 #define F_AEC_PMA_TX_READY V_AEC_PMA_TX_READY(1U)
20036 #define S_AEC_PMA_RX_READY 0
20037 #define V_AEC_PMA_RX_READY(x) ((x) << S_AEC_PMA_RX_READY)
20038 #define F_AEC_PMA_RX_READY V_AEC_PMA_RX_READY(1U)
20040 #define A_XGMAC_PORT_PKT_COUNT 0x101c
20042 #define S_TX_SOP_COUNT 24
20043 #define M_TX_SOP_COUNT 0xffU
20044 #define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT)
20045 #define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT)
20047 #define S_TX_EOP_COUNT 16
20048 #define M_TX_EOP_COUNT 0xffU
20049 #define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT)
20050 #define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT)
20052 #define S_RX_SOP_COUNT 8
20053 #define M_RX_SOP_COUNT 0xffU
20054 #define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT)
20055 #define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT)
20057 #define S_RX_EOP_COUNT 0
20058 #define M_RX_EOP_COUNT 0xffU
20059 #define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT)
20060 #define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT)
20062 #define A_XGMAC_PORT_PERR_INJECT 0x1020
20064 #define S_XGMMEMSEL 1
20065 #define V_XGMMEMSEL(x) ((x) << S_XGMMEMSEL)
20066 #define F_XGMMEMSEL V_XGMMEMSEL(1U)
20068 #define A_XGMAC_PORT_MAGIC_MACID_LO 0x1024
20069 #define A_XGMAC_PORT_MAGIC_MACID_HI 0x1028
20071 #define S_MAC_WOL_DA 0
20072 #define M_MAC_WOL_DA 0xffffU
20073 #define V_MAC_WOL_DA(x) ((x) << S_MAC_WOL_DA)
20074 #define G_MAC_WOL_DA(x) (((x) >> S_MAC_WOL_DA) & M_MAC_WOL_DA)
20076 #define A_XGMAC_PORT_BUILD_REVISION 0x102c
20077 #define A_XGMAC_PORT_XGMII_SE_COUNT 0x1030
20080 #define M_TXSOP 0xffU
20081 #define V_TXSOP(x) ((x) << S_TXSOP)
20082 #define G_TXSOP(x) (((x) >> S_TXSOP) & M_TXSOP)
20085 #define M_TXEOP 0xffU
20086 #define V_TXEOP(x) ((x) << S_TXEOP)
20087 #define G_TXEOP(x) (((x) >> S_TXEOP) & M_TXEOP)
20090 #define M_RXSOP 0xffU
20091 #define V_RXSOP(x) ((x) << S_RXSOP)
20092 #define G_RXSOP(x) (((x) >> S_RXSOP) & M_RXSOP)
20094 #define A_XGMAC_PORT_LINK_STATUS 0x1034
20097 #define V_REMFLT(x) ((x) << S_REMFLT)
20098 #define F_REMFLT V_REMFLT(1U)
20101 #define V_LOCFLT(x) ((x) << S_LOCFLT)
20102 #define F_LOCFLT V_LOCFLT(1U)
20105 #define V_LINKUP(x) ((x) << S_LINKUP)
20106 #define F_LINKUP V_LINKUP(1U)
20109 #define V_LINKDN(x) ((x) << S_LINKDN)
20110 #define F_LINKDN V_LINKDN(1U)
20112 #define A_XGMAC_PORT_CHECKIN 0x1038
20114 #define S_PREAMBLE 1
20115 #define V_PREAMBLE(x) ((x) << S_PREAMBLE)
20116 #define F_PREAMBLE V_PREAMBLE(1U)
20118 #define S_CHECKIN 0
20119 #define V_CHECKIN(x) ((x) << S_CHECKIN)
20120 #define F_CHECKIN V_CHECKIN(1U)
20122 #define A_XGMAC_PORT_FAULT_TEST 0x103c
20124 #define S_FLTTYPE 1
20125 #define V_FLTTYPE(x) ((x) << S_FLTTYPE)
20126 #define F_FLTTYPE V_FLTTYPE(1U)
20128 #define S_FLTCTRL 0
20129 #define V_FLTCTRL(x) ((x) << S_FLTCTRL)
20130 #define F_FLTCTRL V_FLTCTRL(1U)
20132 #define A_XGMAC_PORT_SPARE 0x1040
20133 #define A_XGMAC_PORT_HSS_SIGDET_STATUS 0x1044
20135 #define S_SIGNALDETECT 0
20136 #define M_SIGNALDETECT 0xfU
20137 #define V_SIGNALDETECT(x) ((x) << S_SIGNALDETECT)
20138 #define G_SIGNALDETECT(x) (((x) >> S_SIGNALDETECT) & M_SIGNALDETECT)
20140 #define A_XGMAC_PORT_EXT_LOS_STATUS 0x1048
20141 #define A_XGMAC_PORT_EXT_LOS_CTRL 0x104c
20144 #define M_CTRL 0xfU
20145 #define V_CTRL(x) ((x) << S_CTRL)
20146 #define G_CTRL(x) (((x) >> S_CTRL) & M_CTRL)
20148 #define A_XGMAC_PORT_FPGA_PAUSE_CTL 0x1050
20151 #define V_CTL(x) ((x) << S_CTL)
20152 #define F_CTL V_CTL(1U)
20155 #define M_HWM 0x1fffU
20156 #define V_HWM(x) ((x) << S_HWM)
20157 #define G_HWM(x) (((x) >> S_HWM) & M_HWM)
20160 #define M_LWM 0x1fffU
20161 #define V_LWM(x) ((x) << S_LWM)
20162 #define G_LWM(x) (((x) >> S_LWM) & M_LWM)
20164 #define A_XGMAC_PORT_FPGA_ERRPKT_CNT 0x1054
20165 #define A_XGMAC_PORT_LA_TX_0 0x1058
20166 #define A_XGMAC_PORT_LA_RX_0 0x105c
20167 #define A_XGMAC_PORT_FPGA_LA_CTL 0x1060
20170 #define V_RXRST(x) ((x) << S_RXRST)
20171 #define F_RXRST V_RXRST(1U)
20174 #define V_TXRST(x) ((x) << S_TXRST)
20175 #define F_TXRST V_TXRST(1U)
20178 #define V_XGMII(x) ((x) << S_XGMII)
20179 #define F_XGMII V_XGMII(1U)
20181 #define S_LAPAUSE 2
20182 #define V_LAPAUSE(x) ((x) << S_LAPAUSE)
20183 #define F_LAPAUSE V_LAPAUSE(1U)
20185 #define S_STOPERR 1
20186 #define V_STOPERR(x) ((x) << S_STOPERR)
20187 #define F_STOPERR V_STOPERR(1U)
20190 #define V_LASTOP(x) ((x) << S_LASTOP)
20191 #define F_LASTOP V_LASTOP(1U)
20193 #define A_XGMAC_PORT_EPIO_DATA0 0x10c0
20194 #define A_XGMAC_PORT_EPIO_DATA1 0x10c4
20195 #define A_XGMAC_PORT_EPIO_DATA2 0x10c8
20196 #define A_XGMAC_PORT_EPIO_DATA3 0x10cc
20197 #define A_XGMAC_PORT_EPIO_OP 0x10d0
20200 #define V_EPIOWR(x) ((x) << S_EPIOWR)
20201 #define F_EPIOWR V_EPIOWR(1U)
20203 #define S_ADDRESS 0
20204 #define M_ADDRESS 0xffU
20205 #define V_ADDRESS(x) ((x) << S_ADDRESS)
20206 #define G_ADDRESS(x) (((x) >> S_ADDRESS) & M_ADDRESS)
20208 #define A_XGMAC_PORT_WOL_STATUS 0x10d4
20210 #define S_MAGICDETECTED 31
20211 #define V_MAGICDETECTED(x) ((x) << S_MAGICDETECTED)
20212 #define F_MAGICDETECTED V_MAGICDETECTED(1U)
20214 #define S_PATDETECTED 30
20215 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
20216 #define F_PATDETECTED V_PATDETECTED(1U)
20218 #define S_CLEARMAGIC 4
20219 #define V_CLEARMAGIC(x) ((x) << S_CLEARMAGIC)
20220 #define F_CLEARMAGIC V_CLEARMAGIC(1U)
20222 #define S_CLEARMATCH 3
20223 #define V_CLEARMATCH(x) ((x) << S_CLEARMATCH)
20224 #define F_CLEARMATCH V_CLEARMATCH(1U)
20226 #define S_MATCHEDFILTER 0
20227 #define M_MATCHEDFILTER 0x7U
20228 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
20229 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
20231 #define A_XGMAC_PORT_INT_EN 0x10d8
20233 #define S_EXT_LOS 28
20234 #define V_EXT_LOS(x) ((x) << S_EXT_LOS)
20235 #define F_EXT_LOS V_EXT_LOS(1U)
20237 #define S_INCMPTBL_LINK 27
20238 #define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK)
20239 #define F_INCMPTBL_LINK V_INCMPTBL_LINK(1U)
20241 #define S_PATDETWAKE 26
20242 #define V_PATDETWAKE(x) ((x) << S_PATDETWAKE)
20243 #define F_PATDETWAKE V_PATDETWAKE(1U)
20245 #define S_MAGICWAKE 25
20246 #define V_MAGICWAKE(x) ((x) << S_MAGICWAKE)
20247 #define F_MAGICWAKE V_MAGICWAKE(1U)
20249 #define S_SIGDETCHG 24
20250 #define V_SIGDETCHG(x) ((x) << S_SIGDETCHG)
20251 #define F_SIGDETCHG V_SIGDETCHG(1U)
20253 #define S_PCSR_FEC_CORR 23
20254 #define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR)
20255 #define F_PCSR_FEC_CORR V_PCSR_FEC_CORR(1U)
20257 #define S_AE_TRAIN_LOCAL 22
20258 #define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL)
20259 #define F_AE_TRAIN_LOCAL V_AE_TRAIN_LOCAL(1U)
20261 #define S_HSSPLL_LOCK 21
20262 #define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK)
20263 #define F_HSSPLL_LOCK V_HSSPLL_LOCK(1U)
20265 #define S_HSSPRT_READY 20
20266 #define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY)
20267 #define F_HSSPRT_READY V_HSSPRT_READY(1U)
20269 #define S_AUTONEG_DONE 19
20270 #define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE)
20271 #define F_AUTONEG_DONE V_AUTONEG_DONE(1U)
20273 #define S_PCSR_HI_BER 18
20274 #define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER)
20275 #define F_PCSR_HI_BER V_PCSR_HI_BER(1U)
20277 #define S_PCSR_FEC_ERROR 17
20278 #define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR)
20279 #define F_PCSR_FEC_ERROR V_PCSR_FEC_ERROR(1U)
20281 #define S_PCSR_LINK_FAIL 16
20282 #define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL)
20283 #define F_PCSR_LINK_FAIL V_PCSR_LINK_FAIL(1U)
20285 #define S_XAUI_DEC_ERROR 15
20286 #define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR)
20287 #define F_XAUI_DEC_ERROR V_XAUI_DEC_ERROR(1U)
20289 #define S_XAUI_LINK_FAIL 14
20290 #define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL)
20291 #define F_XAUI_LINK_FAIL V_XAUI_LINK_FAIL(1U)
20293 #define S_PCS_CTC_ERROR 13
20294 #define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR)
20295 #define F_PCS_CTC_ERROR V_PCS_CTC_ERROR(1U)
20297 #define S_PCS_LINK_GOOD 12
20298 #define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD)
20299 #define F_PCS_LINK_GOOD V_PCS_LINK_GOOD(1U)
20301 #define S_PCS_LINK_FAIL 11
20302 #define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL)
20303 #define F_PCS_LINK_FAIL V_PCS_LINK_FAIL(1U)
20305 #define S_RXFIFOOVERFLOW 10
20306 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
20307 #define F_RXFIFOOVERFLOW V_RXFIFOOVERFLOW(1U)
20309 #define S_HSSPRBSERR 9
20310 #define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR)
20311 #define F_HSSPRBSERR V_HSSPRBSERR(1U)
20313 #define S_HSSEYEQUAL 8
20314 #define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL)
20315 #define F_HSSEYEQUAL V_HSSEYEQUAL(1U)
20317 #define S_REMOTEFAULT 7
20318 #define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT)
20319 #define F_REMOTEFAULT V_REMOTEFAULT(1U)
20321 #define S_LOCALFAULT 6
20322 #define V_LOCALFAULT(x) ((x) << S_LOCALFAULT)
20323 #define F_LOCALFAULT V_LOCALFAULT(1U)
20325 #define S_MAC_LINK_DOWN 5
20326 #define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN)
20327 #define F_MAC_LINK_DOWN V_MAC_LINK_DOWN(1U)
20329 #define S_MAC_LINK_UP 4
20330 #define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP)
20331 #define F_MAC_LINK_UP V_MAC_LINK_UP(1U)
20333 #define S_BEAN_INT 3
20334 #define V_BEAN_INT(x) ((x) << S_BEAN_INT)
20335 #define F_BEAN_INT V_BEAN_INT(1U)
20337 #define S_XGM_INT 2
20338 #define V_XGM_INT(x) ((x) << S_XGM_INT)
20339 #define F_XGM_INT V_XGM_INT(1U)
20341 #define A_XGMAC_PORT_INT_CAUSE 0x10dc
20342 #define A_XGMAC_PORT_HSS_CFG0 0x10e0
20345 #define V_TXDTS(x) ((x) << S_TXDTS)
20346 #define F_TXDTS V_TXDTS(1U)
20349 #define V_TXCTS(x) ((x) << S_TXCTS)
20350 #define F_TXCTS V_TXCTS(1U)
20353 #define V_TXBTS(x) ((x) << S_TXBTS)
20354 #define F_TXBTS V_TXBTS(1U)
20357 #define V_TXATS(x) ((x) << S_TXATS)
20358 #define F_TXATS V_TXATS(1U)
20360 #define S_TXDOBS 27
20361 #define V_TXDOBS(x) ((x) << S_TXDOBS)
20362 #define F_TXDOBS V_TXDOBS(1U)
20364 #define S_TXCOBS 26
20365 #define V_TXCOBS(x) ((x) << S_TXCOBS)
20366 #define F_TXCOBS V_TXCOBS(1U)
20368 #define S_TXBOBS 25
20369 #define V_TXBOBS(x) ((x) << S_TXBOBS)
20370 #define F_TXBOBS V_TXBOBS(1U)
20372 #define S_TXAOBS 24
20373 #define V_TXAOBS(x) ((x) << S_TXAOBS)
20374 #define F_TXAOBS V_TXAOBS(1U)
20376 #define S_HSSREFCLKSEL 20
20377 #define V_HSSREFCLKSEL(x) ((x) << S_HSSREFCLKSEL)
20378 #define F_HSSREFCLKSEL V_HSSREFCLKSEL(1U)
20380 #define S_HSSAVDHI 17
20381 #define V_HSSAVDHI(x) ((x) << S_HSSAVDHI)
20382 #define F_HSSAVDHI V_HSSAVDHI(1U)
20384 #define S_HSSRXTS 16
20385 #define V_HSSRXTS(x) ((x) << S_HSSRXTS)
20386 #define F_HSSRXTS V_HSSRXTS(1U)
20388 #define S_HSSTXACMODE 15
20389 #define V_HSSTXACMODE(x) ((x) << S_HSSTXACMODE)
20390 #define F_HSSTXACMODE V_HSSTXACMODE(1U)
20392 #define S_HSSRXACMODE 14
20393 #define V_HSSRXACMODE(x) ((x) << S_HSSRXACMODE)
20394 #define F_HSSRXACMODE V_HSSRXACMODE(1U)
20396 #define S_HSSRESYNC 13
20397 #define V_HSSRESYNC(x) ((x) << S_HSSRESYNC)
20398 #define F_HSSRESYNC V_HSSRESYNC(1U)
20400 #define S_HSSRECCAL 12
20401 #define V_HSSRECCAL(x) ((x) << S_HSSRECCAL)
20402 #define F_HSSRECCAL V_HSSRECCAL(1U)
20404 #define S_HSSPDWNPLL 11
20405 #define V_HSSPDWNPLL(x) ((x) << S_HSSPDWNPLL)
20406 #define F_HSSPDWNPLL V_HSSPDWNPLL(1U)
20408 #define S_HSSDIVSEL 9
20409 #define M_HSSDIVSEL 0x3U
20410 #define V_HSSDIVSEL(x) ((x) << S_HSSDIVSEL)
20411 #define G_HSSDIVSEL(x) (((x) >> S_HSSDIVSEL) & M_HSSDIVSEL)
20413 #define S_HSSREFDIV 8
20414 #define V_HSSREFDIV(x) ((x) << S_HSSREFDIV)
20415 #define F_HSSREFDIV V_HSSREFDIV(1U)
20417 #define S_HSSPLLBYP 7
20418 #define V_HSSPLLBYP(x) ((x) << S_HSSPLLBYP)
20419 #define F_HSSPLLBYP V_HSSPLLBYP(1U)
20421 #define S_HSSLOFREQPLL 6
20422 #define V_HSSLOFREQPLL(x) ((x) << S_HSSLOFREQPLL)
20423 #define F_HSSLOFREQPLL V_HSSLOFREQPLL(1U)
20425 #define S_HSSLOFREQ2PLL 5
20426 #define V_HSSLOFREQ2PLL(x) ((x) << S_HSSLOFREQ2PLL)
20427 #define F_HSSLOFREQ2PLL V_HSSLOFREQ2PLL(1U)
20429 #define S_HSSEXTC16SEL 4
20430 #define V_HSSEXTC16SEL(x) ((x) << S_HSSEXTC16SEL)
20431 #define F_HSSEXTC16SEL V_HSSEXTC16SEL(1U)
20433 #define S_HSSRSTCONFIG 1
20434 #define M_HSSRSTCONFIG 0x7U
20435 #define V_HSSRSTCONFIG(x) ((x) << S_HSSRSTCONFIG)
20436 #define G_HSSRSTCONFIG(x) (((x) >> S_HSSRSTCONFIG) & M_HSSRSTCONFIG)
20438 #define S_HSSPRBSEN 0
20439 #define V_HSSPRBSEN(x) ((x) << S_HSSPRBSEN)
20440 #define F_HSSPRBSEN V_HSSPRBSEN(1U)
20442 #define A_XGMAC_PORT_HSS_CFG1 0x10e4
20444 #define S_RXDPRBSRST 28
20445 #define V_RXDPRBSRST(x) ((x) << S_RXDPRBSRST)
20446 #define F_RXDPRBSRST V_RXDPRBSRST(1U)
20448 #define S_RXDPRBSEN 27
20449 #define V_RXDPRBSEN(x) ((x) << S_RXDPRBSEN)
20450 #define F_RXDPRBSEN V_RXDPRBSEN(1U)
20452 #define S_RXDPRBSFRCERR 26
20453 #define V_RXDPRBSFRCERR(x) ((x) << S_RXDPRBSFRCERR)
20454 #define F_RXDPRBSFRCERR V_RXDPRBSFRCERR(1U)
20456 #define S_TXDPRBSRST 25
20457 #define V_TXDPRBSRST(x) ((x) << S_TXDPRBSRST)
20458 #define F_TXDPRBSRST V_TXDPRBSRST(1U)
20460 #define S_TXDPRBSEN 24
20461 #define V_TXDPRBSEN(x) ((x) << S_TXDPRBSEN)
20462 #define F_TXDPRBSEN V_TXDPRBSEN(1U)
20464 #define S_RXCPRBSRST 20
20465 #define V_RXCPRBSRST(x) ((x) << S_RXCPRBSRST)
20466 #define F_RXCPRBSRST V_RXCPRBSRST(1U)
20468 #define S_RXCPRBSEN 19
20469 #define V_RXCPRBSEN(x) ((x) << S_RXCPRBSEN)
20470 #define F_RXCPRBSEN V_RXCPRBSEN(1U)
20472 #define S_RXCPRBSFRCERR 18
20473 #define V_RXCPRBSFRCERR(x) ((x) << S_RXCPRBSFRCERR)
20474 #define F_RXCPRBSFRCERR V_RXCPRBSFRCERR(1U)
20476 #define S_TXCPRBSRST 17
20477 #define V_TXCPRBSRST(x) ((x) << S_TXCPRBSRST)
20478 #define F_TXCPRBSRST V_TXCPRBSRST(1U)
20480 #define S_TXCPRBSEN 16
20481 #define V_TXCPRBSEN(x) ((x) << S_TXCPRBSEN)
20482 #define F_TXCPRBSEN V_TXCPRBSEN(1U)
20484 #define S_RXBPRBSRST 12
20485 #define V_RXBPRBSRST(x) ((x) << S_RXBPRBSRST)
20486 #define F_RXBPRBSRST V_RXBPRBSRST(1U)
20488 #define S_RXBPRBSEN 11
20489 #define V_RXBPRBSEN(x) ((x) << S_RXBPRBSEN)
20490 #define F_RXBPRBSEN V_RXBPRBSEN(1U)
20492 #define S_RXBPRBSFRCERR 10
20493 #define V_RXBPRBSFRCERR(x) ((x) << S_RXBPRBSFRCERR)
20494 #define F_RXBPRBSFRCERR V_RXBPRBSFRCERR(1U)
20496 #define S_TXBPRBSRST 9
20497 #define V_TXBPRBSRST(x) ((x) << S_TXBPRBSRST)
20498 #define F_TXBPRBSRST V_TXBPRBSRST(1U)
20500 #define S_TXBPRBSEN 8
20501 #define V_TXBPRBSEN(x) ((x) << S_TXBPRBSEN)
20502 #define F_TXBPRBSEN V_TXBPRBSEN(1U)
20504 #define S_RXAPRBSRST 4
20505 #define V_RXAPRBSRST(x) ((x) << S_RXAPRBSRST)
20506 #define F_RXAPRBSRST V_RXAPRBSRST(1U)
20508 #define S_RXAPRBSEN 3
20509 #define V_RXAPRBSEN(x) ((x) << S_RXAPRBSEN)
20510 #define F_RXAPRBSEN V_RXAPRBSEN(1U)
20512 #define S_RXAPRBSFRCERR 2
20513 #define V_RXAPRBSFRCERR(x) ((x) << S_RXAPRBSFRCERR)
20514 #define F_RXAPRBSFRCERR V_RXAPRBSFRCERR(1U)
20516 #define S_TXAPRBSRST 1
20517 #define V_TXAPRBSRST(x) ((x) << S_TXAPRBSRST)
20518 #define F_TXAPRBSRST V_TXAPRBSRST(1U)
20520 #define S_TXAPRBSEN 0
20521 #define V_TXAPRBSEN(x) ((x) << S_TXAPRBSEN)
20522 #define F_TXAPRBSEN V_TXAPRBSEN(1U)
20524 #define A_XGMAC_PORT_HSS_CFG2 0x10e8
20526 #define S_RXDDATASYNC 23
20527 #define V_RXDDATASYNC(x) ((x) << S_RXDDATASYNC)
20528 #define F_RXDDATASYNC V_RXDDATASYNC(1U)
20530 #define S_RXCDATASYNC 22
20531 #define V_RXCDATASYNC(x) ((x) << S_RXCDATASYNC)
20532 #define F_RXCDATASYNC V_RXCDATASYNC(1U)
20534 #define S_RXBDATASYNC 21
20535 #define V_RXBDATASYNC(x) ((x) << S_RXBDATASYNC)
20536 #define F_RXBDATASYNC V_RXBDATASYNC(1U)
20538 #define S_RXADATASYNC 20
20539 #define V_RXADATASYNC(x) ((x) << S_RXADATASYNC)
20540 #define F_RXADATASYNC V_RXADATASYNC(1U)
20542 #define S_RXDEARLYIN 19
20543 #define V_RXDEARLYIN(x) ((x) << S_RXDEARLYIN)
20544 #define F_RXDEARLYIN V_RXDEARLYIN(1U)
20546 #define S_RXDLATEIN 18
20547 #define V_RXDLATEIN(x) ((x) << S_RXDLATEIN)
20548 #define F_RXDLATEIN V_RXDLATEIN(1U)
20550 #define S_RXDPHSLOCK 17
20551 #define V_RXDPHSLOCK(x) ((x) << S_RXDPHSLOCK)
20552 #define F_RXDPHSLOCK V_RXDPHSLOCK(1U)
20554 #define S_RXDPHSDNIN 16
20555 #define V_RXDPHSDNIN(x) ((x) << S_RXDPHSDNIN)
20556 #define F_RXDPHSDNIN V_RXDPHSDNIN(1U)
20558 #define S_RXDPHSUPIN 15
20559 #define V_RXDPHSUPIN(x) ((x) << S_RXDPHSUPIN)
20560 #define F_RXDPHSUPIN V_RXDPHSUPIN(1U)
20562 #define S_RXCEARLYIN 14
20563 #define V_RXCEARLYIN(x) ((x) << S_RXCEARLYIN)
20564 #define F_RXCEARLYIN V_RXCEARLYIN(1U)
20566 #define S_RXCLATEIN 13
20567 #define V_RXCLATEIN(x) ((x) << S_RXCLATEIN)
20568 #define F_RXCLATEIN V_RXCLATEIN(1U)
20570 #define S_RXCPHSLOCK 12
20571 #define V_RXCPHSLOCK(x) ((x) << S_RXCPHSLOCK)
20572 #define F_RXCPHSLOCK V_RXCPHSLOCK(1U)
20574 #define S_RXCPHSDNIN 11
20575 #define V_RXCPHSDNIN(x) ((x) << S_RXCPHSDNIN)
20576 #define F_RXCPHSDNIN V_RXCPHSDNIN(1U)
20578 #define S_RXCPHSUPIN 10
20579 #define V_RXCPHSUPIN(x) ((x) << S_RXCPHSUPIN)
20580 #define F_RXCPHSUPIN V_RXCPHSUPIN(1U)
20582 #define S_RXBEARLYIN 9
20583 #define V_RXBEARLYIN(x) ((x) << S_RXBEARLYIN)
20584 #define F_RXBEARLYIN V_RXBEARLYIN(1U)
20586 #define S_RXBLATEIN 8
20587 #define V_RXBLATEIN(x) ((x) << S_RXBLATEIN)
20588 #define F_RXBLATEIN V_RXBLATEIN(1U)
20590 #define S_RXBPHSLOCK 7
20591 #define V_RXBPHSLOCK(x) ((x) << S_RXBPHSLOCK)
20592 #define F_RXBPHSLOCK V_RXBPHSLOCK(1U)
20594 #define S_RXBPHSDNIN 6
20595 #define V_RXBPHSDNIN(x) ((x) << S_RXBPHSDNIN)
20596 #define F_RXBPHSDNIN V_RXBPHSDNIN(1U)
20598 #define S_RXBPHSUPIN 5
20599 #define V_RXBPHSUPIN(x) ((x) << S_RXBPHSUPIN)
20600 #define F_RXBPHSUPIN V_RXBPHSUPIN(1U)
20602 #define S_RXAEARLYIN 4
20603 #define V_RXAEARLYIN(x) ((x) << S_RXAEARLYIN)
20604 #define F_RXAEARLYIN V_RXAEARLYIN(1U)
20606 #define S_RXALATEIN 3
20607 #define V_RXALATEIN(x) ((x) << S_RXALATEIN)
20608 #define F_RXALATEIN V_RXALATEIN(1U)
20610 #define S_RXAPHSLOCK 2
20611 #define V_RXAPHSLOCK(x) ((x) << S_RXAPHSLOCK)
20612 #define F_RXAPHSLOCK V_RXAPHSLOCK(1U)
20614 #define S_RXAPHSDNIN 1
20615 #define V_RXAPHSDNIN(x) ((x) << S_RXAPHSDNIN)
20616 #define F_RXAPHSDNIN V_RXAPHSDNIN(1U)
20618 #define S_RXAPHSUPIN 0
20619 #define V_RXAPHSUPIN(x) ((x) << S_RXAPHSUPIN)
20620 #define F_RXAPHSUPIN V_RXAPHSUPIN(1U)
20622 #define A_XGMAC_PORT_HSS_STATUS 0x10ec
20624 #define S_RXDPRBSSYNC 15
20625 #define V_RXDPRBSSYNC(x) ((x) << S_RXDPRBSSYNC)
20626 #define F_RXDPRBSSYNC V_RXDPRBSSYNC(1U)
20628 #define S_RXCPRBSSYNC 14
20629 #define V_RXCPRBSSYNC(x) ((x) << S_RXCPRBSSYNC)
20630 #define F_RXCPRBSSYNC V_RXCPRBSSYNC(1U)
20632 #define S_RXBPRBSSYNC 13
20633 #define V_RXBPRBSSYNC(x) ((x) << S_RXBPRBSSYNC)
20634 #define F_RXBPRBSSYNC V_RXBPRBSSYNC(1U)
20636 #define S_RXAPRBSSYNC 12
20637 #define V_RXAPRBSSYNC(x) ((x) << S_RXAPRBSSYNC)
20638 #define F_RXAPRBSSYNC V_RXAPRBSSYNC(1U)
20640 #define S_RXDPRBSERR 11
20641 #define V_RXDPRBSERR(x) ((x) << S_RXDPRBSERR)
20642 #define F_RXDPRBSERR V_RXDPRBSERR(1U)
20644 #define S_RXCPRBSERR 10
20645 #define V_RXCPRBSERR(x) ((x) << S_RXCPRBSERR)
20646 #define F_RXCPRBSERR V_RXCPRBSERR(1U)
20648 #define S_RXBPRBSERR 9
20649 #define V_RXBPRBSERR(x) ((x) << S_RXBPRBSERR)
20650 #define F_RXBPRBSERR V_RXBPRBSERR(1U)
20652 #define S_RXAPRBSERR 8
20653 #define V_RXAPRBSERR(x) ((x) << S_RXAPRBSERR)
20654 #define F_RXAPRBSERR V_RXAPRBSERR(1U)
20656 #define S_RXDSIGDET 7
20657 #define V_RXDSIGDET(x) ((x) << S_RXDSIGDET)
20658 #define F_RXDSIGDET V_RXDSIGDET(1U)
20660 #define S_RXCSIGDET 6
20661 #define V_RXCSIGDET(x) ((x) << S_RXCSIGDET)
20662 #define F_RXCSIGDET V_RXCSIGDET(1U)
20664 #define S_RXBSIGDET 5
20665 #define V_RXBSIGDET(x) ((x) << S_RXBSIGDET)
20666 #define F_RXBSIGDET V_RXBSIGDET(1U)
20668 #define S_RXASIGDET 4
20669 #define V_RXASIGDET(x) ((x) << S_RXASIGDET)
20670 #define F_RXASIGDET V_RXASIGDET(1U)
20672 #define S_HSSPLLLOCK 1
20673 #define V_HSSPLLLOCK(x) ((x) << S_HSSPLLLOCK)
20674 #define F_HSSPLLLOCK V_HSSPLLLOCK(1U)
20676 #define S_HSSPRTREADY 0
20677 #define V_HSSPRTREADY(x) ((x) << S_HSSPRTREADY)
20678 #define F_HSSPRTREADY V_HSSPRTREADY(1U)
20680 #define A_XGMAC_PORT_XGM_TX_CTRL 0x1200
20682 #define S_SENDPAUSE 2
20683 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
20684 #define F_SENDPAUSE V_SENDPAUSE(1U)
20686 #define S_SENDZEROPAUSE 1
20687 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
20688 #define F_SENDZEROPAUSE V_SENDZEROPAUSE(1U)
20690 #define S_XGM_TXEN 0
20691 #define V_XGM_TXEN(x) ((x) << S_XGM_TXEN)
20692 #define F_XGM_TXEN V_XGM_TXEN(1U)
20694 #define A_XGMAC_PORT_XGM_TX_CFG 0x1204
20697 #define M_CRCCAL 0x3U
20698 #define V_CRCCAL(x) ((x) << S_CRCCAL)
20699 #define G_CRCCAL(x) (((x) >> S_CRCCAL) & M_CRCCAL)
20701 #define S_DISDEFIDLECNT 7
20702 #define V_DISDEFIDLECNT(x) ((x) << S_DISDEFIDLECNT)
20703 #define F_DISDEFIDLECNT V_DISDEFIDLECNT(1U)
20705 #define S_DECAVGTXIPG 6
20706 #define V_DECAVGTXIPG(x) ((x) << S_DECAVGTXIPG)
20707 #define F_DECAVGTXIPG V_DECAVGTXIPG(1U)
20709 #define S_UNIDIRTXEN 5
20710 #define V_UNIDIRTXEN(x) ((x) << S_UNIDIRTXEN)
20711 #define F_UNIDIRTXEN V_UNIDIRTXEN(1U)
20713 #define S_CFGCLKSPEED 2
20714 #define M_CFGCLKSPEED 0x7U
20715 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
20716 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
20718 #define S_STRETCHMODE 1
20719 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
20720 #define F_STRETCHMODE V_STRETCHMODE(1U)
20722 #define S_TXPAUSEEN 0
20723 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
20724 #define F_TXPAUSEEN V_TXPAUSEEN(1U)
20726 #define A_XGMAC_PORT_XGM_TX_PAUSE_QUANTA 0x1208
20728 #define S_TXPAUSEQUANTA 0
20729 #define M_TXPAUSEQUANTA 0xffffU
20730 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
20731 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
20733 #define A_XGMAC_PORT_XGM_RX_CTRL 0x120c
20734 #define A_XGMAC_PORT_XGM_RX_CFG 0x1210
20736 #define S_RXCRCCAL 16
20737 #define M_RXCRCCAL 0x3U
20738 #define V_RXCRCCAL(x) ((x) << S_RXCRCCAL)
20739 #define G_RXCRCCAL(x) (((x) >> S_RXCRCCAL) & M_RXCRCCAL)
20741 #define S_STATLOCALFAULT 15
20742 #define V_STATLOCALFAULT(x) ((x) << S_STATLOCALFAULT)
20743 #define F_STATLOCALFAULT V_STATLOCALFAULT(1U)
20745 #define S_STATREMOTEFAULT 14
20746 #define V_STATREMOTEFAULT(x) ((x) << S_STATREMOTEFAULT)
20747 #define F_STATREMOTEFAULT V_STATREMOTEFAULT(1U)
20749 #define S_LENERRFRAMEDIS 13
20750 #define V_LENERRFRAMEDIS(x) ((x) << S_LENERRFRAMEDIS)
20751 #define F_LENERRFRAMEDIS V_LENERRFRAMEDIS(1U)
20753 #define S_CON802_3PREAMBLE 12
20754 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
20755 #define F_CON802_3PREAMBLE V_CON802_3PREAMBLE(1U)
20757 #define S_ENNON802_3PREAMBLE 11
20758 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
20759 #define F_ENNON802_3PREAMBLE V_ENNON802_3PREAMBLE(1U)
20761 #define S_COPYPREAMBLE 10
20762 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
20763 #define F_COPYPREAMBLE V_COPYPREAMBLE(1U)
20765 #define S_DISPAUSEFRAMES 9
20766 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
20767 #define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U)
20769 #define S_EN1536BFRAMES 8
20770 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
20771 #define F_EN1536BFRAMES V_EN1536BFRAMES(1U)
20773 #define S_ENJUMBO 7
20774 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
20775 #define F_ENJUMBO V_ENJUMBO(1U)
20778 #define V_RMFCS(x) ((x) << S_RMFCS)
20779 #define F_RMFCS V_RMFCS(1U)
20781 #define S_DISNONVLAN 5
20782 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
20783 #define F_DISNONVLAN V_DISNONVLAN(1U)
20785 #define S_ENEXTMATCH 4
20786 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
20787 #define F_ENEXTMATCH V_ENEXTMATCH(1U)
20789 #define S_ENHASHUCAST 3
20790 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
20791 #define F_ENHASHUCAST V_ENHASHUCAST(1U)
20793 #define S_ENHASHMCAST 2
20794 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
20795 #define F_ENHASHMCAST V_ENHASHMCAST(1U)
20797 #define S_DISBCAST 1
20798 #define V_DISBCAST(x) ((x) << S_DISBCAST)
20799 #define F_DISBCAST V_DISBCAST(1U)
20801 #define S_COPYALLFRAMES 0
20802 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
20803 #define F_COPYALLFRAMES V_COPYALLFRAMES(1U)
20805 #define A_XGMAC_PORT_XGM_RX_HASH_LOW 0x1214
20806 #define A_XGMAC_PORT_XGM_RX_HASH_HIGH 0x1218
20807 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1 0x121c
20808 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1 0x1220
20810 #define S_ADDRESS_HIGH 0
20811 #define M_ADDRESS_HIGH 0xffffU
20812 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
20813 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
20815 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2 0x1224
20816 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2 0x1228
20817 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3 0x122c
20818 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3 0x1230
20819 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4 0x1234
20820 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4 0x1238
20821 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5 0x123c
20822 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5 0x1240
20823 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6 0x1244
20824 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6 0x1248
20825 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7 0x124c
20826 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7 0x1250
20827 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8 0x1254
20828 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8 0x1258
20829 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_1 0x125c
20831 #define S_ENTYPEMATCH 31
20832 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
20833 #define F_ENTYPEMATCH V_ENTYPEMATCH(1U)
20836 #define M_TYPE 0xffffU
20837 #define V_TYPE(x) ((x) << S_TYPE)
20838 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
20840 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_2 0x1260
20841 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_3 0x1264
20842 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_4 0x1268
20843 #define A_XGMAC_PORT_XGM_INT_STATUS 0x126c
20845 #define S_XGMIIEXTINT 10
20846 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
20847 #define F_XGMIIEXTINT V_XGMIIEXTINT(1U)
20849 #define S_LINKFAULTCHANGE 9
20850 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
20851 #define F_LINKFAULTCHANGE V_LINKFAULTCHANGE(1U)
20853 #define S_PHYFRAMECOMPLETE 8
20854 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
20855 #define F_PHYFRAMECOMPLETE V_PHYFRAMECOMPLETE(1U)
20857 #define S_PAUSEFRAMETXMT 7
20858 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
20859 #define F_PAUSEFRAMETXMT V_PAUSEFRAMETXMT(1U)
20861 #define S_PAUSECNTRTIMEOUT 6
20862 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
20863 #define F_PAUSECNTRTIMEOUT V_PAUSECNTRTIMEOUT(1U)
20865 #define S_NON0PAUSERCVD 5
20866 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
20867 #define F_NON0PAUSERCVD V_NON0PAUSERCVD(1U)
20869 #define S_STATOFLOW 4
20870 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
20871 #define F_STATOFLOW V_STATOFLOW(1U)
20873 #define S_TXERRFIFO 3
20874 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
20875 #define F_TXERRFIFO V_TXERRFIFO(1U)
20877 #define S_TXUFLOW 2
20878 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
20879 #define F_TXUFLOW V_TXUFLOW(1U)
20881 #define S_FRAMETXMT 1
20882 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
20883 #define F_FRAMETXMT V_FRAMETXMT(1U)
20885 #define S_FRAMERCVD 0
20886 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
20887 #define F_FRAMERCVD V_FRAMERCVD(1U)
20889 #define A_XGMAC_PORT_XGM_INT_MASK 0x1270
20890 #define A_XGMAC_PORT_XGM_INT_EN 0x1274
20891 #define A_XGMAC_PORT_XGM_INT_DISABLE 0x1278
20892 #define A_XGMAC_PORT_XGM_TX_PAUSE_TIMER 0x127c
20894 #define S_CURPAUSETIMER 0
20895 #define M_CURPAUSETIMER 0xffffU
20896 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
20897 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
20899 #define A_XGMAC_PORT_XGM_STAT_CTRL 0x1280
20901 #define S_READSNPSHOT 4
20902 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
20903 #define F_READSNPSHOT V_READSNPSHOT(1U)
20905 #define S_TAKESNPSHOT 3
20906 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
20907 #define F_TAKESNPSHOT V_TAKESNPSHOT(1U)
20909 #define S_CLRSTATS 2
20910 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
20911 #define F_CLRSTATS V_CLRSTATS(1U)
20913 #define S_INCRSTATS 1
20914 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
20915 #define F_INCRSTATS V_INCRSTATS(1U)
20917 #define S_ENTESTMODEWR 0
20918 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
20919 #define F_ENTESTMODEWR V_ENTESTMODEWR(1U)
20921 #define A_XGMAC_PORT_XGM_MDIO_CTRL 0x1284
20923 #define S_FRAMETYPE 30
20924 #define M_FRAMETYPE 0x3U
20925 #define V_FRAMETYPE(x) ((x) << S_FRAMETYPE)
20926 #define G_FRAMETYPE(x) (((x) >> S_FRAMETYPE) & M_FRAMETYPE)
20928 #define S_OPERATION 28
20929 #define M_OPERATION 0x3U
20930 #define V_OPERATION(x) ((x) << S_OPERATION)
20931 #define G_OPERATION(x) (((x) >> S_OPERATION) & M_OPERATION)
20933 #define S_PORTADDR 23
20934 #define M_PORTADDR 0x1fU
20935 #define V_PORTADDR(x) ((x) << S_PORTADDR)
20936 #define G_PORTADDR(x) (((x) >> S_PORTADDR) & M_PORTADDR)
20938 #define S_DEVADDR 18
20939 #define M_DEVADDR 0x1fU
20940 #define V_DEVADDR(x) ((x) << S_DEVADDR)
20941 #define G_DEVADDR(x) (((x) >> S_DEVADDR) & M_DEVADDR)
20944 #define M_RESRV 0x3U
20945 #define V_RESRV(x) ((x) << S_RESRV)
20946 #define G_RESRV(x) (((x) >> S_RESRV) & M_RESRV)
20949 #define M_DATA 0xffffU
20950 #define V_DATA(x) ((x) << S_DATA)
20951 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
20953 #define A_XGMAC_PORT_XGM_MODULE_ID 0x12fc
20955 #define S_MODULEID 16
20956 #define M_MODULEID 0xffffU
20957 #define V_MODULEID(x) ((x) << S_MODULEID)
20958 #define G_MODULEID(x) (((x) >> S_MODULEID) & M_MODULEID)
20960 #define S_MODULEREV 0
20961 #define M_MODULEREV 0xffffU
20962 #define V_MODULEREV(x) ((x) << S_MODULEREV)
20963 #define G_MODULEREV(x) (((x) >> S_MODULEREV) & M_MODULEREV)
20965 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_LOW 0x1300
20966 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH 0x1304
20968 #define S_TXBYTES_HIGH 0
20969 #define M_TXBYTES_HIGH 0x1fffU
20970 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
20971 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
20973 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_LOW 0x1308
20974 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH 0x130c
20976 #define S_TXFRAMES_HIGH 0
20977 #define M_TXFRAMES_HIGH 0xfU
20978 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
20979 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
20981 #define A_XGMAC_PORT_XGM_STAT_TX_BCAST 0x1310
20982 #define A_XGMAC_PORT_XGM_STAT_TX_MCAST 0x1314
20983 #define A_XGMAC_PORT_XGM_STAT_TX_PAUSE 0x1318
20984 #define A_XGMAC_PORT_XGM_STAT_TX_64B_FRAMES 0x131c
20985 #define A_XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES 0x1320
20986 #define A_XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES 0x1324
20987 #define A_XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES 0x1328
20988 #define A_XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES 0x132c
20989 #define A_XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES 0x1330
20990 #define A_XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES 0x1334
20991 #define A_XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES 0x1338
20992 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_LOW 0x133c
20993 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH 0x1340
20995 #define S_RXBYTES_HIGH 0
20996 #define M_RXBYTES_HIGH 0x1fffU
20997 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
20998 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
21000 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW 0x1344
21001 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH 0x1348
21003 #define S_RXFRAMES_HIGH 0
21004 #define M_RXFRAMES_HIGH 0xfU
21005 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
21006 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
21008 #define A_XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES 0x134c
21009 #define A_XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES 0x1350
21010 #define A_XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES 0x1354
21012 #define S_RXPAUSEFRAMES 0
21013 #define M_RXPAUSEFRAMES 0xffffU
21014 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
21015 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
21017 #define A_XGMAC_PORT_XGM_STAT_RX_64B_FRAMES 0x1358
21018 #define A_XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES 0x135c
21019 #define A_XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES 0x1360
21020 #define A_XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES 0x1364
21021 #define A_XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES 0x1368
21022 #define A_XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES 0x136c
21023 #define A_XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES 0x1370
21024 #define A_XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES 0x1374
21026 #define S_RXSHORTFRAMES 0
21027 #define M_RXSHORTFRAMES 0xffffU
21028 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
21029 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
21031 #define A_XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES 0x1378
21033 #define S_RXOVERSIZEFRAMES 0
21034 #define M_RXOVERSIZEFRAMES 0xffffU
21035 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
21036 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
21038 #define A_XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES 0x137c
21040 #define S_RXJABBERFRAMES 0
21041 #define M_RXJABBERFRAMES 0xffffU
21042 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
21043 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
21045 #define A_XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES 0x1380
21047 #define S_RXCRCERRFRAMES 0
21048 #define M_RXCRCERRFRAMES 0xffffU
21049 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
21050 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
21052 #define A_XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x1384
21054 #define S_RXLENGTHERRFRAMES 0
21055 #define M_RXLENGTHERRFRAMES 0xffffU
21056 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
21057 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
21059 #define A_XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x1388
21061 #define S_RXSYMCODEERRFRAMES 0
21062 #define M_RXSYMCODEERRFRAMES 0xffffU
21063 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
21064 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
21066 #define A_XGMAC_PORT_XAUI_CTRL 0x1400
21068 #define S_POLARITY_INV_RX 8
21069 #define M_POLARITY_INV_RX 0xfU
21070 #define V_POLARITY_INV_RX(x) ((x) << S_POLARITY_INV_RX)
21071 #define G_POLARITY_INV_RX(x) (((x) >> S_POLARITY_INV_RX) & M_POLARITY_INV_RX)
21073 #define S_POLARITY_INV_TX 4
21074 #define M_POLARITY_INV_TX 0xfU
21075 #define V_POLARITY_INV_TX(x) ((x) << S_POLARITY_INV_TX)
21076 #define G_POLARITY_INV_TX(x) (((x) >> S_POLARITY_INV_TX) & M_POLARITY_INV_TX)
21078 #define S_TEST_SEL 2
21079 #define M_TEST_SEL 0x3U
21080 #define V_TEST_SEL(x) ((x) << S_TEST_SEL)
21081 #define G_TEST_SEL(x) (((x) >> S_TEST_SEL) & M_TEST_SEL)
21083 #define S_TEST_EN 0
21084 #define V_TEST_EN(x) ((x) << S_TEST_EN)
21085 #define F_TEST_EN V_TEST_EN(1U)
21087 #define A_XGMAC_PORT_XAUI_STATUS 0x1404
21089 #define S_DECODE_ERROR 12
21090 #define M_DECODE_ERROR 0xffU
21091 #define V_DECODE_ERROR(x) ((x) << S_DECODE_ERROR)
21092 #define G_DECODE_ERROR(x) (((x) >> S_DECODE_ERROR) & M_DECODE_ERROR)
21094 #define S_LANE3_CTC_STATUS 11
21095 #define V_LANE3_CTC_STATUS(x) ((x) << S_LANE3_CTC_STATUS)
21096 #define F_LANE3_CTC_STATUS V_LANE3_CTC_STATUS(1U)
21098 #define S_LANE2_CTC_STATUS 10
21099 #define V_LANE2_CTC_STATUS(x) ((x) << S_LANE2_CTC_STATUS)
21100 #define F_LANE2_CTC_STATUS V_LANE2_CTC_STATUS(1U)
21102 #define S_LANE1_CTC_STATUS 9
21103 #define V_LANE1_CTC_STATUS(x) ((x) << S_LANE1_CTC_STATUS)
21104 #define F_LANE1_CTC_STATUS V_LANE1_CTC_STATUS(1U)
21106 #define S_LANE0_CTC_STATUS 8
21107 #define V_LANE0_CTC_STATUS(x) ((x) << S_LANE0_CTC_STATUS)
21108 #define F_LANE0_CTC_STATUS V_LANE0_CTC_STATUS(1U)
21110 #define S_ALIGN_STATUS 4
21111 #define V_ALIGN_STATUS(x) ((x) << S_ALIGN_STATUS)
21112 #define F_ALIGN_STATUS V_ALIGN_STATUS(1U)
21114 #define S_LANE3_SYNC_STATUS 3
21115 #define V_LANE3_SYNC_STATUS(x) ((x) << S_LANE3_SYNC_STATUS)
21116 #define F_LANE3_SYNC_STATUS V_LANE3_SYNC_STATUS(1U)
21118 #define S_LANE2_SYNC_STATUS 2
21119 #define V_LANE2_SYNC_STATUS(x) ((x) << S_LANE2_SYNC_STATUS)
21120 #define F_LANE2_SYNC_STATUS V_LANE2_SYNC_STATUS(1U)
21122 #define S_LANE1_SYNC_STATUS 1
21123 #define V_LANE1_SYNC_STATUS(x) ((x) << S_LANE1_SYNC_STATUS)
21124 #define F_LANE1_SYNC_STATUS V_LANE1_SYNC_STATUS(1U)
21126 #define S_LANE0_SYNC_STATUS 0
21127 #define V_LANE0_SYNC_STATUS(x) ((x) << S_LANE0_SYNC_STATUS)
21128 #define F_LANE0_SYNC_STATUS V_LANE0_SYNC_STATUS(1U)
21130 #define A_XGMAC_PORT_PCSR_CTRL 0x1500
21132 #define S_RX_CLK_SPEED 7
21133 #define V_RX_CLK_SPEED(x) ((x) << S_RX_CLK_SPEED)
21134 #define F_RX_CLK_SPEED V_RX_CLK_SPEED(1U)
21136 #define S_SCRBYPASS 6
21137 #define V_SCRBYPASS(x) ((x) << S_SCRBYPASS)
21138 #define F_SCRBYPASS V_SCRBYPASS(1U)
21140 #define S_FECERRINDEN 5
21141 #define V_FECERRINDEN(x) ((x) << S_FECERRINDEN)
21142 #define F_FECERRINDEN V_FECERRINDEN(1U)
21145 #define V_FECEN(x) ((x) << S_FECEN)
21146 #define F_FECEN V_FECEN(1U)
21148 #define S_TESTSEL 2
21149 #define M_TESTSEL 0x3U
21150 #define V_TESTSEL(x) ((x) << S_TESTSEL)
21151 #define G_TESTSEL(x) (((x) >> S_TESTSEL) & M_TESTSEL)
21153 #define S_SCRLOOPEN 1
21154 #define V_SCRLOOPEN(x) ((x) << S_SCRLOOPEN)
21155 #define F_SCRLOOPEN V_SCRLOOPEN(1U)
21157 #define S_XGMIILOOPEN 0
21158 #define V_XGMIILOOPEN(x) ((x) << S_XGMIILOOPEN)
21159 #define F_XGMIILOOPEN V_XGMIILOOPEN(1U)
21161 #define A_XGMAC_PORT_PCSR_TXTEST_CTRL 0x1510
21163 #define S_TX_PRBS9_EN 4
21164 #define V_TX_PRBS9_EN(x) ((x) << S_TX_PRBS9_EN)
21165 #define F_TX_PRBS9_EN V_TX_PRBS9_EN(1U)
21167 #define S_TX_PRBS31_EN 3
21168 #define V_TX_PRBS31_EN(x) ((x) << S_TX_PRBS31_EN)
21169 #define F_TX_PRBS31_EN V_TX_PRBS31_EN(1U)
21171 #define S_TX_TST_DAT_SEL 2
21172 #define V_TX_TST_DAT_SEL(x) ((x) << S_TX_TST_DAT_SEL)
21173 #define F_TX_TST_DAT_SEL V_TX_TST_DAT_SEL(1U)
21175 #define S_TX_TST_SEL 1
21176 #define V_TX_TST_SEL(x) ((x) << S_TX_TST_SEL)
21177 #define F_TX_TST_SEL V_TX_TST_SEL(1U)
21179 #define S_TX_TST_EN 0
21180 #define V_TX_TST_EN(x) ((x) << S_TX_TST_EN)
21181 #define F_TX_TST_EN V_TX_TST_EN(1U)
21183 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER 0x1514
21184 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER 0x1518
21186 #define S_SEEDA_UPPER 0
21187 #define M_SEEDA_UPPER 0x3ffffffU
21188 #define V_SEEDA_UPPER(x) ((x) << S_SEEDA_UPPER)
21189 #define G_SEEDA_UPPER(x) (((x) >> S_SEEDA_UPPER) & M_SEEDA_UPPER)
21191 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER 0x152c
21192 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER 0x1530
21194 #define S_SEEDB_UPPER 0
21195 #define M_SEEDB_UPPER 0x3ffffffU
21196 #define V_SEEDB_UPPER(x) ((x) << S_SEEDB_UPPER)
21197 #define G_SEEDB_UPPER(x) (((x) >> S_SEEDB_UPPER) & M_SEEDB_UPPER)
21199 #define A_XGMAC_PORT_PCSR_RXTEST_CTRL 0x153c
21201 #define S_TPTER_CNT_RST 7
21202 #define V_TPTER_CNT_RST(x) ((x) << S_TPTER_CNT_RST)
21203 #define F_TPTER_CNT_RST V_TPTER_CNT_RST(1U)
21205 #define S_TEST_CNT_125US 6
21206 #define V_TEST_CNT_125US(x) ((x) << S_TEST_CNT_125US)
21207 #define F_TEST_CNT_125US V_TEST_CNT_125US(1U)
21209 #define S_TEST_CNT_PRE 5
21210 #define V_TEST_CNT_PRE(x) ((x) << S_TEST_CNT_PRE)
21211 #define F_TEST_CNT_PRE V_TEST_CNT_PRE(1U)
21213 #define S_BER_CNT_RST 4
21214 #define V_BER_CNT_RST(x) ((x) << S_BER_CNT_RST)
21215 #define F_BER_CNT_RST V_BER_CNT_RST(1U)
21217 #define S_ERR_BLK_CNT_RST 3
21218 #define V_ERR_BLK_CNT_RST(x) ((x) << S_ERR_BLK_CNT_RST)
21219 #define F_ERR_BLK_CNT_RST V_ERR_BLK_CNT_RST(1U)
21221 #define S_RX_PRBS31_EN 2
21222 #define V_RX_PRBS31_EN(x) ((x) << S_RX_PRBS31_EN)
21223 #define F_RX_PRBS31_EN V_RX_PRBS31_EN(1U)
21225 #define S_RX_TST_DAT_SEL 1
21226 #define V_RX_TST_DAT_SEL(x) ((x) << S_RX_TST_DAT_SEL)
21227 #define F_RX_TST_DAT_SEL V_RX_TST_DAT_SEL(1U)
21229 #define S_RX_TST_EN 0
21230 #define V_RX_TST_EN(x) ((x) << S_RX_TST_EN)
21231 #define F_RX_TST_EN V_RX_TST_EN(1U)
21233 #define A_XGMAC_PORT_PCSR_STATUS 0x1550
21235 #define S_ERR_BLK_CNT 16
21236 #define M_ERR_BLK_CNT 0xffU
21237 #define V_ERR_BLK_CNT(x) ((x) << S_ERR_BLK_CNT)
21238 #define G_ERR_BLK_CNT(x) (((x) >> S_ERR_BLK_CNT) & M_ERR_BLK_CNT)
21240 #define S_BER_COUNT 8
21241 #define M_BER_COUNT 0x3fU
21242 #define V_BER_COUNT(x) ((x) << S_BER_COUNT)
21243 #define G_BER_COUNT(x) (((x) >> S_BER_COUNT) & M_BER_COUNT)
21246 #define V_HI_BER(x) ((x) << S_HI_BER)
21247 #define F_HI_BER V_HI_BER(1U)
21249 #define S_RX_FAULT 1
21250 #define V_RX_FAULT(x) ((x) << S_RX_FAULT)
21251 #define F_RX_FAULT V_RX_FAULT(1U)
21253 #define S_TX_FAULT 0
21254 #define V_TX_FAULT(x) ((x) << S_TX_FAULT)
21255 #define F_TX_FAULT V_TX_FAULT(1U)
21257 #define A_XGMAC_PORT_PCSR_TEST_STATUS 0x1554
21259 #define S_TPT_ERR_CNT 0
21260 #define M_TPT_ERR_CNT 0xffffU
21261 #define V_TPT_ERR_CNT(x) ((x) << S_TPT_ERR_CNT)
21262 #define G_TPT_ERR_CNT(x) (((x) >> S_TPT_ERR_CNT) & M_TPT_ERR_CNT)
21264 #define A_XGMAC_PORT_AN_CONTROL 0x1600
21266 #define S_SOFT_RESET 15
21267 #define V_SOFT_RESET(x) ((x) << S_SOFT_RESET)
21268 #define F_SOFT_RESET V_SOFT_RESET(1U)
21270 #define S_AN_ENABLE 12
21271 #define V_AN_ENABLE(x) ((x) << S_AN_ENABLE)
21272 #define F_AN_ENABLE V_AN_ENABLE(1U)
21274 #define S_RESTART_AN 9
21275 #define V_RESTART_AN(x) ((x) << S_RESTART_AN)
21276 #define F_RESTART_AN V_RESTART_AN(1U)
21278 #define A_XGMAC_PORT_AN_STATUS 0x1604
21280 #define S_NONCER_MATCH 31
21281 #define V_NONCER_MATCH(x) ((x) << S_NONCER_MATCH)
21282 #define F_NONCER_MATCH V_NONCER_MATCH(1U)
21284 #define S_PARALLEL_DET_FAULT 9
21285 #define V_PARALLEL_DET_FAULT(x) ((x) << S_PARALLEL_DET_FAULT)
21286 #define F_PARALLEL_DET_FAULT V_PARALLEL_DET_FAULT(1U)
21288 #define S_PAGE_RECEIVED 6
21289 #define V_PAGE_RECEIVED(x) ((x) << S_PAGE_RECEIVED)
21290 #define F_PAGE_RECEIVED V_PAGE_RECEIVED(1U)
21292 #define S_AN_COMPLETE 5
21293 #define V_AN_COMPLETE(x) ((x) << S_AN_COMPLETE)
21294 #define F_AN_COMPLETE V_AN_COMPLETE(1U)
21296 #define S_STAT_REMFAULT 4
21297 #define V_STAT_REMFAULT(x) ((x) << S_STAT_REMFAULT)
21298 #define F_STAT_REMFAULT V_STAT_REMFAULT(1U)
21300 #define S_AN_ABILITY 3
21301 #define V_AN_ABILITY(x) ((x) << S_AN_ABILITY)
21302 #define F_AN_ABILITY V_AN_ABILITY(1U)
21304 #define S_LINK_STATUS 2
21305 #define V_LINK_STATUS(x) ((x) << S_LINK_STATUS)
21306 #define F_LINK_STATUS V_LINK_STATUS(1U)
21308 #define S_PARTNER_AN_ABILITY 0
21309 #define V_PARTNER_AN_ABILITY(x) ((x) << S_PARTNER_AN_ABILITY)
21310 #define F_PARTNER_AN_ABILITY V_PARTNER_AN_ABILITY(1U)
21312 #define A_XGMAC_PORT_AN_ADVERTISEMENT 0x1608
21314 #define S_FEC_ENABLE 31
21315 #define V_FEC_ENABLE(x) ((x) << S_FEC_ENABLE)
21316 #define F_FEC_ENABLE V_FEC_ENABLE(1U)
21318 #define S_FEC_ABILITY 30
21319 #define V_FEC_ABILITY(x) ((x) << S_FEC_ABILITY)
21320 #define F_FEC_ABILITY V_FEC_ABILITY(1U)
21322 #define S_10GBASE_KR_CAPABLE 23
21323 #define V_10GBASE_KR_CAPABLE(x) ((x) << S_10GBASE_KR_CAPABLE)
21324 #define F_10GBASE_KR_CAPABLE V_10GBASE_KR_CAPABLE(1U)
21326 #define S_10GBASE_KX4_CAPABLE 22
21327 #define V_10GBASE_KX4_CAPABLE(x) ((x) << S_10GBASE_KX4_CAPABLE)
21328 #define F_10GBASE_KX4_CAPABLE V_10GBASE_KX4_CAPABLE(1U)
21330 #define S_1000BASE_KX_CAPABLE 21
21331 #define V_1000BASE_KX_CAPABLE(x) ((x) << S_1000BASE_KX_CAPABLE)
21332 #define F_1000BASE_KX_CAPABLE V_1000BASE_KX_CAPABLE(1U)
21334 #define S_TRANSMITTED_NONCE 16
21335 #define M_TRANSMITTED_NONCE 0x1fU
21336 #define V_TRANSMITTED_NONCE(x) ((x) << S_TRANSMITTED_NONCE)
21337 #define G_TRANSMITTED_NONCE(x) (((x) >> S_TRANSMITTED_NONCE) & M_TRANSMITTED_NONCE)
21340 #define V_NP(x) ((x) << S_NP)
21341 #define F_NP V_NP(1U)
21344 #define V_ACK(x) ((x) << S_ACK)
21345 #define F_ACK V_ACK(1U)
21347 #define S_REMOTE_FAULT 13
21348 #define V_REMOTE_FAULT(x) ((x) << S_REMOTE_FAULT)
21349 #define F_REMOTE_FAULT V_REMOTE_FAULT(1U)
21351 #define S_ASM_DIR 11
21352 #define V_ASM_DIR(x) ((x) << S_ASM_DIR)
21353 #define F_ASM_DIR V_ASM_DIR(1U)
21356 #define V_PAUSE(x) ((x) << S_PAUSE)
21357 #define F_PAUSE V_PAUSE(1U)
21359 #define S_ECHOED_NONCE 5
21360 #define M_ECHOED_NONCE 0x1fU
21361 #define V_ECHOED_NONCE(x) ((x) << S_ECHOED_NONCE)
21362 #define G_ECHOED_NONCE(x) (((x) >> S_ECHOED_NONCE) & M_ECHOED_NONCE)
21364 #define A_XGMAC_PORT_AN_LINK_PARTNER_ABILITY 0x160c
21366 #define S_SELECTOR_FIELD 0
21367 #define M_SELECTOR_FIELD 0x1fU
21368 #define V_SELECTOR_FIELD(x) ((x) << S_SELECTOR_FIELD)
21369 #define G_SELECTOR_FIELD(x) (((x) >> S_SELECTOR_FIELD) & M_SELECTOR_FIELD)
21371 #define A_XGMAC_PORT_AN_NP_LOWER_TRANSMIT 0x1610
21373 #define S_NP_INFO 16
21374 #define M_NP_INFO 0xffffU
21375 #define V_NP_INFO(x) ((x) << S_NP_INFO)
21376 #define G_NP_INFO(x) (((x) >> S_NP_INFO) & M_NP_INFO)
21378 #define S_NP_INDICATION 15
21379 #define V_NP_INDICATION(x) ((x) << S_NP_INDICATION)
21380 #define F_NP_INDICATION V_NP_INDICATION(1U)
21382 #define S_MESSAGE_PAGE 13
21383 #define V_MESSAGE_PAGE(x) ((x) << S_MESSAGE_PAGE)
21384 #define F_MESSAGE_PAGE V_MESSAGE_PAGE(1U)
21387 #define V_ACK_2(x) ((x) << S_ACK_2)
21388 #define F_ACK_2 V_ACK_2(1U)
21390 #define S_TOGGLE 11
21391 #define V_TOGGLE(x) ((x) << S_TOGGLE)
21392 #define F_TOGGLE V_TOGGLE(1U)
21394 #define A_XGMAC_PORT_AN_NP_UPPER_TRANSMIT 0x1614
21396 #define S_NP_INFO_HI 0
21397 #define M_NP_INFO_HI 0xffffU
21398 #define V_NP_INFO_HI(x) ((x) << S_NP_INFO_HI)
21399 #define G_NP_INFO_HI(x) (((x) >> S_NP_INFO_HI) & M_NP_INFO_HI)
21401 #define A_XGMAC_PORT_AN_LP_NP_LOWER 0x1618
21402 #define A_XGMAC_PORT_AN_LP_NP_UPPER 0x161c
21403 #define A_XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS 0x1624
21405 #define S_TX_PAUSE_OKAY 6
21406 #define V_TX_PAUSE_OKAY(x) ((x) << S_TX_PAUSE_OKAY)
21407 #define F_TX_PAUSE_OKAY V_TX_PAUSE_OKAY(1U)
21409 #define S_RX_PAUSE_OKAY 5
21410 #define V_RX_PAUSE_OKAY(x) ((x) << S_RX_PAUSE_OKAY)
21411 #define F_RX_PAUSE_OKAY V_RX_PAUSE_OKAY(1U)
21413 #define S_10GBASE_KR_FEC_NEG 4
21414 #define V_10GBASE_KR_FEC_NEG(x) ((x) << S_10GBASE_KR_FEC_NEG)
21415 #define F_10GBASE_KR_FEC_NEG V_10GBASE_KR_FEC_NEG(1U)
21417 #define S_10GBASE_KR_NEG 3
21418 #define V_10GBASE_KR_NEG(x) ((x) << S_10GBASE_KR_NEG)
21419 #define F_10GBASE_KR_NEG V_10GBASE_KR_NEG(1U)
21421 #define S_10GBASE_KX4_NEG 2
21422 #define V_10GBASE_KX4_NEG(x) ((x) << S_10GBASE_KX4_NEG)
21423 #define F_10GBASE_KX4_NEG V_10GBASE_KX4_NEG(1U)
21425 #define S_1000BASE_KX_NEG 1
21426 #define V_1000BASE_KX_NEG(x) ((x) << S_1000BASE_KX_NEG)
21427 #define F_1000BASE_KX_NEG V_1000BASE_KX_NEG(1U)
21429 #define S_BP_AN_ABILITY 0
21430 #define V_BP_AN_ABILITY(x) ((x) << S_BP_AN_ABILITY)
21431 #define F_BP_AN_ABILITY V_BP_AN_ABILITY(1U)
21433 #define A_XGMAC_PORT_AN_TX_NONCE_CONTROL 0x1628
21435 #define S_BYPASS_LFSR 15
21436 #define V_BYPASS_LFSR(x) ((x) << S_BYPASS_LFSR)
21437 #define F_BYPASS_LFSR V_BYPASS_LFSR(1U)
21439 #define S_LFSR_INIT 0
21440 #define M_LFSR_INIT 0x7fffU
21441 #define V_LFSR_INIT(x) ((x) << S_LFSR_INIT)
21442 #define G_LFSR_INIT(x) (((x) >> S_LFSR_INIT) & M_LFSR_INIT)
21444 #define A_XGMAC_PORT_AN_INTERRUPT_STATUS 0x162c
21446 #define S_NP_FROM_LP 3
21447 #define V_NP_FROM_LP(x) ((x) << S_NP_FROM_LP)
21448 #define F_NP_FROM_LP V_NP_FROM_LP(1U)
21450 #define S_PARALLELDETFAULTINT 2
21451 #define V_PARALLELDETFAULTINT(x) ((x) << S_PARALLELDETFAULTINT)
21452 #define F_PARALLELDETFAULTINT V_PARALLELDETFAULTINT(1U)
21454 #define S_BP_FROM_LP 1
21455 #define V_BP_FROM_LP(x) ((x) << S_BP_FROM_LP)
21456 #define F_BP_FROM_LP V_BP_FROM_LP(1U)
21458 #define S_PCS_AN_COMPLETE 0
21459 #define V_PCS_AN_COMPLETE(x) ((x) << S_PCS_AN_COMPLETE)
21460 #define F_PCS_AN_COMPLETE V_PCS_AN_COMPLETE(1U)
21462 #define A_XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT 0x1630
21464 #define S_GENERIC_TIMEOUT 0
21465 #define M_GENERIC_TIMEOUT 0x7fffffU
21466 #define V_GENERIC_TIMEOUT(x) ((x) << S_GENERIC_TIMEOUT)
21467 #define G_GENERIC_TIMEOUT(x) (((x) >> S_GENERIC_TIMEOUT) & M_GENERIC_TIMEOUT)
21469 #define A_XGMAC_PORT_AN_BREAK_LINK_TIMEOUT 0x1634
21471 #define S_BREAK_LINK_TIMEOUT 0
21472 #define M_BREAK_LINK_TIMEOUT 0xffffffU
21473 #define V_BREAK_LINK_TIMEOUT(x) ((x) << S_BREAK_LINK_TIMEOUT)
21474 #define G_BREAK_LINK_TIMEOUT(x) (((x) >> S_BREAK_LINK_TIMEOUT) & M_BREAK_LINK_TIMEOUT)
21476 #define A_XGMAC_PORT_AN_MODULE_ID 0x163c
21478 #define S_MODULE_ID 16
21479 #define M_MODULE_ID 0xffffU
21480 #define V_MODULE_ID(x) ((x) << S_MODULE_ID)
21481 #define G_MODULE_ID(x) (((x) >> S_MODULE_ID) & M_MODULE_ID)
21483 #define S_MODULE_REVISION 0
21484 #define M_MODULE_REVISION 0xffffU
21485 #define V_MODULE_REVISION(x) ((x) << S_MODULE_REVISION)
21486 #define G_MODULE_REVISION(x) (((x) >> S_MODULE_REVISION) & M_MODULE_REVISION)
21488 #define A_XGMAC_PORT_AE_RX_COEF_REQ 0x1700
21490 #define S_RXREQ_CPRE 13
21491 #define V_RXREQ_CPRE(x) ((x) << S_RXREQ_CPRE)
21492 #define F_RXREQ_CPRE V_RXREQ_CPRE(1U)
21494 #define S_RXREQ_CINIT 12
21495 #define V_RXREQ_CINIT(x) ((x) << S_RXREQ_CINIT)
21496 #define F_RXREQ_CINIT V_RXREQ_CINIT(1U)
21498 #define S_RXREQ_C0 4
21499 #define M_RXREQ_C0 0x3U
21500 #define V_RXREQ_C0(x) ((x) << S_RXREQ_C0)
21501 #define G_RXREQ_C0(x) (((x) >> S_RXREQ_C0) & M_RXREQ_C0)
21503 #define S_RXREQ_C1 2
21504 #define M_RXREQ_C1 0x3U
21505 #define V_RXREQ_C1(x) ((x) << S_RXREQ_C1)
21506 #define G_RXREQ_C1(x) (((x) >> S_RXREQ_C1) & M_RXREQ_C1)
21508 #define S_RXREQ_C2 0
21509 #define M_RXREQ_C2 0x3U
21510 #define V_RXREQ_C2(x) ((x) << S_RXREQ_C2)
21511 #define G_RXREQ_C2(x) (((x) >> S_RXREQ_C2) & M_RXREQ_C2)
21513 #define A_XGMAC_PORT_AE_RX_COEF_STAT 0x1704
21515 #define S_RXSTAT_RDY 15
21516 #define V_RXSTAT_RDY(x) ((x) << S_RXSTAT_RDY)
21517 #define F_RXSTAT_RDY V_RXSTAT_RDY(1U)
21519 #define S_RXSTAT_C0 4
21520 #define M_RXSTAT_C0 0x3U
21521 #define V_RXSTAT_C0(x) ((x) << S_RXSTAT_C0)
21522 #define G_RXSTAT_C0(x) (((x) >> S_RXSTAT_C0) & M_RXSTAT_C0)
21524 #define S_RXSTAT_C1 2
21525 #define M_RXSTAT_C1 0x3U
21526 #define V_RXSTAT_C1(x) ((x) << S_RXSTAT_C1)
21527 #define G_RXSTAT_C1(x) (((x) >> S_RXSTAT_C1) & M_RXSTAT_C1)
21529 #define S_RXSTAT_C2 0
21530 #define M_RXSTAT_C2 0x3U
21531 #define V_RXSTAT_C2(x) ((x) << S_RXSTAT_C2)
21532 #define G_RXSTAT_C2(x) (((x) >> S_RXSTAT_C2) & M_RXSTAT_C2)
21534 #define A_XGMAC_PORT_AE_TX_COEF_REQ 0x1708
21536 #define S_TXREQ_CPRE 13
21537 #define V_TXREQ_CPRE(x) ((x) << S_TXREQ_CPRE)
21538 #define F_TXREQ_CPRE V_TXREQ_CPRE(1U)
21540 #define S_TXREQ_CINIT 12
21541 #define V_TXREQ_CINIT(x) ((x) << S_TXREQ_CINIT)
21542 #define F_TXREQ_CINIT V_TXREQ_CINIT(1U)
21544 #define S_TXREQ_C0 4
21545 #define M_TXREQ_C0 0x3U
21546 #define V_TXREQ_C0(x) ((x) << S_TXREQ_C0)
21547 #define G_TXREQ_C0(x) (((x) >> S_TXREQ_C0) & M_TXREQ_C0)
21549 #define S_TXREQ_C1 2
21550 #define M_TXREQ_C1 0x3U
21551 #define V_TXREQ_C1(x) ((x) << S_TXREQ_C1)
21552 #define G_TXREQ_C1(x) (((x) >> S_TXREQ_C1) & M_TXREQ_C1)
21554 #define S_TXREQ_C2 0
21555 #define M_TXREQ_C2 0x3U
21556 #define V_TXREQ_C2(x) ((x) << S_TXREQ_C2)
21557 #define G_TXREQ_C2(x) (((x) >> S_TXREQ_C2) & M_TXREQ_C2)
21559 #define A_XGMAC_PORT_AE_TX_COEF_STAT 0x170c
21561 #define S_TXSTAT_RDY 15
21562 #define V_TXSTAT_RDY(x) ((x) << S_TXSTAT_RDY)
21563 #define F_TXSTAT_RDY V_TXSTAT_RDY(1U)
21565 #define S_TXSTAT_C0 4
21566 #define M_TXSTAT_C0 0x3U
21567 #define V_TXSTAT_C0(x) ((x) << S_TXSTAT_C0)
21568 #define G_TXSTAT_C0(x) (((x) >> S_TXSTAT_C0) & M_TXSTAT_C0)
21570 #define S_TXSTAT_C1 2
21571 #define M_TXSTAT_C1 0x3U
21572 #define V_TXSTAT_C1(x) ((x) << S_TXSTAT_C1)
21573 #define G_TXSTAT_C1(x) (((x) >> S_TXSTAT_C1) & M_TXSTAT_C1)
21575 #define S_TXSTAT_C2 0
21576 #define M_TXSTAT_C2 0x3U
21577 #define V_TXSTAT_C2(x) ((x) << S_TXSTAT_C2)
21578 #define G_TXSTAT_C2(x) (((x) >> S_TXSTAT_C2) & M_TXSTAT_C2)
21580 #define A_XGMAC_PORT_AE_REG_MODE 0x1710
21582 #define S_MAN_DEC 4
21583 #define M_MAN_DEC 0x3U
21584 #define V_MAN_DEC(x) ((x) << S_MAN_DEC)
21585 #define G_MAN_DEC(x) (((x) >> S_MAN_DEC) & M_MAN_DEC)
21587 #define S_MANUAL_RDY 3
21588 #define V_MANUAL_RDY(x) ((x) << S_MANUAL_RDY)
21589 #define F_MANUAL_RDY V_MANUAL_RDY(1U)
21591 #define S_MWT_DISABLE 2
21592 #define V_MWT_DISABLE(x) ((x) << S_MWT_DISABLE)
21593 #define F_MWT_DISABLE V_MWT_DISABLE(1U)
21595 #define S_MDIO_OVR 1
21596 #define V_MDIO_OVR(x) ((x) << S_MDIO_OVR)
21597 #define F_MDIO_OVR V_MDIO_OVR(1U)
21599 #define S_STICKY_MODE 0
21600 #define V_STICKY_MODE(x) ((x) << S_STICKY_MODE)
21601 #define F_STICKY_MODE V_STICKY_MODE(1U)
21603 #define A_XGMAC_PORT_AE_PRBS_CTL 0x1714
21605 #define S_PRBS_CHK_ERRCNT 8
21606 #define M_PRBS_CHK_ERRCNT 0xffU
21607 #define V_PRBS_CHK_ERRCNT(x) ((x) << S_PRBS_CHK_ERRCNT)
21608 #define G_PRBS_CHK_ERRCNT(x) (((x) >> S_PRBS_CHK_ERRCNT) & M_PRBS_CHK_ERRCNT)
21610 #define S_PRBS_SYNCCNT 5
21611 #define M_PRBS_SYNCCNT 0x7U
21612 #define V_PRBS_SYNCCNT(x) ((x) << S_PRBS_SYNCCNT)
21613 #define G_PRBS_SYNCCNT(x) (((x) >> S_PRBS_SYNCCNT) & M_PRBS_SYNCCNT)
21615 #define S_PRBS_CHK_SYNC 4
21616 #define V_PRBS_CHK_SYNC(x) ((x) << S_PRBS_CHK_SYNC)
21617 #define F_PRBS_CHK_SYNC V_PRBS_CHK_SYNC(1U)
21619 #define S_PRBS_CHK_RST 3
21620 #define V_PRBS_CHK_RST(x) ((x) << S_PRBS_CHK_RST)
21621 #define F_PRBS_CHK_RST V_PRBS_CHK_RST(1U)
21623 #define S_PRBS_CHK_OFF 2
21624 #define V_PRBS_CHK_OFF(x) ((x) << S_PRBS_CHK_OFF)
21625 #define F_PRBS_CHK_OFF V_PRBS_CHK_OFF(1U)
21627 #define S_PRBS_GEN_FRCERR 1
21628 #define V_PRBS_GEN_FRCERR(x) ((x) << S_PRBS_GEN_FRCERR)
21629 #define F_PRBS_GEN_FRCERR V_PRBS_GEN_FRCERR(1U)
21631 #define S_PRBS_GEN_OFF 0
21632 #define V_PRBS_GEN_OFF(x) ((x) << S_PRBS_GEN_OFF)
21633 #define F_PRBS_GEN_OFF V_PRBS_GEN_OFF(1U)
21635 #define A_XGMAC_PORT_AE_FSM_CTL 0x1718
21637 #define S_FSM_TR_LCL 14
21638 #define V_FSM_TR_LCL(x) ((x) << S_FSM_TR_LCL)
21639 #define F_FSM_TR_LCL V_FSM_TR_LCL(1U)
21641 #define S_FSM_GDMRK 11
21642 #define M_FSM_GDMRK 0x7U
21643 #define V_FSM_GDMRK(x) ((x) << S_FSM_GDMRK)
21644 #define G_FSM_GDMRK(x) (((x) >> S_FSM_GDMRK) & M_FSM_GDMRK)
21646 #define S_FSM_BADMRK 8
21647 #define M_FSM_BADMRK 0x7U
21648 #define V_FSM_BADMRK(x) ((x) << S_FSM_BADMRK)
21649 #define G_FSM_BADMRK(x) (((x) >> S_FSM_BADMRK) & M_FSM_BADMRK)
21651 #define S_FSM_TR_FAIL 7
21652 #define V_FSM_TR_FAIL(x) ((x) << S_FSM_TR_FAIL)
21653 #define F_FSM_TR_FAIL V_FSM_TR_FAIL(1U)
21655 #define S_FSM_TR_ACT 6
21656 #define V_FSM_TR_ACT(x) ((x) << S_FSM_TR_ACT)
21657 #define F_FSM_TR_ACT V_FSM_TR_ACT(1U)
21659 #define S_FSM_FRM_LCK 5
21660 #define V_FSM_FRM_LCK(x) ((x) << S_FSM_FRM_LCK)
21661 #define F_FSM_FRM_LCK V_FSM_FRM_LCK(1U)
21663 #define S_FSM_TR_COMP 4
21664 #define V_FSM_TR_COMP(x) ((x) << S_FSM_TR_COMP)
21665 #define F_FSM_TR_COMP V_FSM_TR_COMP(1U)
21667 #define S_MC_RX_RDY 3
21668 #define V_MC_RX_RDY(x) ((x) << S_MC_RX_RDY)
21669 #define F_MC_RX_RDY V_MC_RX_RDY(1U)
21671 #define S_FSM_CU_DIS 2
21672 #define V_FSM_CU_DIS(x) ((x) << S_FSM_CU_DIS)
21673 #define F_FSM_CU_DIS V_FSM_CU_DIS(1U)
21675 #define S_FSM_TR_RST 1
21676 #define V_FSM_TR_RST(x) ((x) << S_FSM_TR_RST)
21677 #define F_FSM_TR_RST V_FSM_TR_RST(1U)
21679 #define S_FSM_TR_EN 0
21680 #define V_FSM_TR_EN(x) ((x) << S_FSM_TR_EN)
21681 #define F_FSM_TR_EN V_FSM_TR_EN(1U)
21683 #define A_XGMAC_PORT_AE_FSM_STATE 0x171c
21685 #define S_CC2FSM_STATE 13
21686 #define M_CC2FSM_STATE 0x7U
21687 #define V_CC2FSM_STATE(x) ((x) << S_CC2FSM_STATE)
21688 #define G_CC2FSM_STATE(x) (((x) >> S_CC2FSM_STATE) & M_CC2FSM_STATE)
21690 #define S_CC1FSM_STATE 10
21691 #define M_CC1FSM_STATE 0x7U
21692 #define V_CC1FSM_STATE(x) ((x) << S_CC1FSM_STATE)
21693 #define G_CC1FSM_STATE(x) (((x) >> S_CC1FSM_STATE) & M_CC1FSM_STATE)
21695 #define S_CC0FSM_STATE 7
21696 #define M_CC0FSM_STATE 0x7U
21697 #define V_CC0FSM_STATE(x) ((x) << S_CC0FSM_STATE)
21698 #define G_CC0FSM_STATE(x) (((x) >> S_CC0FSM_STATE) & M_CC0FSM_STATE)
21700 #define S_FLFSM_STATE 4
21701 #define M_FLFSM_STATE 0x7U
21702 #define V_FLFSM_STATE(x) ((x) << S_FLFSM_STATE)
21703 #define G_FLFSM_STATE(x) (((x) >> S_FLFSM_STATE) & M_FLFSM_STATE)
21705 #define S_TFSM_STATE 0
21706 #define M_TFSM_STATE 0x7U
21707 #define V_TFSM_STATE(x) ((x) << S_TFSM_STATE)
21708 #define G_TFSM_STATE(x) (((x) >> S_TFSM_STATE) & M_TFSM_STATE)
21710 #define A_XGMAC_PORT_AE_TX_DIS 0x1780
21712 #define S_PMD_TX_DIS 0
21713 #define V_PMD_TX_DIS(x) ((x) << S_PMD_TX_DIS)
21714 #define F_PMD_TX_DIS V_PMD_TX_DIS(1U)
21716 #define A_XGMAC_PORT_AE_KR_CTRL 0x1784
21718 #define S_TRAINING_ENABLE 1
21719 #define V_TRAINING_ENABLE(x) ((x) << S_TRAINING_ENABLE)
21720 #define F_TRAINING_ENABLE V_TRAINING_ENABLE(1U)
21722 #define S_RESTART_TRAINING 0
21723 #define V_RESTART_TRAINING(x) ((x) << S_RESTART_TRAINING)
21724 #define F_RESTART_TRAINING V_RESTART_TRAINING(1U)
21726 #define A_XGMAC_PORT_AE_RX_SIGDET 0x1788
21728 #define S_PMD_SIGDET 0
21729 #define V_PMD_SIGDET(x) ((x) << S_PMD_SIGDET)
21730 #define F_PMD_SIGDET V_PMD_SIGDET(1U)
21732 #define A_XGMAC_PORT_AE_KR_STATUS 0x178c
21734 #define S_TRAINING_FAILURE 3
21735 #define V_TRAINING_FAILURE(x) ((x) << S_TRAINING_FAILURE)
21736 #define F_TRAINING_FAILURE V_TRAINING_FAILURE(1U)
21738 #define S_TRAINING 2
21739 #define V_TRAINING(x) ((x) << S_TRAINING)
21740 #define F_TRAINING V_TRAINING(1U)
21742 #define S_FRAME_LOCK 1
21743 #define V_FRAME_LOCK(x) ((x) << S_FRAME_LOCK)
21744 #define F_FRAME_LOCK V_FRAME_LOCK(1U)
21746 #define S_RX_TRAINED 0
21747 #define V_RX_TRAINED(x) ((x) << S_RX_TRAINED)
21748 #define F_RX_TRAINED V_RX_TRAINED(1U)
21750 #define A_XGMAC_PORT_HSS_TXA_MODE_CFG 0x1800
21753 #define M_BWSEL 0x3U
21754 #define V_BWSEL(x) ((x) << S_BWSEL)
21755 #define G_BWSEL(x) (((x) >> S_BWSEL) & M_BWSEL)
21758 #define M_RTSEL 0x3U
21759 #define V_RTSEL(x) ((x) << S_RTSEL)
21760 #define G_RTSEL(x) (((x) >> S_RTSEL) & M_RTSEL)
21762 #define A_XGMAC_PORT_HSS_TXA_TEST_CTRL 0x1804
21765 #define V_TWDP(x) ((x) << S_TWDP)
21766 #define F_TWDP V_TWDP(1U)
21769 #define V_TPGRST(x) ((x) << S_TPGRST)
21770 #define F_TPGRST V_TPGRST(1U)
21773 #define V_TPGEN(x) ((x) << S_TPGEN)
21774 #define F_TPGEN V_TPGEN(1U)
21777 #define M_TPSEL 0x7U
21778 #define V_TPSEL(x) ((x) << S_TPSEL)
21779 #define G_TPSEL(x) (((x) >> S_TPSEL) & M_TPSEL)
21781 #define A_XGMAC_PORT_HSS_TXA_COEFF_CTRL 0x1808
21783 #define S_AEINVPOL 6
21784 #define V_AEINVPOL(x) ((x) << S_AEINVPOL)
21785 #define F_AEINVPOL V_AEINVPOL(1U)
21787 #define S_AESOURCE 5
21788 #define V_AESOURCE(x) ((x) << S_AESOURCE)
21789 #define F_AESOURCE V_AESOURCE(1U)
21792 #define V_EQMODE(x) ((x) << S_EQMODE)
21793 #define F_EQMODE V_EQMODE(1U)
21796 #define V_OCOEF(x) ((x) << S_OCOEF)
21797 #define F_OCOEF V_OCOEF(1U)
21799 #define S_COEFRST 2
21800 #define V_COEFRST(x) ((x) << S_COEFRST)
21801 #define F_COEFRST V_COEFRST(1U)
21804 #define V_SPEN(x) ((x) << S_SPEN)
21805 #define F_SPEN V_SPEN(1U)
21808 #define V_ALOAD(x) ((x) << S_ALOAD)
21809 #define F_ALOAD V_ALOAD(1U)
21811 #define A_XGMAC_PORT_HSS_TXA_DRIVER_MODE 0x180c
21813 #define S_DRVOFFT 5
21814 #define V_DRVOFFT(x) ((x) << S_DRVOFFT)
21815 #define F_DRVOFFT V_DRVOFFT(1U)
21818 #define M_SLEW 0x7U
21819 #define V_SLEW(x) ((x) << S_SLEW)
21820 #define G_SLEW(x) (((x) >> S_SLEW) & M_SLEW)
21824 #define V_FFE(x) ((x) << S_FFE)
21825 #define G_FFE(x) (((x) >> S_FFE) & M_FFE)
21827 #define A_XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL 0x1810
21830 #define V_VLINC(x) ((x) << S_VLINC)
21831 #define F_VLINC V_VLINC(1U)
21834 #define V_VLDEC(x) ((x) << S_VLDEC)
21835 #define F_VLDEC V_VLDEC(1U)
21838 #define V_LOPWR(x) ((x) << S_LOPWR)
21839 #define F_LOPWR V_LOPWR(1U)
21842 #define V_TDMEN(x) ((x) << S_TDMEN)
21843 #define F_TDMEN V_TDMEN(1U)
21846 #define V_DCCEN(x) ((x) << S_DCCEN)
21847 #define F_DCCEN V_DCCEN(1U)
21850 #define V_VHSEL(x) ((x) << S_VHSEL)
21851 #define F_VHSEL V_VHSEL(1U)
21854 #define M_IDAC 0x3U
21855 #define V_IDAC(x) ((x) << S_IDAC)
21856 #define G_IDAC(x) (((x) >> S_IDAC) & M_IDAC)
21858 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER 0x1814
21861 #define M_STBY 0xffffU
21862 #define V_STBY(x) ((x) << S_STBY)
21863 #define G_STBY(x) (((x) >> S_STBY) & M_STBY)
21865 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER 0x1818
21868 #define M_PON 0xffffU
21869 #define V_PON(x) ((x) << S_PON)
21870 #define G_PON(x) (((x) >> S_PON) & M_PON)
21872 #define A_XGMAC_PORT_HSS_TXA_TAP0_COEFF 0x1820
21875 #define M_NXTT0 0xfU
21876 #define V_NXTT0(x) ((x) << S_NXTT0)
21877 #define G_NXTT0(x) (((x) >> S_NXTT0) & M_NXTT0)
21879 #define A_XGMAC_PORT_HSS_TXA_TAP1_COEFF 0x1824
21882 #define M_NXTT1 0x3fU
21883 #define V_NXTT1(x) ((x) << S_NXTT1)
21884 #define G_NXTT1(x) (((x) >> S_NXTT1) & M_NXTT1)
21886 #define A_XGMAC_PORT_HSS_TXA_TAP2_COEFF 0x1828
21889 #define M_NXTT2 0x1fU
21890 #define V_NXTT2(x) ((x) << S_NXTT2)
21891 #define G_NXTT2(x) (((x) >> S_NXTT2) & M_NXTT2)
21893 #define A_XGMAC_PORT_HSS_TXA_PWR 0x1830
21896 #define M_TXPWR 0x7fU
21897 #define V_TXPWR(x) ((x) << S_TXPWR)
21898 #define G_TXPWR(x) (((x) >> S_TXPWR) & M_TXPWR)
21900 #define A_XGMAC_PORT_HSS_TXA_POLARITY 0x1834
21903 #define M_TXPOL 0x7U
21904 #define V_TXPOL(x) ((x) << S_TXPOL)
21905 #define G_TXPOL(x) (((x) >> S_TXPOL) & M_TXPOL)
21908 #define M_NTXPOL 0x7U
21909 #define V_NTXPOL(x) ((x) << S_NTXPOL)
21910 #define G_NTXPOL(x) (((x) >> S_NTXPOL) & M_NTXPOL)
21912 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_CMD 0x1838
21914 #define S_CXPRESET 13
21915 #define V_CXPRESET(x) ((x) << S_CXPRESET)
21916 #define F_CXPRESET V_CXPRESET(1U)
21918 #define S_CXINIT 12
21919 #define V_CXINIT(x) ((x) << S_CXINIT)
21920 #define F_CXINIT V_CXINIT(1U)
21923 #define M_C2UPDT 0x3U
21924 #define V_C2UPDT(x) ((x) << S_C2UPDT)
21925 #define G_C2UPDT(x) (((x) >> S_C2UPDT) & M_C2UPDT)
21928 #define M_C1UPDT 0x3U
21929 #define V_C1UPDT(x) ((x) << S_C1UPDT)
21930 #define G_C1UPDT(x) (((x) >> S_C1UPDT) & M_C1UPDT)
21933 #define M_C0UPDT 0x3U
21934 #define V_C0UPDT(x) ((x) << S_C0UPDT)
21935 #define G_C0UPDT(x) (((x) >> S_C0UPDT) & M_C0UPDT)
21937 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS 0x183c
21940 #define M_C2STAT 0x3U
21941 #define V_C2STAT(x) ((x) << S_C2STAT)
21942 #define G_C2STAT(x) (((x) >> S_C2STAT) & M_C2STAT)
21945 #define M_C1STAT 0x3U
21946 #define V_C1STAT(x) ((x) << S_C1STAT)
21947 #define G_C1STAT(x) (((x) >> S_C1STAT) & M_C1STAT)
21950 #define M_C0STAT 0x3U
21951 #define V_C0STAT(x) ((x) << S_C0STAT)
21952 #define G_C0STAT(x) (((x) >> S_C0STAT) & M_C0STAT)
21954 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR 0x1840
21957 #define M_NIDAC0 0x1fU
21958 #define V_NIDAC0(x) ((x) << S_NIDAC0)
21959 #define G_NIDAC0(x) (((x) >> S_NIDAC0) & M_NIDAC0)
21961 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR 0x1844
21964 #define M_NIDAC1 0x7fU
21965 #define V_NIDAC1(x) ((x) << S_NIDAC1)
21966 #define G_NIDAC1(x) (((x) >> S_NIDAC1) & M_NIDAC1)
21968 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR 0x1848
21971 #define M_NIDAC2 0x3fU
21972 #define V_NIDAC2(x) ((x) << S_NIDAC2)
21973 #define G_NIDAC2(x) (((x) >> S_NIDAC2) & M_NIDAC2)
21975 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC_OVR 0x1850
21978 #define V_OPEN(x) ((x) << S_OPEN)
21979 #define F_OPEN V_OPEN(1U)
21982 #define M_OPVAL 0x1fU
21983 #define V_OPVAL(x) ((x) << S_OPVAL)
21984 #define G_OPVAL(x) (((x) >> S_OPVAL) & M_OPVAL)
21986 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC 0x1854
21989 #define M_PDAC 0x1fU
21990 #define V_PDAC(x) ((x) << S_PDAC)
21991 #define G_PDAC(x) (((x) >> S_PDAC) & M_PDAC)
21993 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP 0x1860
21996 #define M_AIDAC0 0x1fU
21997 #define V_AIDAC0(x) ((x) << S_AIDAC0)
21998 #define G_AIDAC0(x) (((x) >> S_AIDAC0) & M_AIDAC0)
22000 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP 0x1864
22003 #define M_AIDAC1 0x1fU
22004 #define V_AIDAC1(x) ((x) << S_AIDAC1)
22005 #define G_AIDAC1(x) (((x) >> S_AIDAC1) & M_AIDAC1)
22007 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP 0x1868
22009 #define S_TXA_AIDAC2 0
22010 #define M_TXA_AIDAC2 0x1fU
22011 #define V_TXA_AIDAC2(x) ((x) << S_TXA_AIDAC2)
22012 #define G_TXA_AIDAC2(x) (((x) >> S_TXA_AIDAC2) & M_TXA_AIDAC2)
22014 #define A_XGMAC_PORT_HSS_TXA_SEG_DIS_APP 0x1870
22017 #define M_CURSD 0x7fU
22018 #define V_CURSD(x) ((x) << S_CURSD)
22019 #define G_CURSD(x) (((x) >> S_CURSD) & M_CURSD)
22021 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA 0x1878
22024 #define M_XDATA 0xffffU
22025 #define V_XDATA(x) ((x) << S_XDATA)
22026 #define G_XDATA(x) (((x) >> S_XDATA) & M_XDATA)
22028 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR 0x187c
22030 #define S_EXTADDR 1
22031 #define M_EXTADDR 0x1fU
22032 #define V_EXTADDR(x) ((x) << S_EXTADDR)
22033 #define G_EXTADDR(x) (((x) >> S_EXTADDR) & M_EXTADDR)
22036 #define V_XWR(x) ((x) << S_XWR)
22037 #define F_XWR V_XWR(1U)
22039 #define A_XGMAC_PORT_HSS_TXB_MODE_CFG 0x1880
22040 #define A_XGMAC_PORT_HSS_TXB_TEST_CTRL 0x1884
22041 #define A_XGMAC_PORT_HSS_TXB_COEFF_CTRL 0x1888
22042 #define A_XGMAC_PORT_HSS_TXB_DRIVER_MODE 0x188c
22043 #define A_XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL 0x1890
22044 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER 0x1894
22045 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER 0x1898
22046 #define A_XGMAC_PORT_HSS_TXB_TAP0_COEFF 0x18a0
22047 #define A_XGMAC_PORT_HSS_TXB_TAP1_COEFF 0x18a4
22048 #define A_XGMAC_PORT_HSS_TXB_TAP2_COEFF 0x18a8
22049 #define A_XGMAC_PORT_HSS_TXB_PWR 0x18b0
22050 #define A_XGMAC_PORT_HSS_TXB_POLARITY 0x18b4
22051 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_CMD 0x18b8
22052 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS 0x18bc
22053 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR 0x18c0
22054 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR 0x18c4
22055 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR 0x18c8
22056 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC_OVR 0x18d0
22057 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC 0x18d4
22058 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP 0x18e0
22059 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP 0x18e4
22060 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP 0x18e8
22063 #define M_AIDAC2 0x3fU
22064 #define V_AIDAC2(x) ((x) << S_AIDAC2)
22065 #define G_AIDAC2(x) (((x) >> S_AIDAC2) & M_AIDAC2)
22067 #define A_XGMAC_PORT_HSS_TXB_SEG_DIS_APP 0x18f0
22068 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA 0x18f8
22069 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR 0x18fc
22072 #define M_XADDR 0xfU
22073 #define V_XADDR(x) ((x) << S_XADDR)
22074 #define G_XADDR(x) (((x) >> S_XADDR) & M_XADDR)
22076 #define A_XGMAC_PORT_HSS_RXA_CFG_MODE 0x1900
22079 #define V_BW810(x) ((x) << S_BW810)
22080 #define F_BW810 V_BW810(1U)
22083 #define V_AUXCLK(x) ((x) << S_AUXCLK)
22084 #define F_AUXCLK V_AUXCLK(1U)
22087 #define M_DMSEL 0x7U
22088 #define V_DMSEL(x) ((x) << S_DMSEL)
22089 #define G_DMSEL(x) (((x) >> S_DMSEL) & M_DMSEL)
22091 #define A_XGMAC_PORT_HSS_RXA_TEST_CTRL 0x1904
22093 #define S_RCLKEN 15
22094 #define V_RCLKEN(x) ((x) << S_RCLKEN)
22095 #define F_RCLKEN V_RCLKEN(1U)
22098 #define M_RRATE 0x3U
22099 #define V_RRATE(x) ((x) << S_RRATE)
22100 #define G_RRATE(x) (((x) >> S_RRATE) & M_RRATE)
22102 #define S_LBFRCERROR 10
22103 #define V_LBFRCERROR(x) ((x) << S_LBFRCERROR)
22104 #define F_LBFRCERROR V_LBFRCERROR(1U)
22106 #define S_LBERROR 9
22107 #define V_LBERROR(x) ((x) << S_LBERROR)
22108 #define F_LBERROR V_LBERROR(1U)
22111 #define V_LBSYNC(x) ((x) << S_LBSYNC)
22112 #define F_LBSYNC V_LBSYNC(1U)
22114 #define S_FDWRAPCLK 7
22115 #define V_FDWRAPCLK(x) ((x) << S_FDWRAPCLK)
22116 #define F_FDWRAPCLK V_FDWRAPCLK(1U)
22119 #define V_FDWRAP(x) ((x) << S_FDWRAP)
22120 #define F_FDWRAP V_FDWRAP(1U)
22123 #define V_PRST(x) ((x) << S_PRST)
22124 #define F_PRST V_PRST(1U)
22127 #define V_PCHKEN(x) ((x) << S_PCHKEN)
22128 #define F_PCHKEN V_PCHKEN(1U)
22130 #define S_PRBSSEL 0
22131 #define M_PRBSSEL 0x7U
22132 #define V_PRBSSEL(x) ((x) << S_PRBSSEL)
22133 #define G_PRBSSEL(x) (((x) >> S_PRBSSEL) & M_PRBSSEL)
22135 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL 0x1908
22137 #define S_FTHROT 12
22138 #define M_FTHROT 0xfU
22139 #define V_FTHROT(x) ((x) << S_FTHROT)
22140 #define G_FTHROT(x) (((x) >> S_FTHROT) & M_FTHROT)
22142 #define S_RTHROT 11
22143 #define V_RTHROT(x) ((x) << S_RTHROT)
22144 #define F_RTHROT V_RTHROT(1U)
22146 #define S_FILTCTL 7
22147 #define M_FILTCTL 0xfU
22148 #define V_FILTCTL(x) ((x) << S_FILTCTL)
22149 #define G_FILTCTL(x) (((x) >> S_FILTCTL) & M_FILTCTL)
22152 #define M_RSRVO 0x3U
22153 #define V_RSRVO(x) ((x) << S_RSRVO)
22154 #define G_RSRVO(x) (((x) >> S_RSRVO) & M_RSRVO)
22157 #define V_EXTEL(x) ((x) << S_EXTEL)
22158 #define F_EXTEL V_EXTEL(1U)
22160 #define S_RSTONSTUCK 3
22161 #define V_RSTONSTUCK(x) ((x) << S_RSTONSTUCK)
22162 #define F_RSTONSTUCK V_RSTONSTUCK(1U)
22164 #define S_FREEZEFW 2
22165 #define V_FREEZEFW(x) ((x) << S_FREEZEFW)
22166 #define F_FREEZEFW V_FREEZEFW(1U)
22168 #define S_RESETFW 1
22169 #define V_RESETFW(x) ((x) << S_RESETFW)
22170 #define F_RESETFW V_RESETFW(1U)
22172 #define S_SSCENABLE 0
22173 #define V_SSCENABLE(x) ((x) << S_SSCENABLE)
22174 #define F_SSCENABLE V_SSCENABLE(1U)
22176 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL 0x190c
22179 #define V_RSNP(x) ((x) << S_RSNP)
22180 #define F_RSNP V_RSNP(1U)
22183 #define V_TSOEN(x) ((x) << S_TSOEN)
22184 #define F_TSOEN V_TSOEN(1U)
22187 #define V_OFFEN(x) ((x) << S_OFFEN)
22188 #define F_OFFEN V_OFFEN(1U)
22191 #define M_TMSCAL 0x3U
22192 #define V_TMSCAL(x) ((x) << S_TMSCAL)
22193 #define G_TMSCAL(x) (((x) >> S_TMSCAL) & M_TMSCAL)
22196 #define V_APADJ(x) ((x) << S_APADJ)
22197 #define F_APADJ V_APADJ(1U)
22200 #define V_RSEL(x) ((x) << S_RSEL)
22201 #define F_RSEL V_RSEL(1U)
22204 #define M_PHOFFS 0x1fU
22205 #define V_PHOFFS(x) ((x) << S_PHOFFS)
22206 #define G_PHOFFS(x) (((x) >> S_PHOFFS) & M_PHOFFS)
22208 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1 0x1910
22211 #define M_ROT0A 0x3fU
22212 #define V_ROT0A(x) ((x) << S_ROT0A)
22213 #define G_ROT0A(x) (((x) >> S_ROT0A) & M_ROT0A)
22215 #define S_RTSEL_SNAPSHOT 0
22216 #define M_RTSEL_SNAPSHOT 0x3fU
22217 #define V_RTSEL_SNAPSHOT(x) ((x) << S_RTSEL_SNAPSHOT)
22218 #define G_RTSEL_SNAPSHOT(x) (((x) >> S_RTSEL_SNAPSHOT) & M_RTSEL_SNAPSHOT)
22220 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2 0x1914
22223 #define M_ROT90 0x3fU
22224 #define V_ROT90(x) ((x) << S_ROT90)
22225 #define G_ROT90(x) (((x) >> S_ROT90) & M_ROT90)
22227 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET 0x1918
22229 #define S_RCALER 15
22230 #define V_RCALER(x) ((x) << S_RCALER)
22231 #define F_RCALER V_RCALER(1U)
22233 #define S_RAOOFF 10
22234 #define M_RAOOFF 0x1fU
22235 #define V_RAOOFF(x) ((x) << S_RAOOFF)
22236 #define G_RAOOFF(x) (((x) >> S_RAOOFF) & M_RAOOFF)
22239 #define M_RAEOFF 0x1fU
22240 #define V_RAEOFF(x) ((x) << S_RAEOFF)
22241 #define G_RAEOFF(x) (((x) >> S_RAEOFF) & M_RAEOFF)
22244 #define M_RDOFF 0x1fU
22245 #define V_RDOFF(x) ((x) << S_RDOFF)
22246 #define G_RDOFF(x) (((x) >> S_RDOFF) & M_RDOFF)
22248 #define A_XGMAC_PORT_HSS_RXA_SIGDET_CTRL 0x191c
22250 #define S_SIGNSD 13
22251 #define M_SIGNSD 0x3U
22252 #define V_SIGNSD(x) ((x) << S_SIGNSD)
22253 #define G_SIGNSD(x) (((x) >> S_SIGNSD) & M_SIGNSD)
22256 #define M_DACSD 0x1fU
22257 #define V_DACSD(x) ((x) << S_DACSD)
22258 #define G_DACSD(x) (((x) >> S_DACSD) & M_DACSD)
22261 #define V_SDPDN(x) ((x) << S_SDPDN)
22262 #define F_SDPDN V_SDPDN(1U)
22265 #define V_SIGDET(x) ((x) << S_SIGDET)
22266 #define F_SIGDET V_SIGDET(1U)
22269 #define M_SDLVL 0x1fU
22270 #define V_SDLVL(x) ((x) << S_SDLVL)
22271 #define G_SDLVL(x) (((x) >> S_SDLVL) & M_SDLVL)
22273 #define A_XGMAC_PORT_HSS_RXA_DFE_CTRL 0x1920
22275 #define S_REQCMP 15
22276 #define V_REQCMP(x) ((x) << S_REQCMP)
22277 #define F_REQCMP V_REQCMP(1U)
22279 #define S_DFEREQ 14
22280 #define V_DFEREQ(x) ((x) << S_DFEREQ)
22281 #define F_DFEREQ V_DFEREQ(1U)
22284 #define V_SPCEN(x) ((x) << S_SPCEN)
22285 #define F_SPCEN V_SPCEN(1U)
22287 #define S_GATEEN 12
22288 #define V_GATEEN(x) ((x) << S_GATEEN)
22289 #define F_GATEEN V_GATEEN(1U)
22292 #define M_SPIFMT 0x7U
22293 #define V_SPIFMT(x) ((x) << S_SPIFMT)
22294 #define G_SPIFMT(x) (((x) >> S_SPIFMT) & M_SPIFMT)
22297 #define M_DFEPWR 0x7U
22298 #define V_DFEPWR(x) ((x) << S_DFEPWR)
22299 #define G_DFEPWR(x) (((x) >> S_DFEPWR) & M_DFEPWR)
22302 #define V_STNDBY(x) ((x) << S_STNDBY)
22303 #define F_STNDBY V_STNDBY(1U)
22306 #define V_FRCH(x) ((x) << S_FRCH)
22307 #define F_FRCH V_FRCH(1U)
22310 #define V_NONRND(x) ((x) << S_NONRND)
22311 #define F_NONRND V_NONRND(1U)
22314 #define V_NONRNF(x) ((x) << S_NONRNF)
22315 #define F_NONRNF V_NONRNF(1U)
22318 #define V_FSTLCK(x) ((x) << S_FSTLCK)
22319 #define F_FSTLCK V_FSTLCK(1U)
22322 #define V_DFERST(x) ((x) << S_DFERST)
22323 #define F_DFERST V_DFERST(1U)
22325 #define A_XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE 0x1924
22328 #define M_ESAMP 0xffU
22329 #define V_ESAMP(x) ((x) << S_ESAMP)
22330 #define G_ESAMP(x) (((x) >> S_ESAMP) & M_ESAMP)
22333 #define M_DSAMP 0xffU
22334 #define V_DSAMP(x) ((x) << S_DSAMP)
22335 #define G_DSAMP(x) (((x) >> S_DSAMP) & M_DSAMP)
22337 #define A_XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE 0x1928
22340 #define M_SMODE 0xfU
22341 #define V_SMODE(x) ((x) << S_SMODE)
22342 #define G_SMODE(x) (((x) >> S_SMODE) & M_SMODE)
22345 #define V_ADCORR(x) ((x) << S_ADCORR)
22346 #define F_ADCORR V_ADCORR(1U)
22348 #define S_TRAINEN 6
22349 #define V_TRAINEN(x) ((x) << S_TRAINEN)
22350 #define F_TRAINEN V_TRAINEN(1U)
22353 #define M_ASAMPQ 0x7U
22354 #define V_ASAMPQ(x) ((x) << S_ASAMPQ)
22355 #define G_ASAMPQ(x) (((x) >> S_ASAMPQ) & M_ASAMPQ)
22358 #define M_ASAMP 0x7U
22359 #define V_ASAMP(x) ((x) << S_ASAMP)
22360 #define G_ASAMP(x) (((x) >> S_ASAMP) & M_ASAMP)
22362 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL1 0x192c
22365 #define M_POLE 0x3U
22366 #define V_POLE(x) ((x) << S_POLE)
22367 #define G_POLE(x) (((x) >> S_POLE) & M_POLE)
22370 #define M_PEAK 0x7U
22371 #define V_PEAK(x) ((x) << S_PEAK)
22372 #define G_PEAK(x) (((x) >> S_PEAK) & M_PEAK)
22375 #define M_VOFFSN 0x3U
22376 #define V_VOFFSN(x) ((x) << S_VOFFSN)
22377 #define G_VOFFSN(x) (((x) >> S_VOFFSN) & M_VOFFSN)
22380 #define M_VOFFA 0x3fU
22381 #define V_VOFFA(x) ((x) << S_VOFFA)
22382 #define G_VOFFA(x) (((x) >> S_VOFFA) & M_VOFFA)
22384 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL2 0x1930
22386 #define S_SHORTV 10
22387 #define V_SHORTV(x) ((x) << S_SHORTV)
22388 #define F_SHORTV V_SHORTV(1U)
22391 #define M_VGAIN 0xfU
22392 #define V_VGAIN(x) ((x) << S_VGAIN)
22393 #define G_VGAIN(x) (((x) >> S_VGAIN) & M_VGAIN)
22395 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL3 0x1934
22398 #define V_HBND1(x) ((x) << S_HBND1)
22399 #define F_HBND1 V_HBND1(1U)
22402 #define V_HBND0(x) ((x) << S_HBND0)
22403 #define F_HBND0 V_HBND0(1U)
22406 #define V_VLCKD(x) ((x) << S_VLCKD)
22407 #define F_VLCKD V_VLCKD(1U)
22410 #define V_VLCKDF(x) ((x) << S_VLCKDF)
22411 #define F_VLCKDF V_VLCKDF(1U)
22414 #define M_AMAXT 0x7fU
22415 #define V_AMAXT(x) ((x) << S_AMAXT)
22416 #define G_AMAXT(x) (((x) >> S_AMAXT) & M_AMAXT)
22418 #define A_XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET 0x1938
22421 #define M_D01SN 0x3U
22422 #define V_D01SN(x) ((x) << S_D01SN)
22423 #define G_D01SN(x) (((x) >> S_D01SN) & M_D01SN)
22426 #define M_D01AMP 0x1fU
22427 #define V_D01AMP(x) ((x) << S_D01AMP)
22428 #define G_D01AMP(x) (((x) >> S_D01AMP) & M_D01AMP)
22431 #define M_D00SN 0x3U
22432 #define V_D00SN(x) ((x) << S_D00SN)
22433 #define G_D00SN(x) (((x) >> S_D00SN) & M_D00SN)
22436 #define M_D00AMP 0x1fU
22437 #define V_D00AMP(x) ((x) << S_D00AMP)
22438 #define G_D00AMP(x) (((x) >> S_D00AMP) & M_D00AMP)
22440 #define A_XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET 0x193c
22443 #define M_D11SN 0x3U
22444 #define V_D11SN(x) ((x) << S_D11SN)
22445 #define G_D11SN(x) (((x) >> S_D11SN) & M_D11SN)
22448 #define M_D11AMP 0x1fU
22449 #define V_D11AMP(x) ((x) << S_D11AMP)
22450 #define G_D11AMP(x) (((x) >> S_D11AMP) & M_D11AMP)
22453 #define M_D10SN 0x3U
22454 #define V_D10SN(x) ((x) << S_D10SN)
22455 #define G_D10SN(x) (((x) >> S_D10SN) & M_D10SN)
22458 #define M_D10AMP 0x1fU
22459 #define V_D10AMP(x) ((x) << S_D10AMP)
22460 #define G_D10AMP(x) (((x) >> S_D10AMP) & M_D10AMP)
22462 #define A_XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET 0x1940
22465 #define M_E1SN 0x3U
22466 #define V_E1SN(x) ((x) << S_E1SN)
22467 #define G_E1SN(x) (((x) >> S_E1SN) & M_E1SN)
22470 #define M_E1AMP 0x1fU
22471 #define V_E1AMP(x) ((x) << S_E1AMP)
22472 #define G_E1AMP(x) (((x) >> S_E1AMP) & M_E1AMP)
22475 #define M_E0SN 0x3U
22476 #define V_E0SN(x) ((x) << S_E0SN)
22477 #define G_E0SN(x) (((x) >> S_E0SN) & M_E0SN)
22480 #define M_E0AMP 0x1fU
22481 #define V_E0AMP(x) ((x) << S_E0AMP)
22482 #define G_E0AMP(x) (((x) >> S_E0AMP) & M_E0AMP)
22484 #define A_XGMAC_PORT_HSS_RXA_DACA_OFFSET 0x1944
22487 #define M_AOFFO 0x3fU
22488 #define V_AOFFO(x) ((x) << S_AOFFO)
22489 #define G_AOFFO(x) (((x) >> S_AOFFO) & M_AOFFO)
22492 #define M_AOFFE 0x3fU
22493 #define V_AOFFE(x) ((x) << S_AOFFE)
22494 #define G_AOFFE(x) (((x) >> S_AOFFE) & M_AOFFE)
22496 #define A_XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET 0x1948
22499 #define M_DACAN 0xffU
22500 #define V_DACAN(x) ((x) << S_DACAN)
22501 #define G_DACAN(x) (((x) >> S_DACAN) & M_DACAN)
22504 #define M_DACAP 0xffU
22505 #define V_DACAP(x) ((x) << S_DACAP)
22506 #define G_DACAP(x) (((x) >> S_DACAP) & M_DACAP)
22508 #define A_XGMAC_PORT_HSS_RXA_DACA_MIN 0x194c
22511 #define M_DACAZ 0xffU
22512 #define V_DACAZ(x) ((x) << S_DACAZ)
22513 #define G_DACAZ(x) (((x) >> S_DACAZ) & M_DACAZ)
22516 #define M_DACAM 0xffU
22517 #define V_DACAM(x) ((x) << S_DACAM)
22518 #define G_DACAM(x) (((x) >> S_DACAM) & M_DACAM)
22520 #define A_XGMAC_PORT_HSS_RXA_ADAC_CTRL 0x1950
22523 #define M_ADSN 0x3U
22524 #define V_ADSN(x) ((x) << S_ADSN)
22525 #define G_ADSN(x) (((x) >> S_ADSN) & M_ADSN)
22528 #define M_ADMAG 0x7fU
22529 #define V_ADMAG(x) ((x) << S_ADMAG)
22530 #define G_ADMAG(x) (((x) >> S_ADMAG) & M_ADMAG)
22532 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL 0x1954
22535 #define V_BLKAZ(x) ((x) << S_BLKAZ)
22536 #define F_BLKAZ V_BLKAZ(1U)
22539 #define M_WIDTH 0x1fU
22540 #define V_WIDTH(x) ((x) << S_WIDTH)
22541 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
22543 #define S_MINWIDTH 5
22544 #define M_MINWIDTH 0x1fU
22545 #define V_MINWIDTH(x) ((x) << S_MINWIDTH)
22546 #define G_MINWIDTH(x) (((x) >> S_MINWIDTH) & M_MINWIDTH)
22549 #define M_MINAMP 0x1fU
22550 #define V_MINAMP(x) ((x) << S_MINAMP)
22551 #define G_MINAMP(x) (((x) >> S_MINAMP) & M_MINAMP)
22553 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS 0x1958
22555 #define S_EMBRDY 10
22556 #define V_EMBRDY(x) ((x) << S_EMBRDY)
22557 #define F_EMBRDY V_EMBRDY(1U)
22560 #define V_EMBUMP(x) ((x) << S_EMBUMP)
22561 #define F_EMBUMP V_EMBUMP(1U)
22564 #define M_EMMD 0x3U
22565 #define V_EMMD(x) ((x) << S_EMMD)
22566 #define G_EMMD(x) (((x) >> S_EMMD) & M_EMMD)
22569 #define V_EMPAT(x) ((x) << S_EMPAT)
22570 #define F_EMPAT V_EMPAT(1U)
22573 #define V_EMEN(x) ((x) << S_EMEN)
22574 #define F_EMEN V_EMEN(1U)
22576 #define A_XGMAC_PORT_HSS_RXA_DFE_H1 0x195c
22579 #define M_H1OSN 0x3U
22580 #define V_H1OSN(x) ((x) << S_H1OSN)
22581 #define G_H1OSN(x) (((x) >> S_H1OSN) & M_H1OSN)
22584 #define M_H1OMAG 0x3fU
22585 #define V_H1OMAG(x) ((x) << S_H1OMAG)
22586 #define G_H1OMAG(x) (((x) >> S_H1OMAG) & M_H1OMAG)
22589 #define M_H1ESN 0x3U
22590 #define V_H1ESN(x) ((x) << S_H1ESN)
22591 #define G_H1ESN(x) (((x) >> S_H1ESN) & M_H1ESN)
22594 #define M_H1EMAG 0x3fU
22595 #define V_H1EMAG(x) ((x) << S_H1EMAG)
22596 #define G_H1EMAG(x) (((x) >> S_H1EMAG) & M_H1EMAG)
22598 #define A_XGMAC_PORT_HSS_RXA_DFE_H2 0x1960
22601 #define M_H2OSN 0x3U
22602 #define V_H2OSN(x) ((x) << S_H2OSN)
22603 #define G_H2OSN(x) (((x) >> S_H2OSN) & M_H2OSN)
22606 #define M_H2OMAG 0x1fU
22607 #define V_H2OMAG(x) ((x) << S_H2OMAG)
22608 #define G_H2OMAG(x) (((x) >> S_H2OMAG) & M_H2OMAG)
22611 #define M_H2ESN 0x3U
22612 #define V_H2ESN(x) ((x) << S_H2ESN)
22613 #define G_H2ESN(x) (((x) >> S_H2ESN) & M_H2ESN)
22616 #define M_H2EMAG 0x1fU
22617 #define V_H2EMAG(x) ((x) << S_H2EMAG)
22618 #define G_H2EMAG(x) (((x) >> S_H2EMAG) & M_H2EMAG)
22620 #define A_XGMAC_PORT_HSS_RXA_DFE_H3 0x1964
22623 #define M_H3OSN 0x3U
22624 #define V_H3OSN(x) ((x) << S_H3OSN)
22625 #define G_H3OSN(x) (((x) >> S_H3OSN) & M_H3OSN)
22628 #define M_H3OMAG 0xfU
22629 #define V_H3OMAG(x) ((x) << S_H3OMAG)
22630 #define G_H3OMAG(x) (((x) >> S_H3OMAG) & M_H3OMAG)
22633 #define M_H3ESN 0x3U
22634 #define V_H3ESN(x) ((x) << S_H3ESN)
22635 #define G_H3ESN(x) (((x) >> S_H3ESN) & M_H3ESN)
22638 #define M_H3EMAG 0xfU
22639 #define V_H3EMAG(x) ((x) << S_H3EMAG)
22640 #define G_H3EMAG(x) (((x) >> S_H3EMAG) & M_H3EMAG)
22642 #define A_XGMAC_PORT_HSS_RXA_DFE_H4 0x1968
22645 #define M_H4OSN 0x3U
22646 #define V_H4OSN(x) ((x) << S_H4OSN)
22647 #define G_H4OSN(x) (((x) >> S_H4OSN) & M_H4OSN)
22650 #define M_H4OMAG 0xfU
22651 #define V_H4OMAG(x) ((x) << S_H4OMAG)
22652 #define G_H4OMAG(x) (((x) >> S_H4OMAG) & M_H4OMAG)
22655 #define M_H4ESN 0x3U
22656 #define V_H4ESN(x) ((x) << S_H4ESN)
22657 #define G_H4ESN(x) (((x) >> S_H4ESN) & M_H4ESN)
22660 #define M_H4EMAG 0xfU
22661 #define V_H4EMAG(x) ((x) << S_H4EMAG)
22662 #define G_H4EMAG(x) (((x) >> S_H4EMAG) & M_H4EMAG)
22664 #define A_XGMAC_PORT_HSS_RXA_DFE_H5 0x196c
22667 #define M_H5OSN 0x3U
22668 #define V_H5OSN(x) ((x) << S_H5OSN)
22669 #define G_H5OSN(x) (((x) >> S_H5OSN) & M_H5OSN)
22672 #define M_H5OMAG 0xfU
22673 #define V_H5OMAG(x) ((x) << S_H5OMAG)
22674 #define G_H5OMAG(x) (((x) >> S_H5OMAG) & M_H5OMAG)
22677 #define M_H5ESN 0x3U
22678 #define V_H5ESN(x) ((x) << S_H5ESN)
22679 #define G_H5ESN(x) (((x) >> S_H5ESN) & M_H5ESN)
22682 #define M_H5EMAG 0xfU
22683 #define V_H5EMAG(x) ((x) << S_H5EMAG)
22684 #define G_H5EMAG(x) (((x) >> S_H5EMAG) & M_H5EMAG)
22686 #define A_XGMAC_PORT_HSS_RXA_DAC_DPC 0x1970
22688 #define S_DPCCVG 13
22689 #define V_DPCCVG(x) ((x) << S_DPCCVG)
22690 #define F_DPCCVG V_DPCCVG(1U)
22692 #define S_DACCVG 12
22693 #define V_DACCVG(x) ((x) << S_DACCVG)
22694 #define F_DACCVG V_DACCVG(1U)
22697 #define M_DPCTGT 0x7U
22698 #define V_DPCTGT(x) ((x) << S_DPCTGT)
22699 #define G_DPCTGT(x) (((x) >> S_DPCTGT) & M_DPCTGT)
22702 #define V_BLKH1T(x) ((x) << S_BLKH1T)
22703 #define F_BLKH1T V_BLKH1T(1U)
22706 #define V_BLKOAE(x) ((x) << S_BLKOAE)
22707 #define F_BLKOAE V_BLKOAE(1U)
22710 #define M_H1TGT 0x7U
22711 #define V_H1TGT(x) ((x) << S_H1TGT)
22712 #define G_H1TGT(x) (((x) >> S_H1TGT) & M_H1TGT)
22716 #define V_OAE(x) ((x) << S_OAE)
22717 #define G_OAE(x) (((x) >> S_OAE) & M_OAE)
22719 #define A_XGMAC_PORT_HSS_RXA_DDC 0x1974
22722 #define M_OLS 0x1fU
22723 #define V_OLS(x) ((x) << S_OLS)
22724 #define G_OLS(x) (((x) >> S_OLS) & M_OLS)
22727 #define M_OES 0x1fU
22728 #define V_OES(x) ((x) << S_OES)
22729 #define G_OES(x) (((x) >> S_OES) & M_OES)
22731 #define S_BLKODEC 5
22732 #define V_BLKODEC(x) ((x) << S_BLKODEC)
22733 #define F_BLKODEC V_BLKODEC(1U)
22736 #define M_ODEC 0x1fU
22737 #define V_ODEC(x) ((x) << S_ODEC)
22738 #define G_ODEC(x) (((x) >> S_ODEC) & M_ODEC)
22740 #define A_XGMAC_PORT_HSS_RXA_INTERNAL_STATUS 0x1978
22743 #define V_BER6(x) ((x) << S_BER6)
22744 #define F_BER6 V_BER6(1U)
22746 #define S_BER6VAL 14
22747 #define V_BER6VAL(x) ((x) << S_BER6VAL)
22748 #define F_BER6VAL V_BER6VAL(1U)
22750 #define S_BER3VAL 13
22751 #define V_BER3VAL(x) ((x) << S_BER3VAL)
22752 #define F_BER3VAL V_BER3VAL(1U)
22755 #define V_DPCCMP(x) ((x) << S_DPCCMP)
22756 #define F_DPCCMP V_DPCCMP(1U)
22759 #define V_DACCMP(x) ((x) << S_DACCMP)
22760 #define F_DACCMP V_DACCMP(1U)
22763 #define V_DDCCMP(x) ((x) << S_DDCCMP)
22764 #define F_DDCCMP V_DDCCMP(1U)
22766 #define S_AERRFLG 6
22767 #define V_AERRFLG(x) ((x) << S_AERRFLG)
22768 #define F_AERRFLG V_AERRFLG(1U)
22770 #define S_WERRFLG 5
22771 #define V_WERRFLG(x) ((x) << S_WERRFLG)
22772 #define F_WERRFLG V_WERRFLG(1U)
22775 #define V_TRCMP(x) ((x) << S_TRCMP)
22776 #define F_TRCMP V_TRCMP(1U)
22779 #define V_VLCKF(x) ((x) << S_VLCKF)
22780 #define F_VLCKF V_VLCKF(1U)
22783 #define V_ROCADJ(x) ((x) << S_ROCADJ)
22784 #define F_ROCADJ V_ROCADJ(1U)
22787 #define V_ROCCMP(x) ((x) << S_ROCCMP)
22788 #define F_ROCCMP V_ROCCMP(1U)
22791 #define V_OCCMP(x) ((x) << S_OCCMP)
22792 #define F_OCCMP V_OCCMP(1U)
22794 #define A_XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL 0x197c
22797 #define V_FDPC(x) ((x) << S_FDPC)
22798 #define F_FDPC V_FDPC(1U)
22801 #define V_FDAC(x) ((x) << S_FDAC)
22802 #define F_FDAC V_FDAC(1U)
22805 #define V_FDDC(x) ((x) << S_FDDC)
22806 #define F_FDDC V_FDDC(1U)
22809 #define V_FNRND(x) ((x) << S_FNRND)
22810 #define F_FNRND V_FNRND(1U)
22812 #define S_FVGAIN 11
22813 #define V_FVGAIN(x) ((x) << S_FVGAIN)
22814 #define F_FVGAIN V_FVGAIN(1U)
22817 #define V_FVOFF(x) ((x) << S_FVOFF)
22818 #define F_FVOFF V_FVOFF(1U)
22821 #define V_FSDET(x) ((x) << S_FSDET)
22822 #define F_FSDET V_FSDET(1U)
22825 #define V_FBER6(x) ((x) << S_FBER6)
22826 #define F_FBER6 V_FBER6(1U)
22829 #define V_FROTO(x) ((x) << S_FROTO)
22830 #define F_FROTO V_FROTO(1U)
22833 #define V_FH4H5(x) ((x) << S_FH4H5)
22834 #define F_FH4H5 V_FH4H5(1U)
22837 #define V_FH2H3(x) ((x) << S_FH2H3)
22838 #define F_FH2H3 V_FH2H3(1U)
22841 #define V_FH1(x) ((x) << S_FH1)
22842 #define F_FH1 V_FH1(1U)
22845 #define V_FH1SN(x) ((x) << S_FH1SN)
22846 #define F_FH1SN V_FH1SN(1U)
22849 #define V_FNRDF(x) ((x) << S_FNRDF)
22850 #define F_FNRDF V_FNRDF(1U)
22853 #define V_FADAC(x) ((x) << S_FADAC)
22854 #define F_FADAC V_FADAC(1U)
22856 #define A_XGMAC_PORT_HSS_RXB_CFG_MODE 0x1980
22857 #define A_XGMAC_PORT_HSS_RXB_TEST_CTRL 0x1984
22858 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL 0x1988
22859 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL 0x198c
22860 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1 0x1990
22861 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2 0x1994
22862 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET 0x1998
22863 #define A_XGMAC_PORT_HSS_RXB_SIGDET_CTRL 0x199c
22864 #define A_XGMAC_PORT_HSS_RXB_DFE_CTRL 0x19a0
22865 #define A_XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE 0x19a4
22866 #define A_XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE 0x19a8
22867 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL1 0x19ac
22868 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL2 0x19b0
22869 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL3 0x19b4
22870 #define A_XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET 0x19b8
22871 #define A_XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET 0x19bc
22872 #define A_XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET 0x19c0
22873 #define A_XGMAC_PORT_HSS_RXB_DACA_OFFSET 0x19c4
22874 #define A_XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET 0x19c8
22875 #define A_XGMAC_PORT_HSS_RXB_DACA_MIN 0x19cc
22876 #define A_XGMAC_PORT_HSS_RXB_ADAC_CTRL 0x19d0
22877 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL 0x19d4
22878 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS 0x19d8
22879 #define A_XGMAC_PORT_HSS_RXB_DFE_H1 0x19dc
22880 #define A_XGMAC_PORT_HSS_RXB_DFE_H2 0x19e0
22881 #define A_XGMAC_PORT_HSS_RXB_DFE_H3 0x19e4
22882 #define A_XGMAC_PORT_HSS_RXB_DFE_H4 0x19e8
22883 #define A_XGMAC_PORT_HSS_RXB_DFE_H5 0x19ec
22884 #define A_XGMAC_PORT_HSS_RXB_DAC_DPC 0x19f0
22885 #define A_XGMAC_PORT_HSS_RXB_DDC 0x19f4
22886 #define A_XGMAC_PORT_HSS_RXB_INTERNAL_STATUS 0x19f8
22887 #define A_XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL 0x19fc
22888 #define A_XGMAC_PORT_HSS_TXC_MODE_CFG 0x1a00
22889 #define A_XGMAC_PORT_HSS_TXC_TEST_CTRL 0x1a04
22890 #define A_XGMAC_PORT_HSS_TXC_COEFF_CTRL 0x1a08
22891 #define A_XGMAC_PORT_HSS_TXC_DRIVER_MODE 0x1a0c
22892 #define A_XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL 0x1a10
22893 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER 0x1a14
22894 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER 0x1a18
22895 #define A_XGMAC_PORT_HSS_TXC_TAP0_COEFF 0x1a20
22896 #define A_XGMAC_PORT_HSS_TXC_TAP1_COEFF 0x1a24
22897 #define A_XGMAC_PORT_HSS_TXC_TAP2_COEFF 0x1a28
22898 #define A_XGMAC_PORT_HSS_TXC_PWR 0x1a30
22899 #define A_XGMAC_PORT_HSS_TXC_POLARITY 0x1a34
22900 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_CMD 0x1a38
22901 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS 0x1a3c
22902 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR 0x1a40
22903 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR 0x1a44
22904 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR 0x1a48
22905 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC_OVR 0x1a50
22906 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC 0x1a54
22907 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP 0x1a60
22908 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP 0x1a64
22909 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP 0x1a68
22910 #define A_XGMAC_PORT_HSS_TXC_SEG_DIS_APP 0x1a70
22911 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA 0x1a78
22912 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR 0x1a7c
22913 #define A_XGMAC_PORT_HSS_TXD_MODE_CFG 0x1a80
22914 #define A_XGMAC_PORT_HSS_TXD_TEST_CTRL 0x1a84
22915 #define A_XGMAC_PORT_HSS_TXD_COEFF_CTRL 0x1a88
22916 #define A_XGMAC_PORT_HSS_TXD_DRIVER_MODE 0x1a8c
22917 #define A_XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL 0x1a90
22918 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER 0x1a94
22919 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER 0x1a98
22920 #define A_XGMAC_PORT_HSS_TXD_TAP0_COEFF 0x1aa0
22921 #define A_XGMAC_PORT_HSS_TXD_TAP1_COEFF 0x1aa4
22922 #define A_XGMAC_PORT_HSS_TXD_TAP2_COEFF 0x1aa8
22923 #define A_XGMAC_PORT_HSS_TXD_PWR 0x1ab0
22924 #define A_XGMAC_PORT_HSS_TXD_POLARITY 0x1ab4
22925 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_CMD 0x1ab8
22926 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS 0x1abc
22927 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR 0x1ac0
22928 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR 0x1ac4
22929 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR 0x1ac8
22930 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC_OVR 0x1ad0
22931 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC 0x1ad4
22932 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP 0x1ae0
22933 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP 0x1ae4
22934 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP 0x1ae8
22935 #define A_XGMAC_PORT_HSS_TXD_SEG_DIS_APP 0x1af0
22936 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA 0x1af8
22937 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR 0x1afc
22938 #define A_XGMAC_PORT_HSS_RXC_CFG_MODE 0x1b00
22939 #define A_XGMAC_PORT_HSS_RXC_TEST_CTRL 0x1b04
22940 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL 0x1b08
22941 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL 0x1b0c
22942 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1 0x1b10
22943 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2 0x1b14
22944 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET 0x1b18
22945 #define A_XGMAC_PORT_HSS_RXC_SIGDET_CTRL 0x1b1c
22946 #define A_XGMAC_PORT_HSS_RXC_DFE_CTRL 0x1b20
22947 #define A_XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE 0x1b24
22948 #define A_XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE 0x1b28
22949 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL1 0x1b2c
22950 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL2 0x1b30
22951 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL3 0x1b34
22952 #define A_XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET 0x1b38
22953 #define A_XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET 0x1b3c
22954 #define A_XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET 0x1b40
22955 #define A_XGMAC_PORT_HSS_RXC_DACA_OFFSET 0x1b44
22956 #define A_XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET 0x1b48
22957 #define A_XGMAC_PORT_HSS_RXC_DACA_MIN 0x1b4c
22958 #define A_XGMAC_PORT_HSS_RXC_ADAC_CTRL 0x1b50
22959 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL 0x1b54
22960 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS 0x1b58
22961 #define A_XGMAC_PORT_HSS_RXC_DFE_H1 0x1b5c
22962 #define A_XGMAC_PORT_HSS_RXC_DFE_H2 0x1b60
22963 #define A_XGMAC_PORT_HSS_RXC_DFE_H3 0x1b64
22964 #define A_XGMAC_PORT_HSS_RXC_DFE_H4 0x1b68
22965 #define A_XGMAC_PORT_HSS_RXC_DFE_H5 0x1b6c
22966 #define A_XGMAC_PORT_HSS_RXC_DAC_DPC 0x1b70
22967 #define A_XGMAC_PORT_HSS_RXC_DDC 0x1b74
22968 #define A_XGMAC_PORT_HSS_RXC_INTERNAL_STATUS 0x1b78
22969 #define A_XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL 0x1b7c
22970 #define A_XGMAC_PORT_HSS_RXD_CFG_MODE 0x1b80
22971 #define A_XGMAC_PORT_HSS_RXD_TEST_CTRL 0x1b84
22972 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL 0x1b88
22973 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL 0x1b8c
22974 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1 0x1b90
22975 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2 0x1b94
22976 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET 0x1b98
22977 #define A_XGMAC_PORT_HSS_RXD_SIGDET_CTRL 0x1b9c
22978 #define A_XGMAC_PORT_HSS_RXD_DFE_CTRL 0x1ba0
22979 #define A_XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE 0x1ba4
22980 #define A_XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE 0x1ba8
22981 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL1 0x1bac
22982 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL2 0x1bb0
22983 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL3 0x1bb4
22984 #define A_XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET 0x1bb8
22985 #define A_XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET 0x1bbc
22986 #define A_XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET 0x1bc0
22987 #define A_XGMAC_PORT_HSS_RXD_DACA_OFFSET 0x1bc4
22988 #define A_XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET 0x1bc8
22989 #define A_XGMAC_PORT_HSS_RXD_DACA_MIN 0x1bcc
22990 #define A_XGMAC_PORT_HSS_RXD_ADAC_CTRL 0x1bd0
22991 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL 0x1bd4
22992 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS 0x1bd8
22993 #define A_XGMAC_PORT_HSS_RXD_DFE_H1 0x1bdc
22994 #define A_XGMAC_PORT_HSS_RXD_DFE_H2 0x1be0
22995 #define A_XGMAC_PORT_HSS_RXD_DFE_H3 0x1be4
22996 #define A_XGMAC_PORT_HSS_RXD_DFE_H4 0x1be8
22997 #define A_XGMAC_PORT_HSS_RXD_DFE_H5 0x1bec
22998 #define A_XGMAC_PORT_HSS_RXD_DAC_DPC 0x1bf0
22999 #define A_XGMAC_PORT_HSS_RXD_DDC 0x1bf4
23000 #define A_XGMAC_PORT_HSS_RXD_INTERNAL_STATUS 0x1bf8
23001 #define A_XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL 0x1bfc
23002 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0 0x1c00
23005 #define M_BSELO 0xfU
23006 #define V_BSELO(x) ((x) << S_BSELO)
23007 #define G_BSELO(x) (((x) >> S_BSELO) & M_BSELO)
23009 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1 0x1c04
23012 #define V_LDET(x) ((x) << S_LDET)
23013 #define F_LDET V_LDET(1U)
23016 #define V_CCERR(x) ((x) << S_CCERR)
23017 #define F_CCERR V_CCERR(1U)
23020 #define V_CCCMP(x) ((x) << S_CCCMP)
23021 #define F_CCCMP V_CCCMP(1U)
23023 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2 0x1c08
23026 #define M_BSELI 0xfU
23027 #define V_BSELI(x) ((x) << S_BSELI)
23028 #define G_BSELI(x) (((x) >> S_BSELI) & M_BSELI)
23030 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3 0x1c0c
23033 #define V_VISEL(x) ((x) << S_VISEL)
23034 #define F_VISEL V_VISEL(1U)
23037 #define V_FMIN(x) ((x) << S_FMIN)
23038 #define F_FMIN V_FMIN(1U)
23041 #define V_FMAX(x) ((x) << S_FMAX)
23042 #define F_FMAX V_FMAX(1U)
23045 #define V_CVHOLD(x) ((x) << S_CVHOLD)
23046 #define F_CVHOLD V_CVHOLD(1U)
23049 #define V_TCDIS(x) ((x) << S_TCDIS)
23050 #define F_TCDIS V_TCDIS(1U)
23052 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4 0x1c10
23055 #define V_CMETH(x) ((x) << S_CMETH)
23056 #define F_CMETH V_CMETH(1U)
23059 #define V_RECAL(x) ((x) << S_RECAL)
23060 #define F_RECAL V_RECAL(1U)
23063 #define V_CCLD(x) ((x) << S_CCLD)
23064 #define F_CCLD V_CCLD(1U)
23066 #define A_XGMAC_PORT_HSS_ANALOG_TEST_MUX 0x1c14
23069 #define M_ATST 0x1fU
23070 #define V_ATST(x) ((x) << S_ATST)
23071 #define G_ATST(x) (((x) >> S_ATST) & M_ATST)
23073 #define A_XGMAC_PORT_HSS_PORT_EN_0 0x1c18
23076 #define V_RXDEN(x) ((x) << S_RXDEN)
23077 #define F_RXDEN V_RXDEN(1U)
23080 #define V_RXCEN(x) ((x) << S_RXCEN)
23081 #define F_RXCEN V_RXCEN(1U)
23084 #define V_TXDEN(x) ((x) << S_TXDEN)
23085 #define F_TXDEN V_TXDEN(1U)
23088 #define V_TXCEN(x) ((x) << S_TXCEN)
23089 #define F_TXCEN V_TXCEN(1U)
23092 #define V_RXBEN(x) ((x) << S_RXBEN)
23093 #define F_RXBEN V_RXBEN(1U)
23096 #define V_RXAEN(x) ((x) << S_RXAEN)
23097 #define F_RXAEN V_RXAEN(1U)
23100 #define V_TXBEN(x) ((x) << S_TXBEN)
23101 #define F_TXBEN V_TXBEN(1U)
23104 #define V_TXAEN(x) ((x) << S_TXAEN)
23105 #define F_TXAEN V_TXAEN(1U)
23107 #define A_XGMAC_PORT_HSS_PORT_RESET_0 0x1c20
23110 #define V_RXDRST(x) ((x) << S_RXDRST)
23111 #define F_RXDRST V_RXDRST(1U)
23114 #define V_RXCRST(x) ((x) << S_RXCRST)
23115 #define F_RXCRST V_RXCRST(1U)
23118 #define V_TXDRST(x) ((x) << S_TXDRST)
23119 #define F_TXDRST V_TXDRST(1U)
23122 #define V_TXCRST(x) ((x) << S_TXCRST)
23123 #define F_TXCRST V_TXCRST(1U)
23126 #define V_RXBRST(x) ((x) << S_RXBRST)
23127 #define F_RXBRST V_RXBRST(1U)
23130 #define V_RXARST(x) ((x) << S_RXARST)
23131 #define F_RXARST V_RXARST(1U)
23134 #define V_TXBRST(x) ((x) << S_TXBRST)
23135 #define F_TXBRST V_TXBRST(1U)
23138 #define V_TXARST(x) ((x) << S_TXARST)
23139 #define F_TXARST V_TXARST(1U)
23141 #define A_XGMAC_PORT_HSS_CHARGE_PUMP_CTRL 0x1c28
23144 #define V_ENCPIS(x) ((x) << S_ENCPIS)
23145 #define F_ENCPIS V_ENCPIS(1U)
23148 #define M_CPISEL 0x3U
23149 #define V_CPISEL(x) ((x) << S_CPISEL)
23150 #define G_CPISEL(x) (((x) >> S_CPISEL) & M_CPISEL)
23152 #define A_XGMAC_PORT_HSS_BAND_GAP_CTRL 0x1c2c
23155 #define M_BGCTL 0x1fU
23156 #define V_BGCTL(x) ((x) << S_BGCTL)
23157 #define G_BGCTL(x) (((x) >> S_BGCTL) & M_BGCTL)
23159 #define A_XGMAC_PORT_HSS_LOFREQ_OVR 0x1c30
23162 #define V_LFREQ2(x) ((x) << S_LFREQ2)
23163 #define F_LFREQ2 V_LFREQ2(1U)
23166 #define V_LFREQ1(x) ((x) << S_LFREQ1)
23167 #define F_LFREQ1 V_LFREQ1(1U)
23170 #define V_LFREQO(x) ((x) << S_LFREQO)
23171 #define F_LFREQO V_LFREQO(1U)
23174 #define V_LFSEL(x) ((x) << S_LFSEL)
23175 #define F_LFSEL V_LFSEL(1U)
23177 #define A_XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL 0x1c38
23180 #define V_PFVAL(x) ((x) << S_PFVAL)
23181 #define F_PFVAL V_PFVAL(1U)
23184 #define V_PFEN(x) ((x) << S_PFEN)
23185 #define F_PFEN V_PFEN(1U)
23188 #define V_VBADJ(x) ((x) << S_VBADJ)
23189 #define F_VBADJ V_VBADJ(1U)
23191 #define A_XGMAC_PORT_HSS_TX_MODE_CFG 0x1c80
23192 #define A_XGMAC_PORT_HSS_TXTEST_CTRL 0x1c84
23193 #define A_XGMAC_PORT_HSS_TX_COEFF_CTRL 0x1c88
23194 #define A_XGMAC_PORT_HSS_TX_DRIVER_MODE 0x1c8c
23195 #define A_XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL 0x1c90
23196 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER 0x1c94
23197 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER 0x1c98
23198 #define A_XGMAC_PORT_HSS_TX_TAP0_COEFF 0x1ca0
23199 #define A_XGMAC_PORT_HSS_TX_TAP1_COEFF 0x1ca4
23200 #define A_XGMAC_PORT_HSS_TX_TAP2_COEFF 0x1ca8
23201 #define A_XGMAC_PORT_HSS_TX_PWR 0x1cb0
23202 #define A_XGMAC_PORT_HSS_TX_POLARITY 0x1cb4
23203 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_CMD 0x1cb8
23204 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_STATUS 0x1cbc
23205 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR 0x1cc0
23206 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR 0x1cc4
23207 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR 0x1cc8
23208 #define A_XGMAC_PORT_HSS_TX_PWR_DAC_OVR 0x1cd0
23209 #define A_XGMAC_PORT_HSS_TX_PWR_DAC 0x1cd4
23210 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_APP 0x1ce0
23211 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_APP 0x1ce4
23212 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_APP 0x1ce8
23213 #define A_XGMAC_PORT_HSS_TX_SEG_DIS_APP 0x1cf0
23214 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR_DATA 0x1cf8
23215 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR 0x1cfc
23216 #define A_XGMAC_PORT_HSS_RX_CFG_MODE 0x1d00
23217 #define A_XGMAC_PORT_HSS_RXTEST_CTRL 0x1d04
23218 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL 0x1d08
23219 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL 0x1d0c
23220 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1 0x1d10
23221 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2 0x1d14
23222 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET 0x1d18
23223 #define A_XGMAC_PORT_HSS_RX_SIGDET_CTRL 0x1d1c
23224 #define A_XGMAC_PORT_HSS_RX_DFE_CTRL 0x1d20
23225 #define A_XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE 0x1d24
23226 #define A_XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE 0x1d28
23227 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL1 0x1d2c
23228 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL2 0x1d30
23229 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL3 0x1d34
23230 #define A_XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET 0x1d38
23231 #define A_XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET 0x1d3c
23232 #define A_XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET 0x1d40
23233 #define A_XGMAC_PORT_HSS_RX_DACA_OFFSET 0x1d44
23234 #define A_XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET 0x1d48
23235 #define A_XGMAC_PORT_HSS_RX_DACA_MIN 0x1d4c
23236 #define A_XGMAC_PORT_HSS_RX_ADAC_CTRL 0x1d50
23237 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL 0x1d54
23238 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS 0x1d58
23239 #define A_XGMAC_PORT_HSS_RX_DFE_H1 0x1d5c
23240 #define A_XGMAC_PORT_HSS_RX_DFE_H2 0x1d60
23241 #define A_XGMAC_PORT_HSS_RX_DFE_H3 0x1d64
23242 #define A_XGMAC_PORT_HSS_RX_DFE_H4 0x1d68
23243 #define A_XGMAC_PORT_HSS_RX_DFE_H5 0x1d6c
23244 #define A_XGMAC_PORT_HSS_RX_DAC_DPC 0x1d70
23245 #define A_XGMAC_PORT_HSS_RX_DDC 0x1d74
23246 #define A_XGMAC_PORT_HSS_RX_INTERNAL_STATUS 0x1d78
23247 #define A_XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL 0x1d7c
23248 #define A_XGMAC_PORT_HSS_TXRX_CFG_MODE 0x1e00
23249 #define A_XGMAC_PORT_HSS_TXRXTEST_CTRL 0x1e04
23251 /* registers for module UP */
23252 #define UP_BASE_ADDR 0x0
23254 #define A_UP_IBQ_CONFIG 0x0
23256 #define S_IBQGEN2 2
23257 #define M_IBQGEN2 0x3fffffffU
23258 #define V_IBQGEN2(x) ((x) << S_IBQGEN2)
23259 #define G_IBQGEN2(x) (((x) >> S_IBQGEN2) & M_IBQGEN2)
23261 #define S_IBQBUSY 1
23262 #define V_IBQBUSY(x) ((x) << S_IBQBUSY)
23263 #define F_IBQBUSY V_IBQBUSY(1U)
23266 #define V_IBQEN(x) ((x) << S_IBQEN)
23267 #define F_IBQEN V_IBQEN(1U)
23269 #define A_UP_OBQ_CONFIG 0x4
23271 #define S_OBQGEN2 2
23272 #define M_OBQGEN2 0x3fffffffU
23273 #define V_OBQGEN2(x) ((x) << S_OBQGEN2)
23274 #define G_OBQGEN2(x) (((x) >> S_OBQGEN2) & M_OBQGEN2)
23276 #define S_OBQBUSY 1
23277 #define V_OBQBUSY(x) ((x) << S_OBQBUSY)
23278 #define F_OBQBUSY V_OBQBUSY(1U)
23281 #define V_OBQEN(x) ((x) << S_OBQEN)
23282 #define F_OBQEN V_OBQEN(1U)
23284 #define A_UP_IBQ_GEN 0x8
23286 #define S_IBQGEN0 22
23287 #define M_IBQGEN0 0x3ffU
23288 #define V_IBQGEN0(x) ((x) << S_IBQGEN0)
23289 #define G_IBQGEN0(x) (((x) >> S_IBQGEN0) & M_IBQGEN0)
23291 #define S_IBQTSCHCHNLRDY 18
23292 #define M_IBQTSCHCHNLRDY 0xfU
23293 #define V_IBQTSCHCHNLRDY(x) ((x) << S_IBQTSCHCHNLRDY)
23294 #define G_IBQTSCHCHNLRDY(x) (((x) >> S_IBQTSCHCHNLRDY) & M_IBQTSCHCHNLRDY)
23296 #define S_IBQMBVFSTATUS 17
23297 #define V_IBQMBVFSTATUS(x) ((x) << S_IBQMBVFSTATUS)
23298 #define F_IBQMBVFSTATUS V_IBQMBVFSTATUS(1U)
23300 #define S_IBQMBSTATUS 16
23301 #define V_IBQMBSTATUS(x) ((x) << S_IBQMBSTATUS)
23302 #define F_IBQMBSTATUS V_IBQMBSTATUS(1U)
23304 #define S_IBQGEN1 6
23305 #define M_IBQGEN1 0x3ffU
23306 #define V_IBQGEN1(x) ((x) << S_IBQGEN1)
23307 #define G_IBQGEN1(x) (((x) >> S_IBQGEN1) & M_IBQGEN1)
23309 #define S_IBQEMPTY 0
23310 #define M_IBQEMPTY 0x3fU
23311 #define V_IBQEMPTY(x) ((x) << S_IBQEMPTY)
23312 #define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY)
23314 #define A_UP_OBQ_GEN 0xc
23317 #define M_OBQGEN 0x3ffffffU
23318 #define V_OBQGEN(x) ((x) << S_OBQGEN)
23319 #define G_OBQGEN(x) (((x) >> S_OBQGEN) & M_OBQGEN)
23321 #define S_OBQFULL 0
23322 #define M_OBQFULL 0x3fU
23323 #define V_OBQFULL(x) ((x) << S_OBQFULL)
23324 #define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL)
23326 #define A_UP_IBQ_0_RDADDR 0x10
23329 #define M_QUEID 0x7ffffU
23330 #define V_QUEID(x) ((x) << S_QUEID)
23331 #define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID)
23333 #define S_IBQRDADDR 0
23334 #define M_IBQRDADDR 0x1fffU
23335 #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
23336 #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)
23338 #define A_UP_IBQ_0_WRADDR 0x14
23340 #define S_IBQWRADDR 0
23341 #define M_IBQWRADDR 0x1fffU
23342 #define V_IBQWRADDR(x) ((x) << S_IBQWRADDR)
23343 #define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR)
23345 #define A_UP_IBQ_0_STATUS 0x18
23347 #define S_QUEERRFRAME 31
23348 #define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME)
23349 #define F_QUEERRFRAME V_QUEERRFRAME(1U)
23351 #define S_QUEREMFLITS 0
23352 #define M_QUEREMFLITS 0x7ffU
23353 #define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS)
23354 #define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS)
23356 #define A_UP_IBQ_0_PKTCNT 0x1c
23358 #define S_QUEEOPCNT 16
23359 #define M_QUEEOPCNT 0xfffU
23360 #define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT)
23361 #define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT)
23363 #define S_QUESOPCNT 0
23364 #define M_QUESOPCNT 0xfffU
23365 #define V_QUESOPCNT(x) ((x) << S_QUESOPCNT)
23366 #define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT)
23368 #define A_UP_IBQ_1_RDADDR 0x20
23369 #define A_UP_IBQ_1_WRADDR 0x24
23370 #define A_UP_IBQ_1_STATUS 0x28
23371 #define A_UP_IBQ_1_PKTCNT 0x2c
23372 #define A_UP_IBQ_2_RDADDR 0x30
23373 #define A_UP_IBQ_2_WRADDR 0x34
23374 #define A_UP_IBQ_2_STATUS 0x38
23375 #define A_UP_IBQ_2_PKTCNT 0x3c
23376 #define A_UP_IBQ_3_RDADDR 0x40
23377 #define A_UP_IBQ_3_WRADDR 0x44
23378 #define A_UP_IBQ_3_STATUS 0x48
23379 #define A_UP_IBQ_3_PKTCNT 0x4c
23380 #define A_UP_IBQ_4_RDADDR 0x50
23381 #define A_UP_IBQ_4_WRADDR 0x54
23382 #define A_UP_IBQ_4_STATUS 0x58
23383 #define A_UP_IBQ_4_PKTCNT 0x5c
23384 #define A_UP_IBQ_5_RDADDR 0x60
23385 #define A_UP_IBQ_5_WRADDR 0x64
23386 #define A_UP_IBQ_5_STATUS 0x68
23387 #define A_UP_IBQ_5_PKTCNT 0x6c
23388 #define A_UP_OBQ_0_RDADDR 0x70
23391 #define M_OBQID 0x1ffffU
23392 #define V_OBQID(x) ((x) << S_OBQID)
23393 #define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID)
23395 #define S_QUERDADDR 0
23396 #define M_QUERDADDR 0x7fffU
23397 #define V_QUERDADDR(x) ((x) << S_QUERDADDR)
23398 #define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR)
23400 #define A_UP_OBQ_0_WRADDR 0x74
23402 #define S_QUEWRADDR 0
23403 #define M_QUEWRADDR 0x7fffU
23404 #define V_QUEWRADDR(x) ((x) << S_QUEWRADDR)
23405 #define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR)
23407 #define A_UP_OBQ_0_STATUS 0x78
23408 #define A_UP_OBQ_0_PKTCNT 0x7c
23409 #define A_UP_OBQ_1_RDADDR 0x80
23410 #define A_UP_OBQ_1_WRADDR 0x84
23411 #define A_UP_OBQ_1_STATUS 0x88
23412 #define A_UP_OBQ_1_PKTCNT 0x8c
23413 #define A_UP_OBQ_2_RDADDR 0x90
23414 #define A_UP_OBQ_2_WRADDR 0x94
23415 #define A_UP_OBQ_2_STATUS 0x98
23416 #define A_UP_OBQ_2_PKTCNT 0x9c
23417 #define A_UP_OBQ_3_RDADDR 0xa0
23418 #define A_UP_OBQ_3_WRADDR 0xa4
23419 #define A_UP_OBQ_3_STATUS 0xa8
23420 #define A_UP_OBQ_3_PKTCNT 0xac
23421 #define A_UP_OBQ_4_RDADDR 0xb0
23422 #define A_UP_OBQ_4_WRADDR 0xb4
23423 #define A_UP_OBQ_4_STATUS 0xb8
23424 #define A_UP_OBQ_4_PKTCNT 0xbc
23425 #define A_UP_OBQ_5_RDADDR 0xc0
23426 #define A_UP_OBQ_5_WRADDR 0xc4
23427 #define A_UP_OBQ_5_STATUS 0xc8
23428 #define A_UP_OBQ_5_PKTCNT 0xcc
23429 #define A_UP_IBQ_0_CONFIG 0xd0
23431 #define S_QUESIZE 26
23432 #define M_QUESIZE 0x3fU
23433 #define V_QUESIZE(x) ((x) << S_QUESIZE)
23434 #define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE)
23436 #define S_QUEBASE 8
23437 #define M_QUEBASE 0x3fU
23438 #define V_QUEBASE(x) ((x) << S_QUEBASE)
23439 #define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE)
23441 #define S_QUEDBG8BEN 7
23442 #define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN)
23443 #define F_QUEDBG8BEN V_QUEDBG8BEN(1U)
23445 #define S_QUEBAREADDR 0
23446 #define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
23447 #define F_QUEBAREADDR V_QUEBAREADDR(1U)
23449 #define A_UP_IBQ_0_REALADDR 0xd4
23451 #define S_QUERDADDRWRAP 31
23452 #define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP)
23453 #define F_QUERDADDRWRAP V_QUERDADDRWRAP(1U)
23455 #define S_QUEWRADDRWRAP 30
23456 #define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP)
23457 #define F_QUEWRADDRWRAP V_QUEWRADDRWRAP(1U)
23459 #define S_QUEMEMADDR 3
23460 #define M_QUEMEMADDR 0x7ffU
23461 #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
23462 #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)
23464 #define A_UP_IBQ_1_CONFIG 0xd8
23465 #define A_UP_IBQ_1_REALADDR 0xdc
23466 #define A_UP_IBQ_2_CONFIG 0xe0
23467 #define A_UP_IBQ_2_REALADDR 0xe4
23468 #define A_UP_IBQ_3_CONFIG 0xe8
23469 #define A_UP_IBQ_3_REALADDR 0xec
23470 #define A_UP_IBQ_4_CONFIG 0xf0
23471 #define A_UP_IBQ_4_REALADDR 0xf4
23472 #define A_UP_IBQ_5_CONFIG 0xf8
23473 #define A_UP_IBQ_5_REALADDR 0xfc
23474 #define A_UP_OBQ_0_CONFIG 0x100
23475 #define A_UP_OBQ_0_REALADDR 0x104
23476 #define A_UP_OBQ_1_CONFIG 0x108
23477 #define A_UP_OBQ_1_REALADDR 0x10c
23478 #define A_UP_OBQ_2_CONFIG 0x110
23479 #define A_UP_OBQ_2_REALADDR 0x114
23480 #define A_UP_OBQ_3_CONFIG 0x118
23481 #define A_UP_OBQ_3_REALADDR 0x11c
23482 #define A_UP_OBQ_4_CONFIG 0x120
23483 #define A_UP_OBQ_4_REALADDR 0x124
23484 #define A_UP_OBQ_5_CONFIG 0x128
23485 #define A_UP_OBQ_5_REALADDR 0x12c
23486 #define A_UP_MAILBOX_STATUS 0x130
23488 #define S_MBGEN0 20
23489 #define M_MBGEN0 0xfffU
23490 #define V_MBGEN0(x) ((x) << S_MBGEN0)
23491 #define G_MBGEN0(x) (((x) >> S_MBGEN0) & M_MBGEN0)
23493 #define S_GENTIMERTRIGGER 16
23494 #define M_GENTIMERTRIGGER 0xfU
23495 #define V_GENTIMERTRIGGER(x) ((x) << S_GENTIMERTRIGGER)
23496 #define G_GENTIMERTRIGGER(x) (((x) >> S_GENTIMERTRIGGER) & M_GENTIMERTRIGGER)
23499 #define M_MBGEN1 0xffU
23500 #define V_MBGEN1(x) ((x) << S_MBGEN1)
23501 #define G_MBGEN1(x) (((x) >> S_MBGEN1) & M_MBGEN1)
23503 #define S_MBPFINT 0
23504 #define M_MBPFINT 0xffU
23505 #define V_MBPFINT(x) ((x) << S_MBPFINT)
23506 #define G_MBPFINT(x) (((x) >> S_MBPFINT) & M_MBPFINT)
23508 #define A_UP_UP_DBG_LA_CFG 0x140
23510 #define S_UPDBGLACAPTBUB 31
23511 #define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB)
23512 #define F_UPDBGLACAPTBUB V_UPDBGLACAPTBUB(1U)
23514 #define S_UPDBGLACAPTPCONLY 30
23515 #define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY)
23516 #define F_UPDBGLACAPTPCONLY V_UPDBGLACAPTPCONLY(1U)
23518 #define S_UPDBGLAMASKSTOP 29
23519 #define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP)
23520 #define F_UPDBGLAMASKSTOP V_UPDBGLAMASKSTOP(1U)
23522 #define S_UPDBGLAMASKTRIG 28
23523 #define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG)
23524 #define F_UPDBGLAMASKTRIG V_UPDBGLAMASKTRIG(1U)
23526 #define S_UPDBGLAWRPTR 16
23527 #define M_UPDBGLAWRPTR 0xfffU
23528 #define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR)
23529 #define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR)
23531 #define S_UPDBGLARDPTR 2
23532 #define M_UPDBGLARDPTR 0xfffU
23533 #define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR)
23534 #define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR)
23536 #define S_UPDBGLARDEN 1
23537 #define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN)
23538 #define F_UPDBGLARDEN V_UPDBGLARDEN(1U)
23540 #define S_UPDBGLAEN 0
23541 #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
23542 #define F_UPDBGLAEN V_UPDBGLAEN(1U)
23544 #define A_UP_UP_DBG_LA_DATA 0x144
23545 #define A_UP_PIO_MST_CONFIG 0x148
23548 #define M_FLSRC 0x7U
23549 #define V_FLSRC(x) ((x) << S_FLSRC)
23550 #define G_FLSRC(x) (((x) >> S_FLSRC) & M_FLSRC)
23552 #define S_SEPROT 23
23553 #define V_SEPROT(x) ((x) << S_SEPROT)
23554 #define F_SEPROT V_SEPROT(1U)
23557 #define M_SESRC 0x7U
23558 #define V_SESRC(x) ((x) << S_SESRC)
23559 #define G_SESRC(x) (((x) >> S_SESRC) & M_SESRC)
23562 #define V_UPRGN(x) ((x) << S_UPRGN)
23563 #define F_UPRGN V_UPRGN(1U)
23566 #define M_UPPF 0x7U
23567 #define V_UPPF(x) ((x) << S_UPPF)
23568 #define G_UPPF(x) (((x) >> S_UPPF) & M_UPPF)
23571 #define M_UPRID 0xffffU
23572 #define V_UPRID(x) ((x) << S_UPRID)
23573 #define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID)
23575 #define A_UP_UP_SELF_CONTROL 0x14c
23577 #define S_UPSELFRESET 0
23578 #define V_UPSELFRESET(x) ((x) << S_UPSELFRESET)
23579 #define F_UPSELFRESET V_UPSELFRESET(1U)
23581 #define A_UP_MAILBOX_PF0_CTL 0x180
23582 #define A_UP_MAILBOX_PF1_CTL 0x190
23583 #define A_UP_MAILBOX_PF2_CTL 0x1a0
23584 #define A_UP_MAILBOX_PF3_CTL 0x1b0
23585 #define A_UP_MAILBOX_PF4_CTL 0x1c0
23586 #define A_UP_MAILBOX_PF5_CTL 0x1d0
23587 #define A_UP_MAILBOX_PF6_CTL 0x1e0
23588 #define A_UP_MAILBOX_PF7_CTL 0x1f0
23589 #define A_UP_TSCH_CHNLN_CLASS_RDY 0x200
23590 #define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204
23592 #define S_TSCHWRRLIMIT 16
23593 #define M_TSCHWRRLIMIT 0xffffU
23594 #define V_TSCHWRRLIMIT(x) ((x) << S_TSCHWRRLIMIT)
23595 #define G_TSCHWRRLIMIT(x) (((x) >> S_TSCHWRRLIMIT) & M_TSCHWRRLIMIT)
23597 #define S_TSCHCHNLCWRDY 0
23598 #define M_TSCHCHNLCWRDY 0xffffU
23599 #define V_TSCHCHNLCWRDY(x) ((x) << S_TSCHCHNLCWRDY)
23600 #define G_TSCHCHNLCWRDY(x) (((x) >> S_TSCHCHNLCWRDY) & M_TSCHCHNLCWRDY)
23602 #define A_UP_TSCH_CHNLN_CLASS_WATCH_LIST 0x208
23604 #define S_TSCHWRRRELOAD 16
23605 #define M_TSCHWRRRELOAD 0xffffU
23606 #define V_TSCHWRRRELOAD(x) ((x) << S_TSCHWRRRELOAD)
23607 #define G_TSCHWRRRELOAD(x) (((x) >> S_TSCHWRRRELOAD) & M_TSCHWRRRELOAD)
23609 #define S_TSCHCHNLCWATCH 0
23610 #define M_TSCHCHNLCWATCH 0xffffU
23611 #define V_TSCHCHNLCWATCH(x) ((x) << S_TSCHCHNLCWATCH)
23612 #define G_TSCHCHNLCWATCH(x) (((x) >> S_TSCHCHNLCWATCH) & M_TSCHCHNLCWATCH)
23614 #define A_UP_TSCH_CHNLN_CLASS_TAKE 0x20c
23616 #define S_TSCHCHNLCNUM 24
23617 #define M_TSCHCHNLCNUM 0x1fU
23618 #define V_TSCHCHNLCNUM(x) ((x) << S_TSCHCHNLCNUM)
23619 #define G_TSCHCHNLCNUM(x) (((x) >> S_TSCHCHNLCNUM) & M_TSCHCHNLCNUM)
23621 #define S_TSCHCHNLCCNT 0
23622 #define M_TSCHCHNLCCNT 0xffffffU
23623 #define V_TSCHCHNLCCNT(x) ((x) << S_TSCHCHNLCCNT)
23624 #define G_TSCHCHNLCCNT(x) (((x) >> S_TSCHCHNLCCNT) & M_TSCHCHNLCCNT)
23626 #define A_UP_UPLADBGPCCHKDATA_0 0x240
23627 #define A_UP_UPLADBGPCCHKMASK_0 0x244
23628 #define A_UP_UPLADBGPCCHKDATA_1 0x250
23629 #define A_UP_UPLADBGPCCHKMASK_1 0x254
23630 #define A_UP_UPLADBGPCCHKDATA_2 0x260
23631 #define A_UP_UPLADBGPCCHKMASK_2 0x264
23632 #define A_UP_UPLADBGPCCHKDATA_3 0x270
23633 #define A_UP_UPLADBGPCCHKMASK_3 0x274
23635 /* registers for module CIM_CTL */
23636 #define CIM_CTL_BASE_ADDR 0x0
23638 #define A_CIM_CTL_CONFIG 0x0
23640 #define S_AUTOPREFLOC 17
23641 #define M_AUTOPREFLOC 0x1fU
23642 #define V_AUTOPREFLOC(x) ((x) << S_AUTOPREFLOC)
23643 #define G_AUTOPREFLOC(x) (((x) >> S_AUTOPREFLOC) & M_AUTOPREFLOC)
23645 #define S_AUTOPREFEN 16
23646 #define V_AUTOPREFEN(x) ((x) << S_AUTOPREFEN)
23647 #define F_AUTOPREFEN V_AUTOPREFEN(1U)
23649 #define S_DISMATIMEOUT 15
23650 #define V_DISMATIMEOUT(x) ((x) << S_DISMATIMEOUT)
23651 #define F_DISMATIMEOUT V_DISMATIMEOUT(1U)
23653 #define S_PIFMULTICMD 8
23654 #define V_PIFMULTICMD(x) ((x) << S_PIFMULTICMD)
23655 #define F_PIFMULTICMD V_PIFMULTICMD(1U)
23657 #define S_UPSELFRESETTOUT 7
23658 #define V_UPSELFRESETTOUT(x) ((x) << S_UPSELFRESETTOUT)
23659 #define F_UPSELFRESETTOUT V_UPSELFRESETTOUT(1U)
23661 #define S_PLSWAPDISWR 6
23662 #define V_PLSWAPDISWR(x) ((x) << S_PLSWAPDISWR)
23663 #define F_PLSWAPDISWR V_PLSWAPDISWR(1U)
23665 #define S_PLSWAPDISRD 5
23666 #define V_PLSWAPDISRD(x) ((x) << S_PLSWAPDISRD)
23667 #define F_PLSWAPDISRD V_PLSWAPDISRD(1U)
23670 #define V_PREFEN(x) ((x) << S_PREFEN)
23671 #define F_PREFEN V_PREFEN(1U)
23673 #define A_CIM_CTL_PREFADDR 0x4
23674 #define A_CIM_CTL_ALLOCADDR 0x8
23675 #define A_CIM_CTL_INVLDTADDR 0xc
23676 #define A_CIM_CTL_STATIC_PREFADDR0 0x10
23677 #define A_CIM_CTL_STATIC_PREFADDR1 0x14
23678 #define A_CIM_CTL_STATIC_PREFADDR2 0x18
23679 #define A_CIM_CTL_STATIC_PREFADDR3 0x1c
23680 #define A_CIM_CTL_STATIC_PREFADDR4 0x20
23681 #define A_CIM_CTL_STATIC_PREFADDR5 0x24
23682 #define A_CIM_CTL_STATIC_PREFADDR6 0x28
23683 #define A_CIM_CTL_STATIC_PREFADDR7 0x2c
23684 #define A_CIM_CTL_STATIC_PREFADDR8 0x30
23685 #define A_CIM_CTL_STATIC_PREFADDR9 0x34
23686 #define A_CIM_CTL_STATIC_PREFADDR10 0x38
23687 #define A_CIM_CTL_STATIC_PREFADDR11 0x3c
23688 #define A_CIM_CTL_STATIC_PREFADDR12 0x40
23689 #define A_CIM_CTL_STATIC_PREFADDR13 0x44
23690 #define A_CIM_CTL_STATIC_PREFADDR14 0x48
23691 #define A_CIM_CTL_STATIC_PREFADDR15 0x4c
23692 #define A_CIM_CTL_STATIC_ALLOCADDR0 0x50
23693 #define A_CIM_CTL_STATIC_ALLOCADDR1 0x54
23694 #define A_CIM_CTL_STATIC_ALLOCADDR2 0x58
23695 #define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c
23696 #define A_CIM_CTL_STATIC_ALLOCADDR4 0x60
23697 #define A_CIM_CTL_STATIC_ALLOCADDR5 0x64
23698 #define A_CIM_CTL_STATIC_ALLOCADDR6 0x68
23699 #define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c
23700 #define A_CIM_CTL_STATIC_ALLOCADDR8 0x70
23701 #define A_CIM_CTL_STATIC_ALLOCADDR9 0x74
23702 #define A_CIM_CTL_STATIC_ALLOCADDR10 0x78
23703 #define A_CIM_CTL_STATIC_ALLOCADDR11 0x7c
23704 #define A_CIM_CTL_STATIC_ALLOCADDR12 0x80
23705 #define A_CIM_CTL_STATIC_ALLOCADDR13 0x84
23706 #define A_CIM_CTL_STATIC_ALLOCADDR14 0x88
23707 #define A_CIM_CTL_STATIC_ALLOCADDR15 0x8c
23708 #define A_CIM_CTL_FIFO_CNT 0x90
23710 #define S_CTLFIFOCNT 0
23711 #define M_CTLFIFOCNT 0xfU
23712 #define V_CTLFIFOCNT(x) ((x) << S_CTLFIFOCNT)
23713 #define G_CTLFIFOCNT(x) (((x) >> S_CTLFIFOCNT) & M_CTLFIFOCNT)
23715 #define A_CIM_CTL_GLB_TIMER 0x94
23716 #define A_CIM_CTL_TIMER0 0x98
23717 #define A_CIM_CTL_TIMER1 0x9c
23718 #define A_CIM_CTL_GEN0 0xa0
23719 #define A_CIM_CTL_GEN1 0xa4
23720 #define A_CIM_CTL_GEN2 0xa8
23721 #define A_CIM_CTL_GEN3 0xac
23722 #define A_CIM_CTL_GLB_TIMER_TICK 0xb0
23723 #define A_CIM_CTL_GEN_TIMER0_CTL 0xb4
23725 #define S_GENTIMERRUN 7
23726 #define V_GENTIMERRUN(x) ((x) << S_GENTIMERRUN)
23727 #define F_GENTIMERRUN V_GENTIMERRUN(1U)
23729 #define S_GENTIMERTRIG 6
23730 #define V_GENTIMERTRIG(x) ((x) << S_GENTIMERTRIG)
23731 #define F_GENTIMERTRIG V_GENTIMERTRIG(1U)
23733 #define S_GENTIMERACT 4
23734 #define M_GENTIMERACT 0x3U
23735 #define V_GENTIMERACT(x) ((x) << S_GENTIMERACT)
23736 #define G_GENTIMERACT(x) (((x) >> S_GENTIMERACT) & M_GENTIMERACT)
23738 #define S_GENTIMERCFG 2
23739 #define M_GENTIMERCFG 0x3U
23740 #define V_GENTIMERCFG(x) ((x) << S_GENTIMERCFG)
23741 #define G_GENTIMERCFG(x) (((x) >> S_GENTIMERCFG) & M_GENTIMERCFG)
23743 #define S_GENTIMERSTOP 1
23744 #define V_GENTIMERSTOP(x) ((x) << S_GENTIMERSTOP)
23745 #define F_GENTIMERSTOP V_GENTIMERSTOP(1U)
23747 #define S_GENTIMERSTRT 0
23748 #define V_GENTIMERSTRT(x) ((x) << S_GENTIMERSTRT)
23749 #define F_GENTIMERSTRT V_GENTIMERSTRT(1U)
23751 #define A_CIM_CTL_GEN_TIMER0 0xb8
23752 #define A_CIM_CTL_GEN_TIMER1_CTL 0xbc
23753 #define A_CIM_CTL_GEN_TIMER1 0xc0
23754 #define A_CIM_CTL_GEN_TIMER2_CTL 0xc4
23755 #define A_CIM_CTL_GEN_TIMER2 0xc8
23756 #define A_CIM_CTL_GEN_TIMER3_CTL 0xcc
23757 #define A_CIM_CTL_GEN_TIMER3 0xd0
23758 #define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0
23759 #define A_CIM_CTL_MAILBOX_VFN_CTL 0x100
23760 #define A_CIM_CTL_TSCH_CHNLN_CTL 0x900
23762 #define S_TSCHNLEN 31
23763 #define V_TSCHNLEN(x) ((x) << S_TSCHNLEN)
23764 #define F_TSCHNLEN V_TSCHNLEN(1U)
23766 #define S_TSCHNRESET 30
23767 #define V_TSCHNRESET(x) ((x) << S_TSCHNRESET)
23768 #define F_TSCHNRESET V_TSCHNRESET(1U)
23770 #define A_CIM_CTL_TSCH_CHNLN_TICK 0x904
23772 #define S_TSCHNLTICK 0
23773 #define M_TSCHNLTICK 0xffffU
23774 #define V_TSCHNLTICK(x) ((x) << S_TSCHNLTICK)
23775 #define G_TSCHNLTICK(x) (((x) >> S_TSCHNLTICK) & M_TSCHNLTICK)
23777 #define A_CIM_CTL_TSCH_CHNLN_CLASS_ENABLE_A 0x908
23779 #define S_TSC15WRREN 31
23780 #define V_TSC15WRREN(x) ((x) << S_TSC15WRREN)
23781 #define F_TSC15WRREN V_TSC15WRREN(1U)
23783 #define S_TSC15RATEEN 30
23784 #define V_TSC15RATEEN(x) ((x) << S_TSC15RATEEN)
23785 #define F_TSC15RATEEN V_TSC15RATEEN(1U)
23787 #define S_TSC14WRREN 29
23788 #define V_TSC14WRREN(x) ((x) << S_TSC14WRREN)
23789 #define F_TSC14WRREN V_TSC14WRREN(1U)
23791 #define S_TSC14RATEEN 28
23792 #define V_TSC14RATEEN(x) ((x) << S_TSC14RATEEN)
23793 #define F_TSC14RATEEN V_TSC14RATEEN(1U)
23795 #define S_TSC13WRREN 27
23796 #define V_TSC13WRREN(x) ((x) << S_TSC13WRREN)
23797 #define F_TSC13WRREN V_TSC13WRREN(1U)
23799 #define S_TSC13RATEEN 26
23800 #define V_TSC13RATEEN(x) ((x) << S_TSC13RATEEN)
23801 #define F_TSC13RATEEN V_TSC13RATEEN(1U)
23803 #define S_TSC12WRREN 25
23804 #define V_TSC12WRREN(x) ((x) << S_TSC12WRREN)
23805 #define F_TSC12WRREN V_TSC12WRREN(1U)
23807 #define S_TSC12RATEEN 24
23808 #define V_TSC12RATEEN(x) ((x) << S_TSC12RATEEN)
23809 #define F_TSC12RATEEN V_TSC12RATEEN(1U)
23811 #define S_TSC11WRREN 23
23812 #define V_TSC11WRREN(x) ((x) << S_TSC11WRREN)
23813 #define F_TSC11WRREN V_TSC11WRREN(1U)
23815 #define S_TSC11RATEEN 22
23816 #define V_TSC11RATEEN(x) ((x) << S_TSC11RATEEN)
23817 #define F_TSC11RATEEN V_TSC11RATEEN(1U)
23819 #define S_TSC10WRREN 21
23820 #define V_TSC10WRREN(x) ((x) << S_TSC10WRREN)
23821 #define F_TSC10WRREN V_TSC10WRREN(1U)
23823 #define S_TSC10RATEEN 20
23824 #define V_TSC10RATEEN(x) ((x) << S_TSC10RATEEN)
23825 #define F_TSC10RATEEN V_TSC10RATEEN(1U)
23827 #define S_TSC9WRREN 19
23828 #define V_TSC9WRREN(x) ((x) << S_TSC9WRREN)
23829 #define F_TSC9WRREN V_TSC9WRREN(1U)
23831 #define S_TSC9RATEEN 18
23832 #define V_TSC9RATEEN(x) ((x) << S_TSC9RATEEN)
23833 #define F_TSC9RATEEN V_TSC9RATEEN(1U)
23835 #define S_TSC8WRREN 17
23836 #define V_TSC8WRREN(x) ((x) << S_TSC8WRREN)
23837 #define F_TSC8WRREN V_TSC8WRREN(1U)
23839 #define S_TSC8RATEEN 16
23840 #define V_TSC8RATEEN(x) ((x) << S_TSC8RATEEN)
23841 #define F_TSC8RATEEN V_TSC8RATEEN(1U)
23843 #define S_TSC7WRREN 15
23844 #define V_TSC7WRREN(x) ((x) << S_TSC7WRREN)
23845 #define F_TSC7WRREN V_TSC7WRREN(1U)
23847 #define S_TSC7RATEEN 14
23848 #define V_TSC7RATEEN(x) ((x) << S_TSC7RATEEN)
23849 #define F_TSC7RATEEN V_TSC7RATEEN(1U)
23851 #define S_TSC6WRREN 13
23852 #define V_TSC6WRREN(x) ((x) << S_TSC6WRREN)
23853 #define F_TSC6WRREN V_TSC6WRREN(1U)
23855 #define S_TSC6RATEEN 12
23856 #define V_TSC6RATEEN(x) ((x) << S_TSC6RATEEN)
23857 #define F_TSC6RATEEN V_TSC6RATEEN(1U)
23859 #define S_TSC5WRREN 11
23860 #define V_TSC5WRREN(x) ((x) << S_TSC5WRREN)
23861 #define F_TSC5WRREN V_TSC5WRREN(1U)
23863 #define S_TSC5RATEEN 10
23864 #define V_TSC5RATEEN(x) ((x) << S_TSC5RATEEN)
23865 #define F_TSC5RATEEN V_TSC5RATEEN(1U)
23867 #define S_TSC4WRREN 9
23868 #define V_TSC4WRREN(x) ((x) << S_TSC4WRREN)
23869 #define F_TSC4WRREN V_TSC4WRREN(1U)
23871 #define S_TSC4RATEEN 8
23872 #define V_TSC4RATEEN(x) ((x) << S_TSC4RATEEN)
23873 #define F_TSC4RATEEN V_TSC4RATEEN(1U)
23875 #define S_TSC3WRREN 7
23876 #define V_TSC3WRREN(x) ((x) << S_TSC3WRREN)
23877 #define F_TSC3WRREN V_TSC3WRREN(1U)
23879 #define S_TSC3RATEEN 6
23880 #define V_TSC3RATEEN(x) ((x) << S_TSC3RATEEN)
23881 #define F_TSC3RATEEN V_TSC3RATEEN(1U)
23883 #define S_TSC2WRREN 5
23884 #define V_TSC2WRREN(x) ((x) << S_TSC2WRREN)
23885 #define F_TSC2WRREN V_TSC2WRREN(1U)
23887 #define S_TSC2RATEEN 4
23888 #define V_TSC2RATEEN(x) ((x) << S_TSC2RATEEN)
23889 #define F_TSC2RATEEN V_TSC2RATEEN(1U)
23891 #define S_TSC1WRREN 3
23892 #define V_TSC1WRREN(x) ((x) << S_TSC1WRREN)
23893 #define F_TSC1WRREN V_TSC1WRREN(1U)
23895 #define S_TSC1RATEEN 2
23896 #define V_TSC1RATEEN(x) ((x) << S_TSC1RATEEN)
23897 #define F_TSC1RATEEN V_TSC1RATEEN(1U)
23899 #define S_TSC0WRREN 1
23900 #define V_TSC0WRREN(x) ((x) << S_TSC0WRREN)
23901 #define F_TSC0WRREN V_TSC0WRREN(1U)
23903 #define S_TSC0RATEEN 0
23904 #define V_TSC0RATEEN(x) ((x) << S_TSC0RATEEN)
23905 #define F_TSC0RATEEN V_TSC0RATEEN(1U)
23907 #define A_CIM_CTL_TSCH_MIN_MAX_EN 0x90c
23909 #define S_MIN_MAX_EN 0
23910 #define V_MIN_MAX_EN(x) ((x) << S_MIN_MAX_EN)
23911 #define F_MIN_MAX_EN V_MIN_MAX_EN(1U)
23913 #define A_CIM_CTL_TSCH_CHNLN_RATE_LIMITER 0x910
23915 #define S_TSCHNLRATENEG 31
23916 #define V_TSCHNLRATENEG(x) ((x) << S_TSCHNLRATENEG)
23917 #define F_TSCHNLRATENEG V_TSCHNLRATENEG(1U)
23919 #define S_TSCHNLRATEL 0
23920 #define M_TSCHNLRATEL 0x7fffffffU
23921 #define V_TSCHNLRATEL(x) ((x) << S_TSCHNLRATEL)
23922 #define G_TSCHNLRATEL(x) (((x) >> S_TSCHNLRATEL) & M_TSCHNLRATEL)
23924 #define A_CIM_CTL_TSCH_CHNLN_RATE_PROPERTIES 0x914
23926 #define S_TSCHNLRMAX 16
23927 #define M_TSCHNLRMAX 0xffffU
23928 #define V_TSCHNLRMAX(x) ((x) << S_TSCHNLRMAX)
23929 #define G_TSCHNLRMAX(x) (((x) >> S_TSCHNLRMAX) & M_TSCHNLRMAX)
23931 #define S_TSCHNLRINCR 0
23932 #define M_TSCHNLRINCR 0xffffU
23933 #define V_TSCHNLRINCR(x) ((x) << S_TSCHNLRINCR)
23934 #define G_TSCHNLRINCR(x) (((x) >> S_TSCHNLRINCR) & M_TSCHNLRINCR)
23936 #define A_CIM_CTL_TSCH_CHNLN_WRR 0x918
23937 #define A_CIM_CTL_TSCH_CHNLN_WEIGHT 0x91c
23939 #define S_TSCHNLWEIGHT 0
23940 #define M_TSCHNLWEIGHT 0x3fffffU
23941 #define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT)
23942 #define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT)
23944 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
23946 #define S_TSCCLRMAX 16
23947 #define M_TSCCLRMAX 0xffffU
23948 #define V_TSCCLRMAX(x) ((x) << S_TSCCLRMAX)
23949 #define G_TSCCLRMAX(x) (((x) >> S_TSCCLRMAX) & M_TSCCLRMAX)
23951 #define S_TSCCLRINCR 0
23952 #define M_TSCCLRINCR 0xffffU
23953 #define V_TSCCLRINCR(x) ((x) << S_TSCCLRINCR)
23954 #define G_TSCCLRINCR(x) (((x) >> S_TSCCLRINCR) & M_TSCCLRINCR)
23956 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WRR 0x928
23958 #define S_TSCCLWRRNEG 31
23959 #define V_TSCCLWRRNEG(x) ((x) << S_TSCCLWRRNEG)
23960 #define F_TSCCLWRRNEG V_TSCCLWRRNEG(1U)
23962 #define S_TSCCLWRR 0
23963 #define M_TSCCLWRR 0x3ffffffU
23964 #define V_TSCCLWRR(x) ((x) << S_TSCCLWRR)
23965 #define G_TSCCLWRR(x) (((x) >> S_TSCCLWRR) & M_TSCCLWRR)
23967 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WEIGHT 0x92c
23969 #define S_TSCCLWEIGHT 0
23970 #define M_TSCCLWEIGHT 0xffffU
23971 #define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT)
23972 #define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT)