2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN983 (www.admtek.com.tw)
47 * ADMtek CardBus AN985 (www.admtek.com.tw)
48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985
49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
50 * Accton EN1217 (www.accton.com)
51 * Xircom X3201 (www.xircom.com)
53 * Conexant LANfinity (www.conexant.com)
54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
56 * Datasheets for the 21143 are available at developer.intel.com.
57 * Datasheets for the clone parts can be found at their respective sites.
58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
59 * The PNIC II is essentially a Macronix 98715A chip; the only difference
60 * worth noting is that its multicast hash table is only 128 bits wide
63 * Written by Bill Paul <wpaul@ee.columbia.edu>
64 * Electrical Engineering Department
65 * Columbia University, New York City
68 * The Intel 21143 is the successor to the DEC 21140. It is basically
69 * the same as the 21140 but with a few new features. The 21143 supports
70 * three kinds of media attachments:
72 * o MII port, for 10Mbps and 100Mbps support and NWAY
73 * autonegotiation provided by an external PHY.
74 * o SYM port, for symbol mode 100Mbps support.
78 * The 100Mbps SYM port and 10baseT port can be used together in
79 * combination with the internal NWAY support to create a 10/100
80 * autosensing configuration.
82 * Note that not all tulip workalikes are handled in this driver: we only
83 * deal with those which are relatively well behaved. The Winbond is
84 * handled separately due to its different register offsets and the
85 * special handling needed for its various bugs. The PNIC is handled
86 * here, but I'm not thrilled about it.
88 * All of the workalike chips use some form of MII transceiver support
89 * with the exception of the Macronix chips, which also have a SYM port.
90 * The ASIX AX88140A is also documented to have a SYM port, but all
91 * the cards I've seen use an MII transceiver, probably because the
92 * AX88140A doesn't support internal NWAY.
95 #ifdef HAVE_KERNEL_OPTION_HEADERS
96 #include "opt_device_polling.h"
99 #include <sys/param.h>
100 #include <sys/endian.h>
101 #include <sys/systm.h>
102 #include <sys/sockio.h>
103 #include <sys/mbuf.h>
104 #include <sys/malloc.h>
105 #include <sys/kernel.h>
106 #include <sys/module.h>
107 #include <sys/socket.h>
110 #include <net/if_arp.h>
111 #include <net/ethernet.h>
112 #include <net/if_dl.h>
113 #include <net/if_media.h>
114 #include <net/if_types.h>
115 #include <net/if_vlan_var.h>
119 #include <machine/bus.h>
120 #include <machine/resource.h>
122 #include <sys/rman.h>
124 #include <dev/mii/mii.h>
125 #include <dev/mii/mii_bitbang.h>
126 #include <dev/mii/miivar.h>
128 #include <dev/pci/pcireg.h>
129 #include <dev/pci/pcivar.h>
131 #define DC_USEIOSPACE
133 #include <dev/dc/if_dcreg.h>
136 #include <dev/ofw/openfirm.h>
137 #include <machine/ofw_machdep.h>
140 MODULE_DEPEND(dc, pci, 1, 1, 1);
141 MODULE_DEPEND(dc, ether, 1, 1, 1);
142 MODULE_DEPEND(dc, miibus, 1, 1, 1);
145 * "device miibus" is required in kernel config. See GENERIC if you get
148 #include "miibus_if.h"
151 * Various supported device vendors/types and their names.
153 static const struct dc_type const dc_devs[] = {
154 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
155 "Intel 21143 10/100BaseTX" },
156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
157 "Davicom DM9009 10/100BaseTX" },
158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
159 "Davicom DM9100 10/100BaseTX" },
160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
161 "Davicom DM9102A 10/100BaseTX" },
162 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
163 "Davicom DM9102 10/100BaseTX" },
164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
165 "ADMtek AL981 10/100BaseTX" },
166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0,
167 "ADMtek AN983 10/100BaseTX" },
168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
169 "ADMtek AN985 CardBus 10/100BaseTX or clone" },
170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
171 "ADMtek ADM9511 10/100BaseTX" },
172 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
173 "ADMtek ADM9513 10/100BaseTX" },
174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
175 "ASIX AX88141 10/100BaseTX" },
176 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
177 "ASIX AX88140A 10/100BaseTX" },
178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
179 "Macronix 98713A 10/100BaseTX" },
180 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
181 "Macronix 98713 10/100BaseTX" },
182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
183 "Compex RL100-TX 10/100BaseTX" },
184 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
185 "Compex RL100-TX 10/100BaseTX" },
186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
187 "Macronix 98725 10/100BaseTX" },
188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
189 "Macronix 98715AEC-C 10/100BaseTX" },
190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
191 "Macronix 98715/98715A 10/100BaseTX" },
192 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
193 "Macronix 98727/98732 10/100BaseTX" },
194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
195 "LC82C115 PNIC II 10/100BaseTX" },
196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
197 "82c169 PNIC 10/100BaseTX" },
198 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
199 "82c168 PNIC 10/100BaseTX" },
200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
201 "Accton EN1217 10/100BaseTX" },
202 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
203 "Accton EN2242 MiniPCI 10/100BaseTX" },
204 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
205 "Xircom X3201 10/100BaseTX" },
206 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
207 "Neteasy DRP-32TXD Cardbus 10/100" },
208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
209 "Abocom FE2500 10/100BaseTX" },
210 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
211 "Abocom FE2500MX 10/100BaseTX" },
212 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
213 "Conexant LANfinity MiniPCI 10/100BaseTX" },
214 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
215 "Hawking CB102 CardBus 10/100" },
216 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
217 "PlaneX FNW-3602-T CardBus 10/100" },
218 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
219 "3Com OfficeConnect 10/100B" },
220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
221 "Microsoft MN-120 CardBus 10/100" },
222 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
223 "Microsoft MN-130 10/100" },
224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
225 "Linksys PCMPC200 CardBus 10/100" },
226 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
227 "Linksys PCMPC200 CardBus 10/100" },
231 static int dc_probe(device_t);
232 static int dc_attach(device_t);
233 static int dc_detach(device_t);
234 static int dc_suspend(device_t);
235 static int dc_resume(device_t);
236 static const struct dc_type *dc_devtype(device_t);
237 static void dc_discard_rxbuf(struct dc_softc *, int);
238 static int dc_newbuf(struct dc_softc *, int);
239 static int dc_encap(struct dc_softc *, struct mbuf **);
240 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
241 static int dc_rx_resync(struct dc_softc *);
242 static int dc_rxeof(struct dc_softc *);
243 static void dc_txeof(struct dc_softc *);
244 static void dc_tick(void *);
245 static void dc_tx_underrun(struct dc_softc *);
246 static void dc_intr(void *);
247 static void dc_start(struct ifnet *);
248 static void dc_start_locked(struct ifnet *);
249 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
250 static void dc_init(void *);
251 static void dc_init_locked(struct dc_softc *);
252 static void dc_stop(struct dc_softc *);
253 static void dc_watchdog(void *);
254 static int dc_shutdown(device_t);
255 static int dc_ifmedia_upd(struct ifnet *);
256 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
258 static int dc_dma_alloc(struct dc_softc *);
259 static void dc_dma_free(struct dc_softc *);
260 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int);
262 static void dc_delay(struct dc_softc *);
263 static void dc_eeprom_idle(struct dc_softc *);
264 static void dc_eeprom_putbyte(struct dc_softc *, int);
265 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *);
266 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *);
267 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *);
268 static void dc_eeprom_width(struct dc_softc *);
269 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
271 static int dc_miibus_readreg(device_t, int, int);
272 static int dc_miibus_writereg(device_t, int, int, int);
273 static void dc_miibus_statchg(device_t);
274 static void dc_miibus_mediainit(device_t);
276 static void dc_setcfg(struct dc_softc *, int);
277 static void dc_netcfg_wait(struct dc_softc *);
278 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
279 static uint32_t dc_mchash_be(const uint8_t *);
280 static void dc_setfilt_21143(struct dc_softc *);
281 static void dc_setfilt_asix(struct dc_softc *);
282 static void dc_setfilt_admtek(struct dc_softc *);
283 static void dc_setfilt_xircom(struct dc_softc *);
285 static void dc_setfilt(struct dc_softc *);
287 static void dc_reset(struct dc_softc *);
288 static int dc_list_rx_init(struct dc_softc *);
289 static int dc_list_tx_init(struct dc_softc *);
291 static int dc_read_srom(struct dc_softc *, int);
292 static int dc_parse_21143_srom(struct dc_softc *);
293 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
294 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
295 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
296 static void dc_apply_fixup(struct dc_softc *, int);
297 static int dc_check_multiport(struct dc_softc *);
302 static uint32_t dc_mii_bitbang_read(device_t);
303 static void dc_mii_bitbang_write(device_t, uint32_t);
305 static const struct mii_bitbang_ops dc_mii_bitbang_ops = {
307 dc_mii_bitbang_write,
309 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */
310 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */
311 DC_SIO_MII_CLK, /* MII_BIT_MDC */
312 0, /* MII_BIT_DIR_HOST_PHY */
313 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */
318 #define DC_RES SYS_RES_IOPORT
319 #define DC_RID DC_PCI_CFBIO
321 #define DC_RES SYS_RES_MEMORY
322 #define DC_RID DC_PCI_CFBMA
325 static device_method_t dc_methods[] = {
326 /* Device interface */
327 DEVMETHOD(device_probe, dc_probe),
328 DEVMETHOD(device_attach, dc_attach),
329 DEVMETHOD(device_detach, dc_detach),
330 DEVMETHOD(device_suspend, dc_suspend),
331 DEVMETHOD(device_resume, dc_resume),
332 DEVMETHOD(device_shutdown, dc_shutdown),
335 DEVMETHOD(bus_print_child, bus_generic_print_child),
336 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
339 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
340 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
341 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
342 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
347 static driver_t dc_driver = {
350 sizeof(struct dc_softc)
353 static devclass_t dc_devclass;
355 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
356 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
358 #define DC_SETBIT(sc, reg, x) \
359 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
361 #define DC_CLRBIT(sc, reg, x) \
362 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
364 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
365 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
368 dc_delay(struct dc_softc *sc)
372 for (idx = (300 / 33) + 1; idx > 0; idx--)
373 CSR_READ_4(sc, DC_BUSCTL);
377 dc_eeprom_width(struct dc_softc *sc)
381 /* Force EEPROM to idle state. */
384 /* Enter EEPROM access mode. */
385 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
387 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
391 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
398 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
400 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
406 for (i = 1; i <= 12; i++) {
407 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
409 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
418 /* Turn off EEPROM access mode. */
426 /* Enter EEPROM access mode. */
427 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
429 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
431 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
433 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
436 /* Turn off EEPROM access mode. */
441 dc_eeprom_idle(struct dc_softc *sc)
445 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
447 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
454 for (i = 0; i < 25; i++) {
455 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
457 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
463 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
465 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
469 * Send a read command and address to the EEPROM, check for ACK.
472 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
476 d = DC_EECMD_READ >> 6;
479 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
481 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
483 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
485 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
490 * Feed in each bit and strobe the clock.
492 for (i = sc->dc_romwidth; i--;) {
493 if (addr & (1 << i)) {
494 SIO_SET(DC_SIO_EE_DATAIN);
496 SIO_CLR(DC_SIO_EE_DATAIN);
499 SIO_SET(DC_SIO_EE_CLK);
501 SIO_CLR(DC_SIO_EE_CLK);
507 * Read a word of data stored in the EEPROM at address 'addr.'
508 * The PNIC 82c168/82c169 has its own non-standard way to read
512 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest)
517 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
519 for (i = 0; i < DC_TIMEOUT; i++) {
521 r = CSR_READ_4(sc, DC_SIO);
522 if (!(r & DC_PN_SIOCTL_BUSY)) {
523 *dest = (uint16_t)(r & 0xFFFF);
530 * Read a word of data stored in the EEPROM at address 'addr.'
531 * The Xircom X3201 has its own non-standard way to read
535 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest)
538 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
541 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
542 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
544 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
545 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
547 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
551 * Read a word of data stored in the EEPROM at address 'addr.'
554 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest)
559 /* Force EEPROM to idle state. */
562 /* Enter EEPROM access mode. */
563 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
565 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
567 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
569 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
573 * Send address of word we want to read.
575 dc_eeprom_putbyte(sc, addr);
578 * Start reading bits from EEPROM.
580 for (i = 0x8000; i; i >>= 1) {
581 SIO_SET(DC_SIO_EE_CLK);
583 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
586 SIO_CLR(DC_SIO_EE_CLK);
590 /* Turn off EEPROM access mode. */
597 * Read a sequence of words from the EEPROM.
600 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
603 uint16_t word = 0, *ptr;
605 for (i = 0; i < cnt; i++) {
607 dc_eeprom_getword_pnic(sc, off + i, &word);
608 else if (DC_IS_XIRCOM(sc))
609 dc_eeprom_getword_xircom(sc, off + i, &word);
611 dc_eeprom_getword(sc, off + i, &word);
612 ptr = (uint16_t *)(dest + (i * 2));
614 *ptr = be16toh(word);
616 *ptr = le16toh(word);
621 * Write the MII serial port for the MII bit-bang module.
624 dc_mii_bitbang_write(device_t dev, uint32_t val)
628 sc = device_get_softc(dev);
630 CSR_WRITE_4(sc, DC_SIO, val);
631 CSR_BARRIER_4(sc, DC_SIO,
632 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
636 * Read the MII serial port for the MII bit-bang module.
639 dc_mii_bitbang_read(device_t dev)
644 sc = device_get_softc(dev);
646 val = CSR_READ_4(sc, DC_SIO);
647 CSR_BARRIER_4(sc, DC_SIO,
648 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
654 dc_miibus_readreg(device_t dev, int phy, int reg)
657 int i, rval, phy_reg = 0;
659 sc = device_get_softc(dev);
661 if (sc->dc_pmode != DC_PMODE_MII) {
662 if (phy == (MII_NPHY - 1)) {
666 * Fake something to make the probe
667 * code think there's a PHY here.
669 return (BMSR_MEDIAMASK);
673 return (DC_VENDORID_LO);
674 return (DC_VENDORID_DEC);
678 return (DC_DEVICEID_82C168);
679 return (DC_DEVICEID_21143);
689 if (DC_IS_PNIC(sc)) {
690 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
691 (phy << 23) | (reg << 18));
692 for (i = 0; i < DC_TIMEOUT; i++) {
694 rval = CSR_READ_4(sc, DC_PN_MII);
695 if (!(rval & DC_PN_MII_BUSY)) {
697 return (rval == 0xFFFF ? 0 : rval);
703 if (DC_IS_COMET(sc)) {
706 phy_reg = DC_AL_BMCR;
709 phy_reg = DC_AL_BMSR;
712 phy_reg = DC_AL_VENID;
715 phy_reg = DC_AL_DEVID;
718 phy_reg = DC_AL_ANAR;
721 phy_reg = DC_AL_LPAR;
724 phy_reg = DC_AL_ANER;
727 device_printf(dev, "phy_read: bad phy register %x\n",
733 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
739 if (sc->dc_type == DC_TYPE_98713) {
740 phy_reg = CSR_READ_4(sc, DC_NETCFG);
741 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
743 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg);
744 if (sc->dc_type == DC_TYPE_98713)
745 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
751 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
756 sc = device_get_softc(dev);
758 if (DC_IS_PNIC(sc)) {
759 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
760 (phy << 23) | (reg << 10) | data);
761 for (i = 0; i < DC_TIMEOUT; i++) {
762 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
768 if (DC_IS_COMET(sc)) {
771 phy_reg = DC_AL_BMCR;
774 phy_reg = DC_AL_BMSR;
777 phy_reg = DC_AL_VENID;
780 phy_reg = DC_AL_DEVID;
783 phy_reg = DC_AL_ANAR;
786 phy_reg = DC_AL_LPAR;
789 phy_reg = DC_AL_ANER;
792 device_printf(dev, "phy_write: bad phy register %x\n",
798 CSR_WRITE_4(sc, phy_reg, data);
802 if (sc->dc_type == DC_TYPE_98713) {
803 phy_reg = CSR_READ_4(sc, DC_NETCFG);
804 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
806 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data);
807 if (sc->dc_type == DC_TYPE_98713)
808 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
814 dc_miibus_statchg(device_t dev)
818 struct mii_data *mii;
821 sc = device_get_softc(dev);
823 mii = device_get_softc(sc->dc_miibus);
825 if (mii == NULL || ifp == NULL ||
826 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
829 ifm = &mii->mii_media;
830 if (DC_IS_DAVICOM(sc) &&
831 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
832 dc_setcfg(sc, ifm->ifm_media);
833 sc->dc_if_media = ifm->ifm_media;
838 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
839 (IFM_ACTIVE | IFM_AVALID)) {
840 switch (IFM_SUBTYPE(mii->mii_media_active)) {
849 if (sc->dc_link == 0)
852 sc->dc_if_media = mii->mii_media_active;
853 if (DC_IS_ADMTEK(sc))
855 dc_setcfg(sc, mii->mii_media_active);
859 * Special support for DM9102A cards with HomePNA PHYs. Note:
860 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
861 * to be impossible to talk to the management interface of the DM9801
862 * PHY (its MDIO pin is not connected to anything). Consequently,
863 * the driver has to just 'know' about the additional mode and deal
864 * with it itself. *sigh*
867 dc_miibus_mediainit(device_t dev)
870 struct mii_data *mii;
874 rev = pci_get_revid(dev);
876 sc = device_get_softc(dev);
877 mii = device_get_softc(sc->dc_miibus);
878 ifm = &mii->mii_media;
880 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
881 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
884 #define DC_BITS_512 9
885 #define DC_BITS_128 7
889 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
893 /* Compute CRC for the address value. */
894 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
897 * The hash table on the PNIC II and the MX98715AEC-C/D/E
898 * chips is only 128 bits wide.
900 if (sc->dc_flags & DC_128BIT_HASH)
901 return (crc & ((1 << DC_BITS_128) - 1));
903 /* The hash table on the MX98715BEC is only 64 bits wide. */
904 if (sc->dc_flags & DC_64BIT_HASH)
905 return (crc & ((1 << DC_BITS_64) - 1));
907 /* Xircom's hash filtering table is different (read: weird) */
908 /* Xircom uses the LEAST significant bits */
909 if (DC_IS_XIRCOM(sc)) {
910 if ((crc & 0x180) == 0x180)
911 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
913 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
917 return (crc & ((1 << DC_BITS_512) - 1));
921 * Calculate CRC of a multicast group address, return the lower 6 bits.
924 dc_mchash_be(const uint8_t *addr)
928 /* Compute CRC for the address value. */
929 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
931 /* Return the filter bit position. */
932 return ((crc >> 26) & 0x0000003F);
936 * 21143-style RX filter setup routine. Filter programming is done by
937 * downloading a special setup frame into the TX engine. 21143, Macronix,
938 * PNIC, PNIC II and Davicom chips are programmed this way.
940 * We always program the chip using 'hash perfect' mode, i.e. one perfect
941 * address (our node address) and a 512-bit hash filter for multicast
942 * frames. We also sneak the broadcast address into the hash filter since
946 dc_setfilt_21143(struct dc_softc *sc)
948 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
949 struct dc_desc *sframe;
951 struct ifmultiaddr *ifma;
957 i = sc->dc_cdata.dc_tx_prod;
958 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
959 sc->dc_cdata.dc_tx_cnt++;
960 sframe = &sc->dc_ldata.dc_tx_list[i];
961 sp = sc->dc_cdata.dc_sbuf;
962 bzero(sp, DC_SFRAME_LEN);
964 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
965 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
966 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
968 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
970 /* If we want promiscuous mode, set the allframes bit. */
971 if (ifp->if_flags & IFF_PROMISC)
972 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
974 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
976 if (ifp->if_flags & IFF_ALLMULTI)
977 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
979 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
982 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
983 if (ifma->ifma_addr->sa_family != AF_LINK)
986 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
987 sp[h >> 4] |= htole32(1 << (h & 0xF));
989 if_maddr_runlock(ifp);
991 if (ifp->if_flags & IFF_BROADCAST) {
992 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
993 sp[h >> 4] |= htole32(1 << (h & 0xF));
996 /* Set our MAC address. */
997 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
998 sp[39] = DC_SP_MAC(eaddr[0]);
999 sp[40] = DC_SP_MAC(eaddr[1]);
1000 sp[41] = DC_SP_MAC(eaddr[2]);
1002 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1003 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1004 BUS_DMASYNC_PREWRITE);
1005 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1006 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1009 * The PNIC takes an exceedingly long time to process its
1010 * setup frame; wait 10ms after posting the setup frame
1011 * before proceeding, just so it has time to swallow its
1016 sc->dc_wdog_timer = 5;
1020 dc_setfilt_admtek(struct dc_softc *sc)
1022 uint8_t eaddr[ETHER_ADDR_LEN];
1024 struct ifmultiaddr *ifma;
1026 uint32_t hashes[2] = { 0, 0 };
1030 /* Init our MAC address. */
1031 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1032 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 |
1033 eaddr[1] << 8 | eaddr[0]);
1034 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]);
1036 /* If we want promiscuous mode, set the allframes bit. */
1037 if (ifp->if_flags & IFF_PROMISC)
1038 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1040 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1042 if (ifp->if_flags & IFF_ALLMULTI)
1043 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1045 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1047 /* First, zot all the existing hash bits. */
1048 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1049 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1052 * If we're already in promisc or allmulti mode, we
1053 * don't have to bother programming the multicast filter.
1055 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1058 /* Now program new ones. */
1059 if_maddr_rlock(ifp);
1060 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1061 if (ifma->ifma_addr->sa_family != AF_LINK)
1063 if (DC_IS_CENTAUR(sc))
1064 h = dc_mchash_le(sc,
1065 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1068 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1070 hashes[0] |= (1 << h);
1072 hashes[1] |= (1 << (h - 32));
1074 if_maddr_runlock(ifp);
1076 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1077 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1081 dc_setfilt_asix(struct dc_softc *sc)
1083 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1085 struct ifmultiaddr *ifma;
1087 uint32_t hashes[2] = { 0, 0 };
1091 /* Init our MAC address. */
1092 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1093 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1094 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
1095 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1096 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
1098 /* If we want promiscuous mode, set the allframes bit. */
1099 if (ifp->if_flags & IFF_PROMISC)
1100 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1102 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1104 if (ifp->if_flags & IFF_ALLMULTI)
1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1110 * The ASIX chip has a special bit to enable reception
1111 * of broadcast frames.
1113 if (ifp->if_flags & IFF_BROADCAST)
1114 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1116 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1118 /* first, zot all the existing hash bits */
1119 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1120 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1121 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1122 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1125 * If we're already in promisc or allmulti mode, we
1126 * don't have to bother programming the multicast filter.
1128 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1131 /* now program new ones */
1132 if_maddr_rlock(ifp);
1133 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1134 if (ifma->ifma_addr->sa_family != AF_LINK)
1136 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1138 hashes[0] |= (1 << h);
1140 hashes[1] |= (1 << (h - 32));
1142 if_maddr_runlock(ifp);
1144 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1145 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1146 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1147 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1151 dc_setfilt_xircom(struct dc_softc *sc)
1153 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1155 struct ifmultiaddr *ifma;
1156 struct dc_desc *sframe;
1161 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1163 i = sc->dc_cdata.dc_tx_prod;
1164 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1165 sc->dc_cdata.dc_tx_cnt++;
1166 sframe = &sc->dc_ldata.dc_tx_list[i];
1167 sp = sc->dc_cdata.dc_sbuf;
1168 bzero(sp, DC_SFRAME_LEN);
1170 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1171 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1172 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1174 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1176 /* If we want promiscuous mode, set the allframes bit. */
1177 if (ifp->if_flags & IFF_PROMISC)
1178 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1180 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1182 if (ifp->if_flags & IFF_ALLMULTI)
1183 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1185 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1187 if_maddr_rlock(ifp);
1188 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1189 if (ifma->ifma_addr->sa_family != AF_LINK)
1191 h = dc_mchash_le(sc,
1192 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1193 sp[h >> 4] |= htole32(1 << (h & 0xF));
1195 if_maddr_runlock(ifp);
1197 if (ifp->if_flags & IFF_BROADCAST) {
1198 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1199 sp[h >> 4] |= htole32(1 << (h & 0xF));
1202 /* Set our MAC address. */
1203 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1204 sp[0] = DC_SP_MAC(eaddr[0]);
1205 sp[1] = DC_SP_MAC(eaddr[1]);
1206 sp[2] = DC_SP_MAC(eaddr[2]);
1208 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1209 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1210 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1211 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1212 BUS_DMASYNC_PREWRITE);
1213 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1214 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1221 sc->dc_wdog_timer = 5;
1225 dc_setfilt(struct dc_softc *sc)
1228 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1229 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1230 dc_setfilt_21143(sc);
1233 dc_setfilt_asix(sc);
1235 if (DC_IS_ADMTEK(sc))
1236 dc_setfilt_admtek(sc);
1238 if (DC_IS_XIRCOM(sc))
1239 dc_setfilt_xircom(sc);
1243 dc_netcfg_wait(struct dc_softc *sc)
1248 for (i = 0; i < DC_TIMEOUT; i++) {
1249 isr = CSR_READ_4(sc, DC_ISR);
1250 if (isr & DC_ISR_TX_IDLE &&
1251 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1252 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1256 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) {
1257 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
1258 device_printf(sc->dc_dev,
1259 "%s: failed to force tx to idle state\n", __func__);
1260 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1261 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
1262 !DC_HAS_BROKEN_RXSTATE(sc))
1263 device_printf(sc->dc_dev,
1264 "%s: failed to force rx to idle state\n", __func__);
1269 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1270 * the netconfig register, we first have to put the transmit and/or
1271 * receive logic in the idle state.
1274 dc_setcfg(struct dc_softc *sc, int media)
1276 int restart = 0, watchdogreg;
1278 if (IFM_SUBTYPE(media) == IFM_NONE)
1281 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1283 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1287 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1288 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1289 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1290 if (sc->dc_pmode == DC_PMODE_MII) {
1291 if (DC_IS_INTEL(sc)) {
1292 /* There's a write enable bit here that reads as 1. */
1293 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1294 watchdogreg &= ~DC_WDOG_CTLWREN;
1295 watchdogreg |= DC_WDOG_JABBERDIS;
1296 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1298 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1300 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1301 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1302 if (sc->dc_type == DC_TYPE_98713)
1303 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1304 DC_NETCFG_SCRAMBLER));
1305 if (!DC_IS_DAVICOM(sc))
1306 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1307 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1309 if (DC_IS_PNIC(sc)) {
1310 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1311 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1312 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1315 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1316 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1320 if (IFM_SUBTYPE(media) == IFM_10_T) {
1321 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1322 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1323 if (sc->dc_pmode == DC_PMODE_MII) {
1324 /* There's a write enable bit here that reads as 1. */
1325 if (DC_IS_INTEL(sc)) {
1326 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1327 watchdogreg &= ~DC_WDOG_CTLWREN;
1328 watchdogreg |= DC_WDOG_JABBERDIS;
1329 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1331 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1333 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1334 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1335 if (sc->dc_type == DC_TYPE_98713)
1336 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1337 if (!DC_IS_DAVICOM(sc))
1338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1339 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1341 if (DC_IS_PNIC(sc)) {
1342 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1343 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1344 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1346 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1347 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1348 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1349 if (DC_IS_INTEL(sc)) {
1350 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1351 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1352 if ((media & IFM_GMASK) == IFM_FDX)
1353 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1355 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1356 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1357 DC_CLRBIT(sc, DC_10BTCTRL,
1358 DC_TCTL_AUTONEGENBL);
1365 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1366 * PHY and we want HomePNA mode, set the portsel bit to turn
1367 * on the external MII port.
1369 if (DC_IS_DAVICOM(sc)) {
1370 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1371 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1374 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1378 if ((media & IFM_GMASK) == IFM_FDX) {
1379 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1380 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1381 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1383 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1384 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1385 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1389 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1393 dc_reset(struct dc_softc *sc)
1397 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1399 for (i = 0; i < DC_TIMEOUT; i++) {
1401 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1405 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1406 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
1408 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1412 if (i == DC_TIMEOUT)
1413 device_printf(sc->dc_dev, "reset never completed!\n");
1415 /* Wait a little while for the chip to get its brains in order. */
1418 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1419 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1420 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1423 * Bring the SIA out of reset. In some cases, it looks
1424 * like failing to unreset the SIA soon enough gets it
1425 * into a state where it will never come out of reset
1426 * until we reset the whole chip again.
1428 if (DC_IS_INTEL(sc)) {
1429 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1430 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF);
1431 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1435 static const struct dc_type *
1436 dc_devtype(device_t dev)
1438 const struct dc_type *t;
1443 devid = pci_get_devid(dev);
1444 rev = pci_get_revid(dev);
1446 while (t->dc_name != NULL) {
1447 if (devid == t->dc_devid && rev >= t->dc_minrev)
1456 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1457 * IDs against our list and return a device name if we find a match.
1458 * We do a little bit of extra work to identify the exact type of
1459 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1460 * but different revision IDs. The same is true for 98715/98715A
1461 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1462 * cases, the exact chip revision affects driver behavior.
1465 dc_probe(device_t dev)
1467 const struct dc_type *t;
1469 t = dc_devtype(dev);
1472 device_set_desc(dev, t->dc_name);
1473 return (BUS_PROBE_DEFAULT);
1480 dc_apply_fixup(struct dc_softc *sc, int media)
1482 struct dc_mediainfo *m;
1490 if (m->dc_media == media)
1498 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1499 reg = (p[0] | (p[1] << 8)) << 16;
1500 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1503 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1504 reg = (p[0] | (p[1] << 8)) << 16;
1505 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1510 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1512 struct dc_mediainfo *m;
1514 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1516 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1519 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1520 case DC_SIA_CODE_10BT:
1521 m->dc_media = IFM_10_T;
1523 case DC_SIA_CODE_10BT_FDX:
1524 m->dc_media = IFM_10_T | IFM_FDX;
1526 case DC_SIA_CODE_10B2:
1527 m->dc_media = IFM_10_2;
1529 case DC_SIA_CODE_10B5:
1530 m->dc_media = IFM_10_5;
1537 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1538 * Things apparently already work for cards that do
1539 * supply Media Specific Data.
1541 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1544 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1548 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1551 m->dc_next = sc->dc_mi;
1554 sc->dc_pmode = DC_PMODE_SIA;
1559 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1561 struct dc_mediainfo *m;
1563 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1565 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1568 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1569 m->dc_media = IFM_100_TX;
1571 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1572 m->dc_media = IFM_100_TX | IFM_FDX;
1575 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl;
1577 m->dc_next = sc->dc_mi;
1580 sc->dc_pmode = DC_PMODE_SYM;
1585 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1587 struct dc_mediainfo *m;
1590 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1592 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1595 /* We abuse IFM_AUTO to represent MII. */
1596 m->dc_media = IFM_AUTO;
1597 m->dc_gp_len = l->dc_gpr_len;
1600 p += sizeof(struct dc_eblock_mii);
1602 p += 2 * l->dc_gpr_len;
1603 m->dc_reset_len = *p;
1605 m->dc_reset_ptr = p;
1607 m->dc_next = sc->dc_mi;
1613 dc_read_srom(struct dc_softc *sc, int bits)
1617 size = DC_ROM_SIZE(bits);
1618 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1619 if (sc->dc_srom == NULL) {
1620 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n");
1623 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1628 dc_parse_21143_srom(struct dc_softc *sc)
1630 struct dc_leaf_hdr *lhdr;
1631 struct dc_eblock_hdr *hdr;
1632 int error, have_mii, i, loff;
1636 loff = sc->dc_srom[27];
1637 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1640 ptr += sizeof(struct dc_leaf_hdr) - 1;
1642 * Look if we got a MII media block.
1644 for (i = 0; i < lhdr->dc_mcnt; i++) {
1645 hdr = (struct dc_eblock_hdr *)ptr;
1646 if (hdr->dc_type == DC_EBLOCK_MII)
1649 ptr += (hdr->dc_len & 0x7F);
1654 * Do the same thing again. Only use SIA and SYM media
1655 * blocks if no MII media block is available.
1658 ptr += sizeof(struct dc_leaf_hdr) - 1;
1660 for (i = 0; i < lhdr->dc_mcnt; i++) {
1661 hdr = (struct dc_eblock_hdr *)ptr;
1662 switch (hdr->dc_type) {
1664 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1668 error = dc_decode_leaf_sia(sc,
1669 (struct dc_eblock_sia *)hdr);
1673 error = dc_decode_leaf_sym(sc,
1674 (struct dc_eblock_sym *)hdr);
1677 /* Don't care. Yet. */
1680 ptr += (hdr->dc_len & 0x7F);
1687 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1692 ("%s: wrong number of segments (%d)", __func__, nseg));
1694 *paddr = segs->ds_addr;
1698 dc_dma_alloc(struct dc_softc *sc)
1702 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0,
1703 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1704 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1705 NULL, NULL, &sc->dc_ptag);
1707 device_printf(sc->dc_dev,
1708 "failed to allocate parent DMA tag\n");
1712 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1713 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1714 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1,
1715 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag);
1717 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n");
1721 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1722 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1,
1723 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag);
1725 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n");
1729 /* RX descriptor list. */
1730 error = bus_dmamem_alloc(sc->dc_rx_ltag,
1731 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT |
1732 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap);
1734 device_printf(sc->dc_dev,
1735 "failed to allocate DMA'able memory for RX list\n");
1738 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap,
1739 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr,
1740 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT);
1742 device_printf(sc->dc_dev,
1743 "failed to load DMA'able memory for RX list\n");
1746 /* TX descriptor list. */
1747 error = bus_dmamem_alloc(sc->dc_tx_ltag,
1748 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT |
1749 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap);
1751 device_printf(sc->dc_dev,
1752 "failed to allocate DMA'able memory for TX list\n");
1755 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap,
1756 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr,
1757 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT);
1759 device_printf(sc->dc_dev,
1760 "cannot load DMA'able memory for TX list\n");
1765 * Allocate a busdma tag and DMA safe memory for the multicast
1768 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1769 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1770 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
1771 0, NULL, NULL, &sc->dc_stag);
1773 device_printf(sc->dc_dev,
1774 "failed to create DMA tag for setup frame\n");
1777 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
1778 BUS_DMA_NOWAIT, &sc->dc_smap);
1780 device_printf(sc->dc_dev,
1781 "failed to allocate DMA'able memory for setup frame\n");
1784 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
1785 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
1787 device_printf(sc->dc_dev,
1788 "cannot load DMA'able memory for setup frame\n");
1792 /* Allocate a busdma tag for RX mbufs. */
1793 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0,
1794 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1795 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag);
1797 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n");
1801 /* Allocate a busdma tag for TX mbufs. */
1802 error = bus_dma_tag_create(sc->dc_ptag, 1, 0,
1803 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1804 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
1805 0, NULL, NULL, &sc->dc_tx_mtag);
1807 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n");
1811 /* Create the TX/RX busdma maps. */
1812 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1813 error = bus_dmamap_create(sc->dc_tx_mtag, 0,
1814 &sc->dc_cdata.dc_tx_map[i]);
1816 device_printf(sc->dc_dev,
1817 "failed to create TX mbuf dmamap\n");
1821 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1822 error = bus_dmamap_create(sc->dc_rx_mtag, 0,
1823 &sc->dc_cdata.dc_rx_map[i]);
1825 device_printf(sc->dc_dev,
1826 "failed to create RX mbuf dmamap\n");
1830 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap);
1832 device_printf(sc->dc_dev,
1833 "failed to create spare RX mbuf dmamap\n");
1842 dc_dma_free(struct dc_softc *sc)
1847 if (sc->dc_rx_mtag != NULL) {
1848 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1849 if (sc->dc_cdata.dc_rx_map[i] != NULL)
1850 bus_dmamap_destroy(sc->dc_rx_mtag,
1851 sc->dc_cdata.dc_rx_map[i]);
1853 if (sc->dc_sparemap != NULL)
1854 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap);
1855 bus_dma_tag_destroy(sc->dc_rx_mtag);
1859 if (sc->dc_rx_mtag != NULL) {
1860 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1861 if (sc->dc_cdata.dc_tx_map[i] != NULL)
1862 bus_dmamap_destroy(sc->dc_tx_mtag,
1863 sc->dc_cdata.dc_tx_map[i]);
1865 bus_dma_tag_destroy(sc->dc_tx_mtag);
1868 /* RX descriptor list. */
1869 if (sc->dc_rx_ltag) {
1870 if (sc->dc_rx_lmap != NULL)
1871 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap);
1872 if (sc->dc_rx_lmap != NULL && sc->dc_ldata.dc_rx_list != NULL)
1873 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list,
1875 bus_dma_tag_destroy(sc->dc_rx_ltag);
1878 /* TX descriptor list. */
1879 if (sc->dc_tx_ltag) {
1880 if (sc->dc_tx_lmap != NULL)
1881 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap);
1882 if (sc->dc_tx_lmap != NULL && sc->dc_ldata.dc_tx_list != NULL)
1883 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list,
1885 bus_dma_tag_destroy(sc->dc_tx_ltag);
1888 /* multicast setup frame. */
1890 if (sc->dc_smap != NULL)
1891 bus_dmamap_unload(sc->dc_stag, sc->dc_smap);
1892 if (sc->dc_smap != NULL && sc->dc_cdata.dc_sbuf != NULL)
1893 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf,
1895 bus_dma_tag_destroy(sc->dc_stag);
1900 * Attach the interface. Allocate softc structures, do ifmedia
1901 * setup and ethernet/BPF attach.
1904 dc_attach(device_t dev)
1906 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1908 struct dc_softc *sc;
1910 struct dc_mediainfo *m;
1911 uint32_t reg, revision;
1912 int error, mac_offset, phy, rid, tmp;
1915 sc = device_get_softc(dev);
1918 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1922 * Map control/status registers.
1924 pci_enable_busmaster(dev);
1927 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1929 if (sc->dc_res == NULL) {
1930 device_printf(dev, "couldn't map ports/memory\n");
1935 sc->dc_btag = rman_get_bustag(sc->dc_res);
1936 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1938 /* Allocate interrupt. */
1940 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1941 RF_SHAREABLE | RF_ACTIVE);
1943 if (sc->dc_irq == NULL) {
1944 device_printf(dev, "couldn't map interrupt\n");
1949 /* Need this info to decide on a chip type. */
1950 sc->dc_info = dc_devtype(dev);
1951 revision = pci_get_revid(dev);
1954 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1955 if (sc->dc_info->dc_devid !=
1956 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
1957 sc->dc_info->dc_devid !=
1958 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
1959 dc_eeprom_width(sc);
1961 switch (sc->dc_info->dc_devid) {
1962 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
1963 sc->dc_type = DC_TYPE_21143;
1964 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1965 sc->dc_flags |= DC_REDUCED_MII_POLL;
1966 /* Save EEPROM contents so we can parse them later. */
1967 error = dc_read_srom(sc, sc->dc_romwidth);
1971 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
1972 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
1973 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
1974 sc->dc_type = DC_TYPE_DM9102;
1975 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
1976 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
1977 sc->dc_flags |= DC_TX_ALIGN;
1978 sc->dc_pmode = DC_PMODE_MII;
1980 /* Increase the latency timer value. */
1981 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
1983 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
1984 sc->dc_type = DC_TYPE_AL981;
1985 sc->dc_flags |= DC_TX_USE_TX_INTR;
1986 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1987 sc->dc_pmode = DC_PMODE_MII;
1988 error = dc_read_srom(sc, sc->dc_romwidth);
1992 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983):
1993 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
1994 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
1995 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
1996 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
1997 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
1998 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
1999 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
2000 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
2001 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
2002 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
2003 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
2004 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
2005 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08):
2006 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09):
2007 sc->dc_type = DC_TYPE_AN983;
2008 sc->dc_flags |= DC_64BIT_HASH;
2009 sc->dc_flags |= DC_TX_USE_TX_INTR;
2010 sc->dc_flags |= DC_TX_ADMTEK_WAR;
2011 sc->dc_pmode = DC_PMODE_MII;
2012 /* Don't read SROM for - auto-loaded on reset */
2014 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
2015 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
2016 if (revision < DC_REVISION_98713A) {
2017 sc->dc_type = DC_TYPE_98713;
2019 if (revision >= DC_REVISION_98713A) {
2020 sc->dc_type = DC_TYPE_98713A;
2021 sc->dc_flags |= DC_21143_NWAY;
2023 sc->dc_flags |= DC_REDUCED_MII_POLL;
2024 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2026 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
2027 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
2029 * Macronix MX98715AEC-C/D/E parts have only a
2030 * 128-bit hash table. We need to deal with these
2031 * in the same manner as the PNIC II so that we
2032 * get the right number of bits out of the
2035 if (revision >= DC_REVISION_98715AEC_C &&
2036 revision < DC_REVISION_98725)
2037 sc->dc_flags |= DC_128BIT_HASH;
2038 sc->dc_type = DC_TYPE_987x5;
2039 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2040 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2042 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
2043 sc->dc_type = DC_TYPE_987x5;
2044 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2045 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2047 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
2048 sc->dc_type = DC_TYPE_PNICII;
2049 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
2050 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2052 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
2053 sc->dc_type = DC_TYPE_PNIC;
2054 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
2055 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
2056 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2057 if (sc->dc_pnic_rx_buf == NULL) {
2058 device_printf(sc->dc_dev,
2059 "Could not allocate PNIC RX buffer\n");
2063 if (revision < DC_REVISION_82C169)
2064 sc->dc_pmode = DC_PMODE_SYM;
2066 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
2067 sc->dc_type = DC_TYPE_ASIX;
2068 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
2069 sc->dc_flags |= DC_REDUCED_MII_POLL;
2070 sc->dc_pmode = DC_PMODE_MII;
2072 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
2073 sc->dc_type = DC_TYPE_XIRCOM;
2074 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2077 * We don't actually need to coalesce, but we're doing
2078 * it to obtain a double word aligned buffer.
2079 * The DC_TX_COALESCE flag is required.
2081 sc->dc_pmode = DC_PMODE_MII;
2083 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
2084 sc->dc_type = DC_TYPE_CONEXANT;
2085 sc->dc_flags |= DC_TX_INTR_ALWAYS;
2086 sc->dc_flags |= DC_REDUCED_MII_POLL;
2087 sc->dc_pmode = DC_PMODE_MII;
2088 error = dc_read_srom(sc, sc->dc_romwidth);
2093 device_printf(dev, "unknown device: %x\n",
2094 sc->dc_info->dc_devid);
2098 /* Save the cache line size. */
2099 if (DC_IS_DAVICOM(sc))
2100 sc->dc_cachesize = 0;
2102 sc->dc_cachesize = pci_get_cachelnsz(dev);
2104 /* Reset the adapter. */
2107 /* Take 21143 out of snooze mode */
2108 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2109 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2110 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2111 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2115 * Try to learn something about the supported media.
2116 * We know that ASIX and ADMtek and Davicom devices
2117 * will *always* be using MII media, so that's a no-brainer.
2118 * The tricky ones are the Macronix/PNIC II and the
2121 if (DC_IS_INTEL(sc)) {
2122 error = dc_parse_21143_srom(sc);
2125 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2126 if (sc->dc_type == DC_TYPE_98713)
2127 sc->dc_pmode = DC_PMODE_MII;
2129 sc->dc_pmode = DC_PMODE_SYM;
2130 } else if (!sc->dc_pmode)
2131 sc->dc_pmode = DC_PMODE_MII;
2134 * Get station address from the EEPROM.
2136 switch(sc->dc_type) {
2138 case DC_TYPE_98713A:
2140 case DC_TYPE_PNICII:
2141 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2142 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2143 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2146 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2148 case DC_TYPE_DM9102:
2149 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2152 * If this is an onboard dc(4) the station address read from
2153 * the EEPROM is all zero and we have to get it from the FCode.
2155 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
2156 OF_getetheraddr(dev, (caddr_t)&eaddr);
2161 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2165 reg = CSR_READ_4(sc, DC_AL_PAR0);
2166 mac = (uint8_t *)&eaddr[0];
2167 mac[0] = (reg >> 0) & 0xff;
2168 mac[1] = (reg >> 8) & 0xff;
2169 mac[2] = (reg >> 16) & 0xff;
2170 mac[3] = (reg >> 24) & 0xff;
2171 reg = CSR_READ_4(sc, DC_AL_PAR1);
2172 mac[4] = (reg >> 0) & 0xff;
2173 mac[5] = (reg >> 8) & 0xff;
2175 case DC_TYPE_CONEXANT:
2176 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2179 case DC_TYPE_XIRCOM:
2180 /* The MAC comes from the CIS. */
2181 mac = pci_get_ether(dev);
2183 device_printf(dev, "No station address in CIS!\n");
2187 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2190 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2194 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr));
2196 * If we still have invalid station address, see whether we can
2197 * find station address for chip 0. Some multi-port controllers
2198 * just store station address for chip 0 if they have a shared
2201 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) ||
2202 (sc->dc_eaddr[0] == 0xffffffff &&
2203 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) {
2204 error = dc_check_multiport(sc);
2206 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr));
2207 /* Extract media information. */
2208 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) {
2209 while (sc->dc_mi != NULL) {
2210 m = sc->dc_mi->dc_next;
2211 free(sc->dc_mi, M_DEVBUF);
2214 error = dc_parse_21143_srom(sc);
2218 } else if (error == ENOMEM)
2224 if ((error = dc_dma_alloc(sc)) != 0)
2227 ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2229 device_printf(dev, "can not if_alloc()\n");
2234 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2235 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2236 ifp->if_ioctl = dc_ioctl;
2237 ifp->if_start = dc_start;
2238 ifp->if_init = dc_init;
2239 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2240 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2241 IFQ_SET_READY(&ifp->if_snd);
2244 * Do MII setup. If this is a 21143, check for a PHY on the
2245 * MII bus after applying any necessary fixups to twiddle the
2246 * GPIO bits. If we don't end up finding a PHY, restore the
2247 * old selection (SIA only or SIA/SYM) and attach the dcphy
2251 if (DC_IS_INTEL(sc)) {
2252 dc_apply_fixup(sc, IFM_AUTO);
2254 sc->dc_pmode = DC_PMODE_MII;
2258 * Setup General Purpose port mode and data so the tulip can talk
2259 * to the MII. This needs to be done before mii_attach so that
2260 * we can actually see them.
2262 if (DC_IS_XIRCOM(sc)) {
2263 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2264 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2266 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2267 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2273 * Note: both the AL981 and AN983 have internal PHYs, however the
2274 * AL981 provides direct access to the PHY registers while the AN983
2275 * uses a serial MII interface. The AN983's MII interface is also
2276 * buggy in that you can read from any MII address (0 to 31), but
2277 * only address 1 behaves normally. To deal with both cases, we
2278 * pretend that the PHY is at MII address 1.
2280 if (DC_IS_ADMTEK(sc))
2281 phy = DC_ADMTEK_PHYADDR;
2284 * Note: the ukphy probes of the RS7112 report a PHY at MII address
2285 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the
2288 if (DC_IS_CONEXANT(sc))
2289 phy = DC_CONEXANT_PHYADDR;
2291 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2292 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
2294 if (error && DC_IS_INTEL(sc)) {
2296 if (sc->dc_pmode != DC_PMODE_SIA)
2297 sc->dc_pmode = DC_PMODE_SYM;
2298 sc->dc_flags |= DC_21143_NWAY;
2299 mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2300 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
2303 * For non-MII cards, we need to have the 21143
2304 * drive the LEDs. Except there are some systems
2305 * like the NEC VersaPro NoteBook PC which have no
2306 * LEDs, and twiddling these bits has adverse effects
2307 * on them. (I.e. you suddenly can't get a link.)
2309 if (!(pci_get_subvendor(dev) == 0x1033 &&
2310 pci_get_subdevice(dev) == 0x8028))
2311 sc->dc_flags |= DC_TULIP_LEDS;
2316 device_printf(dev, "attaching PHYs failed\n");
2320 if (DC_IS_ADMTEK(sc)) {
2322 * Set automatic TX underrun recovery for the ADMtek chips
2324 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2328 * Tell the upper layer(s) we support long frames.
2330 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2331 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2332 ifp->if_capenable = ifp->if_capabilities;
2333 #ifdef DEVICE_POLLING
2334 ifp->if_capabilities |= IFCAP_POLLING;
2337 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2338 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0);
2341 * Call MI attach routine.
2343 ether_ifattach(ifp, (caddr_t)eaddr);
2345 /* Hook interrupt last to avoid having to lock softc */
2346 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2347 NULL, dc_intr, sc, &sc->dc_intrhand);
2350 device_printf(dev, "couldn't set up irq\n");
2351 ether_ifdetach(ifp);
2362 * Shutdown hardware and free up resources. This can be called any
2363 * time after the mutex has been initialized. It is called in both
2364 * the error case in attach and the normal detach case so it needs
2365 * to be careful about only freeing resources that have actually been
2369 dc_detach(device_t dev)
2371 struct dc_softc *sc;
2373 struct dc_mediainfo *m;
2375 sc = device_get_softc(dev);
2376 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2380 #ifdef DEVICE_POLLING
2381 if (ifp->if_capenable & IFCAP_POLLING)
2382 ether_poll_deregister(ifp);
2385 /* These should only be active if attach succeeded */
2386 if (device_is_attached(dev)) {
2390 callout_drain(&sc->dc_stat_ch);
2391 callout_drain(&sc->dc_wdog_ch);
2392 ether_ifdetach(ifp);
2395 device_delete_child(dev, sc->dc_miibus);
2396 bus_generic_detach(dev);
2398 if (sc->dc_intrhand)
2399 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2401 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2403 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2410 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2412 while (sc->dc_mi != NULL) {
2413 m = sc->dc_mi->dc_next;
2414 free(sc->dc_mi, M_DEVBUF);
2417 free(sc->dc_srom, M_DEVBUF);
2419 mtx_destroy(&sc->dc_mtx);
2425 * Initialize the transmit descriptors.
2428 dc_list_tx_init(struct dc_softc *sc)
2430 struct dc_chain_data *cd;
2431 struct dc_list_data *ld;
2436 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2437 if (i == DC_TX_LIST_CNT - 1)
2441 ld->dc_tx_list[i].dc_status = 0;
2442 ld->dc_tx_list[i].dc_ctl = 0;
2443 ld->dc_tx_list[i].dc_data = 0;
2444 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2445 cd->dc_tx_chain[i] = NULL;
2448 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2450 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
2451 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2457 * Initialize the RX descriptors and allocate mbufs for them. Note that
2458 * we arrange the descriptors in a closed ring, so that the last descriptor
2459 * points back to the first.
2462 dc_list_rx_init(struct dc_softc *sc)
2464 struct dc_chain_data *cd;
2465 struct dc_list_data *ld;
2471 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2472 if (dc_newbuf(sc, i) != 0)
2474 if (i == DC_RX_LIST_CNT - 1)
2478 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2482 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2488 * Initialize an RX descriptor and attach an MBUF cluster.
2491 dc_newbuf(struct dc_softc *sc, int i)
2495 bus_dma_segment_t segs[1];
2498 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2501 m->m_len = m->m_pkthdr.len = MCLBYTES;
2502 m_adj(m, sizeof(u_int64_t));
2505 * If this is a PNIC chip, zero the buffer. This is part
2506 * of the workaround for the receive bug in the 82c168 and
2509 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2510 bzero(mtod(m, char *), m->m_len);
2512 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap,
2518 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__,
2520 if (sc->dc_cdata.dc_rx_chain[i] != NULL)
2521 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]);
2523 map = sc->dc_cdata.dc_rx_map[i];
2524 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2525 sc->dc_sparemap = map;
2526 sc->dc_cdata.dc_rx_chain[i] = m;
2527 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
2528 BUS_DMASYNC_PREREAD);
2530 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2531 sc->dc_ldata.dc_rx_list[i].dc_data =
2532 htole32(DC_ADDR_LO(segs[0].ds_addr));
2533 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2534 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2535 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2541 * The PNIC chip has a terrible bug in it that manifests itself during
2542 * periods of heavy activity. The exact mode of failure if difficult to
2543 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2544 * will happen on slow machines. The bug is that sometimes instead of
2545 * uploading one complete frame during reception, it uploads what looks
2546 * like the entire contents of its FIFO memory. The frame we want is at
2547 * the end of the whole mess, but we never know exactly how much data has
2548 * been uploaded, so salvaging the frame is hard.
2550 * There is only one way to do it reliably, and it's disgusting.
2551 * Here's what we know:
2553 * - We know there will always be somewhere between one and three extra
2554 * descriptors uploaded.
2556 * - We know the desired received frame will always be at the end of the
2557 * total data upload.
2559 * - We know the size of the desired received frame because it will be
2560 * provided in the length field of the status word in the last descriptor.
2562 * Here's what we do:
2564 * - When we allocate buffers for the receive ring, we bzero() them.
2565 * This means that we know that the buffer contents should be all
2566 * zeros, except for data uploaded by the chip.
2568 * - We also force the PNIC chip to upload frames that include the
2569 * ethernet CRC at the end.
2571 * - We gather all of the bogus frame data into a single buffer.
2573 * - We then position a pointer at the end of this buffer and scan
2574 * backwards until we encounter the first non-zero byte of data.
2575 * This is the end of the received frame. We know we will encounter
2576 * some data at the end of the frame because the CRC will always be
2577 * there, so even if the sender transmits a packet of all zeros,
2578 * we won't be fooled.
2580 * - We know the size of the actual received frame, so we subtract
2581 * that value from the current pointer location. This brings us
2582 * to the start of the actual received packet.
2584 * - We copy this into an mbuf and pass it on, along with the actual
2587 * The performance hit is tremendous, but it beats dropping frames all
2591 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2593 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2595 struct dc_desc *cur_rx;
2596 struct dc_desc *c = NULL;
2597 struct mbuf *m = NULL;
2600 uint32_t rxstat = 0;
2602 i = sc->dc_pnic_rx_bug_save;
2603 cur_rx = &sc->dc_ldata.dc_rx_list[idx];
2604 ptr = sc->dc_pnic_rx_buf;
2605 bzero(ptr, DC_RXLEN * 5);
2607 /* Copy all the bytes from the bogus buffers. */
2609 c = &sc->dc_ldata.dc_rx_list[i];
2610 rxstat = le32toh(c->dc_status);
2611 m = sc->dc_cdata.dc_rx_chain[i];
2612 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2614 /* If this is the last buffer, break out. */
2615 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2617 dc_discard_rxbuf(sc, i);
2618 DC_INC(i, DC_RX_LIST_CNT);
2621 /* Find the length of the actual receive frame. */
2622 total_len = DC_RXBYTES(rxstat);
2624 /* Scan backwards until we hit a non-zero byte. */
2625 while (*ptr == 0x00)
2629 if ((uintptr_t)(ptr) & 0x3)
2632 /* Now find the start of the frame. */
2634 if (ptr < sc->dc_pnic_rx_buf)
2635 ptr = sc->dc_pnic_rx_buf;
2638 * Now copy the salvaged frame to the last mbuf and fake up
2639 * the status word to make it look like a successful
2642 bcopy(ptr, mtod(m, char *), total_len);
2643 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2647 * This routine searches the RX ring for dirty descriptors in the
2648 * event that the rxeof routine falls out of sync with the chip's
2649 * current descriptor pointer. This may happen sometimes as a result
2650 * of a "no RX buffer available" condition that happens when the chip
2651 * consumes all of the RX buffers before the driver has a chance to
2652 * process the RX ring. This routine may need to be called more than
2653 * once to bring the driver back in sync with the chip, however we
2654 * should still be getting RX DONE interrupts to drive the search
2655 * for new packets in the RX ring, so we should catch up eventually.
2658 dc_rx_resync(struct dc_softc *sc)
2660 struct dc_desc *cur_rx;
2663 pos = sc->dc_cdata.dc_rx_prod;
2665 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2666 cur_rx = &sc->dc_ldata.dc_rx_list[pos];
2667 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2669 DC_INC(pos, DC_RX_LIST_CNT);
2672 /* If the ring really is empty, then just return. */
2673 if (i == DC_RX_LIST_CNT)
2676 /* We've fallen behing the chip: catch it. */
2677 sc->dc_cdata.dc_rx_prod = pos;
2683 dc_discard_rxbuf(struct dc_softc *sc, int i)
2687 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2688 m = sc->dc_cdata.dc_rx_chain[i];
2689 bzero(mtod(m, char *), m->m_len);
2692 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2693 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2694 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD |
2695 BUS_DMASYNC_PREWRITE);
2699 * A frame has been uploaded: pass the resulting mbuf chain up to
2700 * the higher level protocols.
2703 dc_rxeof(struct dc_softc *sc)
2707 struct dc_desc *cur_rx;
2708 int i, total_len, rx_npkts;
2716 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD |
2717 BUS_DMASYNC_POSTWRITE);
2718 for (i = sc->dc_cdata.dc_rx_prod;
2719 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
2720 DC_INC(i, DC_RX_LIST_CNT)) {
2721 #ifdef DEVICE_POLLING
2722 if (ifp->if_capenable & IFCAP_POLLING) {
2723 if (sc->rxcycles <= 0)
2728 cur_rx = &sc->dc_ldata.dc_rx_list[i];
2729 rxstat = le32toh(cur_rx->dc_status);
2730 if ((rxstat & DC_RXSTAT_OWN) != 0)
2732 m = sc->dc_cdata.dc_rx_chain[i];
2733 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
2734 BUS_DMASYNC_POSTREAD);
2735 total_len = DC_RXBYTES(rxstat);
2738 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2739 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2740 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2741 sc->dc_pnic_rx_bug_save = i;
2742 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0)
2744 dc_pnic_rx_bug_war(sc, i);
2745 rxstat = le32toh(cur_rx->dc_status);
2746 total_len = DC_RXBYTES(rxstat);
2751 * If an error occurs, update stats, clear the
2752 * status word and leave the mbuf cluster in place:
2753 * it should simply get re-used next time this descriptor
2754 * comes up in the ring. However, don't report long
2755 * frames as errors since they could be vlans.
2757 if ((rxstat & DC_RXSTAT_RXERR)) {
2758 if (!(rxstat & DC_RXSTAT_GIANT) ||
2759 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2760 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2761 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2763 if (rxstat & DC_RXSTAT_COLLSEEN)
2764 ifp->if_collisions++;
2765 dc_discard_rxbuf(sc, i);
2766 if (rxstat & DC_RXSTAT_CRCERR)
2769 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2776 /* No errors; receive the packet. */
2777 total_len -= ETHER_CRC_LEN;
2778 #ifdef __NO_STRICT_ALIGNMENT
2780 * On architectures without alignment problems we try to
2781 * allocate a new buffer for the receive ring, and pass up
2782 * the one where the packet is already, saving the expensive
2783 * copy done in m_devget().
2784 * If we are on an architecture with alignment problems, or
2785 * if the allocation fails, then use m_devget and leave the
2786 * existing buffer in the receive ring.
2788 if (dc_newbuf(sc, i) != 0) {
2789 dc_discard_rxbuf(sc, i);
2793 m->m_pkthdr.rcvif = ifp;
2794 m->m_pkthdr.len = m->m_len = total_len;
2799 m0 = m_devget(mtod(m, char *), total_len,
2800 ETHER_ALIGN, ifp, NULL);
2801 dc_discard_rxbuf(sc, i);
2812 (*ifp->if_input)(ifp, m);
2816 sc->dc_cdata.dc_rx_prod = i;
2821 * A frame was downloaded to the chip. It's safe for us to clean up
2825 dc_txeof(struct dc_softc *sc)
2827 struct dc_desc *cur_tx;
2830 uint32_t ctl, txstat;
2832 if (sc->dc_cdata.dc_tx_cnt == 0)
2838 * Go through our tx list and free mbufs for those
2839 * frames that have been transmitted.
2841 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD |
2842 BUS_DMASYNC_POSTWRITE);
2844 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod;
2845 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) {
2846 cur_tx = &sc->dc_ldata.dc_tx_list[idx];
2847 txstat = le32toh(cur_tx->dc_status);
2848 ctl = le32toh(cur_tx->dc_ctl);
2850 if (txstat & DC_TXSTAT_OWN)
2853 if (sc->dc_cdata.dc_tx_chain[idx] == NULL)
2856 if (ctl & DC_TXCTL_SETUP) {
2857 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP);
2859 bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
2860 BUS_DMASYNC_POSTWRITE);
2862 * Yes, the PNIC is so brain damaged
2863 * that it will sometimes generate a TX
2864 * underrun error while DMAing the RX
2865 * filter setup frame. If we detect this,
2866 * we have to send the setup frame again,
2867 * or else the filter won't be programmed
2870 if (DC_IS_PNIC(sc)) {
2871 if (txstat & DC_TXSTAT_ERRSUM)
2874 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2878 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2880 * XXX: Why does my Xircom taunt me so?
2881 * For some reason it likes setting the CARRLOST flag
2882 * even when the carrier is there. wtf?!?
2883 * Who knows, but Conexant chips have the
2884 * same problem. Maybe they took lessons
2887 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2888 sc->dc_pmode == DC_PMODE_MII &&
2889 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2890 DC_TXSTAT_NOCARRIER)))
2891 txstat &= ~DC_TXSTAT_ERRSUM;
2893 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2894 sc->dc_pmode == DC_PMODE_MII &&
2895 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2896 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
2897 txstat &= ~DC_TXSTAT_ERRSUM;
2900 if (txstat & DC_TXSTAT_ERRSUM) {
2902 if (txstat & DC_TXSTAT_EXCESSCOLL)
2903 ifp->if_collisions++;
2904 if (txstat & DC_TXSTAT_LATECOLL)
2905 ifp->if_collisions++;
2906 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2907 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2913 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2915 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
2916 BUS_DMASYNC_POSTWRITE);
2917 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
2918 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2919 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2921 sc->dc_cdata.dc_tx_cons = idx;
2923 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
2924 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2925 if (sc->dc_cdata.dc_tx_cnt == 0)
2926 sc->dc_wdog_timer = 0;
2929 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
2930 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2936 struct dc_softc *sc;
2937 struct mii_data *mii;
2944 mii = device_get_softc(sc->dc_miibus);
2947 * Reclaim transmitted frames for controllers that do
2948 * not generate TX completion interrupt for every frame.
2950 if (sc->dc_flags & DC_TX_USE_TX_INTR)
2953 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2954 if (sc->dc_flags & DC_21143_NWAY) {
2955 r = CSR_READ_4(sc, DC_10BTSTAT);
2956 if (IFM_SUBTYPE(mii->mii_media_active) ==
2957 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2961 if (IFM_SUBTYPE(mii->mii_media_active) ==
2962 IFM_10_T && (r & DC_TSTAT_LS10)) {
2966 if (sc->dc_link == 0)
2970 * For NICs which never report DC_RXSTATE_WAIT, we
2971 * have to bite the bullet...
2973 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
2974 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
2975 sc->dc_cdata.dc_tx_cnt == 0)
2982 * When the init routine completes, we expect to be able to send
2983 * packets right away, and in fact the network code will send a
2984 * gratuitous ARP the moment the init routine marks the interface
2985 * as running. However, even though the MAC may have been initialized,
2986 * there may be a delay of a few seconds before the PHY completes
2987 * autonegotiation and the link is brought up. Any transmissions
2988 * made during that delay will be lost. Dealing with this is tricky:
2989 * we can't just pause in the init routine while waiting for the
2990 * PHY to come ready since that would bring the whole system to
2991 * a screeching halt for several seconds.
2993 * What we do here is prevent the TX start routine from sending
2994 * any packets until a link has been established. After the
2995 * interface has been initialized, the tick routine will poll
2996 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2997 * that time, packets will stay in the send queue, and once the
2998 * link comes up, they will be flushed out to the wire.
3000 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3001 dc_start_locked(ifp);
3003 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
3004 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3006 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3010 * A transmit underrun has occurred. Back off the transmit threshold,
3011 * or switch to store and forward mode if we have to.
3014 dc_tx_underrun(struct dc_softc *sc)
3016 uint32_t netcfg, isr;
3020 netcfg = CSR_READ_4(sc, DC_NETCFG);
3021 device_printf(sc->dc_dev, "TX underrun -- ");
3022 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) {
3023 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) {
3024 printf("using store and forward mode\n");
3025 netcfg |= DC_NETCFG_STORENFWD;
3027 printf("increasing TX threshold\n");
3028 sc->dc_txthresh += DC_TXTHRESH_INC;
3029 netcfg &= ~DC_NETCFG_TX_THRESH;
3030 netcfg |= sc->dc_txthresh;
3033 if (DC_IS_INTEL(sc)) {
3035 * The real 21143 requires that the transmitter be idle
3036 * in order to change the transmit threshold or store
3037 * and forward state.
3039 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON);
3041 for (i = 0; i < DC_TIMEOUT; i++) {
3042 isr = CSR_READ_4(sc, DC_ISR);
3043 if (isr & DC_ISR_TX_IDLE)
3047 if (i == DC_TIMEOUT) {
3048 device_printf(sc->dc_dev,
3049 "%s: failed to force tx to idle state\n",
3055 printf("resetting\n");
3060 CSR_WRITE_4(sc, DC_NETCFG, netcfg);
3061 if (DC_IS_INTEL(sc))
3062 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON);
3064 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3069 #ifdef DEVICE_POLLING
3070 static poll_handler_t dc_poll;
3073 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3075 struct dc_softc *sc = ifp->if_softc;
3080 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3085 sc->rxcycles = count;
3086 rx_npkts = dc_rxeof(sc);
3088 if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
3089 !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3090 dc_start_locked(ifp);
3092 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3095 status = CSR_READ_4(sc, DC_ISR);
3096 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3097 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3103 /* ack what we have */
3104 CSR_WRITE_4(sc, DC_ISR, status);
3106 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3107 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3108 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3110 if (dc_rx_resync(sc))
3113 /* restart transmit unit if necessary */
3114 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3115 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3117 if (status & DC_ISR_TX_UNDERRUN)
3120 if (status & DC_ISR_BUS_ERR) {
3121 if_printf(ifp, "%s: bus error\n", __func__);
3122 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3129 #endif /* DEVICE_POLLING */
3134 struct dc_softc *sc;
3145 status = CSR_READ_4(sc, DC_ISR);
3146 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) {
3151 #ifdef DEVICE_POLLING
3152 if (ifp->if_capenable & IFCAP_POLLING) {
3157 /* Disable interrupts. */
3158 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3160 for (n = 16; n > 0; n--) {
3161 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3163 /* Ack interrupts. */
3164 CSR_WRITE_4(sc, DC_ISR, status);
3166 if (status & DC_ISR_RX_OK) {
3167 if (dc_rxeof(sc) == 0) {
3168 while (dc_rx_resync(sc))
3173 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3176 if (status & DC_ISR_TX_IDLE) {
3178 if (sc->dc_cdata.dc_tx_cnt) {
3179 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3180 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3184 if (status & DC_ISR_TX_UNDERRUN)
3187 if ((status & DC_ISR_RX_WATDOGTIMEO)
3188 || (status & DC_ISR_RX_NOBUF)) {
3189 r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3190 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3191 if (dc_rxeof(sc) == 0) {
3192 while (dc_rx_resync(sc))
3197 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3198 dc_start_locked(ifp);
3200 if (status & DC_ISR_BUS_ERR) {
3201 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3206 status = CSR_READ_4(sc, DC_ISR);
3207 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0)
3211 /* Re-enable interrupts. */
3212 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3213 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3219 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3220 * pointers to the fragment pointers.
3223 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3225 bus_dma_segment_t segs[DC_MAXFRAGS];
3229 int cur, defragged, error, first, frag, i, idx, nseg;
3233 if (sc->dc_flags & DC_TX_COALESCE &&
3234 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) {
3235 m = m_defrag(*m_head, M_DONTWAIT);
3239 * Count the number of frags in this chain to see if we
3240 * need to m_collapse. Since the descriptor list is shared
3241 * by all packets, we'll m_collapse long chains so that they
3242 * do not use up the entire list, even if they would fit.
3245 for (m = *m_head; m != NULL; m = m->m_next)
3247 if (i > DC_TX_LIST_CNT / 4 ||
3248 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <=
3250 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS);
3254 if (defragged != 0) {
3263 idx = sc->dc_cdata.dc_tx_prod;
3264 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3265 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3266 if (error == EFBIG) {
3267 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT,
3268 DC_MAXFRAGS)) == NULL) {
3271 return (defragged != 0 ? error : ENOBUFS);
3274 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3275 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3281 } else if (error != 0)
3283 KASSERT(nseg <= DC_MAXFRAGS,
3284 ("%s: wrong number of segments (%d)", __func__, nseg));
3291 /* Check descriptor overruns. */
3292 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3293 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
3296 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
3297 BUS_DMASYNC_PREWRITE);
3299 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3300 for (i = 0; i < nseg; i++) {
3301 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3302 (frag == (DC_TX_LIST_CNT - 1)) &&
3303 (first != sc->dc_cdata.dc_tx_first)) {
3304 bus_dmamap_unload(sc->dc_tx_mtag,
3305 sc->dc_cdata.dc_tx_map[first]);
3311 f = &sc->dc_ldata.dc_tx_list[frag];
3312 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3315 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3317 f->dc_status = htole32(DC_TXSTAT_OWN);
3318 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr));
3320 DC_INC(frag, DC_TX_LIST_CNT);
3323 sc->dc_cdata.dc_tx_prod = frag;
3324 sc->dc_cdata.dc_tx_cnt += nseg;
3325 sc->dc_cdata.dc_tx_chain[cur] = *m_head;
3326 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3327 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3328 sc->dc_ldata.dc_tx_list[first].dc_ctl |=
3329 htole32(DC_TXCTL_FINT);
3330 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3331 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3332 if (sc->dc_flags & DC_TX_USE_TX_INTR &&
3333 ++sc->dc_cdata.dc_tx_pkts >= 8) {
3334 sc->dc_cdata.dc_tx_pkts = 0;
3335 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3337 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3339 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3340 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3343 * Swap the last and the first dmamaps to ensure the map for
3344 * this transmission is placed at the last descriptor.
3346 map = sc->dc_cdata.dc_tx_map[cur];
3347 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first];
3348 sc->dc_cdata.dc_tx_map[first] = map;
3354 dc_start(struct ifnet *ifp)
3356 struct dc_softc *sc;
3360 dc_start_locked(ifp);
3365 * Main transmit routine
3366 * To avoid having to do mbuf copies, we put pointers to the mbuf data
3367 * regions directly in the transmit lists. We also save a copy of the
3368 * pointers since the transmit list fragment pointers are physical
3372 dc_start_locked(struct ifnet *ifp)
3374 struct dc_softc *sc;
3375 struct mbuf *m_head;
3382 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
3383 IFF_DRV_RUNNING || sc->dc_link == 0)
3386 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3388 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
3390 * If there's no way we can send any packets, return now.
3392 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3393 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3396 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3400 if (dc_encap(sc, &m_head)) {
3403 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3404 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3410 * If there's a BPF listener, bounce a copy of this frame
3413 BPF_MTAP(ifp, m_head);
3418 if (!(sc->dc_flags & DC_TX_POLL))
3419 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3422 * Set a timeout in case the chip goes out to lunch.
3424 sc->dc_wdog_timer = 5;
3431 struct dc_softc *sc = xsc;
3439 dc_init_locked(struct dc_softc *sc)
3441 struct ifnet *ifp = sc->dc_ifp;
3442 struct mii_data *mii;
3443 struct ifmedia *ifm;
3447 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3450 mii = device_get_softc(sc->dc_miibus);
3453 * Cancel pending I/O and free all RX/TX buffers.
3457 if (DC_IS_INTEL(sc)) {
3458 ifm = &mii->mii_media;
3459 dc_apply_fixup(sc, ifm->ifm_media);
3463 * Set cache alignment and burst length.
3465 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3466 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3468 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3470 * Evenly share the bus between receive and transmit process.
3472 if (DC_IS_INTEL(sc))
3473 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3474 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3475 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3477 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3479 if (sc->dc_flags & DC_TX_POLL)
3480 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3481 switch(sc->dc_cachesize) {
3483 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3486 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3489 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3493 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3497 if (sc->dc_flags & DC_TX_STORENFWD)
3498 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3500 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3501 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3503 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3504 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3508 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3509 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3511 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3513 * The app notes for the 98713 and 98715A say that
3514 * in order to have the chips operate properly, a magic
3515 * number must be written to CSR16. Macronix does not
3516 * document the meaning of these bits so there's no way
3517 * to know exactly what they do. The 98713 has a magic
3518 * number all its own; the rest all use a different one.
3520 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3521 if (sc->dc_type == DC_TYPE_98713)
3522 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3524 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3527 if (DC_IS_XIRCOM(sc)) {
3529 * setup General Purpose Port mode and data so the tulip
3530 * can talk to the MII.
3532 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3533 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3535 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3536 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3540 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3541 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3543 /* Init circular RX list. */
3544 if (dc_list_rx_init(sc) == ENOBUFS) {
3545 device_printf(sc->dc_dev,
3546 "initialization failed: no memory for rx buffers\n");
3552 * Init TX descriptors.
3554 dc_list_tx_init(sc);
3557 * Load the address of the RX list.
3559 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3560 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3563 * Enable interrupts.
3565 #ifdef DEVICE_POLLING
3567 * ... but only if we are not polling, and make sure they are off in
3568 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3571 if (ifp->if_capenable & IFCAP_POLLING)
3572 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3575 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3576 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3578 /* Enable transmitter. */
3579 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3582 * If this is an Intel 21143 and we're not using the
3583 * MII port, program the LED control pins so we get
3584 * link and activity indications.
3586 if (sc->dc_flags & DC_TULIP_LEDS) {
3587 CSR_WRITE_4(sc, DC_WATCHDOG,
3588 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3589 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3593 * Load the RX/multicast filter. We do this sort of late
3594 * because the filter programming scheme on the 21143 and
3595 * some clones requires DMAing a setup frame via the TX
3596 * engine, and we need the transmitter enabled for that.
3600 /* Enable receiver. */
3601 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3602 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3604 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3605 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3608 dc_setcfg(sc, sc->dc_if_media);
3610 /* Clear missed frames and overflow counter. */
3611 CSR_READ_4(sc, DC_FRAMESDISCARDED);
3613 /* Don't start the ticker if this is a homePNA link. */
3614 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3617 if (sc->dc_flags & DC_21143_NWAY)
3618 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3620 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3623 sc->dc_wdog_timer = 0;
3624 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3628 * Set media options.
3631 dc_ifmedia_upd(struct ifnet *ifp)
3633 struct dc_softc *sc;
3634 struct mii_data *mii;
3635 struct ifmedia *ifm;
3638 mii = device_get_softc(sc->dc_miibus);
3641 ifm = &mii->mii_media;
3643 if (DC_IS_INTEL(sc))
3644 dc_setcfg(sc, ifm->ifm_media);
3645 else if (DC_IS_DAVICOM(sc) &&
3646 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3647 dc_setcfg(sc, ifm->ifm_media);
3656 * Report current media status.
3659 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3661 struct dc_softc *sc;
3662 struct mii_data *mii;
3663 struct ifmedia *ifm;
3666 mii = device_get_softc(sc->dc_miibus);
3669 ifm = &mii->mii_media;
3670 if (DC_IS_DAVICOM(sc)) {
3671 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3672 ifmr->ifm_active = ifm->ifm_media;
3673 ifmr->ifm_status = 0;
3678 ifmr->ifm_active = mii->mii_media_active;
3679 ifmr->ifm_status = mii->mii_media_status;
3684 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3686 struct dc_softc *sc = ifp->if_softc;
3687 struct ifreq *ifr = (struct ifreq *)data;
3688 struct mii_data *mii;
3694 if (ifp->if_flags & IFF_UP) {
3695 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3696 (IFF_PROMISC | IFF_ALLMULTI);
3698 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3702 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3706 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3709 sc->dc_if_flags = ifp->if_flags;
3715 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3721 mii = device_get_softc(sc->dc_miibus);
3722 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3725 #ifdef DEVICE_POLLING
3726 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3727 !(ifp->if_capenable & IFCAP_POLLING)) {
3728 error = ether_poll_register(dc_poll, ifp);
3732 /* Disable interrupts */
3733 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3734 ifp->if_capenable |= IFCAP_POLLING;
3738 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3739 ifp->if_capenable & IFCAP_POLLING) {
3740 error = ether_poll_deregister(ifp);
3741 /* Enable interrupts. */
3743 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3744 ifp->if_capenable &= ~IFCAP_POLLING;
3748 #endif /* DEVICE_POLLING */
3751 error = ether_ioctl(ifp, command, data);
3759 dc_watchdog(void *xsc)
3761 struct dc_softc *sc = xsc;
3766 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) {
3767 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3773 device_printf(sc->dc_dev, "watchdog timeout\n");
3775 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3778 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3779 dc_start_locked(ifp);
3783 * Stop the adapter and free any mbufs allocated to the
3787 dc_stop(struct dc_softc *sc)
3790 struct dc_list_data *ld;
3791 struct dc_chain_data *cd;
3793 uint32_t ctl, netcfg;
3801 callout_stop(&sc->dc_stat_ch);
3802 callout_stop(&sc->dc_wdog_ch);
3803 sc->dc_wdog_timer = 0;
3806 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3808 netcfg = CSR_READ_4(sc, DC_NETCFG);
3809 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
3810 CSR_WRITE_4(sc, DC_NETCFG,
3811 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3812 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3813 /* Wait the completion of TX/RX SM. */
3814 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
3817 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3818 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3821 * Free data in the RX lists.
3823 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3824 if (cd->dc_rx_chain[i] != NULL) {
3825 bus_dmamap_sync(sc->dc_rx_mtag,
3826 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD);
3827 bus_dmamap_unload(sc->dc_rx_mtag,
3829 m_freem(cd->dc_rx_chain[i]);
3830 cd->dc_rx_chain[i] = NULL;
3833 bzero(ld->dc_rx_list, DC_RX_LIST_SZ);
3834 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
3835 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3838 * Free the TX list buffers.
3840 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3841 if (cd->dc_tx_chain[i] != NULL) {
3842 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
3843 if (ctl & DC_TXCTL_SETUP) {
3844 bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
3845 BUS_DMASYNC_POSTWRITE);
3847 bus_dmamap_sync(sc->dc_tx_mtag,
3848 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE);
3849 bus_dmamap_unload(sc->dc_tx_mtag,
3851 m_freem(cd->dc_tx_chain[i]);
3853 cd->dc_tx_chain[i] = NULL;
3856 bzero(ld->dc_tx_list, DC_TX_LIST_SZ);
3857 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3858 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3862 * Device suspend routine. Stop the interface and save some PCI
3863 * settings in case the BIOS doesn't restore them properly on
3867 dc_suspend(device_t dev)
3869 struct dc_softc *sc;
3871 sc = device_get_softc(dev);
3881 * Device resume routine. Restore some PCI settings in case the BIOS
3882 * doesn't, re-enable busmastering, and restart the interface if
3886 dc_resume(device_t dev)
3888 struct dc_softc *sc;
3891 sc = device_get_softc(dev);
3894 /* reinitialize interface if necessary */
3896 if (ifp->if_flags & IFF_UP)
3906 * Stop all chip I/O so that the kernel's probe routines don't
3907 * get confused by errant DMAs when rebooting.
3910 dc_shutdown(device_t dev)
3912 struct dc_softc *sc;
3914 sc = device_get_softc(dev);
3924 dc_check_multiport(struct dc_softc *sc)
3926 struct dc_softc *dsc;
3932 dc = devclass_find("dc");
3933 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) {
3934 child = devclass_get_device(dc, unit);
3937 if (child == sc->dc_dev)
3939 if (device_get_parent(child) != device_get_parent(sc->dc_dev))
3941 if (unit > device_get_unit(sc->dc_dev))
3943 if (device_is_attached(child) == 0)
3945 dsc = device_get_softc(child);
3946 device_printf(sc->dc_dev,
3947 "Using station address of %s as base\n",
3948 device_get_nameunit(child));
3949 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN);
3950 eaddr = (uint8_t *)sc->dc_eaddr;
3952 /* Prepare SROM to parse again. */
3953 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL &&
3954 sc->dc_romwidth != 0) {
3955 free(sc->dc_srom, M_DEVBUF);
3956 sc->dc_romwidth = dsc->dc_romwidth;
3957 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth),
3958 M_DEVBUF, M_NOWAIT);
3959 if (sc->dc_srom == NULL) {
3960 device_printf(sc->dc_dev,
3961 "Could not allocate SROM buffer\n");
3964 bcopy(dsc->dc_srom, sc->dc_srom,
3965 DC_ROM_SIZE(sc->dc_romwidth));