sys/dev/e1000/e1000_80003es2lan.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  37  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  38  */
  39
  40 #include "e1000_api.h"
  41
  42 static s32  e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
  43 static s32  e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
  44 static s32  e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
  45 static s32  e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
  46 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
  47 static s32  e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
  48 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
  49 static s32  e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  50                                                    u32 offset,
  51                                                    u16 *data);
  52 static s32  e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  53                                                     u32 offset,
  54                                                     u16 data);
  55 static s32  e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
  56                                         u16 words, u16 *data);
  57 static s32  e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
  58 static s32  e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
  59 static s32  e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
  60 static s32  e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
  61                                                u16 *duplex);
  62 static s32  e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
  63 static s32  e1000_init_hw_80003es2lan(struct e1000_hw *hw);
  64 static s32  e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  65 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  66 static s32  e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  67 static s32  e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  68 static s32  e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  69 static s32  e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
  70 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  71                                             u16 *data);
  72 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  73                                              u16 data);
  74 static s32  e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
  75 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  76 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  77 static s32  e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
  78 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
  79
  80 /*
  81  * A table for the GG82563 cable length where the range is defined
  82  * with a lower bound at "index" and the upper bound at
  83  * "index + 5".
  84  */
  85 static const u16 e1000_gg82563_cable_length_table[] = {
  86         0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
  87 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
  88                 (sizeof(e1000_gg82563_cable_length_table) / \
  89                  sizeof(e1000_gg82563_cable_length_table[0]))
  90
  91 /**
  92  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  93  *  @hw: pointer to the HW structure
  94  **/
  95 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  96 {
  97         struct e1000_phy_info *phy = &hw->phy;
  98         s32 ret_val = E1000_SUCCESS;
  99
 100         DEBUGFUNC("e1000_init_phy_params_80003es2lan");
 101
 102         if (hw->phy.media_type != e1000_media_type_copper) {
 103                 phy->type        = e1000_phy_none;
 104                 goto out;
 105         } else {
 106                 phy->ops.power_up = e1000_power_up_phy_copper;
 107                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 108         }
 109
 110         phy->addr                = 1;
 111         phy->autoneg_mask        = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 112         phy->reset_delay_us      = 100;
 113         phy->type                = e1000_phy_gg82563;
 114
 115         phy->ops.acquire            = e1000_acquire_phy_80003es2lan;
 116         phy->ops.check_polarity     = e1000_check_polarity_m88;
 117         phy->ops.check_reset_block  = e1000_check_reset_block_generic;
 118         phy->ops.commit             = e1000_phy_sw_reset_generic;
 119         phy->ops.get_cfg_done       = e1000_get_cfg_done_80003es2lan;
 120         phy->ops.get_info           = e1000_get_phy_info_m88;
 121         phy->ops.release            = e1000_release_phy_80003es2lan;
 122         phy->ops.reset              = e1000_phy_hw_reset_generic;
 123         phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_generic;
 124
 125         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
 126         phy->ops.get_cable_length   = e1000_get_cable_length_80003es2lan;
 127         phy->ops.read_reg           = e1000_read_phy_reg_gg82563_80003es2lan;
 128         phy->ops.write_reg          = e1000_write_phy_reg_gg82563_80003es2lan;
 129
 130         phy->ops.cfg_on_link_up    = e1000_cfg_on_link_up_80003es2lan;
 131
 132         /* This can only be done after all function pointers are setup. */
 133         ret_val = e1000_get_phy_id(hw);
 134
 135         /* Verify phy id */
 136         if (phy->id != GG82563_E_PHY_ID) {
 137                 ret_val = -E1000_ERR_PHY;
 138                 goto out;
 139         }
 140
 141 out:
 142         return ret_val;
 143 }
 144
 145 /**
 146  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 147  *  @hw: pointer to the HW structure
 148  **/
 149 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 150 {
 151         struct e1000_nvm_info *nvm = &hw->nvm;
 152         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 153         u16 size;
 154
 155         DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
 156
 157         nvm->opcode_bits        = 8;
 158         nvm->delay_usec         = 1;
 159         switch (nvm->override) {
 160         case e1000_nvm_override_spi_large:
 161                 nvm->page_size    = 32;
 162                 nvm->address_bits = 16;
 163                 break;
 164         case e1000_nvm_override_spi_small:
 165                 nvm->page_size    = 8;
 166                 nvm->address_bits = 8;
 167                 break;
 168         default:
 169                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 170                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 171                 break;
 172         }
 173
 174         nvm->type = e1000_nvm_eeprom_spi;
 175
 176         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 177                           E1000_EECD_SIZE_EX_SHIFT);
 178
 179         /*
 180          * Added to a constant, "size" becomes the left-shift value
 181          * for setting word_size.
 182          */
 183         size += NVM_WORD_SIZE_BASE_SHIFT;
 184
 185         /* EEPROM access above 16k is unsupported */
 186         if (size > 14)
 187                 size = 14;
 188         nvm->word_size  = 1 << size;
 189
 190         /* Function Pointers */
 191         nvm->ops.acquire           = e1000_acquire_nvm_80003es2lan;
 192         nvm->ops.read              = e1000_read_nvm_eerd;
 193         nvm->ops.release           = e1000_release_nvm_80003es2lan;
 194         nvm->ops.update            = e1000_update_nvm_checksum_generic;
 195         nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 196         nvm->ops.validate          = e1000_validate_nvm_checksum_generic;
 197         nvm->ops.write             = e1000_write_nvm_80003es2lan;
 198
 199         return E1000_SUCCESS;
 200 }
 201
 202 /**
 203  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 204  *  @hw: pointer to the HW structure
 205  **/
 206 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 207 {
 208         struct e1000_mac_info *mac = &hw->mac;
 209
 210         DEBUGFUNC("e1000_init_mac_params_80003es2lan");
 211
 212         /* Set media type and media-dependent function pointers */
 213         switch (hw->device_id) {
 214         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 215                 hw->phy.media_type = e1000_media_type_internal_serdes;
 216                 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
 217                 mac->ops.setup_physical_interface =
 218                         e1000_setup_fiber_serdes_link_generic;
 219                 break;
 220         default:
 221                 hw->phy.media_type = e1000_media_type_copper;
 222                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 223                 mac->ops.setup_physical_interface =
 224                         e1000_setup_copper_link_80003es2lan;
 225                 break;
 226         }
 227
 228         /* Set mta register count */
 229         mac->mta_reg_count = 128;
 230         /* Set rar entry count */
 231         mac->rar_entry_count = E1000_RAR_ENTRIES;
 232         /* Set if part includes ASF firmware */
 233         mac->asf_firmware_present = TRUE;
 234         /* FWSM register */
 235         mac->has_fwsm = TRUE;
 236         /* ARC supported; valid only if manageability features are enabled. */
 237         mac->arc_subsystem_valid =
 238                 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 239                         ? TRUE : FALSE;
 240         /* Adaptive IFS not supported */
 241         mac->adaptive_ifs = FALSE;
 242
 243         /* Function pointers */
 244
 245         /* bus type/speed/width */
 246         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 247         /* reset */
 248         mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
 249         /* hw initialization */
 250         mac->ops.init_hw = e1000_init_hw_80003es2lan;
 251         /* link setup */
 252         mac->ops.setup_link = e1000_setup_link_generic;
 253         /* check management mode */
 254         mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 255         /* multicast address update */
 256         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 257         /* writing VFTA */
 258         mac->ops.write_vfta = e1000_write_vfta_generic;
 259         /* clearing VFTA */
 260         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 261         /* read mac address */
 262         mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
 263         /* ID LED init */
 264         mac->ops.id_led_init = e1000_id_led_init_generic;
 265         /* blink LED */
 266         mac->ops.blink_led = e1000_blink_led_generic;
 267         /* setup LED */
 268         mac->ops.setup_led = e1000_setup_led_generic;
 269         /* cleanup LED */
 270         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 271         /* turn on/off LED */
 272         mac->ops.led_on = e1000_led_on_generic;
 273         mac->ops.led_off = e1000_led_off_generic;
 274         /* clear hardware counters */
 275         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
 276         /* link info */
 277         mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
 278
 279         /* set lan id for port to determine which phy lock to use */
 280         hw->mac.ops.set_lan_id(hw);
 281
 282         return E1000_SUCCESS;
 283 }
 284
 285 /**
 286  *  e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
 287  *  @hw: pointer to the HW structure
 288  *
 289  *  Called to initialize all function pointers and parameters.
 290  **/
 291 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
 292 {
 293         DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
 294
 295         hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
 296         hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
 297         hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
 298 }
 299
 300 /**
 301  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 302  *  @hw: pointer to the HW structure
 303  *
 304  *  A wrapper to acquire access rights to the correct PHY.
 305  **/
 306 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 307 {
 308         u16 mask;
 309
 310         DEBUGFUNC("e1000_acquire_phy_80003es2lan");
 311
 312         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 313         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 314 }
 315
 316 /**
 317  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 318  *  @hw: pointer to the HW structure
 319  *
 320  *  A wrapper to release access rights to the correct PHY.
 321  **/
 322 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 323 {
 324         u16 mask;
 325
 326         DEBUGFUNC("e1000_release_phy_80003es2lan");
 327
 328         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 329         e1000_release_swfw_sync_80003es2lan(hw, mask);
 330 }
 331
 332 /**
 333  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
 334  *  @hw: pointer to the HW structure
 335  *
 336  *  Acquire the semaphore to access the Kumeran interface.
 337  *
 338  **/
 339 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 340 {
 341         u16 mask;
 342
 343         DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
 344
 345         mask = E1000_SWFW_CSR_SM;
 346
 347         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 348 }
 349
 350 /**
 351  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
 352  *  @hw: pointer to the HW structure
 353  *
 354  *  Release the semaphore used to access the Kumeran interface
 355  **/
 356 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 357 {
 358         u16 mask;
 359
 360         DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
 361
 362         mask = E1000_SWFW_CSR_SM;
 363
 364         e1000_release_swfw_sync_80003es2lan(hw, mask);
 365 }
 366
 367 /**
 368  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 369  *  @hw: pointer to the HW structure
 370  *
 371  *  Acquire the semaphore to access the EEPROM.
 372  **/
 373 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 374 {
 375         s32 ret_val;
 376
 377         DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
 378
 379         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 380         if (ret_val)
 381                 goto out;
 382
 383         ret_val = e1000_acquire_nvm_generic(hw);
 384
 385         if (ret_val)
 386                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 387
 388 out:
 389         return ret_val;
 390 }
 391
 392 /**
 393  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 394  *  @hw: pointer to the HW structure
 395  *
 396  *  Release the semaphore used to access the EEPROM.
 397  **/
 398 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 399 {
 400         DEBUGFUNC("e1000_release_nvm_80003es2lan");
 401
 402         e1000_release_nvm_generic(hw);
 403         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 404 }
 405
 406 /**
 407  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 408  *  @hw: pointer to the HW structure
 409  *  @mask: specifies which semaphore to acquire
 410  *
 411  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 412  *  will also specify which port we're acquiring the lock for.
 413  **/
 414 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 415 {
 416         u32 swfw_sync;
 417         u32 swmask = mask;
 418         u32 fwmask = mask << 16;
 419         s32 ret_val = E1000_SUCCESS;
 420         s32 i = 0, timeout = 50;
 421
 422         DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
 423
 424         while (i < timeout) {
 425                 if (e1000_get_hw_semaphore_generic(hw)) {
 426                         ret_val = -E1000_ERR_SWFW_SYNC;
 427                         goto out;
 428                 }
 429
 430                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 431                 if (!(swfw_sync & (fwmask | swmask)))
 432                         break;
 433
 434                 /*
 435                  * Firmware currently using resource (fwmask)
 436                  * or other software thread using resource (swmask)
 437                  */
 438                 e1000_put_hw_semaphore_generic(hw);
 439                 msec_delay_irq(5);
 440                 i++;
 441         }
 442
 443         if (i == timeout) {
 444                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
 445                 ret_val = -E1000_ERR_SWFW_SYNC;
 446                 goto out;
 447         }
 448
 449         swfw_sync |= swmask;
 450         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
 451
 452         e1000_put_hw_semaphore_generic(hw);
 453
 454 out:
 455         return ret_val;
 456 }
 457
 458 /**
 459  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 460  *  @hw: pointer to the HW structure
 461  *  @mask: specifies which semaphore to acquire
 462  *
 463  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 464  *  will also specify which port we're releasing the lock for.
 465  **/
 466 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 467 {
 468         u32 swfw_sync;
 469
 470         DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
 471
 472         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
 473                 ; /* Empty */
 474
 475         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 476         swfw_sync &= ~mask;
 477         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
 478
 479         e1000_put_hw_semaphore_generic(hw);
 480 }
 481
 482 /**
 483  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 484  *  @hw: pointer to the HW structure
 485  *  @offset: offset of the register to read
 486  *  @data: pointer to the data returned from the operation
 487  *
 488  *  Read the GG82563 PHY register.
 489  **/
 490 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 491                                                   u32 offset, u16 *data)
 492 {
 493         s32 ret_val;
 494         u32 page_select;
 495         u16 temp;
 496
 497         DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
 498
 499         ret_val = e1000_acquire_phy_80003es2lan(hw);
 500         if (ret_val)
 501                 goto out;
 502
 503         /* Select Configuration Page */
 504         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 505                 page_select = GG82563_PHY_PAGE_SELECT;
 506         } else {
 507                 /*
 508                  * Use Alternative Page Select register to access
 509                  * registers 30 and 31
 510                  */
 511                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 512         }
 513
 514         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 515         ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
 516         if (ret_val) {
 517                 e1000_release_phy_80003es2lan(hw);
 518                 goto out;
 519         }
 520
 521         if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
 522                 /*
 523                  * The "ready" bit in the MDIC register may be incorrectly set
 524                  * before the device has completed the "Page Select" MDI
 525                  * transaction.  So we wait 200us after each MDI command...
 526                  */
 527                 usec_delay(200);
 528
 529                 /* ...and verify the command was successful. */
 530                 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
 531
 532                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 533                         ret_val = -E1000_ERR_PHY;
 534                         e1000_release_phy_80003es2lan(hw);
 535                         goto out;
 536                 }
 537
 538                 usec_delay(200);
 539
 540                 ret_val = e1000_read_phy_reg_mdic(hw,
 541                                                   MAX_PHY_REG_ADDRESS & offset,
 542                                                   data);
 543
 544                 usec_delay(200);
 545         } else {
 546                 ret_val = e1000_read_phy_reg_mdic(hw,
 547                                                   MAX_PHY_REG_ADDRESS & offset,
 548                                                   data);
 549         }
 550
 551         e1000_release_phy_80003es2lan(hw);
 552
 553 out:
 554         return ret_val;
 555 }
 556
 557 /**
 558  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 559  *  @hw: pointer to the HW structure
 560  *  @offset: offset of the register to read
 561  *  @data: value to write to the register
 562  *
 563  *  Write to the GG82563 PHY register.
 564  **/
 565 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 566                                                    u32 offset, u16 data)
 567 {
 568         s32 ret_val;
 569         u32 page_select;
 570         u16 temp;
 571
 572         DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
 573
 574         ret_val = e1000_acquire_phy_80003es2lan(hw);
 575         if (ret_val)
 576                 goto out;
 577
 578         /* Select Configuration Page */
 579         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 580                 page_select = GG82563_PHY_PAGE_SELECT;
 581         } else {
 582                 /*
 583                  * Use Alternative Page Select register to access
 584                  * registers 30 and 31
 585                  */
 586                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 587         }
 588
 589         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 590         ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
 591         if (ret_val) {
 592                 e1000_release_phy_80003es2lan(hw);
 593                 goto out;
 594         }
 595
 596         if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
 597                 /*
 598                  * The "ready" bit in the MDIC register may be incorrectly set
 599                  * before the device has completed the "Page Select" MDI
 600                  * transaction.  So we wait 200us after each MDI command...
 601                  */
 602                 usec_delay(200);
 603
 604                 /* ...and verify the command was successful. */
 605                 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
 606
 607                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 608                         ret_val = -E1000_ERR_PHY;
 609                         e1000_release_phy_80003es2lan(hw);
 610                         goto out;
 611                 }
 612
 613                 usec_delay(200);
 614
 615                 ret_val = e1000_write_phy_reg_mdic(hw,
 616                                                   MAX_PHY_REG_ADDRESS & offset,
 617                                                   data);
 618
 619                 usec_delay(200);
 620         } else {
 621                 ret_val = e1000_write_phy_reg_mdic(hw,
 622                                                   MAX_PHY_REG_ADDRESS & offset,
 623                                                   data);
 624         }
 625
 626         e1000_release_phy_80003es2lan(hw);
 627
 628 out:
 629         return ret_val;
 630 }
 631
 632 /**
 633  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 634  *  @hw: pointer to the HW structure
 635  *  @offset: offset of the register to read
 636  *  @words: number of words to write
 637  *  @data: buffer of data to write to the NVM
 638  *
 639  *  Write "words" of data to the ESB2 NVM.
 640  **/
 641 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 642                             u16 words, u16 *data)
 643 {
 644         DEBUGFUNC("e1000_write_nvm_80003es2lan");
 645
 646         return e1000_write_nvm_spi(hw, offset, words, data);
 647 }
 648
 649 /**
 650  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 651  *  @hw: pointer to the HW structure
 652  *
 653  *  Wait a specific amount of time for manageability processes to complete.
 654  *  This is a function pointer entry point called by the phy module.
 655  **/
 656 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 657 {
 658         s32 timeout = PHY_CFG_TIMEOUT;
 659         s32 ret_val = E1000_SUCCESS;
 660         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 661
 662         DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
 663
 664         if (hw->bus.func == 1)
 665                 mask = E1000_NVM_CFG_DONE_PORT_1;
 666
 667         while (timeout) {
 668                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
 669                         break;
 670                 msec_delay(1);
 671                 timeout--;
 672         }
 673         if (!timeout) {
 674                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 675                 ret_val = -E1000_ERR_RESET;
 676                 goto out;
 677         }
 678
 679 out:
 680         return ret_val;
 681 }
 682
 683 /**
 684  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 685  *  @hw: pointer to the HW structure
 686  *
 687  *  Force the speed and duplex settings onto the PHY.  This is a
 688  *  function pointer entry point called by the phy module.
 689  **/
 690 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 691 {
 692         s32 ret_val = E1000_SUCCESS;
 693         u16 phy_data;
 694         bool link;
 695
 696         DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
 697
 698         if (!(hw->phy.ops.read_reg))
 699                 goto out;
 700
 701         /*
 702          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 703          * forced whenever speed and duplex are forced.
 704          */
 705         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 706         if (ret_val)
 707                 goto out;
 708
 709         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 710         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 711         if (ret_val)
 712                 goto out;
 713
 714         DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
 715
 716         ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
 717         if (ret_val)
 718                 goto out;
 719
 720         e1000_phy_force_speed_duplex_setup(hw, &phy_data);
 721
 722         /* Reset the phy to commit changes. */
 723         phy_data |= MII_CR_RESET;
 724
 725         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
 726         if (ret_val)
 727                 goto out;
 728
 729         usec_delay(1);
 730
 731         if (hw->phy.autoneg_wait_to_complete) {
 732                 DEBUGOUT("Waiting for forced speed/duplex link "
 733                          "on GG82563 phy.\n");
 734
 735                 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 736                                                      100000, &link);
 737                 if (ret_val)
 738                         goto out;
 739
 740                 if (!link) {
 741                         /*
 742                          * We didn't get link.
 743                          * Reset the DSP and cross our fingers.
 744                          */
 745                         ret_val = e1000_phy_reset_dsp_generic(hw);
 746                         if (ret_val)
 747                                 goto out;
 748                 }
 749
 750                 /* Try once more */
 751                 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 752                                                      100000, &link);
 753                 if (ret_val)
 754                         goto out;
 755         }
 756
 757         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 758         if (ret_val)
 759                 goto out;
 760
 761         /*
 762          * Resetting the phy means we need to verify the TX_CLK corresponds
 763          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 764          */
 765         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 766         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 767                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 768         else
 769                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 770
 771         /*
 772          * In addition, we must re-enable CRS on Tx for both half and full
 773          * duplex.
 774          */
 775         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 776         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 777
 778 out:
 779         return ret_val;
 780 }
 781
 782 /**
 783  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 784  *  @hw: pointer to the HW structure
 785  *
 786  *  Find the approximate cable length as measured by the GG82563 PHY.
 787  *  This is a function pointer entry point called by the phy module.
 788  **/
 789 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 790 {
 791         struct e1000_phy_info *phy = &hw->phy;
 792         s32 ret_val = E1000_SUCCESS;
 793         u16 phy_data, index;
 794
 795         DEBUGFUNC("e1000_get_cable_length_80003es2lan");
 796
 797         if (!(hw->phy.ops.read_reg))
 798                 goto out;
 799
 800         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 801         if (ret_val)
 802                 goto out;
 803
 804         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 805
 806         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
 807                 ret_val = -E1000_ERR_PHY;
 808                 goto out;
 809         }
 810
 811         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 812         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 813
 814         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 815
 816 out:
 817         return ret_val;
 818 }
 819
 820 /**
 821  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 822  *  @hw: pointer to the HW structure
 823  *  @speed: pointer to speed buffer
 824  *  @duplex: pointer to duplex buffer
 825  *
 826  *  Retrieve the current speed and duplex configuration.
 827  **/
 828 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 829                                               u16 *duplex)
 830 {
 831         s32 ret_val;
 832
 833         DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
 834
 835         if (hw->phy.media_type == e1000_media_type_copper) {
 836                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
 837                                                                     speed,
 838                                                                     duplex);
 839                 hw->phy.ops.cfg_on_link_up(hw);
 840         } else {
 841                 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
 842                                                                   speed,
 843                                                                   duplex);
 844         }
 845
 846         return ret_val;
 847 }
 848
 849 /**
 850  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 851  *  @hw: pointer to the HW structure
 852  *
 853  *  Perform a global reset to the ESB2 controller.
 854  **/
 855 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 856 {
 857         u32 ctrl;
 858         s32 ret_val;
 859
 860         DEBUGFUNC("e1000_reset_hw_80003es2lan");
 861
 862         /*
 863          * Prevent the PCI-E bus from sticking if there is no TLP connection
 864          * on the last TLP read/write transaction when MAC is reset.
 865          */
 866         ret_val = e1000_disable_pcie_master_generic(hw);
 867         if (ret_val)
 868                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
 869
 870         DEBUGOUT("Masking off all interrupts\n");
 871         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 872
 873         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 874         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 875         E1000_WRITE_FLUSH(hw);
 876
 877         msec_delay(10);
 878
 879         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 880
 881         ret_val = e1000_acquire_phy_80003es2lan(hw);
 882         DEBUGOUT("Issuing a global reset to MAC\n");
 883         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 884         e1000_release_phy_80003es2lan(hw);
 885
 886         ret_val = e1000_get_auto_rd_done_generic(hw);
 887         if (ret_val)
 888                 /* We don't want to continue accessing MAC registers. */
 889                 goto out;
 890
 891         /* Clear any pending interrupt events. */
 892         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 893         E1000_READ_REG(hw, E1000_ICR);
 894
 895         ret_val = e1000_check_alt_mac_addr_generic(hw);
 896
 897 out:
 898         return ret_val;
 899 }
 900
 901 /**
 902  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 903  *  @hw: pointer to the HW structure
 904  *
 905  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 906  **/
 907 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 908 {
 909         struct e1000_mac_info *mac = &hw->mac;
 910         u32 reg_data;
 911         s32 ret_val;
 912         u16 kum_reg_data;
 913         u16 i;
 914
 915         DEBUGFUNC("e1000_init_hw_80003es2lan");
 916
 917         e1000_initialize_hw_bits_80003es2lan(hw);
 918
 919         /* Initialize identification LED */
 920         ret_val = mac->ops.id_led_init(hw);
 921         if (ret_val)
 922                 DEBUGOUT("Error initializing identification LED\n");
 923                 /* This is not fatal and we should not stop init due to this */
 924
 925         /* Disabling VLAN filtering */
 926         DEBUGOUT("Initializing the IEEE VLAN\n");
 927         mac->ops.clear_vfta(hw);
 928
 929         /* Setup the receive address. */
 930         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 931
 932         /* Zero out the Multicast HASH table */
 933         DEBUGOUT("Zeroing the MTA\n");
 934         for (i = 0; i < mac->mta_reg_count; i++)
 935                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 936
 937         /* Setup link and flow control */
 938         ret_val = mac->ops.setup_link(hw);
 939
 940         /* Disable IBIST slave mode (far-end loopback) */
 941         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 942                                         &kum_reg_data);
 943         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 944         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 945                                          kum_reg_data);
 946
 947         /* Set the transmit descriptor write-back policy */
 948         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
 949         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 950                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 951         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
 952
 953         /* ...for both queues. */
 954         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
 955         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 956                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 957         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
 958
 959         /* Enable retransmit on late collisions */
 960         reg_data = E1000_READ_REG(hw, E1000_TCTL);
 961         reg_data |= E1000_TCTL_RTLC;
 962         E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
 963
 964         /* Configure Gigabit Carry Extend Padding */
 965         reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
 966         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 967         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 968         E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
 969
 970         /* Configure Transmit Inter-Packet Gap */
 971         reg_data = E1000_READ_REG(hw, E1000_TIPG);
 972         reg_data &= ~E1000_TIPG_IPGT_MASK;
 973         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 974         E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
 975
 976         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 977         reg_data &= ~0x00100000;
 978         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 979
 980         /* default to TRUE to enable the MDIC W/A */
 981         hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
 982
 983         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
 984                                       E1000_KMRNCTRLSTA_OFFSET >>
 985                                       E1000_KMRNCTRLSTA_OFFSET_SHIFT,
 986                                       &i);
 987         if (!ret_val) {
 988                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 989                      E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 990                         hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
 991         }
 992
 993         /*
 994          * Clear all of the statistics registers (clear on read).  It is
 995          * important that we do this after we have tried to establish link
 996          * because the symbol error count will increment wildly if there
 997          * is no link.
 998          */
 999         e1000_clear_hw_cntrs_80003es2lan(hw);
1000
1001         return ret_val;
1002 }
1003
1004 /**
1005  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
1006  *  @hw: pointer to the HW structure
1007  *
1008  *  Initializes required hardware-dependent bits needed for normal operation.
1009  **/
1010 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
1011 {
1012         u32 reg;
1013
1014         DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
1015
1016         /* Transmit Descriptor Control 0 */
1017         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1018         reg |= (1 << 22);
1019         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1020
1021         /* Transmit Descriptor Control 1 */
1022         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1023         reg |= (1 << 22);
1024         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1025
1026         /* Transmit Arbitration Control 0 */
1027         reg = E1000_READ_REG(hw, E1000_TARC(0));
1028         reg &= ~(0xF << 27); /* 30:27 */
1029         if (hw->phy.media_type != e1000_media_type_copper)
1030                 reg &= ~(1 << 20);
1031         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1032
1033         /* Transmit Arbitration Control 1 */
1034         reg = E1000_READ_REG(hw, E1000_TARC(1));
1035         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1036                 reg &= ~(1 << 28);
1037         else
1038                 reg |= (1 << 28);
1039         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1040
1041         return;
1042 }
1043
1044 /**
1045  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
1046  *  @hw: pointer to the HW structure
1047  *
1048  *  Setup some GG82563 PHY registers for obtaining link
1049  **/
1050 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1051 {
1052         struct e1000_phy_info *phy = &hw->phy;
1053         s32 ret_val;
1054         u32 ctrl_ext;
1055         u16 data;
1056
1057         DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1058
1059         if (phy->reset_disable)
1060                 goto skip_reset;
1061
1062         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1063                                      &data);
1064         if (ret_val)
1065                 goto out;
1066
1067         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1068         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1069         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1070
1071         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1072                                       data);
1073         if (ret_val)
1074                 goto out;
1075
1076         /*
1077          * Options:
1078          *   MDI/MDI-X = 0 (default)
1079          *   0 - Auto for all speeds
1080          *   1 - MDI mode
1081          *   2 - MDI-X mode
1082          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1083          */
1084         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1085         if (ret_val)
1086                 goto out;
1087
1088         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1089
1090         switch (phy->mdix) {
1091         case 1:
1092                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1093                 break;
1094         case 2:
1095                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1096                 break;
1097         case 0:
1098         default:
1099                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1100                 break;
1101         }
1102
1103         /*
1104          * Options:
1105          *   disable_polarity_correction = 0 (default)
1106          *       Automatic Correction for Reversed Cable Polarity
1107          *   0 - Disabled
1108          *   1 - Enabled
1109          */
1110         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1111         if (phy->disable_polarity_correction)
1112                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1113
1114         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1115         if (ret_val)
1116                 goto out;
1117
1118         /* SW Reset the PHY so all changes take effect */
1119         ret_val = hw->phy.ops.commit(hw);
1120         if (ret_val) {
1121                 DEBUGOUT("Error Resetting the PHY\n");
1122                 goto out;
1123         }
1124
1125 skip_reset:
1126         /* Bypass Rx and Tx FIFO's */
1127         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1128                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1129                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1130                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1131         if (ret_val)
1132                 goto out;
1133
1134         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1135                                       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1136                                       &data);
1137         if (ret_val)
1138                 goto out;
1139         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1140         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1141                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1142                                        data);
1143         if (ret_val)
1144                 goto out;
1145
1146         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1147         if (ret_val)
1148                 goto out;
1149
1150         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1151         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1152         if (ret_val)
1153                 goto out;
1154
1155         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1156         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1157         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1158
1159         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1160         if (ret_val)
1161                 goto out;
1162
1163         /*
1164          * Do not init these registers when the HW is in IAMT mode, since the
1165          * firmware will have already initialized them.  We only initialize
1166          * them if the HW is not in IAMT mode.
1167          */
1168         if (!(hw->mac.ops.check_mng_mode(hw))) {
1169                 /* Enable Electrical Idle on the PHY */
1170                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1171                 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1172                                                 data);
1173                 if (ret_val)
1174                         goto out;
1175
1176                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1177                                                &data);
1178                 if (ret_val)
1179                         goto out;
1180
1181                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1182                 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1183                                                 data);
1184                 if (ret_val)
1185                         goto out;
1186         }
1187
1188         /*
1189          * Workaround: Disable padding in Kumeran interface in the MAC
1190          * and in the PHY to avoid CRC errors.
1191          */
1192         ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1193         if (ret_val)
1194                 goto out;
1195
1196         data |= GG82563_ICR_DIS_PADDING;
1197         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1198         if (ret_val)
1199                 goto out;
1200
1201 out:
1202         return ret_val;
1203 }
1204
1205 /**
1206  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1207  *  @hw: pointer to the HW structure
1208  *
1209  *  Essentially a wrapper for setting up all things "copper" related.
1210  *  This is a function pointer entry point called by the mac module.
1211  **/
1212 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1213 {
1214         u32 ctrl;
1215         s32 ret_val;
1216         u16 reg_data;
1217
1218         DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1219
1220         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1221         ctrl |= E1000_CTRL_SLU;
1222         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1223         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1224
1225         /*
1226          * Set the mac to wait the maximum time between each
1227          * iteration and increase the max iterations when
1228          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1229          */
1230         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1231                                                    0xFFFF);
1232         if (ret_val)
1233                 goto out;
1234         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1235                                                   &reg_data);
1236         if (ret_val)
1237                 goto out;
1238         reg_data |= 0x3F;
1239         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1240                                                    reg_data);
1241         if (ret_val)
1242                 goto out;
1243         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1244                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1245                                       &reg_data);
1246         if (ret_val)
1247                 goto out;
1248         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1249         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1250                                        E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1251                                        reg_data);
1252         if (ret_val)
1253                 goto out;
1254
1255         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1256         if (ret_val)
1257                 goto out;
1258
1259         ret_val = e1000_setup_copper_link_generic(hw);
1260
1261 out:
1262         return ret_val;
1263 }
1264
1265 /**
1266  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1267  *  @hw: pointer to the HW structure
1268  *  @duplex: current duplex setting
1269  *
1270  *  Configure the KMRN interface by applying last minute quirks for
1271  *  10/100 operation.
1272  **/
1273 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1274 {
1275         s32 ret_val = E1000_SUCCESS;
1276         u16 speed;
1277         u16 duplex;
1278
1279         DEBUGFUNC("e1000_configure_on_link_up");
1280
1281         if (hw->phy.media_type == e1000_media_type_copper) {
1282                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
1283                                                                     &speed,
1284                                                                     &duplex);
1285                 if (ret_val)
1286                         goto out;
1287
1288                 if (speed == SPEED_1000)
1289                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1290                 else
1291                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1292         }
1293
1294 out:
1295         return ret_val;
1296 }
1297
1298 /**
1299  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1300  *  @hw: pointer to the HW structure
1301  *  @duplex: current duplex setting
1302  *
1303  *  Configure the KMRN interface by applying last minute quirks for
1304  *  10/100 operation.
1305  **/
1306 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1307 {
1308         s32 ret_val = E1000_SUCCESS;
1309         u32 tipg;
1310         u32 i = 0;
1311         u16 reg_data, reg_data2;
1312
1313         DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1314
1315         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1316         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1317                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1318                                        reg_data);
1319         if (ret_val)
1320                 goto out;
1321
1322         /* Configure Transmit Inter-Packet Gap */
1323         tipg = E1000_READ_REG(hw, E1000_TIPG);
1324         tipg &= ~E1000_TIPG_IPGT_MASK;
1325         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1326         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1327
1328         do {
1329                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1330                                                &reg_data);
1331                 if (ret_val)
1332                         goto out;
1333
1334                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1335                                                &reg_data2);
1336                 if (ret_val)
1337                         goto out;
1338                 i++;
1339         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1340
1341         if (duplex == HALF_DUPLEX)
1342                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1343         else
1344                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1345
1346         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1347
1348 out:
1349         return ret_val;
1350 }
1351
1352 /**
1353  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1354  *  @hw: pointer to the HW structure
1355  *
1356  *  Configure the KMRN interface by applying last minute quirks for
1357  *  gigabit operation.
1358  **/
1359 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1360 {
1361         s32 ret_val = E1000_SUCCESS;
1362         u16 reg_data, reg_data2;
1363         u32 tipg;
1364         u32 i = 0;
1365
1366         DEBUGFUNC("e1000_configure_kmrn_for_1000");
1367
1368         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1369         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1370                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1371                                        reg_data);
1372         if (ret_val)
1373                 goto out;
1374
1375         /* Configure Transmit Inter-Packet Gap */
1376         tipg = E1000_READ_REG(hw, E1000_TIPG);
1377         tipg &= ~E1000_TIPG_IPGT_MASK;
1378         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1379         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1380
1381         do {
1382                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1383                                                &reg_data);
1384                 if (ret_val)
1385                         goto out;
1386
1387                 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1388                                                &reg_data2);
1389                 if (ret_val)
1390                         goto out;
1391                 i++;
1392         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1393
1394         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1395         ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1396
1397 out:
1398         return ret_val;
1399 }
1400
1401 /**
1402  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1403  *  @hw: pointer to the HW structure
1404  *  @offset: register offset to be read
1405  *  @data: pointer to the read data
1406  *
1407  *  Acquire semaphore, then read the PHY register at offset
1408  *  using the kumeran interface.  The information retrieved is stored in data.
1409  *  Release the semaphore before exiting.
1410  **/
1411 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1412                                            u16 *data)
1413 {
1414         u32 kmrnctrlsta;
1415         s32 ret_val = E1000_SUCCESS;
1416
1417         DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1418
1419         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1420         if (ret_val)
1421                 goto out;
1422
1423         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1424                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1425         E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1426
1427         usec_delay(2);
1428
1429         kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1430         *data = (u16)kmrnctrlsta;
1431
1432         e1000_release_mac_csr_80003es2lan(hw);
1433
1434 out:
1435         return ret_val;
1436 }
1437
1438 /**
1439  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1440  *  @hw: pointer to the HW structure
1441  *  @offset: register offset to write to
1442  *  @data: data to write at register offset
1443  *
1444  *  Acquire semaphore, then write the data to PHY register
1445  *  at the offset using the kumeran interface.  Release semaphore
1446  *  before exiting.
1447  **/
1448 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1449                                             u16 data)
1450 {
1451         u32 kmrnctrlsta;
1452         s32 ret_val = E1000_SUCCESS;
1453
1454         DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1455
1456         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1457         if (ret_val)
1458                 goto out;
1459
1460         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1461                        E1000_KMRNCTRLSTA_OFFSET) | data;
1462         E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1463
1464         usec_delay(2);
1465
1466         e1000_release_mac_csr_80003es2lan(hw);
1467
1468 out:
1469         return ret_val;
1470 }
1471
1472 /**
1473  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1474  *  @hw: pointer to the HW structure
1475  **/
1476 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1477 {
1478         s32 ret_val = E1000_SUCCESS;
1479
1480         DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1481
1482         /*
1483          * If there's an alternate MAC address place it in RAR0
1484          * so that it will override the Si installed default perm
1485          * address.
1486          */
1487         ret_val = e1000_check_alt_mac_addr_generic(hw);
1488         if (ret_val)
1489                 goto out;
1490
1491         ret_val = e1000_read_mac_addr_generic(hw);
1492
1493 out:
1494         return ret_val;
1495 }
1496
1497 /**
1498  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1499  * @hw: pointer to the HW structure
1500  *
1501  * In the case of a PHY power down to save power, or to turn off link during a
1502  * driver unload, or wake on lan is not enabled, remove the link.
1503  **/
1504 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1505 {
1506         /* If the management interface is not enabled, then power down */
1507         if (!(hw->mac.ops.check_mng_mode(hw) ||
1508               hw->phy.ops.check_reset_block(hw)))
1509                 e1000_power_down_phy_copper(hw);
1510
1511         return;
1512 }
1513
1514 /**
1515  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1516  *  @hw: pointer to the HW structure
1517  *
1518  *  Clears the hardware counters by reading the counter registers.
1519  **/
1520 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1521 {
1522         DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1523
1524         e1000_clear_hw_cntrs_base_generic(hw);
1525
1526         E1000_READ_REG(hw, E1000_PRC64);
1527         E1000_READ_REG(hw, E1000_PRC127);
1528         E1000_READ_REG(hw, E1000_PRC255);
1529         E1000_READ_REG(hw, E1000_PRC511);
1530         E1000_READ_REG(hw, E1000_PRC1023);
1531         E1000_READ_REG(hw, E1000_PRC1522);
1532         E1000_READ_REG(hw, E1000_PTC64);
1533         E1000_READ_REG(hw, E1000_PTC127);
1534         E1000_READ_REG(hw, E1000_PTC255);
1535         E1000_READ_REG(hw, E1000_PTC511);
1536         E1000_READ_REG(hw, E1000_PTC1023);
1537         E1000_READ_REG(hw, E1000_PTC1522);
1538
1539         E1000_READ_REG(hw, E1000_ALGNERRC);
1540         E1000_READ_REG(hw, E1000_RXERRC);
1541         E1000_READ_REG(hw, E1000_TNCRS);
1542         E1000_READ_REG(hw, E1000_CEXTERR);
1543         E1000_READ_REG(hw, E1000_TSCTC);
1544         E1000_READ_REG(hw, E1000_TSCTFC);
1545
1546         E1000_READ_REG(hw, E1000_MGTPRC);
1547         E1000_READ_REG(hw, E1000_MGTPDC);
1548         E1000_READ_REG(hw, E1000_MGTPTC);
1549
1550         E1000_READ_REG(hw, E1000_IAC);
1551         E1000_READ_REG(hw, E1000_ICRXOC);
1552
1553         E1000_READ_REG(hw, E1000_ICRXPTC);
1554         E1000_READ_REG(hw, E1000_ICRXATC);
1555         E1000_READ_REG(hw, E1000_ICTXPTC);
1556         E1000_READ_REG(hw, E1000_ICTXATC);
1557         E1000_READ_REG(hw, E1000_ICTXQEC);
1558         E1000_READ_REG(hw, E1000_ICTXQMTC);
1559         E1000_READ_REG(hw, E1000_ICRXDMTC);
1560 }