sys/dev/e1000/e1000_82571.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82571EB Gigabit Ethernet Controller
  37  * 82571EB Gigabit Ethernet Controller (Copper)
  38  * 82571EB Gigabit Ethernet Controller (Fiber)
  39  * 82571EB Dual Port Gigabit Mezzanine Adapter
  40  * 82571EB Quad Port Gigabit Mezzanine Adapter
  41  * 82571PT Gigabit PT Quad Port Server ExpressModule
  42  * 82572EI Gigabit Ethernet Controller (Copper)
  43  * 82572EI Gigabit Ethernet Controller (Fiber)
  44  * 82572EI Gigabit Ethernet Controller
  45  * 82573V Gigabit Ethernet Controller (Copper)
  46  * 82573E Gigabit Ethernet Controller (Copper)
  47  * 82573L Gigabit Ethernet Controller
  48  * 82574L Gigabit Network Connection
  49  * 82583V Gigabit Network Connection
  50  */
  51
  52 #include "e1000_api.h"
  53
  54 static s32  e1000_init_phy_params_82571(struct e1000_hw *hw);
  55 static s32  e1000_init_nvm_params_82571(struct e1000_hw *hw);
  56 static s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
  57 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  58 static void e1000_release_nvm_82571(struct e1000_hw *hw);
  59 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  60                                   u16 words, u16 *data);
  61 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  62 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  63 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  64 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  65                                           bool active);
  66 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  67 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
  68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  71 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
  72 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  73 static s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  74 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  75 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  77 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  78 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  79 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  81 static s32  e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
  82 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  83 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  84 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  85 static s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
  86                                           bool active);
  87 static s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
  88                                           bool active);
  89 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  90 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  91                                        u16 words, u16 *data);
  92 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  93 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  94
  95 /**
  96  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  97  *  @hw: pointer to the HW structure
  98  **/
  99 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
 100 {
 101         struct e1000_phy_info *phy = &hw->phy;
 102         s32 ret_val = E1000_SUCCESS;
 103
 104         DEBUGFUNC("e1000_init_phy_params_82571");
 105
 106         if (hw->phy.media_type != e1000_media_type_copper) {
 107                 phy->type = e1000_phy_none;
 108                 goto out;
 109         }
 110
 111         phy->addr                        = 1;
 112         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 113         phy->reset_delay_us              = 100;
 114
 115         phy->ops.check_reset_block       = e1000_check_reset_block_generic;
 116         phy->ops.reset                   = e1000_phy_hw_reset_generic;
 117         phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
 118         phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
 119         phy->ops.power_up                = e1000_power_up_phy_copper;
 120         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
 121
 122         switch (hw->mac.type) {
 123         case e1000_82571:
 124         case e1000_82572:
 125                 phy->type                   = e1000_phy_igp_2;
 126                 phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
 127                 phy->ops.get_info           = e1000_get_phy_info_igp;
 128                 phy->ops.check_polarity     = e1000_check_polarity_igp;
 129                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 130                 phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
 131                 phy->ops.read_reg           = e1000_read_phy_reg_igp;
 132                 phy->ops.write_reg          = e1000_write_phy_reg_igp;
 133                 phy->ops.acquire            = e1000_get_hw_semaphore_82571;
 134                 phy->ops.release            = e1000_put_hw_semaphore_82571;
 135                 break;
 136         case e1000_82573:
 137                 phy->type                   = e1000_phy_m88;
 138                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 139                 phy->ops.get_info           = e1000_get_phy_info_m88;
 140                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 141                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 142                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 143                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 144                 phy->ops.read_reg           = e1000_read_phy_reg_m88;
 145                 phy->ops.write_reg          = e1000_write_phy_reg_m88;
 146                 phy->ops.acquire            = e1000_get_hw_semaphore_82571;
 147                 phy->ops.release            = e1000_put_hw_semaphore_82571;
 148                 break;
 149         case e1000_82574:
 150         case e1000_82583:
 151                 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
 152
 153                 phy->type                   = e1000_phy_bm;
 154                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 155                 phy->ops.get_info           = e1000_get_phy_info_m88;
 156                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 157                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 158                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 159                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 160                 phy->ops.read_reg           = e1000_read_phy_reg_bm2;
 161                 phy->ops.write_reg          = e1000_write_phy_reg_bm2;
 162                 phy->ops.acquire            = e1000_get_hw_semaphore_82574;
 163                 phy->ops.release            = e1000_put_hw_semaphore_82574;
 164                 phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82574;
 165                 phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_82574;
 166                 break;
 167         default:
 168                 ret_val = -E1000_ERR_PHY;
 169                 goto out;
 170                 break;
 171         }
 172
 173         /* This can only be done after all function pointers are setup. */
 174         ret_val = e1000_get_phy_id_82571(hw);
 175         if (ret_val) {
 176                 DEBUGOUT("Error getting PHY ID\n");
 177                 goto out;
 178         }
 179
 180         /* Verify phy id */
 181         switch (hw->mac.type) {
 182         case e1000_82571:
 183         case e1000_82572:
 184                 if (phy->id != IGP01E1000_I_PHY_ID)
 185                         ret_val = -E1000_ERR_PHY;
 186                 break;
 187         case e1000_82573:
 188                 if (phy->id != M88E1111_I_PHY_ID)
 189                         ret_val = -E1000_ERR_PHY;
 190                 break;
 191         case e1000_82574:
 192         case e1000_82583:
 193                 if (phy->id != BME1000_E_PHY_ID_R2)
 194                         ret_val = -E1000_ERR_PHY;
 195                 break;
 196         default:
 197                 ret_val = -E1000_ERR_PHY;
 198                 break;
 199         }
 200
 201         if (ret_val)
 202                 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 203
 204 out:
 205         return ret_val;
 206 }
 207
 208 /**
 209  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 210  *  @hw: pointer to the HW structure
 211  **/
 212 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 213 {
 214         struct e1000_nvm_info *nvm = &hw->nvm;
 215         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 216         u16 size;
 217
 218         DEBUGFUNC("e1000_init_nvm_params_82571");
 219
 220         nvm->opcode_bits = 8;
 221         nvm->delay_usec = 1;
 222         switch (nvm->override) {
 223         case e1000_nvm_override_spi_large:
 224                 nvm->page_size = 32;
 225                 nvm->address_bits = 16;
 226                 break;
 227         case e1000_nvm_override_spi_small:
 228                 nvm->page_size = 8;
 229                 nvm->address_bits = 8;
 230                 break;
 231         default:
 232                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 233                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 234                 break;
 235         }
 236
 237         switch (hw->mac.type) {
 238         case e1000_82573:
 239         case e1000_82574:
 240         case e1000_82583:
 241                 if (((eecd >> 15) & 0x3) == 0x3) {
 242                         nvm->type = e1000_nvm_flash_hw;
 243                         nvm->word_size = 2048;
 244                         /*
 245                          * Autonomous Flash update bit must be cleared due
 246                          * to Flash update issue.
 247                          */
 248                         eecd &= ~E1000_EECD_AUPDEN;
 249                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 250                         break;
 251                 }
 252                 /* Fall Through */
 253         default:
 254                 nvm->type = e1000_nvm_eeprom_spi;
 255                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 256                                   E1000_EECD_SIZE_EX_SHIFT);
 257                 /*
 258                  * Added to a constant, "size" becomes the left-shift value
 259                  * for setting word_size.
 260                  */
 261                 size += NVM_WORD_SIZE_BASE_SHIFT;
 262
 263                 /* EEPROM access above 16k is unsupported */
 264                 if (size > 14)
 265                         size = 14;
 266                 nvm->word_size  = 1 << size;
 267                 break;
 268         }
 269
 270         /* Function Pointers */
 271         switch (hw->mac.type) {
 272         case e1000_82574:
 273         case e1000_82583:
 274                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 275                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 276                 break;
 277         default:
 278                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 279                 nvm->ops.release = e1000_release_nvm_82571;
 280                 break;
 281         }
 282         nvm->ops.read          = e1000_read_nvm_eerd;
 283         nvm->ops.update        = e1000_update_nvm_checksum_82571;
 284         nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
 285         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 286         nvm->ops.write         = e1000_write_nvm_82571;
 287
 288         return E1000_SUCCESS;
 289 }
 290
 291 /**
 292  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 293  *  @hw: pointer to the HW structure
 294  **/
 295 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 296 {
 297         struct e1000_mac_info *mac = &hw->mac;
 298         u32 swsm = 0;
 299         u32 swsm2 = 0;
 300         bool force_clear_smbi = FALSE;
 301
 302         DEBUGFUNC("e1000_init_mac_params_82571");
 303
 304         /* Set media type and media-dependent function pointers */
 305         switch (hw->device_id) {
 306         case E1000_DEV_ID_82571EB_FIBER:
 307         case E1000_DEV_ID_82572EI_FIBER:
 308         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 309                 hw->phy.media_type = e1000_media_type_fiber;
 310                 mac->ops.setup_physical_interface =
 311                         e1000_setup_fiber_serdes_link_82571;
 312                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 313                 mac->ops.get_link_up_info =
 314                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 315                 break;
 316         case E1000_DEV_ID_82571EB_SERDES:
 317         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 318         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 319         case E1000_DEV_ID_82572EI_SERDES:
 320                 hw->phy.media_type = e1000_media_type_internal_serdes;
 321                 mac->ops.setup_physical_interface =
 322                         e1000_setup_fiber_serdes_link_82571;
 323                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 324                 mac->ops.get_link_up_info =
 325                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 326                 break;
 327         default:
 328                 hw->phy.media_type = e1000_media_type_copper;
 329                 mac->ops.setup_physical_interface =
 330                         e1000_setup_copper_link_82571;
 331                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 332                 mac->ops.get_link_up_info =
 333                         e1000_get_speed_and_duplex_copper_generic;
 334                 break;
 335         }
 336
 337         /* Set mta register count */
 338         mac->mta_reg_count = 128;
 339         /* Set rar entry count */
 340         mac->rar_entry_count = E1000_RAR_ENTRIES;
 341         /* Set if part includes ASF firmware */
 342         mac->asf_firmware_present = TRUE;
 343         /* Adaptive IFS supported */
 344         mac->adaptive_ifs = TRUE;
 345
 346         /* Function pointers */
 347
 348         /* bus type/speed/width */
 349         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 350         /* reset */
 351         mac->ops.reset_hw = e1000_reset_hw_82571;
 352         /* hw initialization */
 353         mac->ops.init_hw = e1000_init_hw_82571;
 354         /* link setup */
 355         mac->ops.setup_link = e1000_setup_link_82571;
 356         /* multicast address update */
 357         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 358         /* writing VFTA */
 359         mac->ops.write_vfta = e1000_write_vfta_generic;
 360         /* clearing VFTA */
 361         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 362         /* read mac address */
 363         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 364         /* ID LED init */
 365         mac->ops.id_led_init = e1000_id_led_init_generic;
 366         /* blink LED */
 367         mac->ops.blink_led = e1000_blink_led_generic;
 368         /* setup LED */
 369         mac->ops.setup_led = e1000_setup_led_generic;
 370         /* cleanup LED */
 371         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 372         /* turn off LED */
 373         mac->ops.led_off = e1000_led_off_generic;
 374         /* clear hardware counters */
 375         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 376
 377         /* MAC-specific function pointers */
 378         switch (hw->mac.type) {
 379         case e1000_82573:
 380                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 381                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 382                 mac->ops.led_on = e1000_led_on_generic;
 383
 384                 /* FWSM register */
 385                 mac->has_fwsm = TRUE;
 386                 /*
 387                  * ARC supported; valid only if manageability features are
 388                  * enabled.
 389                  */
 390                 mac->arc_subsystem_valid =
 391                         (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 392                         ? TRUE : FALSE;
 393                 break;
 394         case e1000_82574:
 395         case e1000_82583:
 396                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 397                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 398                 mac->ops.led_on = e1000_led_on_82574;
 399                 break;
 400         default:
 401                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 402                 mac->ops.led_on = e1000_led_on_generic;
 403
 404                 /* FWSM register */
 405                 mac->has_fwsm = TRUE;
 406                 break;
 407         }
 408
 409         /*
 410          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 411          * first NVM or PHY acess. This should be done for single-port
 412          * devices, and for one port only on dual-port devices so that
 413          * for those devices we can still use the SMBI lock to synchronize
 414          * inter-port accesses to the PHY & NVM.
 415          */
 416         switch (hw->mac.type) {
 417         case e1000_82571:
 418         case e1000_82572:
 419                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 420
 421                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 422                         /* Only do this for the first interface on this card */
 423                         E1000_WRITE_REG(hw, E1000_SWSM2,
 424                             swsm2 | E1000_SWSM2_LOCK);
 425                         force_clear_smbi = TRUE;
 426                 } else
 427                         force_clear_smbi = FALSE;
 428                 break;
 429         default:
 430                 force_clear_smbi = TRUE;
 431                 break;
 432         }
 433
 434         if (force_clear_smbi) {
 435                 /* Make sure SWSM.SMBI is clear */
 436                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 437                 if (swsm & E1000_SWSM_SMBI) {
 438                         /* This bit should not be set on a first interface, and
 439                          * indicates that the bootagent or EFI code has
 440                          * improperly left this bit enabled
 441                          */
 442                         DEBUGOUT("Please update your 82571 Bootagent\n");
 443                 }
 444                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 445         }
 446
 447         /*
 448          * Initialze device specific counter of SMBI acquisition
 449          * timeouts.
 450          */
 451          hw->dev_spec._82571.smb_counter = 0;
 452
 453         return E1000_SUCCESS;
 454 }
 455
 456 /**
 457  *  e1000_init_function_pointers_82571 - Init func ptrs.
 458  *  @hw: pointer to the HW structure
 459  *
 460  *  Called to initialize all function pointers and parameters.
 461  **/
 462 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 463 {
 464         DEBUGFUNC("e1000_init_function_pointers_82571");
 465
 466         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 467         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 468         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 469 }
 470
 471 /**
 472  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 473  *  @hw: pointer to the HW structure
 474  *
 475  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 476  *  revision in the hardware structure.
 477  **/
 478 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 479 {
 480         struct e1000_phy_info *phy = &hw->phy;
 481         s32 ret_val = E1000_SUCCESS;
 482         u16 phy_id = 0;
 483
 484         DEBUGFUNC("e1000_get_phy_id_82571");
 485
 486         switch (hw->mac.type) {
 487         case e1000_82571:
 488         case e1000_82572:
 489                 /*
 490                  * The 82571 firmware may still be configuring the PHY.
 491                  * In this case, we cannot access the PHY until the
 492                  * configuration is done.  So we explicitly set the
 493                  * PHY ID.
 494                  */
 495                 phy->id = IGP01E1000_I_PHY_ID;
 496                 break;
 497         case e1000_82573:
 498                 ret_val = e1000_get_phy_id(hw);
 499                 break;
 500         case e1000_82574:
 501         case e1000_82583:
 502                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 503                 if (ret_val)
 504                         goto out;
 505
 506                 phy->id = (u32)(phy_id << 16);
 507                 usec_delay(20);
 508                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 509                 if (ret_val)
 510                         goto out;
 511
 512                 phy->id |= (u32)(phy_id);
 513                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 514                 break;
 515         default:
 516                 ret_val = -E1000_ERR_PHY;
 517                 break;
 518         }
 519 out:
 520         return ret_val;
 521 }
 522
 523 /**
 524  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 525  *  @hw: pointer to the HW structure
 526  *
 527  *  Acquire the HW semaphore to access the PHY or NVM
 528  **/
 529 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 530 {
 531         u32 swsm;
 532         s32 ret_val = E1000_SUCCESS;
 533         s32 sw_timeout = hw->nvm.word_size + 1;
 534         s32 fw_timeout = hw->nvm.word_size + 1;
 535         s32 i = 0;
 536
 537         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 538
 539         /*
 540          * If we have timedout 3 times on trying to acquire
 541          * the inter-port SMBI semaphore, there is old code
 542          * operating on the other port, and it is not
 543          * releasing SMBI. Modify the number of times that
 544          * we try for the semaphore to interwork with this
 545          * older code.
 546          */
 547         if (hw->dev_spec._82571.smb_counter > 2)
 548                 sw_timeout = 1;
 549
 550         /* Get the SW semaphore */
 551         while (i < sw_timeout) {
 552                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 553                 if (!(swsm & E1000_SWSM_SMBI))
 554                         break;
 555
 556                 usec_delay(50);
 557                 i++;
 558         }
 559
 560         if (i == sw_timeout) {
 561                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 562                 hw->dev_spec._82571.smb_counter++;
 563         }
 564         /* Get the FW semaphore. */
 565         for (i = 0; i < fw_timeout; i++) {
 566                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 567                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 568
 569                 /* Semaphore acquired if bit latched */
 570                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 571                         break;
 572
 573                 usec_delay(50);
 574         }
 575
 576         if (i == fw_timeout) {
 577                 /* Release semaphores */
 578                 e1000_put_hw_semaphore_82571(hw);
 579                 DEBUGOUT("Driver can't access the NVM\n");
 580                 ret_val = -E1000_ERR_NVM;
 581                 goto out;
 582         }
 583
 584 out:
 585         return ret_val;
 586 }
 587
 588 /**
 589  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 590  *  @hw: pointer to the HW structure
 591  *
 592  *  Release hardware semaphore used to access the PHY or NVM
 593  **/
 594 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 595 {
 596         u32 swsm;
 597
 598         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 599
 600         swsm = E1000_READ_REG(hw, E1000_SWSM);
 601
 602         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 603
 604         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 605 }
 606
 607 /**
 608  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 609  *  @hw: pointer to the HW structure
 610  *
 611  *  Acquire the HW semaphore during reset.
 612  *
 613  **/
 614 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 615 {
 616         u32 extcnf_ctrl;
 617         s32 ret_val = E1000_SUCCESS;
 618         s32 i = 0;
 619
 620         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 621
 622         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 623         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 624         do {
 625                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 626                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 627
 628                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 629                         break;
 630
 631                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 632
 633                 msec_delay(2);
 634                 i++;
 635         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 636
 637         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 638                 /* Release semaphores */
 639                 e1000_put_hw_semaphore_82573(hw);
 640                 DEBUGOUT("Driver can't access the PHY\n");
 641                 ret_val = -E1000_ERR_PHY;
 642                 goto out;
 643         }
 644
 645 out:
 646         return ret_val;
 647 }
 648
 649 /**
 650  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 651  *  @hw: pointer to the HW structure
 652  *
 653  *  Release hardware semaphore used during reset.
 654  *
 655  **/
 656 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 657 {
 658         u32 extcnf_ctrl;
 659
 660         DEBUGFUNC("e1000_put_hw_semaphore_82573");
 661
 662         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 663         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 664         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 665 }
 666
 667 /**
 668  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 669  *  @hw: pointer to the HW structure
 670  *
 671  *  Acquire the HW semaphore to access the PHY or NVM.
 672  *
 673  **/
 674 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 675 {
 676         s32 ret_val;
 677
 678         DEBUGFUNC("e1000_get_hw_semaphore_82574");
 679
 680         E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
 681         ret_val = e1000_get_hw_semaphore_82573(hw);
 682         if (ret_val)
 683                 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 684         return ret_val;
 685 }
 686
 687 /**
 688  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 689  *  @hw: pointer to the HW structure
 690  *
 691  *  Release hardware semaphore used to access the PHY or NVM
 692  *
 693  **/
 694 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 695 {
 696         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 697
 698         e1000_put_hw_semaphore_82573(hw);
 699         E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 700 }
 701
 702 /**
 703  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 704  *  @hw: pointer to the HW structure
 705  *  @active: TRUE to enable LPLU, FALSE to disable
 706  *
 707  *  Sets the LPLU D0 state according to the active flag.
 708  *  LPLU will not be activated unless the
 709  *  device autonegotiation advertisement meets standards of
 710  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 711  *  This is a function pointer entry point only called by
 712  *  PHY setup routines.
 713  **/
 714 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 715 {
 716         u16 data = E1000_READ_REG(hw, E1000_POEMB);
 717
 718         DEBUGFUNC("e1000_set_d0_lplu_state_82574");
 719
 720         if (active)
 721                 data |= E1000_PHY_CTRL_D0A_LPLU;
 722         else
 723                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 724
 725         E1000_WRITE_REG(hw, E1000_POEMB, data);
 726         return E1000_SUCCESS;
 727 }
 728
 729 /**
 730  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 731  *  @hw: pointer to the HW structure
 732  *  @active: boolean used to enable/disable lplu
 733  *
 734  *  The low power link up (lplu) state is set to the power management level D3
 735  *  when active is TRUE, else clear lplu for D3. LPLU
 736  *  is used during Dx states where the power conservation is most important.
 737  *  During driver activity, SmartSpeed should be enabled so performance is
 738  *  maintained.
 739  **/
 740 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 741 {
 742         u16 data = E1000_READ_REG(hw, E1000_POEMB);
 743
 744         DEBUGFUNC("e1000_set_d3_lplu_state_82574");
 745
 746         if (!active) {
 747                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 748         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 749                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 750                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 751                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 752         }
 753
 754         E1000_WRITE_REG(hw, E1000_POEMB, data);
 755         return E1000_SUCCESS;
 756 }
 757
 758 /**
 759  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 760  *  @hw: pointer to the HW structure
 761  *
 762  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 763  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 764  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 765  *  hardware semaphore.
 766  **/
 767 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 768 {
 769         s32 ret_val;
 770
 771         DEBUGFUNC("e1000_acquire_nvm_82571");
 772
 773         ret_val = e1000_get_hw_semaphore_82571(hw);
 774         if (ret_val)
 775                 goto out;
 776
 777         switch (hw->mac.type) {
 778         case e1000_82573:
 779                 break;
 780         default:
 781                 ret_val = e1000_acquire_nvm_generic(hw);
 782                 break;
 783         }
 784
 785         if (ret_val)
 786                 e1000_put_hw_semaphore_82571(hw);
 787
 788 out:
 789         return ret_val;
 790 }
 791
 792 /**
 793  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 794  *  @hw: pointer to the HW structure
 795  *
 796  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 797  **/
 798 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 799 {
 800         DEBUGFUNC("e1000_release_nvm_82571");
 801
 802         e1000_release_nvm_generic(hw);
 803         e1000_put_hw_semaphore_82571(hw);
 804 }
 805
 806 /**
 807  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 808  *  @hw: pointer to the HW structure
 809  *  @offset: offset within the EEPROM to be written to
 810  *  @words: number of words to write
 811  *  @data: 16 bit word(s) to be written to the EEPROM
 812  *
 813  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 814  *
 815  *  If e1000_update_nvm_checksum is not called after this function, the
 816  *  EEPROM will most likely contain an invalid checksum.
 817  **/
 818 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 819                                  u16 *data)
 820 {
 821         s32 ret_val = E1000_SUCCESS;
 822
 823         DEBUGFUNC("e1000_write_nvm_82571");
 824
 825         switch (hw->mac.type) {
 826         case e1000_82573:
 827         case e1000_82574:
 828         case e1000_82583:
 829                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 830                 break;
 831         case e1000_82571:
 832         case e1000_82572:
 833                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 834                 break;
 835         default:
 836                 ret_val = -E1000_ERR_NVM;
 837                 break;
 838         }
 839
 840         return ret_val;
 841 }
 842
 843 /**
 844  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 845  *  @hw: pointer to the HW structure
 846  *
 847  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 848  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 849  *  value to the EEPROM.
 850  **/
 851 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 852 {
 853         u32 eecd;
 854         s32 ret_val;
 855         u16 i;
 856
 857         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 858
 859         ret_val = e1000_update_nvm_checksum_generic(hw);
 860         if (ret_val)
 861                 goto out;
 862
 863         /*
 864          * If our nvm is an EEPROM, then we're done
 865          * otherwise, commit the checksum to the flash NVM.
 866          */
 867         if (hw->nvm.type != e1000_nvm_flash_hw)
 868                 goto out;
 869
 870         /* Check for pending operations. */
 871         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 872                 msec_delay(1);
 873                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 874                         break;
 875         }
 876
 877         if (i == E1000_FLASH_UPDATES) {
 878                 ret_val = -E1000_ERR_NVM;
 879                 goto out;
 880         }
 881
 882         /* Reset the firmware if using STM opcode. */
 883         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 884                 /*
 885                  * The enabling of and the actual reset must be done
 886                  * in two write cycles.
 887                  */
 888                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 889                 E1000_WRITE_FLUSH(hw);
 890                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 891         }
 892
 893         /* Commit the write to flash */
 894         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 895         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 896
 897         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 898                 msec_delay(1);
 899                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 900                         break;
 901         }
 902
 903         if (i == E1000_FLASH_UPDATES) {
 904                 ret_val = -E1000_ERR_NVM;
 905                 goto out;
 906         }
 907
 908 out:
 909         return ret_val;
 910 }
 911
 912 /**
 913  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 914  *  @hw: pointer to the HW structure
 915  *
 916  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 917  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 918  **/
 919 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 920 {
 921         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 922
 923         if (hw->nvm.type == e1000_nvm_flash_hw)
 924                 e1000_fix_nvm_checksum_82571(hw);
 925
 926         return e1000_validate_nvm_checksum_generic(hw);
 927 }
 928
 929 /**
 930  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 931  *  @hw: pointer to the HW structure
 932  *  @offset: offset within the EEPROM to be written to
 933  *  @words: number of words to write
 934  *  @data: 16 bit word(s) to be written to the EEPROM
 935  *
 936  *  After checking for invalid values, poll the EEPROM to ensure the previous
 937  *  command has completed before trying to write the next word.  After write
 938  *  poll for completion.
 939  *
 940  *  If e1000_update_nvm_checksum is not called after this function, the
 941  *  EEPROM will most likely contain an invalid checksum.
 942  **/
 943 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 944                                       u16 words, u16 *data)
 945 {
 946         struct e1000_nvm_info *nvm = &hw->nvm;
 947         u32 i, eewr = 0;
 948         s32 ret_val = 0;
 949
 950         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 951
 952         /*
 953          * A check for invalid values:  offset too large, too many words,
 954          * and not enough words.
 955          */
 956         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 957             (words == 0)) {
 958                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 959                 ret_val = -E1000_ERR_NVM;
 960                 goto out;
 961         }
 962
 963         for (i = 0; i < words; i++) {
 964                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 965                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 966                        E1000_NVM_RW_REG_START;
 967
 968                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 969                 if (ret_val)
 970                         break;
 971
 972                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 973
 974                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 975                 if (ret_val)
 976                         break;
 977         }
 978
 979 out:
 980         return ret_val;
 981 }
 982
 983 /**
 984  *  e1000_get_cfg_done_82571 - Poll for configuration done
 985  *  @hw: pointer to the HW structure
 986  *
 987  *  Reads the management control register for the config done bit to be set.
 988  **/
 989 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 990 {
 991         s32 timeout = PHY_CFG_TIMEOUT;
 992         s32 ret_val = E1000_SUCCESS;
 993
 994         DEBUGFUNC("e1000_get_cfg_done_82571");
 995
 996         while (timeout) {
 997                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 998                     E1000_NVM_CFG_DONE_PORT_0)
 999                         break;
1000                 msec_delay(1);
1001                 timeout--;
1002         }
1003         if (!timeout) {
1004                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1005                 ret_val = -E1000_ERR_RESET;
1006                 goto out;
1007         }
1008
1009 out:
1010         return ret_val;
1011 }
1012
1013 /**
1014  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
1015  *  @hw: pointer to the HW structure
1016  *  @active: TRUE to enable LPLU, FALSE to disable
1017  *
1018  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
1019  *  this function also disables smart speed and vice versa.  LPLU will not be
1020  *  activated unless the device autonegotiation advertisement meets standards
1021  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
1022  *  pointer entry point only called by PHY setup routines.
1023  **/
1024 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
1025 {
1026         struct e1000_phy_info *phy = &hw->phy;
1027         s32 ret_val = E1000_SUCCESS;
1028         u16 data;
1029
1030         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
1031
1032         if (!(phy->ops.read_reg))
1033                 goto out;
1034
1035         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1036         if (ret_val)
1037                 goto out;
1038
1039         if (active) {
1040                 data |= IGP02E1000_PM_D0_LPLU;
1041                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1042                                              data);
1043                 if (ret_val)
1044                         goto out;
1045
1046                 /* When LPLU is enabled, we should disable SmartSpeed */
1047                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1048                                             &data);
1049                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1050                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1051                                              data);
1052                 if (ret_val)
1053                         goto out;
1054         } else {
1055                 data &= ~IGP02E1000_PM_D0_LPLU;
1056                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1057                                              data);
1058                 /*
1059                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1060                  * during Dx states where the power conservation is most
1061                  * important.  During driver activity we should enable
1062                  * SmartSpeed, so performance is maintained.
1063                  */
1064                 if (phy->smart_speed == e1000_smart_speed_on) {
1065                         ret_val = phy->ops.read_reg(hw,
1066                                                     IGP01E1000_PHY_PORT_CONFIG,
1067                                                     &data);
1068                         if (ret_val)
1069                                 goto out;
1070
1071                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1072                         ret_val = phy->ops.write_reg(hw,
1073                                                      IGP01E1000_PHY_PORT_CONFIG,
1074                                                      data);
1075                         if (ret_val)
1076                                 goto out;
1077                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1078                         ret_val = phy->ops.read_reg(hw,
1079                                                     IGP01E1000_PHY_PORT_CONFIG,
1080                                                     &data);
1081                         if (ret_val)
1082                                 goto out;
1083
1084                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1085                         ret_val = phy->ops.write_reg(hw,
1086                                                      IGP01E1000_PHY_PORT_CONFIG,
1087                                                      data);
1088                         if (ret_val)
1089                                 goto out;
1090                 }
1091         }
1092
1093 out:
1094         return ret_val;
1095 }
1096
1097 /**
1098  *  e1000_reset_hw_82571 - Reset hardware
1099  *  @hw: pointer to the HW structure
1100  *
1101  *  This resets the hardware into a known state.
1102  **/
1103 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1104 {
1105         u32 ctrl, ctrl_ext;
1106         s32 ret_val;
1107
1108         DEBUGFUNC("e1000_reset_hw_82571");
1109
1110         /*
1111          * Prevent the PCI-E bus from sticking if there is no TLP connection
1112          * on the last TLP read/write transaction when MAC is reset.
1113          */
1114         ret_val = e1000_disable_pcie_master_generic(hw);
1115         if (ret_val)
1116                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1117
1118         DEBUGOUT("Masking off all interrupts\n");
1119         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1120
1121         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1122         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1123         E1000_WRITE_FLUSH(hw);
1124
1125         msec_delay(10);
1126
1127         /*
1128          * Must acquire the MDIO ownership before MAC reset.
1129          * Ownership defaults to firmware after a reset.
1130          */
1131         switch (hw->mac.type) {
1132         case e1000_82573:
1133                 ret_val = e1000_get_hw_semaphore_82573(hw);
1134                 break;
1135         case e1000_82574:
1136         case e1000_82583:
1137                 ret_val = e1000_get_hw_semaphore_82574(hw);
1138                 break;
1139         default:
1140                 break;
1141         }
1142         if (ret_val)
1143                 DEBUGOUT("Cannot acquire MDIO ownership\n");
1144
1145         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1146
1147         DEBUGOUT("Issuing a global reset to MAC\n");
1148         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1149
1150         /* Must release MDIO ownership and mutex after MAC reset. */
1151         switch (hw->mac.type) {
1152         case e1000_82574:
1153         case e1000_82583:
1154                 e1000_put_hw_semaphore_82574(hw);
1155                 break;
1156         default:
1157                 break;
1158         }
1159
1160         if (hw->nvm.type == e1000_nvm_flash_hw) {
1161                 usec_delay(10);
1162                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1163                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1164                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1165                 E1000_WRITE_FLUSH(hw);
1166         }
1167
1168         ret_val = e1000_get_auto_rd_done_generic(hw);
1169         if (ret_val)
1170                 /* We don't want to continue accessing MAC registers. */
1171                 goto out;
1172
1173         /*
1174          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1175          * Need to wait for Phy configuration completion before accessing
1176          * NVM and Phy.
1177          */
1178
1179         switch (hw->mac.type) {
1180         case e1000_82573:
1181         case e1000_82574:
1182         case e1000_82583:
1183                 msec_delay(25);
1184                 break;
1185         default:
1186                 break;
1187         }
1188
1189         /* Clear any pending interrupt events. */
1190         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1191         E1000_READ_REG(hw, E1000_ICR);
1192
1193         if (hw->mac.type == e1000_82571) {
1194                 /* Install any alternate MAC address into RAR0 */
1195                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1196                 if (ret_val)
1197                         goto out;
1198
1199                 e1000_set_laa_state_82571(hw, TRUE);
1200         }
1201
1202         /* Reinitialize the 82571 serdes link state machine */
1203         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1204                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1205
1206 out:
1207         return ret_val;
1208 }
1209
1210 /**
1211  *  e1000_init_hw_82571 - Initialize hardware
1212  *  @hw: pointer to the HW structure
1213  *
1214  *  This inits the hardware readying it for operation.
1215  **/
1216 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1217 {
1218         struct e1000_mac_info *mac = &hw->mac;
1219         u32 reg_data;
1220         s32 ret_val;
1221         u16 i, rar_count = mac->rar_entry_count;
1222
1223         DEBUGFUNC("e1000_init_hw_82571");
1224
1225         e1000_initialize_hw_bits_82571(hw);
1226
1227         /* Initialize identification LED */
1228         ret_val = mac->ops.id_led_init(hw);
1229         if (ret_val)
1230                 DEBUGOUT("Error initializing identification LED\n");
1231                 /* This is not fatal and we should not stop init due to this */
1232
1233         /* Disabling VLAN filtering */
1234         DEBUGOUT("Initializing the IEEE VLAN\n");
1235         mac->ops.clear_vfta(hw);
1236
1237         /* Setup the receive address. */
1238         /*
1239          * If, however, a locally administered address was assigned to the
1240          * 82571, we must reserve a RAR for it to work around an issue where
1241          * resetting one port will reload the MAC on the other port.
1242          */
1243         if (e1000_get_laa_state_82571(hw))
1244                 rar_count--;
1245         e1000_init_rx_addrs_generic(hw, rar_count);
1246
1247         /* Zero out the Multicast HASH table */
1248         DEBUGOUT("Zeroing the MTA\n");
1249         for (i = 0; i < mac->mta_reg_count; i++)
1250                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1251
1252         /* Setup link and flow control */
1253         ret_val = mac->ops.setup_link(hw);
1254
1255         /* Set the transmit descriptor write-back policy */
1256         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1257         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1258                    E1000_TXDCTL_FULL_TX_DESC_WB |
1259                    E1000_TXDCTL_COUNT_DESC;
1260         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1261
1262         /* ...for both queues. */
1263         switch (mac->type) {
1264         case e1000_82573:
1265                 e1000_enable_tx_pkt_filtering_generic(hw);
1266                 /* fall through */
1267         case e1000_82574:
1268         case e1000_82583:
1269                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1270                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1271                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1272                 break;
1273         default:
1274                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1275                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1276                            E1000_TXDCTL_FULL_TX_DESC_WB |
1277                            E1000_TXDCTL_COUNT_DESC;
1278                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1279                 break;
1280         }
1281
1282         /*
1283          * Clear all of the statistics registers (clear on read).  It is
1284          * important that we do this after we have tried to establish link
1285          * because the symbol error count will increment wildly if there
1286          * is no link.
1287          */
1288         e1000_clear_hw_cntrs_82571(hw);
1289
1290         return ret_val;
1291 }
1292
1293 /**
1294  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1295  *  @hw: pointer to the HW structure
1296  *
1297  *  Initializes required hardware-dependent bits needed for normal operation.
1298  **/
1299 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1300 {
1301         u32 reg;
1302
1303         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1304
1305         /* Transmit Descriptor Control 0 */
1306         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1307         reg |= (1 << 22);
1308         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1309
1310         /* Transmit Descriptor Control 1 */
1311         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1312         reg |= (1 << 22);
1313         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1314
1315         /* Transmit Arbitration Control 0 */
1316         reg = E1000_READ_REG(hw, E1000_TARC(0));
1317         reg &= ~(0xF << 27); /* 30:27 */
1318         switch (hw->mac.type) {
1319         case e1000_82571:
1320         case e1000_82572:
1321                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1322                 break;
1323         default:
1324                 break;
1325         }
1326         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1327
1328         /* Transmit Arbitration Control 1 */
1329         reg = E1000_READ_REG(hw, E1000_TARC(1));
1330         switch (hw->mac.type) {
1331         case e1000_82571:
1332         case e1000_82572:
1333                 reg &= ~((1 << 29) | (1 << 30));
1334                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1335                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1336                         reg &= ~(1 << 28);
1337                 else
1338                         reg |= (1 << 28);
1339                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1340                 break;
1341         default:
1342                 break;
1343         }
1344
1345         /* Device Control */
1346         switch (hw->mac.type) {
1347         case e1000_82573:
1348         case e1000_82574:
1349         case e1000_82583:
1350                 reg = E1000_READ_REG(hw, E1000_CTRL);
1351                 reg &= ~(1 << 29);
1352                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1353                 break;
1354         default:
1355                 break;
1356         }
1357
1358         /* Extended Device Control */
1359         switch (hw->mac.type) {
1360         case e1000_82573:
1361         case e1000_82574:
1362         case e1000_82583:
1363                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1364                 reg &= ~(1 << 23);
1365                 reg |= (1 << 22);
1366                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1367                 break;
1368         default:
1369                 break;
1370         }
1371
1372         if (hw->mac.type == e1000_82571) {
1373                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1374                 reg |= E1000_PBA_ECC_CORR_EN;
1375                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1376         }
1377
1378         /*
1379          * Workaround for hardware errata.
1380          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1381          */
1382         if ((hw->mac.type == e1000_82571) ||
1383            (hw->mac.type == e1000_82572)) {
1384                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1385                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1386                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1387         }
1388
1389         /* PCI-Ex Control Registers */
1390         switch (hw->mac.type) {
1391         case e1000_82574:
1392         case e1000_82583:
1393                 reg = E1000_READ_REG(hw, E1000_GCR);
1394                 reg |= (1 << 22);
1395                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1396
1397                 /*
1398                  * Workaround for hardware errata.
1399                  * apply workaround for hardware errata documented in errata
1400                  * docs Fixes issue where some error prone or unreliable PCIe
1401                  * completions are occurring, particularly with ASPM enabled.
1402                  * Without fix, issue can cause Tx timeouts.
1403                  */
1404                 reg = E1000_READ_REG(hw, E1000_GCR2);
1405                 reg |= 1;
1406                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1407                 break;
1408         default:
1409                 break;
1410         }
1411
1412         return;
1413 }
1414
1415 /**
1416  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1417  *  @hw: pointer to the HW structure
1418  *
1419  *  Clears the register array which contains the VLAN filter table by
1420  *  setting all the values to 0.
1421  **/
1422 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1423 {
1424         u32 offset;
1425         u32 vfta_value = 0;
1426         u32 vfta_offset = 0;
1427         u32 vfta_bit_in_reg = 0;
1428
1429         DEBUGFUNC("e1000_clear_vfta_82571");
1430
1431         switch (hw->mac.type) {
1432         case e1000_82573:
1433         case e1000_82574:
1434         case e1000_82583:
1435                 if (hw->mng_cookie.vlan_id != 0) {
1436                         /*
1437                          * The VFTA is a 4096b bit-field, each identifying
1438                          * a single VLAN ID.  The following operations
1439                          * determine which 32b entry (i.e. offset) into the
1440                          * array we want to set the VLAN ID (i.e. bit) of
1441                          * the manageability unit.
1442                          */
1443                         vfta_offset = (hw->mng_cookie.vlan_id >>
1444                                 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1445                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1446                                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1447                 }
1448                 break;
1449         default:
1450                 break;
1451         }
1452         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1453                 /*
1454                  * If the offset we want to clear is the same offset of the
1455                  * manageability VLAN ID, then clear all bits except that of
1456                  * the manageability unit.
1457                  */
1458                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1459                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1460                 E1000_WRITE_FLUSH(hw);
1461         }
1462 }
1463
1464 /**
1465  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1466  *  @hw: pointer to the HW structure
1467  *
1468  *  Reads the NVM Initialization Control Word 2 and returns TRUE
1469  *  (>0) if any manageability is enabled, else FALSE (0).
1470  **/
1471 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1472 {
1473         u16 data;
1474
1475         DEBUGFUNC("e1000_check_mng_mode_82574");
1476
1477         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1478         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1479 }
1480
1481 /**
1482  *  e1000_led_on_82574 - Turn LED on
1483  *  @hw: pointer to the HW structure
1484  *
1485  *  Turn LED on.
1486  **/
1487 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1488 {
1489         u32 ctrl;
1490         u32 i;
1491
1492         DEBUGFUNC("e1000_led_on_82574");
1493
1494         ctrl = hw->mac.ledctl_mode2;
1495         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1496                 /*
1497                  * If no link, then turn LED on by setting the invert bit
1498                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1499                  */
1500                 for (i = 0; i < 4; i++)
1501                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1502                             E1000_LEDCTL_MODE_LED_ON)
1503                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1504         }
1505         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1506
1507         return E1000_SUCCESS;
1508 }
1509
1510 /**
1511  *  e1000_check_phy_82574 - check 82574 phy hung state
1512  *  @hw: pointer to the HW structure
1513  *
1514  *  Returns whether phy is hung or not
1515  **/
1516 bool e1000_check_phy_82574(struct e1000_hw *hw)
1517 {
1518         u16 status_1kbt = 0;
1519         u16 receive_errors = 0;
1520         bool phy_hung = FALSE;
1521         s32 ret_val = E1000_SUCCESS;
1522
1523         DEBUGFUNC("e1000_check_phy_82574");
1524
1525         /*
1526          * Read PHY Receive Error counter first, if its is max - all F's then
1527          * read the Base1000T status register If both are max then PHY is hung.
1528          */
1529         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1530                                        &receive_errors);
1531         if (ret_val)
1532                 goto out;
1533         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1534                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1535                                                &status_1kbt);
1536                 if (ret_val)
1537                         goto out;
1538                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1539                     E1000_IDLE_ERROR_COUNT_MASK)
1540                         phy_hung = TRUE;
1541         }
1542 out:
1543         return phy_hung;
1544 }
1545
1546
1547 /**
1548  *  e1000_setup_link_82571 - Setup flow control and link settings
1549  *  @hw: pointer to the HW structure
1550  *
1551  *  Determines which flow control settings to use, then configures flow
1552  *  control.  Calls the appropriate media-specific link configuration
1553  *  function.  Assuming the adapter has a valid link partner, a valid link
1554  *  should be established.  Assumes the hardware has previously been reset
1555  *  and the transmitter and receiver are not enabled.
1556  **/
1557 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1558 {
1559         DEBUGFUNC("e1000_setup_link_82571");
1560
1561         /*
1562          * 82573 does not have a word in the NVM to determine
1563          * the default flow control setting, so we explicitly
1564          * set it to full.
1565          */
1566         switch (hw->mac.type) {
1567         case e1000_82573:
1568         case e1000_82574:
1569         case e1000_82583:
1570                 if (hw->fc.requested_mode == e1000_fc_default)
1571                         hw->fc.requested_mode = e1000_fc_full;
1572                 break;
1573         default:
1574                 break;
1575         }
1576
1577         return e1000_setup_link_generic(hw);
1578 }
1579
1580 /**
1581  *  e1000_setup_copper_link_82571 - Configure copper link settings
1582  *  @hw: pointer to the HW structure
1583  *
1584  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1585  *  for link, once link is established calls to configure collision distance
1586  *  and flow control are called.
1587  **/
1588 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1589 {
1590         u32 ctrl;
1591         s32 ret_val;
1592
1593         DEBUGFUNC("e1000_setup_copper_link_82571");
1594
1595         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1596         ctrl |= E1000_CTRL_SLU;
1597         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1598         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1599
1600         switch (hw->phy.type) {
1601         case e1000_phy_m88:
1602         case e1000_phy_bm:
1603                 ret_val = e1000_copper_link_setup_m88(hw);
1604                 break;
1605         case e1000_phy_igp_2:
1606                 ret_val = e1000_copper_link_setup_igp(hw);
1607                 break;
1608         default:
1609                 ret_val = -E1000_ERR_PHY;
1610                 break;
1611         }
1612
1613         if (ret_val)
1614                 goto out;
1615
1616         ret_val = e1000_setup_copper_link_generic(hw);
1617
1618 out:
1619         return ret_val;
1620 }
1621
1622 /**
1623  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1624  *  @hw: pointer to the HW structure
1625  *
1626  *  Configures collision distance and flow control for fiber and serdes links.
1627  *  Upon successful setup, poll for link.
1628  **/
1629 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1630 {
1631         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1632
1633         switch (hw->mac.type) {
1634         case e1000_82571:
1635         case e1000_82572:
1636                 /*
1637                  * If SerDes loopback mode is entered, there is no form
1638                  * of reset to take the adapter out of that mode.  So we
1639                  * have to explicitly take the adapter out of loopback
1640                  * mode.  This prevents drivers from twiddling their thumbs
1641                  * if another tool failed to take it out of loopback mode.
1642                  */
1643                 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1644                 break;
1645         default:
1646                 break;
1647         }
1648
1649         return e1000_setup_fiber_serdes_link_generic(hw);
1650 }
1651
1652 /**
1653  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1654  *  @hw: pointer to the HW structure
1655  *
1656  *  Reports the link state as up or down.
1657  *
1658  *  If autonegotiation is supported by the link partner, the link state is
1659  *  determined by the result of autonegotiation. This is the most likely case.
1660  *  If autonegotiation is not supported by the link partner, and the link
1661  *  has a valid signal, force the link up.
1662  *
1663  *  The link state is represented internally here by 4 states:
1664  *
1665  *  1) down
1666  *  2) autoneg_progress
1667  *  3) autoneg_complete (the link sucessfully autonegotiated)
1668  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1669  *
1670  **/
1671 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1672 {
1673         struct e1000_mac_info *mac = &hw->mac;
1674         u32 rxcw;
1675         u32 ctrl;
1676         u32 status;
1677         u32 txcw;
1678         u32 i;
1679         s32 ret_val = E1000_SUCCESS;
1680
1681         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1682
1683         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1684         status = E1000_READ_REG(hw, E1000_STATUS);
1685         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1686
1687         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1688
1689                 /* Receiver is synchronized with no invalid bits.  */
1690                 switch (mac->serdes_link_state) {
1691                 case e1000_serdes_link_autoneg_complete:
1692                         if (!(status & E1000_STATUS_LU)) {
1693                                 /*
1694                                  * We have lost link, retry autoneg before
1695                                  * reporting link failure
1696                                  */
1697                                 mac->serdes_link_state =
1698                                     e1000_serdes_link_autoneg_progress;
1699                                 mac->serdes_has_link = FALSE;
1700                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1701                         } else {
1702                                 mac->serdes_has_link = TRUE;
1703                         }
1704                         break;
1705
1706                 case e1000_serdes_link_forced_up:
1707                         /*
1708                          * If we are receiving /C/ ordered sets, re-enable
1709                          * auto-negotiation in the TXCW register and disable
1710                          * forced link in the Device Control register in an
1711                          * attempt to auto-negotiate with our link partner.
1712                          * If the partner code word is null, stop forcing
1713                          * and restart auto negotiation.
1714                          */
1715                         if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW))  {
1716                                 /* Enable autoneg, and unforce link up */
1717                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1718                                 E1000_WRITE_REG(hw, E1000_CTRL,
1719                                     (ctrl & ~E1000_CTRL_SLU));
1720                                 mac->serdes_link_state =
1721                                     e1000_serdes_link_autoneg_progress;
1722                                 mac->serdes_has_link = FALSE;
1723                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1724                         } else {
1725                                 mac->serdes_has_link = TRUE;
1726                         }
1727                         break;
1728
1729                 case e1000_serdes_link_autoneg_progress:
1730                         if (rxcw & E1000_RXCW_C) {
1731                                 /*
1732                                  * We received /C/ ordered sets, meaning the
1733                                  * link partner has autonegotiated, and we can
1734                                  * trust the Link Up (LU) status bit.
1735                                  */
1736                                 if (status & E1000_STATUS_LU) {
1737                                         mac->serdes_link_state =
1738                                             e1000_serdes_link_autoneg_complete;
1739                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1740                                         mac->serdes_has_link = TRUE;
1741                                 } else {
1742                                         /* Autoneg completed, but failed. */
1743                                         mac->serdes_link_state =
1744                                             e1000_serdes_link_down;
1745                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1746                                 }
1747                         } else {
1748                                 /*
1749                                  * The link partner did not autoneg.
1750                                  * Force link up and full duplex, and change
1751                                  * state to forced.
1752                                  */
1753                                 E1000_WRITE_REG(hw, E1000_TXCW,
1754                                 (mac->txcw & ~E1000_TXCW_ANE));
1755                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1756                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1757
1758                                 /* Configure Flow Control after link up. */
1759                                 ret_val =
1760                                     e1000_config_fc_after_link_up_generic(hw);
1761                                 if (ret_val) {
1762                                         DEBUGOUT("Error config flow control\n");
1763                                         break;
1764                                 }
1765                                 mac->serdes_link_state =
1766                                 e1000_serdes_link_forced_up;
1767                                 mac->serdes_has_link = TRUE;
1768                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1769                         }
1770                         break;
1771
1772                 case e1000_serdes_link_down:
1773                 default:
1774                         /*
1775                          * The link was down but the receiver has now gained
1776                          * valid sync, so lets see if we can bring the link
1777                          * up.
1778                          */
1779                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1780                         E1000_WRITE_REG(hw, E1000_CTRL,
1781                             (ctrl & ~E1000_CTRL_SLU));
1782                         mac->serdes_link_state =
1783                             e1000_serdes_link_autoneg_progress;
1784                         mac->serdes_has_link = FALSE;
1785                         DEBUGOUT("DOWN      -> AN_PROG\n");
1786                         break;
1787                 }
1788         } else {
1789                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1790                         mac->serdes_has_link = FALSE;
1791                         mac->serdes_link_state = e1000_serdes_link_down;
1792                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1793                 } else {
1794                         /*
1795                          * Check several times, if Sync and Config
1796                          * both are consistently 1 then simply ignore
1797                          * the Invalid bit and restart Autoneg
1798                          */
1799                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1800                                 usec_delay(10);
1801                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1802                                 if ((rxcw & E1000_RXCW_IV) &&
1803                                     !((rxcw & E1000_RXCW_SYNCH) &&
1804                                       (rxcw & E1000_RXCW_C))) {
1805                                         mac->serdes_has_link = FALSE;
1806                                         mac->serdes_link_state =
1807                                             e1000_serdes_link_down;
1808                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1809                                         break;
1810                                 }
1811                         }
1812
1813                         if (i == AN_RETRY_COUNT) {
1814                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1815                                 txcw |= E1000_TXCW_ANE;
1816                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1817                                 mac->serdes_link_state =
1818                                     e1000_serdes_link_autoneg_progress;
1819                                 mac->serdes_has_link = FALSE;
1820                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1821                         }
1822                 }
1823         }
1824
1825         return ret_val;
1826 }
1827
1828 /**
1829  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1830  *  @hw: pointer to the HW structure
1831  *  @data: pointer to the NVM (EEPROM)
1832  *
1833  *  Read the EEPROM for the current default LED configuration.  If the
1834  *  LED configuration is not valid, set to a valid LED configuration.
1835  **/
1836 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1837 {
1838         s32 ret_val;
1839
1840         DEBUGFUNC("e1000_valid_led_default_82571");
1841
1842         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1843         if (ret_val) {
1844                 DEBUGOUT("NVM Read Error\n");
1845                 goto out;
1846         }
1847
1848         switch (hw->mac.type) {
1849         case e1000_82573:
1850         case e1000_82574:
1851         case e1000_82583:
1852                 if (*data == ID_LED_RESERVED_F746)
1853                         *data = ID_LED_DEFAULT_82573;
1854                 break;
1855         default:
1856                 if (*data == ID_LED_RESERVED_0000 ||
1857                     *data == ID_LED_RESERVED_FFFF)
1858                         *data = ID_LED_DEFAULT;
1859                 break;
1860         }
1861
1862 out:
1863         return ret_val;
1864 }
1865
1866 /**
1867  *  e1000_get_laa_state_82571 - Get locally administered address state
1868  *  @hw: pointer to the HW structure
1869  *
1870  *  Retrieve and return the current locally administered address state.
1871  **/
1872 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1873 {
1874         DEBUGFUNC("e1000_get_laa_state_82571");
1875
1876         if (hw->mac.type != e1000_82571)
1877                 return FALSE;
1878
1879         return hw->dev_spec._82571.laa_is_present;
1880 }
1881
1882 /**
1883  *  e1000_set_laa_state_82571 - Set locally administered address state
1884  *  @hw: pointer to the HW structure
1885  *  @state: enable/disable locally administered address
1886  *
1887  *  Enable/Disable the current locally administered address state.
1888  **/
1889 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1890 {
1891         DEBUGFUNC("e1000_set_laa_state_82571");
1892
1893         if (hw->mac.type != e1000_82571)
1894                 return;
1895
1896         hw->dev_spec._82571.laa_is_present = state;
1897
1898         /* If workaround is activated... */
1899         if (state)
1900                 /*
1901                  * Hold a copy of the LAA in RAR[14] This is done so that
1902                  * between the time RAR[0] gets clobbered and the time it
1903                  * gets fixed, the actual LAA is in one of the RARs and no
1904                  * incoming packets directed to this port are dropped.
1905                  * Eventually the LAA will be in RAR[0] and RAR[14].
1906                  */
1907                 e1000_rar_set_generic(hw, hw->mac.addr,
1908                                       hw->mac.rar_entry_count - 1);
1909         return;
1910 }
1911
1912 /**
1913  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1914  *  @hw: pointer to the HW structure
1915  *
1916  *  Verifies that the EEPROM has completed the update.  After updating the
1917  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1918  *  the checksum fix is not implemented, we need to set the bit and update
1919  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1920  *  we need to return bad checksum.
1921  **/
1922 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1923 {
1924         struct e1000_nvm_info *nvm = &hw->nvm;
1925         s32 ret_val = E1000_SUCCESS;
1926         u16 data;
1927
1928         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1929
1930         if (nvm->type != e1000_nvm_flash_hw)
1931                 goto out;
1932
1933         /*
1934          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1935          * 10h-12h.  Checksum may need to be fixed.
1936          */
1937         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1938         if (ret_val)
1939                 goto out;
1940
1941         if (!(data & 0x10)) {
1942                 /*
1943                  * Read 0x23 and check bit 15.  This bit is a 1
1944                  * when the checksum has already been fixed.  If
1945                  * the checksum is still wrong and this bit is a
1946                  * 1, we need to return bad checksum.  Otherwise,
1947                  * we need to set this bit to a 1 and update the
1948                  * checksum.
1949                  */
1950                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1951                 if (ret_val)
1952                         goto out;
1953
1954                 if (!(data & 0x8000)) {
1955                         data |= 0x8000;
1956                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1957                         if (ret_val)
1958                                 goto out;
1959                         ret_val = nvm->ops.update(hw);
1960                 }
1961         }
1962
1963 out:
1964         return ret_val;
1965 }
1966
1967
1968 /**
1969  *  e1000_read_mac_addr_82571 - Read device MAC address
1970  *  @hw: pointer to the HW structure
1971  **/
1972 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1973 {
1974         s32 ret_val = E1000_SUCCESS;
1975
1976         DEBUGFUNC("e1000_read_mac_addr_82571");
1977
1978         if (hw->mac.type == e1000_82571) {
1979                 /*
1980                  * If there's an alternate MAC address place it in RAR0
1981                  * so that it will override the Si installed default perm
1982                  * address.
1983                  */
1984                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1985                 if (ret_val)
1986                         goto out;
1987         }
1988
1989         ret_val = e1000_read_mac_addr_generic(hw);
1990
1991 out:
1992         return ret_val;
1993 }
1994
1995 /**
1996  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1997  * @hw: pointer to the HW structure
1998  *
1999  * In the case of a PHY power down to save power, or to turn off link during a
2000  * driver unload, or wake on lan is not enabled, remove the link.
2001  **/
2002 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
2003 {
2004         struct e1000_phy_info *phy = &hw->phy;
2005         struct e1000_mac_info *mac = &hw->mac;
2006
2007         if (!(phy->ops.check_reset_block))
2008                 return;
2009
2010         /* If the management interface is not enabled, then power down */
2011         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
2012                 e1000_power_down_phy_copper(hw);
2013
2014         return;
2015 }
2016
2017 /**
2018  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
2019  *  @hw: pointer to the HW structure
2020  *
2021  *  Clears the hardware counters by reading the counter registers.
2022  **/
2023 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
2024 {
2025         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
2026
2027         e1000_clear_hw_cntrs_base_generic(hw);
2028
2029         E1000_READ_REG(hw, E1000_PRC64);
2030         E1000_READ_REG(hw, E1000_PRC127);
2031         E1000_READ_REG(hw, E1000_PRC255);
2032         E1000_READ_REG(hw, E1000_PRC511);
2033         E1000_READ_REG(hw, E1000_PRC1023);
2034         E1000_READ_REG(hw, E1000_PRC1522);
2035         E1000_READ_REG(hw, E1000_PTC64);
2036         E1000_READ_REG(hw, E1000_PTC127);
2037         E1000_READ_REG(hw, E1000_PTC255);
2038         E1000_READ_REG(hw, E1000_PTC511);
2039         E1000_READ_REG(hw, E1000_PTC1023);
2040         E1000_READ_REG(hw, E1000_PTC1522);
2041
2042         E1000_READ_REG(hw, E1000_ALGNERRC);
2043         E1000_READ_REG(hw, E1000_RXERRC);
2044         E1000_READ_REG(hw, E1000_TNCRS);
2045         E1000_READ_REG(hw, E1000_CEXTERR);
2046         E1000_READ_REG(hw, E1000_TSCTC);
2047         E1000_READ_REG(hw, E1000_TSCTFC);
2048
2049         E1000_READ_REG(hw, E1000_MGTPRC);
2050         E1000_READ_REG(hw, E1000_MGTPDC);
2051         E1000_READ_REG(hw, E1000_MGTPTC);
2052
2053         E1000_READ_REG(hw, E1000_IAC);
2054         E1000_READ_REG(hw, E1000_ICRXOC);
2055
2056         E1000_READ_REG(hw, E1000_ICRXPTC);
2057         E1000_READ_REG(hw, E1000_ICRXATC);
2058         E1000_READ_REG(hw, E1000_ICTXPTC);
2059         E1000_READ_REG(hw, E1000_ICTXATC);
2060         E1000_READ_REG(hw, E1000_ICTXQEC);
2061         E1000_READ_REG(hw, E1000_ICTXQMTC);
2062         E1000_READ_REG(hw, E1000_ICRXDMTC);
2063 }