sys/dev/hwpmc/hwpmc_intel.c

   1 /*-
   2  * Copyright (c) 2008 Joseph Koshy
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * Common code for handling Intel CPUs.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/pmc.h>
  36 #include <sys/pmckern.h>
  37 #include <sys/systm.h>
  38
  39 #include <machine/cpu.h>
  40 #include <machine/cputypes.h>
  41 #include <machine/md_var.h>
  42 #include <machine/specialreg.h>
  43
  44 static int
  45 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
  46 {
  47         (void) pc;
  48
  49         PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
  50             pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
  51
  52         /* allow the RDPMC instruction if needed */
  53         if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
  54                 load_cr4(rcr4() | CR4_PCE);
  55
  56         PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
  57
  58         return 0;
  59 }
  60
  61 static int
  62 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
  63 {
  64         (void) pc;
  65         (void) pp;              /* can be NULL */
  66
  67         PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
  68             (uintmax_t) rcr4());
  69
  70         /* always turn off the RDPMC instruction */
  71         load_cr4(rcr4() & ~CR4_PCE);
  72
  73         return 0;
  74 }
  75
  76 struct pmc_mdep *
  77 pmc_intel_initialize(void)
  78 {
  79         struct pmc_mdep *pmc_mdep;
  80         enum pmc_cputype cputype;
  81         int error, model, nclasses, ncpus;
  82
  83         KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
  84             ("[intel,%d] Initializing non-intel processor", __LINE__));
  85
  86         PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
  87
  88         cputype = -1;
  89         nclasses = 2;
  90
  91         model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
  92
  93         switch (cpu_id & 0xF00) {
  94 #if     defined(__i386__)
  95         case 0x500:             /* Pentium family processors */
  96                 cputype = PMC_CPU_INTEL_P5;
  97                 break;
  98 #endif
  99         case 0x600:             /* Pentium Pro, Celeron, Pentium II & III */
 100                 switch (model) {
 101 #if     defined(__i386__)
 102                 case 0x1:
 103                         cputype = PMC_CPU_INTEL_P6;
 104                         break;
 105                 case 0x3: case 0x5:
 106                         cputype = PMC_CPU_INTEL_PII;
 107                         break;
 108                 case 0x6: case 0x16:
 109                         cputype = PMC_CPU_INTEL_CL;
 110                         break;
 111                 case 0x7: case 0x8: case 0xA: case 0xB:
 112                         cputype = PMC_CPU_INTEL_PIII;
 113                         break;
 114                 case 0x9: case 0xD:
 115                         cputype = PMC_CPU_INTEL_PM;
 116                         break;
 117 #endif
 118                 case 0xE:
 119                         cputype = PMC_CPU_INTEL_CORE;
 120                         break;
 121                 case 0xF:
 122                         cputype = PMC_CPU_INTEL_CORE2;
 123                         nclasses = 3;
 124                         break;
 125                 case 0x17:
 126                         cputype = PMC_CPU_INTEL_CORE2EXTREME;
 127                         nclasses = 3;
 128                         break;
 129                 case 0x1C:      /* Per Intel document 320047-002. */
 130                         cputype = PMC_CPU_INTEL_ATOM;
 131                         nclasses = 3;
 132                         break;
 133                 case 0x1A:
 134                 case 0x1E:      /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
 135                 case 0x1F:      /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
 136                 case 0x2E:
 137                         cputype = PMC_CPU_INTEL_COREI7;
 138                         nclasses = 5;
 139                         break;
 140                 case 0x25:      /* Per Intel document 253669-033US 12/2009. */
 141                 case 0x2C:      /* Per Intel document 253669-033US 12/2009. */
 142                         cputype = PMC_CPU_INTEL_WESTMERE;
 143                         nclasses = 5;
 144                         break;
 145                 }
 146                 break;
 147 #if     defined(__i386__) || defined(__amd64__)
 148         case 0xF00:             /* P4 */
 149                 if (model >= 0 && model <= 6) /* known models */
 150                         cputype = PMC_CPU_INTEL_PIV;
 151                 break;
 152         }
 153 #endif
 154
 155         if ((int) cputype == -1) {
 156                 printf("pmc: Unknown Intel CPU.\n");
 157                 return (NULL);
 158         }
 159
 160         pmc_mdep = malloc(sizeof(struct pmc_mdep) + nclasses *
 161             sizeof(struct pmc_classdep), M_PMC, M_WAITOK|M_ZERO);
 162
 163         pmc_mdep->pmd_cputype    = cputype;
 164         pmc_mdep->pmd_nclass     = nclasses;
 165
 166         pmc_mdep->pmd_switch_in  = intel_switch_in;
 167         pmc_mdep->pmd_switch_out = intel_switch_out;
 168
 169         ncpus = pmc_cpu_max();
 170
 171         error = pmc_tsc_initialize(pmc_mdep, ncpus);
 172         if (error)
 173                 goto error;
 174
 175         switch (cputype) {
 176 #if     defined(__i386__) || defined(__amd64__)
 177                 /*
 178                  * Intel Core, Core 2 and Atom processors.
 179                  */
 180         case PMC_CPU_INTEL_ATOM:
 181         case PMC_CPU_INTEL_CORE:
 182         case PMC_CPU_INTEL_CORE2:
 183         case PMC_CPU_INTEL_CORE2EXTREME:
 184         case PMC_CPU_INTEL_COREI7:
 185         case PMC_CPU_INTEL_WESTMERE:
 186                 error = pmc_core_initialize(pmc_mdep, ncpus);
 187                 break;
 188
 189                 /*
 190                  * Intel Pentium 4 Processors, and P4/EMT64 processors.
 191                  */
 192
 193         case PMC_CPU_INTEL_PIV:
 194                 error = pmc_p4_initialize(pmc_mdep, ncpus);
 195
 196                 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P4_NPMCS,
 197                     ("[intel,%d] incorrect npmc count %d", __LINE__,
 198                     pmc_mdep->pmd_npmc));
 199                 break;
 200 #endif
 201
 202 #if     defined(__i386__)
 203                 /*
 204                  * P6 Family Processors
 205                  */
 206
 207         case PMC_CPU_INTEL_P6:
 208         case PMC_CPU_INTEL_CL:
 209         case PMC_CPU_INTEL_PII:
 210         case PMC_CPU_INTEL_PIII:
 211         case PMC_CPU_INTEL_PM:
 212                 error = pmc_p6_initialize(pmc_mdep, ncpus);
 213
 214                 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P6_NPMCS,
 215                     ("[intel,%d] incorrect npmc count %d", __LINE__,
 216                     pmc_mdep->pmd_npmc));
 217                 break;
 218
 219                 /*
 220                  * Intel Pentium PMCs.
 221                  */
 222
 223         case PMC_CPU_INTEL_P5:
 224                 error = pmc_p5_initialize(pmc_mdep, ncpus);
 225
 226                 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + PENTIUM_NPMCS,
 227                     ("[intel,%d] incorrect npmc count %d", __LINE__,
 228                     pmc_mdep->pmd_npmc));
 229                 break;
 230 #endif
 231
 232         default:
 233                 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
 234         }
 235
 236         /*
 237          * Init the uncore class.
 238          */
 239 #if     defined(__i386__) || defined(__amd64__)
 240         switch (cputype) {
 241                 /*
 242                  * Intel Corei7 and Westmere processors.
 243                  */
 244         case PMC_CPU_INTEL_COREI7:
 245         case PMC_CPU_INTEL_WESTMERE:
 246                 error = pmc_uncore_initialize(pmc_mdep, ncpus);
 247                 break;
 248         default:
 249                 break;
 250         }
 251 #endif
 252
 253   error:
 254         if (error) {
 255                 free(pmc_mdep, M_PMC);
 256                 pmc_mdep = NULL;
 257         }
 258
 259         return (pmc_mdep);
 260 }
 261
 262 void
 263 pmc_intel_finalize(struct pmc_mdep *md)
 264 {
 265         pmc_tsc_finalize(md);
 266
 267         switch (md->pmd_cputype) {
 268 #if     defined(__i386__) || defined(__amd64__)
 269         case PMC_CPU_INTEL_ATOM:
 270         case PMC_CPU_INTEL_CORE:
 271         case PMC_CPU_INTEL_CORE2:
 272         case PMC_CPU_INTEL_CORE2EXTREME:
 273         case PMC_CPU_INTEL_COREI7:
 274         case PMC_CPU_INTEL_WESTMERE:
 275                 pmc_core_finalize(md);
 276                 break;
 277
 278         case PMC_CPU_INTEL_PIV:
 279                 pmc_p4_finalize(md);
 280                 break;
 281 #endif
 282 #if     defined(__i386__)
 283         case PMC_CPU_INTEL_P6:
 284         case PMC_CPU_INTEL_CL:
 285         case PMC_CPU_INTEL_PII:
 286         case PMC_CPU_INTEL_PIII:
 287         case PMC_CPU_INTEL_PM:
 288                 pmc_p6_finalize(md);
 289                 break;
 290         case PMC_CPU_INTEL_P5:
 291                 pmc_p5_finalize(md);
 292                 break;
 293 #endif
 294         default:
 295                 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
 296         }
 297
 298         /*
 299          * Uncore.
 300          */
 301 #if     defined(__i386__) || defined(__amd64__)
 302         switch (md->pmd_cputype) {
 303         case PMC_CPU_INTEL_COREI7:
 304         case PMC_CPU_INTEL_WESTMERE:
 305                 pmc_uncore_finalize(md);
 306                 break;
 307         default:
 308                 break;
 309         }
 310 #endif
 311 }