2 * Copyright (c) 2007-2009
3 * Damien Bergamini <damien.bergamini@free.fr>
5 * Benjamin Close <benjsc@FreeBSD.org>
6 * Copyright (c) 2008 Sam Leffler, Errno Consulting
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/sockio.h>
31 #include <sys/sysctl.h>
33 #include <sys/kernel.h>
34 #include <sys/socket.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
39 #include <sys/endian.h>
40 #include <sys/firmware.h>
41 #include <sys/limits.h>
42 #include <sys/module.h>
43 #include <sys/queue.h>
44 #include <sys/taskqueue.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/clock.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
55 #include <net/if_arp.h>
56 #include <net/ethernet.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/if_ether.h>
65 #include <netinet/ip.h>
67 #include <net80211/ieee80211_var.h>
68 #include <net80211/ieee80211_radiotap.h>
69 #include <net80211/ieee80211_regdomain.h>
70 #include <net80211/ieee80211_ratectl.h>
72 #include <dev/iwn/if_iwnreg.h>
73 #include <dev/iwn/if_iwnvar.h>
81 static const struct iwn_ident iwn_ident_table[] = {
82 { 0x8086, 0x0082, "Intel(R) Centrino(R) Advanced-N 6205" },
83 { 0x8086, 0x0083, "Intel(R) Centrino(R) Wireless-N 1000" },
84 { 0x8086, 0x0084, "Intel(R) Centrino(R) Wireless-N 1000" },
85 { 0x8086, 0x0085, "Intel(R) Centrino(R) Advanced-N 6205" },
86 { 0x8086, 0x0087, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" },
87 { 0x8086, 0x0089, "Intel(R) Centrino(R) Advanced-N + WiMAX 6250" },
88 { 0x8086, 0x008a, "Intel(R) Centrino(R) Wireless-N 1030" },
89 { 0x8086, 0x008b, "Intel(R) Centrino(R) Wireless-N 1030" },
90 { 0x8086, 0x0090, "Intel(R) Centrino(R) Advanced-N 6230" },
91 { 0x8086, 0x0091, "Intel(R) Centrino(R) Advanced-N 6230" },
92 { 0x8086, 0x0896, "Intel(R) Centrino(R) Wireless-N 130" },
93 { 0x8086, 0x4229, "Intel(R) Wireless WiFi Link 4965" },
94 { 0x8086, 0x422b, "Intel(R) Centrino(R) Ultimate-N 6300" },
95 { 0x8086, 0x422c, "Intel(R) Centrino(R) Advanced-N 6200" },
96 { 0x8086, 0x422d, "Intel(R) Wireless WiFi Link 4965" },
97 { 0x8086, 0x4230, "Intel(R) Wireless WiFi Link 4965" },
98 { 0x8086, 0x4232, "Intel(R) WiFi Link 5100" },
99 { 0x8086, 0x4233, "Intel(R) Wireless WiFi Link 4965" },
100 { 0x8086, 0x4235, "Intel(R) Ultimate N WiFi Link 5300" },
101 { 0x8086, 0x4236, "Intel(R) Ultimate N WiFi Link 5300" },
102 { 0x8086, 0x4237, "Intel(R) WiFi Link 5100" },
103 { 0x8086, 0x4238, "Intel(R) Centrino(R) Ultimate-N 6300" },
104 { 0x8086, 0x4239, "Intel(R) Centrino(R) Advanced-N 6200" },
105 { 0x8086, 0x423a, "Intel(R) WiMAX/WiFi Link 5350" },
106 { 0x8086, 0x423b, "Intel(R) WiMAX/WiFi Link 5350" },
107 { 0x8086, 0x423c, "Intel(R) WiMAX/WiFi Link 5150" },
108 { 0x8086, 0x423d, "Intel(R) WiMAX/WiFi Link 5150" },
112 static int iwn_probe(device_t);
113 static int iwn_attach(device_t);
114 static int iwn4965_attach(struct iwn_softc *, uint16_t);
115 static int iwn5000_attach(struct iwn_softc *, uint16_t);
116 static void iwn_radiotap_attach(struct iwn_softc *);
117 static void iwn_sysctlattach(struct iwn_softc *);
118 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *,
119 const char name[IFNAMSIZ], int unit, int opmode,
120 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
121 const uint8_t mac[IEEE80211_ADDR_LEN]);
122 static void iwn_vap_delete(struct ieee80211vap *);
123 static int iwn_detach(device_t);
124 static int iwn_shutdown(device_t);
125 static int iwn_suspend(device_t);
126 static int iwn_resume(device_t);
127 static int iwn_nic_lock(struct iwn_softc *);
128 static int iwn_eeprom_lock(struct iwn_softc *);
129 static int iwn_init_otprom(struct iwn_softc *);
130 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
131 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int);
132 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *,
133 void **, bus_size_t, bus_size_t);
134 static void iwn_dma_contig_free(struct iwn_dma_info *);
135 static int iwn_alloc_sched(struct iwn_softc *);
136 static void iwn_free_sched(struct iwn_softc *);
137 static int iwn_alloc_kw(struct iwn_softc *);
138 static void iwn_free_kw(struct iwn_softc *);
139 static int iwn_alloc_ict(struct iwn_softc *);
140 static void iwn_free_ict(struct iwn_softc *);
141 static int iwn_alloc_fwmem(struct iwn_softc *);
142 static void iwn_free_fwmem(struct iwn_softc *);
143 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
144 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
145 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
146 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
148 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
149 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
150 static void iwn5000_ict_reset(struct iwn_softc *);
151 static int iwn_read_eeprom(struct iwn_softc *,
152 uint8_t macaddr[IEEE80211_ADDR_LEN]);
153 static void iwn4965_read_eeprom(struct iwn_softc *);
154 static void iwn4965_print_power_group(struct iwn_softc *, int);
155 static void iwn5000_read_eeprom(struct iwn_softc *);
156 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *);
157 static void iwn_read_eeprom_band(struct iwn_softc *, int);
158 static void iwn_read_eeprom_ht40(struct iwn_softc *, int);
159 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t);
160 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *,
161 struct ieee80211_channel *);
162 static int iwn_setregdomain(struct ieee80211com *,
163 struct ieee80211_regdomain *, int,
164 struct ieee80211_channel[]);
165 static void iwn_read_eeprom_enhinfo(struct iwn_softc *);
166 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *,
167 const uint8_t mac[IEEE80211_ADDR_LEN]);
168 static void iwn_newassoc(struct ieee80211_node *, int);
169 static int iwn_media_change(struct ifnet *);
170 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
171 static void iwn_calib_timeout(void *);
172 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *,
173 struct iwn_rx_data *);
174 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
175 struct iwn_rx_data *);
176 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *,
177 struct iwn_rx_data *);
178 static void iwn5000_rx_calib_results(struct iwn_softc *,
179 struct iwn_rx_desc *, struct iwn_rx_data *);
180 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *,
181 struct iwn_rx_data *);
182 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
183 struct iwn_rx_data *);
184 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
185 struct iwn_rx_data *);
186 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int,
188 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *);
189 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
190 static void iwn_notif_intr(struct iwn_softc *);
191 static void iwn_wakeup_intr(struct iwn_softc *);
192 static void iwn_rftoggle_intr(struct iwn_softc *);
193 static void iwn_fatal_intr(struct iwn_softc *);
194 static void iwn_intr(void *);
195 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
197 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
200 static void iwn5000_reset_sched(struct iwn_softc *, int, int);
202 static int iwn_tx_data(struct iwn_softc *, struct mbuf *,
203 struct ieee80211_node *);
204 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *,
205 struct ieee80211_node *,
206 const struct ieee80211_bpf_params *params);
207 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
208 const struct ieee80211_bpf_params *);
209 static void iwn_start(struct ifnet *);
210 static void iwn_start_locked(struct ifnet *);
211 static void iwn_watchdog(void *);
212 static int iwn_ioctl(struct ifnet *, u_long, caddr_t);
213 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int);
214 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
216 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
218 static int iwn_set_link_quality(struct iwn_softc *,
219 struct ieee80211_node *);
220 static int iwn_add_broadcast_node(struct iwn_softc *, int);
221 static int iwn_updateedca(struct ieee80211com *);
222 static void iwn_update_mcast(struct ifnet *);
223 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
224 static int iwn_set_critical_temp(struct iwn_softc *);
225 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
226 static void iwn4965_power_calibration(struct iwn_softc *, int);
227 static int iwn4965_set_txpower(struct iwn_softc *,
228 struct ieee80211_channel *, int);
229 static int iwn5000_set_txpower(struct iwn_softc *,
230 struct ieee80211_channel *, int);
231 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
232 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
233 static int iwn_get_noise(const struct iwn_rx_general_stats *);
234 static int iwn4965_get_temperature(struct iwn_softc *);
235 static int iwn5000_get_temperature(struct iwn_softc *);
236 static int iwn_init_sensitivity(struct iwn_softc *);
237 static void iwn_collect_noise(struct iwn_softc *,
238 const struct iwn_rx_general_stats *);
239 static int iwn4965_init_gains(struct iwn_softc *);
240 static int iwn5000_init_gains(struct iwn_softc *);
241 static int iwn4965_set_gains(struct iwn_softc *);
242 static int iwn5000_set_gains(struct iwn_softc *);
243 static void iwn_tune_sensitivity(struct iwn_softc *,
244 const struct iwn_rx_stats *);
245 static int iwn_send_sensitivity(struct iwn_softc *);
246 static int iwn_set_pslevel(struct iwn_softc *, int, int, int);
247 static int iwn_send_btcoex(struct iwn_softc *);
248 static int iwn_send_advanced_btcoex(struct iwn_softc *);
249 static int iwn_config(struct iwn_softc *);
250 static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int);
251 static int iwn_scan(struct iwn_softc *);
252 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap);
253 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap);
254 static int iwn_ampdu_rx_start(struct ieee80211_node *,
255 struct ieee80211_rx_ampdu *, int, int, int);
256 static void iwn_ampdu_rx_stop(struct ieee80211_node *,
257 struct ieee80211_rx_ampdu *);
258 static int iwn_addba_request(struct ieee80211_node *,
259 struct ieee80211_tx_ampdu *, int, int, int);
260 static int iwn_addba_response(struct ieee80211_node *,
261 struct ieee80211_tx_ampdu *, int, int, int);
262 static int iwn_ampdu_tx_start(struct ieee80211com *,
263 struct ieee80211_node *, uint8_t);
264 static void iwn_ampdu_tx_stop(struct ieee80211_node *,
265 struct ieee80211_tx_ampdu *);
266 static void iwn4965_ampdu_tx_start(struct iwn_softc *,
267 struct ieee80211_node *, int, uint8_t, uint16_t);
268 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int,
270 static void iwn5000_ampdu_tx_start(struct iwn_softc *,
271 struct ieee80211_node *, int, uint8_t, uint16_t);
272 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int,
274 static int iwn5000_query_calibration(struct iwn_softc *);
275 static int iwn5000_send_calibration(struct iwn_softc *);
276 static int iwn5000_send_wimax_coex(struct iwn_softc *);
277 static int iwn5000_crystal_calib(struct iwn_softc *);
278 static int iwn5000_temp_offset_calib(struct iwn_softc *);
279 static int iwn4965_post_alive(struct iwn_softc *);
280 static int iwn5000_post_alive(struct iwn_softc *);
281 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
283 static int iwn4965_load_firmware(struct iwn_softc *);
284 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
285 const uint8_t *, int);
286 static int iwn5000_load_firmware(struct iwn_softc *);
287 static int iwn_read_firmware_leg(struct iwn_softc *,
288 struct iwn_fw_info *);
289 static int iwn_read_firmware_tlv(struct iwn_softc *,
290 struct iwn_fw_info *, uint16_t);
291 static int iwn_read_firmware(struct iwn_softc *);
292 static int iwn_clock_wait(struct iwn_softc *);
293 static int iwn_apm_init(struct iwn_softc *);
294 static void iwn_apm_stop_master(struct iwn_softc *);
295 static void iwn_apm_stop(struct iwn_softc *);
296 static int iwn4965_nic_config(struct iwn_softc *);
297 static int iwn5000_nic_config(struct iwn_softc *);
298 static int iwn_hw_prepare(struct iwn_softc *);
299 static int iwn_hw_init(struct iwn_softc *);
300 static void iwn_hw_stop(struct iwn_softc *);
301 static void iwn_radio_on(void *, int);
302 static void iwn_radio_off(void *, int);
303 static void iwn_init_locked(struct iwn_softc *);
304 static void iwn_init(void *);
305 static void iwn_stop_locked(struct iwn_softc *);
306 static void iwn_stop(struct iwn_softc *);
307 static void iwn_scan_start(struct ieee80211com *);
308 static void iwn_scan_end(struct ieee80211com *);
309 static void iwn_set_channel(struct ieee80211com *);
310 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long);
311 static void iwn_scan_mindwell(struct ieee80211_scan_state *);
312 static void iwn_hw_reset(void *, int);
317 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
318 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */
319 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */
320 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */
321 IWN_DEBUG_RESET = 0x00000010, /* reset processing */
322 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */
323 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */
324 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */
325 IWN_DEBUG_INTR = 0x00000100, /* ISR */
326 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */
327 IWN_DEBUG_NODE = 0x00000400, /* node management */
328 IWN_DEBUG_LED = 0x00000800, /* led management */
329 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */
330 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */
331 IWN_DEBUG_ANY = 0xffffffff
334 #define DPRINTF(sc, m, fmt, ...) do { \
335 if (sc->sc_debug & (m)) \
336 printf(fmt, __VA_ARGS__); \
340 iwn_intr_str(uint8_t cmd)
344 case IWN_UC_READY: return "UC_READY";
345 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE";
346 case IWN_TX_DONE: return "TX_DONE";
347 case IWN_START_SCAN: return "START_SCAN";
348 case IWN_STOP_SCAN: return "STOP_SCAN";
349 case IWN_RX_STATISTICS: return "RX_STATS";
350 case IWN_BEACON_STATISTICS: return "BEACON_STATS";
351 case IWN_STATE_CHANGED: return "STATE_CHANGED";
352 case IWN_BEACON_MISSED: return "BEACON_MISSED";
353 case IWN_RX_PHY: return "RX_PHY";
354 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE";
355 case IWN_RX_DONE: return "RX_DONE";
357 /* Command Notifications */
358 case IWN_CMD_RXON: return "IWN_CMD_RXON";
359 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC";
360 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS";
361 case IWN_CMD_TIMING: return "IWN_CMD_TIMING";
362 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY";
363 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED";
364 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX";
365 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG";
366 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT";
367 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE";
368 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE";
369 case IWN_CMD_SCAN: return "IWN_CMD_SCAN";
370 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS";
371 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER";
372 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM";
373 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG";
374 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX";
375 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP";
376 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY";
377 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB";
379 return "UNKNOWN INTR NOTIF/CMD";
382 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0)
385 static device_method_t iwn_methods[] = {
386 /* Device interface */
387 DEVMETHOD(device_probe, iwn_probe),
388 DEVMETHOD(device_attach, iwn_attach),
389 DEVMETHOD(device_detach, iwn_detach),
390 DEVMETHOD(device_shutdown, iwn_shutdown),
391 DEVMETHOD(device_suspend, iwn_suspend),
392 DEVMETHOD(device_resume, iwn_resume),
396 static driver_t iwn_driver = {
399 sizeof(struct iwn_softc)
401 static devclass_t iwn_devclass;
403 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0);
405 MODULE_VERSION(iwn, 1);
407 MODULE_DEPEND(iwn, firmware, 1, 1, 1);
408 MODULE_DEPEND(iwn, pci, 1, 1, 1);
409 MODULE_DEPEND(iwn, wlan, 1, 1, 1);
412 iwn_probe(device_t dev)
414 const struct iwn_ident *ident;
416 for (ident = iwn_ident_table; ident->name != NULL; ident++) {
417 if (pci_get_vendor(dev) == ident->vendor &&
418 pci_get_device(dev) == ident->device) {
419 device_set_desc(dev, ident->name);
427 iwn_attach(device_t dev)
429 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
430 struct ieee80211com *ic;
433 int i, error, result;
434 uint8_t macaddr[IEEE80211_ADDR_LEN];
439 * Get the offset of the PCI Express Capability Structure in PCI
440 * Configuration Space.
442 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
444 device_printf(dev, "PCIe capability structure not found!\n");
448 /* Clear device-specific "PCI retry timeout" register (41h). */
449 pci_write_config(dev, 0x41, 0, 1);
451 /* Hardware bug workaround. */
452 reg = pci_read_config(dev, PCIR_COMMAND, 1);
453 if (reg & PCIM_CMD_INTxDIS) {
454 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n",
456 reg &= ~PCIM_CMD_INTxDIS;
457 pci_write_config(dev, PCIR_COMMAND, reg, 1);
460 /* Enable bus-mastering. */
461 pci_enable_busmaster(dev);
463 sc->mem_rid = PCIR_BAR(0);
464 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
466 if (sc->mem == NULL) {
467 device_printf(dev, "can't map mem space\n");
471 sc->sc_st = rman_get_bustag(sc->mem);
472 sc->sc_sh = rman_get_bushandle(sc->mem);
475 if ((result = pci_msi_count(dev)) == 1 &&
476 pci_alloc_msi(dev, &result) == 0)
478 /* Install interrupt handler. */
479 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
480 RF_ACTIVE | RF_SHAREABLE);
481 if (sc->irq == NULL) {
482 device_printf(dev, "can't map interrupt\n");
489 /* Read hardware revision and attach. */
490 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf;
491 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
492 error = iwn4965_attach(sc, pci_get_device(dev));
494 error = iwn5000_attach(sc, pci_get_device(dev));
496 device_printf(dev, "could not attach device, error %d\n",
501 if ((error = iwn_hw_prepare(sc)) != 0) {
502 device_printf(dev, "hardware not ready, error %d\n", error);
506 /* Allocate DMA memory for firmware transfers. */
507 if ((error = iwn_alloc_fwmem(sc)) != 0) {
509 "could not allocate memory for firmware, error %d\n",
514 /* Allocate "Keep Warm" page. */
515 if ((error = iwn_alloc_kw(sc)) != 0) {
517 "could not allocate keep warm page, error %d\n", error);
521 /* Allocate ICT table for 5000 Series. */
522 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
523 (error = iwn_alloc_ict(sc)) != 0) {
524 device_printf(dev, "could not allocate ICT table, error %d\n",
529 /* Allocate TX scheduler "rings". */
530 if ((error = iwn_alloc_sched(sc)) != 0) {
532 "could not allocate TX scheduler rings, error %d\n", error);
536 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */
537 for (i = 0; i < sc->ntxqs; i++) {
538 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) {
540 "could not allocate TX ring %d, error %d\n", i,
546 /* Allocate RX ring. */
547 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) {
548 device_printf(dev, "could not allocate RX ring, error %d\n",
553 /* Clear pending interrupts. */
554 IWN_WRITE(sc, IWN_INT, 0xffffffff);
556 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
558 device_printf(dev, "can not allocate ifnet structure\n");
564 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
565 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
567 /* Set device capabilities. */
569 IEEE80211_C_STA /* station mode supported */
570 | IEEE80211_C_MONITOR /* monitor mode supported */
571 | IEEE80211_C_BGSCAN /* background scanning */
572 | IEEE80211_C_TXPMGT /* tx power management */
573 | IEEE80211_C_SHSLOT /* short slot time supported */
575 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
577 | IEEE80211_C_IBSS /* ibss/adhoc mode */
579 | IEEE80211_C_WME /* WME */
582 /* Read MAC address, channels, etc from EEPROM. */
583 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) {
584 device_printf(dev, "could not read EEPROM, error %d\n",
589 /* Count the number of available chains. */
591 ((sc->txchainmask >> 2) & 1) +
592 ((sc->txchainmask >> 1) & 1) +
593 ((sc->txchainmask >> 0) & 1);
595 ((sc->rxchainmask >> 2) & 1) +
596 ((sc->rxchainmask >> 1) & 1) +
597 ((sc->rxchainmask >> 0) & 1);
599 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n",
600 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
604 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
605 ic->ic_rxstream = sc->nrxchains;
606 ic->ic_txstream = sc->ntxchains;
608 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */
609 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */
610 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/
611 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */
613 | IEEE80211_HTCAP_GREENFIELD
614 #if IWN_RBUF_SIZE == 8192
615 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */
617 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */
620 /* s/w capabilities */
621 | IEEE80211_HTC_HT /* HT operation */
622 | IEEE80211_HTC_AMPDU /* tx A-MPDU */
624 | IEEE80211_HTC_AMSDU /* tx A-MSDU */
629 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
631 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
632 ifp->if_init = iwn_init;
633 ifp->if_ioctl = iwn_ioctl;
634 ifp->if_start = iwn_start;
635 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
636 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
637 IFQ_SET_READY(&ifp->if_snd);
639 ieee80211_ifattach(ic, macaddr);
640 ic->ic_vap_create = iwn_vap_create;
641 ic->ic_vap_delete = iwn_vap_delete;
642 ic->ic_raw_xmit = iwn_raw_xmit;
643 ic->ic_node_alloc = iwn_node_alloc;
644 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start;
645 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
646 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop;
647 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
648 sc->sc_addba_request = ic->ic_addba_request;
649 ic->ic_addba_request = iwn_addba_request;
650 sc->sc_addba_response = ic->ic_addba_response;
651 ic->ic_addba_response = iwn_addba_response;
652 sc->sc_addba_stop = ic->ic_addba_stop;
653 ic->ic_addba_stop = iwn_ampdu_tx_stop;
654 ic->ic_newassoc = iwn_newassoc;
655 ic->ic_wme.wme_update = iwn_updateedca;
656 ic->ic_update_mcast = iwn_update_mcast;
657 ic->ic_scan_start = iwn_scan_start;
658 ic->ic_scan_end = iwn_scan_end;
659 ic->ic_set_channel = iwn_set_channel;
660 ic->ic_scan_curchan = iwn_scan_curchan;
661 ic->ic_scan_mindwell = iwn_scan_mindwell;
662 ic->ic_setregdomain = iwn_setregdomain;
664 iwn_radiotap_attach(sc);
666 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0);
667 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0);
668 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc);
669 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc);
670 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc);
672 iwn_sysctlattach(sc);
675 * Hook our interrupt after all initialization is complete.
677 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
678 NULL, iwn_intr, sc, &sc->sc_ih);
680 device_printf(dev, "can't establish interrupt, error %d\n",
686 ieee80211_announce(ic);
694 iwn4965_attach(struct iwn_softc *sc, uint16_t pid)
696 struct iwn_ops *ops = &sc->ops;
698 ops->load_firmware = iwn4965_load_firmware;
699 ops->read_eeprom = iwn4965_read_eeprom;
700 ops->post_alive = iwn4965_post_alive;
701 ops->nic_config = iwn4965_nic_config;
702 ops->update_sched = iwn4965_update_sched;
703 ops->get_temperature = iwn4965_get_temperature;
704 ops->get_rssi = iwn4965_get_rssi;
705 ops->set_txpower = iwn4965_set_txpower;
706 ops->init_gains = iwn4965_init_gains;
707 ops->set_gains = iwn4965_set_gains;
708 ops->add_node = iwn4965_add_node;
709 ops->tx_done = iwn4965_tx_done;
710 ops->ampdu_tx_start = iwn4965_ampdu_tx_start;
711 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop;
712 sc->ntxqs = IWN4965_NTXQUEUES;
713 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE;
714 sc->ndmachnls = IWN4965_NDMACHNLS;
715 sc->broadcast_id = IWN4965_ID_BROADCAST;
716 sc->rxonsz = IWN4965_RXONSZ;
717 sc->schedsz = IWN4965_SCHEDSZ;
718 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ;
719 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ;
720 sc->fwsz = IWN4965_FWSZ;
721 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT;
722 sc->limits = &iwn4965_sensitivity_limits;
723 sc->fwname = "iwn4965fw";
724 /* Override chains masks, ROM is known to be broken. */
725 sc->txchainmask = IWN_ANT_AB;
726 sc->rxchainmask = IWN_ANT_ABC;
732 iwn5000_attach(struct iwn_softc *sc, uint16_t pid)
734 struct iwn_ops *ops = &sc->ops;
736 ops->load_firmware = iwn5000_load_firmware;
737 ops->read_eeprom = iwn5000_read_eeprom;
738 ops->post_alive = iwn5000_post_alive;
739 ops->nic_config = iwn5000_nic_config;
740 ops->update_sched = iwn5000_update_sched;
741 ops->get_temperature = iwn5000_get_temperature;
742 ops->get_rssi = iwn5000_get_rssi;
743 ops->set_txpower = iwn5000_set_txpower;
744 ops->init_gains = iwn5000_init_gains;
745 ops->set_gains = iwn5000_set_gains;
746 ops->add_node = iwn5000_add_node;
747 ops->tx_done = iwn5000_tx_done;
748 ops->ampdu_tx_start = iwn5000_ampdu_tx_start;
749 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop;
750 sc->ntxqs = IWN5000_NTXQUEUES;
751 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE;
752 sc->ndmachnls = IWN5000_NDMACHNLS;
753 sc->broadcast_id = IWN5000_ID_BROADCAST;
754 sc->rxonsz = IWN5000_RXONSZ;
755 sc->schedsz = IWN5000_SCHEDSZ;
756 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ;
757 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ;
758 sc->fwsz = IWN5000_FWSZ;
759 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT;
760 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN;
761 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN;
763 switch (sc->hw_type) {
764 case IWN_HW_REV_TYPE_5100:
765 sc->limits = &iwn5000_sensitivity_limits;
766 sc->fwname = "iwn5000fw";
767 /* Override chains masks, ROM is known to be broken. */
768 sc->txchainmask = IWN_ANT_B;
769 sc->rxchainmask = IWN_ANT_AB;
771 case IWN_HW_REV_TYPE_5150:
772 sc->limits = &iwn5150_sensitivity_limits;
773 sc->fwname = "iwn5150fw";
775 case IWN_HW_REV_TYPE_5300:
776 case IWN_HW_REV_TYPE_5350:
777 sc->limits = &iwn5000_sensitivity_limits;
778 sc->fwname = "iwn5000fw";
780 case IWN_HW_REV_TYPE_1000:
781 sc->limits = &iwn1000_sensitivity_limits;
782 sc->fwname = "iwn1000fw";
784 case IWN_HW_REV_TYPE_6000:
785 sc->limits = &iwn6000_sensitivity_limits;
786 sc->fwname = "iwn6000fw";
787 if (pid == 0x422c || pid == 0x4239) {
788 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
789 /* Override chains masks, ROM is known to be broken. */
790 sc->txchainmask = IWN_ANT_BC;
791 sc->rxchainmask = IWN_ANT_BC;
794 case IWN_HW_REV_TYPE_6050:
795 sc->limits = &iwn6000_sensitivity_limits;
796 sc->fwname = "iwn6050fw";
797 /* Override chains masks, ROM is known to be broken. */
798 sc->txchainmask = IWN_ANT_AB;
799 sc->rxchainmask = IWN_ANT_AB;
801 case IWN_HW_REV_TYPE_6005:
802 sc->limits = &iwn6000_sensitivity_limits;
803 if (pid != 0x0082 && pid != 0x0085) {
804 sc->fwname = "iwn6000g2bfw";
805 sc->sc_flags |= IWN_FLAG_ADV_BTCOEX;
807 sc->fwname = "iwn6000g2afw";
810 device_printf(sc->sc_dev, "adapter type %d not supported\n",
818 * Attach the interface to 802.11 radiotap.
821 iwn_radiotap_attach(struct iwn_softc *sc)
823 struct ifnet *ifp = sc->sc_ifp;
824 struct ieee80211com *ic = ifp->if_l2com;
826 ieee80211_radiotap_attach(ic,
827 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
828 IWN_TX_RADIOTAP_PRESENT,
829 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
830 IWN_RX_RADIOTAP_PRESENT);
834 iwn_sysctlattach(struct iwn_softc *sc)
836 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
837 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
841 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
842 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs");
846 static struct ieee80211vap *
847 iwn_vap_create(struct ieee80211com *ic,
848 const char name[IFNAMSIZ], int unit, int opmode, int flags,
849 const uint8_t bssid[IEEE80211_ADDR_LEN],
850 const uint8_t mac[IEEE80211_ADDR_LEN])
853 struct ieee80211vap *vap;
855 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
857 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap),
858 M_80211_VAP, M_NOWAIT | M_ZERO);
862 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
863 vap->iv_bmissthreshold = 10; /* override default */
864 /* Override with driver methods. */
865 ivp->iv_newstate = vap->iv_newstate;
866 vap->iv_newstate = iwn_newstate;
868 ieee80211_ratectl_init(vap);
869 /* Complete setup. */
870 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status);
871 ic->ic_opmode = opmode;
876 iwn_vap_delete(struct ieee80211vap *vap)
878 struct iwn_vap *ivp = IWN_VAP(vap);
880 ieee80211_ratectl_deinit(vap);
881 ieee80211_vap_detach(vap);
882 free(ivp, M_80211_VAP);
886 iwn_detach(device_t dev)
888 struct iwn_softc *sc = device_get_softc(dev);
889 struct ifnet *ifp = sc->sc_ifp;
890 struct ieee80211com *ic;
896 ieee80211_draintask(ic, &sc->sc_reinit_task);
897 ieee80211_draintask(ic, &sc->sc_radioon_task);
898 ieee80211_draintask(ic, &sc->sc_radiooff_task);
901 callout_drain(&sc->watchdog_to);
902 callout_drain(&sc->calib_to);
903 ieee80211_ifdetach(ic);
906 /* Uninstall interrupt handler. */
907 if (sc->irq != NULL) {
908 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
909 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
910 if (sc->irq_rid == 1)
911 pci_release_msi(dev);
914 /* Free DMA resources. */
915 iwn_free_rx_ring(sc, &sc->rxq);
916 for (qid = 0; qid < sc->ntxqs; qid++)
917 iwn_free_tx_ring(sc, &sc->txq[qid]);
925 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
930 IWN_LOCK_DESTROY(sc);
935 iwn_shutdown(device_t dev)
937 struct iwn_softc *sc = device_get_softc(dev);
944 iwn_suspend(device_t dev)
946 struct iwn_softc *sc = device_get_softc(dev);
947 struct ifnet *ifp = sc->sc_ifp;
948 struct ieee80211com *ic = ifp->if_l2com;
949 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
958 iwn_resume(device_t dev)
960 struct iwn_softc *sc = device_get_softc(dev);
961 struct ifnet *ifp = sc->sc_ifp;
962 struct ieee80211com *ic = ifp->if_l2com;
963 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
965 /* Clear device-specific "PCI retry timeout" register (41h). */
966 pci_write_config(dev, 0x41, 0, 1);
968 if (ifp->if_flags & IFF_UP) {
972 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
979 iwn_nic_lock(struct iwn_softc *sc)
983 /* Request exclusive access to NIC. */
984 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
986 /* Spin until we actually get the lock. */
987 for (ntries = 0; ntries < 1000; ntries++) {
988 if ((IWN_READ(sc, IWN_GP_CNTRL) &
989 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
990 IWN_GP_CNTRL_MAC_ACCESS_ENA)
998 iwn_nic_unlock(struct iwn_softc *sc)
1000 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
1003 static __inline uint32_t
1004 iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
1006 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
1007 IWN_BARRIER_READ_WRITE(sc);
1008 return IWN_READ(sc, IWN_PRPH_RDATA);
1011 static __inline void
1012 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1014 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
1015 IWN_BARRIER_WRITE(sc);
1016 IWN_WRITE(sc, IWN_PRPH_WDATA, data);
1019 static __inline void
1020 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1022 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
1025 static __inline void
1026 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1028 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
1031 static __inline void
1032 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
1033 const uint32_t *data, int count)
1035 for (; count > 0; count--, data++, addr += 4)
1036 iwn_prph_write(sc, addr, *data);
1039 static __inline uint32_t
1040 iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
1042 IWN_WRITE(sc, IWN_MEM_RADDR, addr);
1043 IWN_BARRIER_READ_WRITE(sc);
1044 return IWN_READ(sc, IWN_MEM_RDATA);
1047 static __inline void
1048 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1050 IWN_WRITE(sc, IWN_MEM_WADDR, addr);
1051 IWN_BARRIER_WRITE(sc);
1052 IWN_WRITE(sc, IWN_MEM_WDATA, data);
1055 static __inline void
1056 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
1060 tmp = iwn_mem_read(sc, addr & ~3);
1062 tmp = (tmp & 0x0000ffff) | data << 16;
1064 tmp = (tmp & 0xffff0000) | data;
1065 iwn_mem_write(sc, addr & ~3, tmp);
1068 static __inline void
1069 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
1072 for (; count > 0; count--, addr += 4)
1073 *data++ = iwn_mem_read(sc, addr);
1076 static __inline void
1077 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
1080 for (; count > 0; count--, addr += 4)
1081 iwn_mem_write(sc, addr, val);
1085 iwn_eeprom_lock(struct iwn_softc *sc)
1089 for (i = 0; i < 100; i++) {
1090 /* Request exclusive access to EEPROM. */
1091 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1092 IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1094 /* Spin until we actually get the lock. */
1095 for (ntries = 0; ntries < 100; ntries++) {
1096 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1097 IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1105 static __inline void
1106 iwn_eeprom_unlock(struct iwn_softc *sc)
1108 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1112 * Initialize access by host to One Time Programmable ROM.
1113 * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1116 iwn_init_otprom(struct iwn_softc *sc)
1118 uint16_t prev, base, next;
1121 /* Wait for clock stabilization before accessing prph. */
1122 if ((error = iwn_clock_wait(sc)) != 0)
1125 if ((error = iwn_nic_lock(sc)) != 0)
1127 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1129 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1132 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1133 if (sc->hw_type != IWN_HW_REV_TYPE_1000) {
1134 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1135 IWN_RESET_LINK_PWR_MGMT_DIS);
1137 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1138 /* Clear ECC status. */
1139 IWN_SETBITS(sc, IWN_OTP_GP,
1140 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1143 * Find the block before last block (contains the EEPROM image)
1144 * for HW without OTP shadow RAM.
1146 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
1147 /* Switch to absolute addressing mode. */
1148 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1150 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) {
1151 error = iwn_read_prom_data(sc, base, &next, 2);
1154 if (next == 0) /* End of linked-list. */
1157 base = le16toh(next);
1159 if (count == 0 || count == IWN1000_OTP_NBLOCKS)
1161 /* Skip "next" word. */
1162 sc->prom_base = prev + 1;
1168 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1170 uint8_t *out = data;
1174 addr += sc->prom_base;
1175 for (; count > 0; count -= 2, addr++) {
1176 IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1177 for (ntries = 0; ntries < 10; ntries++) {
1178 val = IWN_READ(sc, IWN_EEPROM);
1179 if (val & IWN_EEPROM_READ_VALID)
1184 device_printf(sc->sc_dev,
1185 "timeout reading ROM at 0x%x\n", addr);
1188 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1189 /* OTPROM, check for ECC errors. */
1190 tmp = IWN_READ(sc, IWN_OTP_GP);
1191 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1192 device_printf(sc->sc_dev,
1193 "OTPROM ECC error at 0x%x\n", addr);
1196 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1197 /* Correctable ECC error, clear bit. */
1198 IWN_SETBITS(sc, IWN_OTP_GP,
1199 IWN_OTP_GP_ECC_CORR_STTS);
1210 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1214 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs));
1215 *(bus_addr_t *)arg = segs[0].ds_addr;
1219 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
1220 void **kvap, bus_size_t size, bus_size_t alignment)
1227 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment,
1228 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size,
1229 1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag);
1233 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
1234 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map);
1238 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size,
1239 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT);
1243 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
1250 fail: iwn_dma_contig_free(dma);
1255 iwn_dma_contig_free(struct iwn_dma_info *dma)
1257 if (dma->map != NULL) {
1258 if (dma->vaddr != NULL) {
1259 bus_dmamap_sync(dma->tag, dma->map,
1260 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1261 bus_dmamap_unload(dma->tag, dma->map);
1262 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map);
1265 bus_dmamap_destroy(dma->tag, dma->map);
1268 if (dma->tag != NULL) {
1269 bus_dma_tag_destroy(dma->tag);
1275 iwn_alloc_sched(struct iwn_softc *sc)
1277 /* TX scheduler rings must be aligned on a 1KB boundary. */
1278 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched,
1283 iwn_free_sched(struct iwn_softc *sc)
1285 iwn_dma_contig_free(&sc->sched_dma);
1289 iwn_alloc_kw(struct iwn_softc *sc)
1291 /* "Keep Warm" page must be aligned on a 4KB boundary. */
1292 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096);
1296 iwn_free_kw(struct iwn_softc *sc)
1298 iwn_dma_contig_free(&sc->kw_dma);
1302 iwn_alloc_ict(struct iwn_softc *sc)
1304 /* ICT table must be aligned on a 4KB boundary. */
1305 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict,
1306 IWN_ICT_SIZE, 4096);
1310 iwn_free_ict(struct iwn_softc *sc)
1312 iwn_dma_contig_free(&sc->ict_dma);
1316 iwn_alloc_fwmem(struct iwn_softc *sc)
1318 /* Must be aligned on a 16-byte boundary. */
1319 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16);
1323 iwn_free_fwmem(struct iwn_softc *sc)
1325 iwn_dma_contig_free(&sc->fw_dma);
1329 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1336 /* Allocate RX descriptors (256-byte aligned). */
1337 size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1338 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
1341 device_printf(sc->sc_dev,
1342 "%s: could not allocate RX ring DMA memory, error %d\n",
1347 /* Allocate RX status area (16-byte aligned). */
1348 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat,
1349 sizeof (struct iwn_rx_status), 16);
1351 device_printf(sc->sc_dev,
1352 "%s: could not allocate RX status DMA memory, error %d\n",
1357 /* Create RX buffer DMA tag. */
1358 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
1359 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1360 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL,
1363 device_printf(sc->sc_dev,
1364 "%s: could not create RX buf DMA tag, error %d\n",
1370 * Allocate and map RX buffers.
1372 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1373 struct iwn_rx_data *data = &ring->data[i];
1376 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1378 device_printf(sc->sc_dev,
1379 "%s: could not create RX buf DMA map, error %d\n",
1384 data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR,
1386 if (data->m == NULL) {
1387 device_printf(sc->sc_dev,
1388 "%s: could not allocate RX mbuf\n", __func__);
1393 error = bus_dmamap_load(ring->data_dmat, data->map,
1394 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
1395 &paddr, BUS_DMA_NOWAIT);
1396 if (error != 0 && error != EFBIG) {
1397 device_printf(sc->sc_dev,
1398 "%s: can't not map mbuf, error %d\n", __func__,
1403 /* Set physical address of RX buffer (256-byte aligned). */
1404 ring->desc[i] = htole32(paddr >> 8);
1407 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1408 BUS_DMASYNC_PREWRITE);
1412 fail: iwn_free_rx_ring(sc, ring);
1417 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1421 if (iwn_nic_lock(sc) == 0) {
1422 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1423 for (ntries = 0; ntries < 1000; ntries++) {
1424 if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1425 IWN_FH_RX_STATUS_IDLE)
1432 sc->last_rx_valid = 0;
1436 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1440 iwn_dma_contig_free(&ring->desc_dma);
1441 iwn_dma_contig_free(&ring->stat_dma);
1443 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1444 struct iwn_rx_data *data = &ring->data[i];
1446 if (data->m != NULL) {
1447 bus_dmamap_sync(ring->data_dmat, data->map,
1448 BUS_DMASYNC_POSTREAD);
1449 bus_dmamap_unload(ring->data_dmat, data->map);
1453 if (data->map != NULL)
1454 bus_dmamap_destroy(ring->data_dmat, data->map);
1456 if (ring->data_dmat != NULL) {
1457 bus_dma_tag_destroy(ring->data_dmat);
1458 ring->data_dmat = NULL;
1463 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1473 /* Allocate TX descriptors (256-byte aligned). */
1474 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc);
1475 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
1478 device_printf(sc->sc_dev,
1479 "%s: could not allocate TX ring DMA memory, error %d\n",
1484 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd);
1485 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd,
1488 device_printf(sc->sc_dev,
1489 "%s: could not allocate TX cmd DMA memory, error %d\n",
1494 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
1495 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
1496 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL,
1499 device_printf(sc->sc_dev,
1500 "%s: could not create TX buf DMA tag, error %d\n",
1505 paddr = ring->cmd_dma.paddr;
1506 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1507 struct iwn_tx_data *data = &ring->data[i];
1509 data->cmd_paddr = paddr;
1510 data->scratch_paddr = paddr + 12;
1511 paddr += sizeof (struct iwn_tx_cmd);
1513 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1515 device_printf(sc->sc_dev,
1516 "%s: could not create TX buf DMA map, error %d\n",
1523 fail: iwn_free_tx_ring(sc, ring);
1528 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1532 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1533 struct iwn_tx_data *data = &ring->data[i];
1535 if (data->m != NULL) {
1536 bus_dmamap_sync(ring->data_dmat, data->map,
1537 BUS_DMASYNC_POSTWRITE);
1538 bus_dmamap_unload(ring->data_dmat, data->map);
1543 /* Clear TX descriptors. */
1544 memset(ring->desc, 0, ring->desc_dma.size);
1545 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1546 BUS_DMASYNC_PREWRITE);
1547 sc->qfullmsk &= ~(1 << ring->qid);
1553 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1557 iwn_dma_contig_free(&ring->desc_dma);
1558 iwn_dma_contig_free(&ring->cmd_dma);
1560 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1561 struct iwn_tx_data *data = &ring->data[i];
1563 if (data->m != NULL) {
1564 bus_dmamap_sync(ring->data_dmat, data->map,
1565 BUS_DMASYNC_POSTWRITE);
1566 bus_dmamap_unload(ring->data_dmat, data->map);
1569 if (data->map != NULL)
1570 bus_dmamap_destroy(ring->data_dmat, data->map);
1572 if (ring->data_dmat != NULL) {
1573 bus_dma_tag_destroy(ring->data_dmat);
1574 ring->data_dmat = NULL;
1579 iwn5000_ict_reset(struct iwn_softc *sc)
1581 /* Disable interrupts. */
1582 IWN_WRITE(sc, IWN_INT_MASK, 0);
1584 /* Reset ICT table. */
1585 memset(sc->ict, 0, IWN_ICT_SIZE);
1588 /* Set physical address of ICT table (4KB aligned). */
1589 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__);
1590 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
1591 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
1593 /* Enable periodic RX interrupt. */
1594 sc->int_mask |= IWN_INT_RX_PERIODIC;
1595 /* Switch to ICT interrupt mode in driver. */
1596 sc->sc_flags |= IWN_FLAG_USE_ICT;
1598 /* Re-enable interrupts. */
1599 IWN_WRITE(sc, IWN_INT, 0xffffffff);
1600 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
1604 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
1606 struct iwn_ops *ops = &sc->ops;
1610 /* Check whether adapter has an EEPROM or an OTPROM. */
1611 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
1612 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
1613 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
1614 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n",
1615 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM");
1617 /* Adapter has to be powered on for EEPROM access to work. */
1618 if ((error = iwn_apm_init(sc)) != 0) {
1619 device_printf(sc->sc_dev,
1620 "%s: could not power ON adapter, error %d\n", __func__,
1625 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
1626 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__);
1629 if ((error = iwn_eeprom_lock(sc)) != 0) {
1630 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n",
1634 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1635 if ((error = iwn_init_otprom(sc)) != 0) {
1636 device_printf(sc->sc_dev,
1637 "%s: could not initialize OTPROM, error %d\n",
1643 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2);
1644 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val));
1645 /* Check if HT support is bonded out. */
1646 if (val & htole16(IWN_EEPROM_SKU_CAP_11N))
1647 sc->sc_flags |= IWN_FLAG_HAS_11N;
1649 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
1650 sc->rfcfg = le16toh(val);
1651 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg);
1652 /* Read Tx/Rx chains from ROM unless it's known to be broken. */
1653 if (sc->txchainmask == 0)
1654 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg);
1655 if (sc->rxchainmask == 0)
1656 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg);
1658 /* Read MAC address. */
1659 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6);
1661 /* Read adapter-specific information from EEPROM. */
1662 ops->read_eeprom(sc);
1664 iwn_apm_stop(sc); /* Power OFF adapter. */
1666 iwn_eeprom_unlock(sc);
1671 iwn4965_read_eeprom(struct iwn_softc *sc)
1677 /* Read regulatory domain (4 ASCII characters). */
1678 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
1680 /* Read the list of authorized channels (20MHz ones only). */
1681 for (i = 0; i < 7; i++) {
1682 addr = iwn4965_regulatory_bands[i];
1683 iwn_read_eeprom_channels(sc, i, addr);
1686 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */
1687 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
1688 sc->maxpwr2GHz = val & 0xff;
1689 sc->maxpwr5GHz = val >> 8;
1690 /* Check that EEPROM values are within valid range. */
1691 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
1692 sc->maxpwr5GHz = 38;
1693 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
1694 sc->maxpwr2GHz = 38;
1695 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n",
1696 sc->maxpwr2GHz, sc->maxpwr5GHz);
1698 /* Read samples for each TX power group. */
1699 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
1702 /* Read voltage at which samples were taken. */
1703 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
1704 sc->eeprom_voltage = (int16_t)le16toh(val);
1705 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n",
1706 sc->eeprom_voltage);
1709 /* Print samples. */
1710 if (sc->sc_debug & IWN_DEBUG_ANY) {
1711 for (i = 0; i < IWN_NBANDS; i++)
1712 iwn4965_print_power_group(sc, i);
1719 iwn4965_print_power_group(struct iwn_softc *sc, int i)
1721 struct iwn4965_eeprom_band *band = &sc->bands[i];
1722 struct iwn4965_eeprom_chan_samples *chans = band->chans;
1725 printf("===band %d===\n", i);
1726 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
1727 printf("chan1 num=%d\n", chans[0].num);
1728 for (c = 0; c < 2; c++) {
1729 for (j = 0; j < IWN_NSAMPLES; j++) {
1730 printf("chain %d, sample %d: temp=%d gain=%d "
1731 "power=%d pa_det=%d\n", c, j,
1732 chans[0].samples[c][j].temp,
1733 chans[0].samples[c][j].gain,
1734 chans[0].samples[c][j].power,
1735 chans[0].samples[c][j].pa_det);
1738 printf("chan2 num=%d\n", chans[1].num);
1739 for (c = 0; c < 2; c++) {
1740 for (j = 0; j < IWN_NSAMPLES; j++) {
1741 printf("chain %d, sample %d: temp=%d gain=%d "
1742 "power=%d pa_det=%d\n", c, j,
1743 chans[1].samples[c][j].temp,
1744 chans[1].samples[c][j].gain,
1745 chans[1].samples[c][j].power,
1746 chans[1].samples[c][j].pa_det);
1753 iwn5000_read_eeprom(struct iwn_softc *sc)
1755 struct iwn5000_eeprom_calib_hdr hdr;
1757 uint32_t base, addr;
1761 /* Read regulatory domain (4 ASCII characters). */
1762 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1763 base = le16toh(val);
1764 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
1765 sc->eeprom_domain, 4);
1767 /* Read the list of authorized channels (20MHz ones only). */
1768 for (i = 0; i < 7; i++) {
1769 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1770 addr = base + iwn6000_regulatory_bands[i];
1772 addr = base + iwn5000_regulatory_bands[i];
1773 iwn_read_eeprom_channels(sc, i, addr);
1776 /* Read enhanced TX power information for 6000 Series. */
1777 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1778 iwn_read_eeprom_enhinfo(sc);
1780 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
1781 base = le16toh(val);
1782 iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
1783 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
1784 "%s: calib version=%u pa type=%u voltage=%u\n", __func__,
1785 hdr.version, hdr.pa_type, le16toh(hdr.volt));
1786 sc->calib_ver = hdr.version;
1788 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
1789 /* Compute temperature offset. */
1790 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1791 sc->eeprom_temp = le16toh(val);
1792 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
1793 volt = le16toh(val);
1794 sc->temp_off = sc->eeprom_temp - (volt / -5);
1795 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n",
1796 sc->eeprom_temp, volt, sc->temp_off);
1798 /* Read crystal calibration. */
1799 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
1800 &sc->eeprom_crystal, sizeof (uint32_t));
1801 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n",
1802 le32toh(sc->eeprom_crystal));
1807 * Translate EEPROM flags to net80211.
1810 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel)
1815 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0)
1816 nflags |= IEEE80211_CHAN_PASSIVE;
1817 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0)
1818 nflags |= IEEE80211_CHAN_NOADHOC;
1819 if (channel->flags & IWN_EEPROM_CHAN_RADAR) {
1820 nflags |= IEEE80211_CHAN_DFS;
1821 /* XXX apparently IBSS may still be marked */
1822 nflags |= IEEE80211_CHAN_NOADHOC;
1829 iwn_read_eeprom_band(struct iwn_softc *sc, int n)
1831 struct ifnet *ifp = sc->sc_ifp;
1832 struct ieee80211com *ic = ifp->if_l2com;
1833 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1834 const struct iwn_chan_band *band = &iwn_bands[n];
1835 struct ieee80211_channel *c;
1839 for (i = 0; i < band->nchan; i++) {
1840 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
1841 DPRINTF(sc, IWN_DEBUG_RESET,
1842 "skip chan %d flags 0x%x maxpwr %d\n",
1843 band->chan[i], channels[i].flags,
1844 channels[i].maxpwr);
1847 chan = band->chan[i];
1848 nflags = iwn_eeprom_channel_flags(&channels[i]);
1850 c = &ic->ic_channels[ic->ic_nchans++];
1852 c->ic_maxregpower = channels[i].maxpwr;
1853 c->ic_maxpower = 2*c->ic_maxregpower;
1855 if (n == 0) { /* 2GHz band */
1856 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G);
1857 /* G =>'s B is supported */
1858 c->ic_flags = IEEE80211_CHAN_B | nflags;
1859 c = &ic->ic_channels[ic->ic_nchans++];
1861 c->ic_flags = IEEE80211_CHAN_G | nflags;
1862 } else { /* 5GHz band */
1863 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A);
1864 c->ic_flags = IEEE80211_CHAN_A | nflags;
1867 /* Save maximum allowed TX power for this channel. */
1868 sc->maxpwr[chan] = channels[i].maxpwr;
1870 DPRINTF(sc, IWN_DEBUG_RESET,
1871 "add chan %d flags 0x%x maxpwr %d\n", chan,
1872 channels[i].flags, channels[i].maxpwr);
1874 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
1875 /* add HT20, HT40 added separately */
1876 c = &ic->ic_channels[ic->ic_nchans++];
1878 c->ic_flags |= IEEE80211_CHAN_HT20;
1884 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n)
1886 struct ifnet *ifp = sc->sc_ifp;
1887 struct ieee80211com *ic = ifp->if_l2com;
1888 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1889 const struct iwn_chan_band *band = &iwn_bands[n];
1890 struct ieee80211_channel *c, *cent, *extc;
1894 if (!(sc->sc_flags & IWN_FLAG_HAS_11N))
1897 for (i = 0; i < band->nchan; i++) {
1898 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
1899 DPRINTF(sc, IWN_DEBUG_RESET,
1900 "skip chan %d flags 0x%x maxpwr %d\n",
1901 band->chan[i], channels[i].flags,
1902 channels[i].maxpwr);
1905 chan = band->chan[i];
1906 nflags = iwn_eeprom_channel_flags(&channels[i]);
1909 * Each entry defines an HT40 channel pair; find the
1910 * center channel, then the extension channel above.
1912 cent = ieee80211_find_channel_byieee(ic, chan,
1913 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A));
1914 if (cent == NULL) { /* XXX shouldn't happen */
1915 device_printf(sc->sc_dev,
1916 "%s: no entry for channel %d\n", __func__, chan);
1919 extc = ieee80211_find_channel(ic, cent->ic_freq+20,
1920 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A));
1922 DPRINTF(sc, IWN_DEBUG_RESET,
1923 "%s: skip chan %d, extension channel not found\n",
1928 DPRINTF(sc, IWN_DEBUG_RESET,
1929 "add ht40 chan %d flags 0x%x maxpwr %d\n",
1930 chan, channels[i].flags, channels[i].maxpwr);
1932 c = &ic->ic_channels[ic->ic_nchans++];
1934 c->ic_extieee = extc->ic_ieee;
1935 c->ic_flags &= ~IEEE80211_CHAN_HT;
1936 c->ic_flags |= IEEE80211_CHAN_HT40U | nflags;
1937 c = &ic->ic_channels[ic->ic_nchans++];
1939 c->ic_extieee = cent->ic_ieee;
1940 c->ic_flags &= ~IEEE80211_CHAN_HT;
1941 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags;
1946 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
1948 struct ifnet *ifp = sc->sc_ifp;
1949 struct ieee80211com *ic = ifp->if_l2com;
1951 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n],
1952 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan));
1955 iwn_read_eeprom_band(sc, n);
1957 iwn_read_eeprom_ht40(sc, n);
1958 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
1961 static struct iwn_eeprom_chan *
1962 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c)
1964 int band, chan, i, j;
1966 if (IEEE80211_IS_CHAN_HT40(c)) {
1967 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5;
1968 if (IEEE80211_IS_CHAN_HT40D(c))
1969 chan = c->ic_extieee;
1972 for (i = 0; i < iwn_bands[band].nchan; i++) {
1973 if (iwn_bands[band].chan[i] == chan)
1974 return &sc->eeprom_channels[band][i];
1977 for (j = 0; j < 5; j++) {
1978 for (i = 0; i < iwn_bands[j].nchan; i++) {
1979 if (iwn_bands[j].chan[i] == c->ic_ieee)
1980 return &sc->eeprom_channels[j][i];
1988 * Enforce flags read from EEPROM.
1991 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd,
1992 int nchan, struct ieee80211_channel chans[])
1994 struct iwn_softc *sc = ic->ic_ifp->if_softc;
1997 for (i = 0; i < nchan; i++) {
1998 struct ieee80211_channel *c = &chans[i];
1999 struct iwn_eeprom_chan *channel;
2001 channel = iwn_find_eeprom_channel(sc, c);
2002 if (channel == NULL) {
2003 if_printf(ic->ic_ifp,
2004 "%s: invalid channel %u freq %u/0x%x\n",
2005 __func__, c->ic_ieee, c->ic_freq, c->ic_flags);
2008 c->ic_flags |= iwn_eeprom_channel_flags(channel);
2014 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0]))
2017 iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
2019 struct iwn_eeprom_enhinfo enhinfo[35];
2020 struct ifnet *ifp = sc->sc_ifp;
2021 struct ieee80211com *ic = ifp->if_l2com;
2022 struct ieee80211_channel *c;
2028 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
2029 base = le16toh(val);
2030 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO,
2031 enhinfo, sizeof enhinfo);
2033 for (i = 0; i < nitems(enhinfo); i++) {
2034 flags = enhinfo[i].flags;
2035 if (!(flags & IWN_ENHINFO_VALID))
2036 continue; /* Skip invalid entries. */
2039 if (sc->txchainmask & IWN_ANT_A)
2040 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]);
2041 if (sc->txchainmask & IWN_ANT_B)
2042 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]);
2043 if (sc->txchainmask & IWN_ANT_C)
2044 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]);
2045 if (sc->ntxchains == 2)
2046 maxpwr = MAX(maxpwr, enhinfo[i].mimo2);
2047 else if (sc->ntxchains == 3)
2048 maxpwr = MAX(maxpwr, enhinfo[i].mimo3);
2050 for (j = 0; j < ic->ic_nchans; j++) {
2051 c = &ic->ic_channels[j];
2052 if ((flags & IWN_ENHINFO_5GHZ)) {
2053 if (!IEEE80211_IS_CHAN_A(c))
2055 } else if ((flags & IWN_ENHINFO_OFDM)) {
2056 if (!IEEE80211_IS_CHAN_G(c))
2058 } else if (!IEEE80211_IS_CHAN_B(c))
2060 if ((flags & IWN_ENHINFO_HT40)) {
2061 if (!IEEE80211_IS_CHAN_HT40(c))
2064 if (IEEE80211_IS_CHAN_HT40(c))
2067 if (enhinfo[i].chan != 0 &&
2068 enhinfo[i].chan != c->ic_ieee)
2071 DPRINTF(sc, IWN_DEBUG_RESET,
2072 "channel %d(%x), maxpwr %d\n", c->ic_ieee,
2073 c->ic_flags, maxpwr / 2);
2074 c->ic_maxregpower = maxpwr / 2;
2075 c->ic_maxpower = maxpwr;
2080 static struct ieee80211_node *
2081 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
2083 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO);
2089 switch (rate & 0xff) {
2090 case 12: return 0xd;
2091 case 18: return 0xf;
2092 case 24: return 0x5;
2093 case 36: return 0x7;
2094 case 48: return 0x9;
2095 case 72: return 0xb;
2096 case 96: return 0x1;
2097 case 108: return 0x3;
2101 case 22: return 110;
2107 iwn_newassoc(struct ieee80211_node *ni, int isnew)
2109 #define RV(v) ((v) & IEEE80211_RATE_VAL)
2110 struct ieee80211com *ic = ni->ni_ic;
2111 struct iwn_softc *sc = ic->ic_ifp->if_softc;
2112 struct iwn_node *wn = (void *)ni;
2113 uint8_t txant1, txant2;
2114 int i, plcp, rate, ridx;
2116 /* Use the first valid TX antenna. */
2117 txant1 = IWN_LSB(sc->txchainmask);
2118 txant2 = IWN_LSB(sc->txchainmask & ~txant1);
2120 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
2121 ridx = ni->ni_rates.rs_nrates - 1;
2122 for (i = ni->ni_htrates.rs_nrates - 1; i >= 0; i--) {
2123 plcp = RV(ni->ni_htrates.rs_rates[i]) | IWN_RFLAG_MCS;
2124 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
2125 plcp |= IWN_RFLAG_HT40;
2126 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40)
2127 plcp |= IWN_RFLAG_SGI;
2128 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20)
2129 plcp |= IWN_RFLAG_SGI;
2131 plcp |= IWN_RFLAG_ANT(txant1 | txant2);
2133 plcp |= IWN_RFLAG_ANT(txant1);
2135 rate = RV(ni->ni_rates.rs_rates[ridx]);
2136 wn->ridx[rate] = plcp;
2138 wn->ridx[IEEE80211_RATE_MCS | i] = plcp;
2142 for (i = 0; i < ni->ni_rates.rs_nrates; i++) {
2143 rate = RV(ni->ni_rates.rs_rates[i]);
2144 plcp = rate2plcp(rate);
2145 ridx = ic->ic_rt->rateCodeToIndex[rate];
2146 if (ridx < IWN_RIDX_OFDM6 &&
2147 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
2148 plcp |= IWN_RFLAG_CCK;
2149 plcp |= IWN_RFLAG_ANT(txant1);
2150 wn->ridx[rate] = htole32(plcp);
2157 iwn_media_change(struct ifnet *ifp)
2161 error = ieee80211_media_change(ifp);
2162 /* NB: only the fixed rate can change and that doesn't need a reset */
2163 return (error == ENETRESET ? 0 : error);
2167 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
2169 struct iwn_vap *ivp = IWN_VAP(vap);
2170 struct ieee80211com *ic = vap->iv_ic;
2171 struct iwn_softc *sc = ic->ic_ifp->if_softc;
2174 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
2175 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]);
2177 IEEE80211_UNLOCK(ic);
2179 callout_stop(&sc->calib_to);
2182 case IEEE80211_S_ASSOC:
2183 if (vap->iv_state != IEEE80211_S_RUN)
2186 case IEEE80211_S_AUTH:
2187 if (vap->iv_state == IEEE80211_S_AUTH)
2191 * !AUTH -> AUTH transition requires state reset to handle
2192 * reassociations correctly.
2194 sc->rxon.associd = 0;
2195 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS);
2196 sc->calib.state = IWN_CALIB_STATE_INIT;
2198 if ((error = iwn_auth(sc, vap)) != 0) {
2199 device_printf(sc->sc_dev,
2200 "%s: could not move to auth state\n", __func__);
2204 case IEEE80211_S_RUN:
2206 * RUN -> RUN transition; Just restart the timers.
2208 if (vap->iv_state == IEEE80211_S_RUN) {
2214 * !RUN -> RUN requires setting the association id
2215 * which is done with a firmware cmd. We also defer
2216 * starting the timers until that work is done.
2218 if ((error = iwn_run(sc, vap)) != 0) {
2219 device_printf(sc->sc_dev,
2220 "%s: could not move to run state\n", __func__);
2224 case IEEE80211_S_INIT:
2225 sc->calib.state = IWN_CALIB_STATE_INIT;
2235 return ivp->iv_newstate(vap, nstate, arg);
2239 iwn_calib_timeout(void *arg)
2241 struct iwn_softc *sc = arg;
2243 IWN_LOCK_ASSERT(sc);
2245 /* Force automatic TX power calibration every 60 secs. */
2246 if (++sc->calib_cnt >= 120) {
2249 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n",
2250 "sending request for statistics");
2251 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags,
2255 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
2260 * Process an RX_PHY firmware notification. This is usually immediately
2261 * followed by an MPDU_RX_DONE notification.
2264 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2265 struct iwn_rx_data *data)
2267 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1);
2269 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__);
2270 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2272 /* Save RX statistics, they will be used on MPDU_RX_DONE. */
2273 memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
2274 sc->last_rx_valid = 1;
2278 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification.
2279 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one.
2282 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2283 struct iwn_rx_data *data)
2285 struct iwn_ops *ops = &sc->ops;
2286 struct ifnet *ifp = sc->sc_ifp;
2287 struct ieee80211com *ic = ifp->if_l2com;
2288 struct iwn_rx_ring *ring = &sc->rxq;
2289 struct ieee80211_frame *wh;
2290 struct ieee80211_node *ni;
2291 struct mbuf *m, *m1;
2292 struct iwn_rx_stat *stat;
2296 int error, len, rssi, nf;
2298 if (desc->type == IWN_MPDU_RX_DONE) {
2299 /* Check for prior RX_PHY notification. */
2300 if (!sc->last_rx_valid) {
2301 DPRINTF(sc, IWN_DEBUG_ANY,
2302 "%s: missing RX_PHY\n", __func__);
2305 stat = &sc->last_rx_stat;
2307 stat = (struct iwn_rx_stat *)(desc + 1);
2309 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2311 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
2312 device_printf(sc->sc_dev,
2313 "%s: invalid RX statistic header, len %d\n", __func__,
2317 if (desc->type == IWN_MPDU_RX_DONE) {
2318 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1);
2319 head = (caddr_t)(mpdu + 1);
2320 len = le16toh(mpdu->len);
2322 head = (caddr_t)(stat + 1) + stat->cfg_phy_len;
2323 len = le16toh(stat->len);
2326 flags = le32toh(*(uint32_t *)(head + len));
2328 /* Discard frames with a bad FCS early. */
2329 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) {
2330 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n",
2335 /* Discard frames that are too short. */
2336 if (len < sizeof (*wh)) {
2337 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n",
2343 m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE);
2345 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n",
2350 bus_dmamap_unload(ring->data_dmat, data->map);
2352 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *),
2353 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
2354 if (error != 0 && error != EFBIG) {
2355 device_printf(sc->sc_dev,
2356 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
2359 /* Try to reload the old mbuf. */
2360 error = bus_dmamap_load(ring->data_dmat, data->map,
2361 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
2362 &paddr, BUS_DMA_NOWAIT);
2363 if (error != 0 && error != EFBIG) {
2364 panic("%s: could not load old RX mbuf", __func__);
2366 /* Physical address may have changed. */
2367 ring->desc[ring->cur] = htole32(paddr >> 8);
2368 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map,
2369 BUS_DMASYNC_PREWRITE);
2376 /* Update RX descriptor. */
2377 ring->desc[ring->cur] = htole32(paddr >> 8);
2378 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
2379 BUS_DMASYNC_PREWRITE);
2381 /* Finalize mbuf. */
2382 m->m_pkthdr.rcvif = ifp;
2384 m->m_pkthdr.len = m->m_len = len;
2386 /* Grab a reference to the source node. */
2387 wh = mtod(m, struct ieee80211_frame *);
2388 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
2389 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN &&
2390 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95;
2392 rssi = ops->get_rssi(sc, stat);
2394 if (ieee80211_radiotap_active(ic)) {
2395 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
2398 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
2399 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2400 tap->wr_dbm_antsignal = (int8_t)rssi;
2401 tap->wr_dbm_antnoise = (int8_t)nf;
2402 tap->wr_tsft = stat->tstamp;
2403 switch (stat->rate) {
2405 case 10: tap->wr_rate = 2; break;
2406 case 20: tap->wr_rate = 4; break;
2407 case 55: tap->wr_rate = 11; break;
2408 case 110: tap->wr_rate = 22; break;
2410 case 0xd: tap->wr_rate = 12; break;
2411 case 0xf: tap->wr_rate = 18; break;
2412 case 0x5: tap->wr_rate = 24; break;
2413 case 0x7: tap->wr_rate = 36; break;
2414 case 0x9: tap->wr_rate = 48; break;
2415 case 0xb: tap->wr_rate = 72; break;
2416 case 0x1: tap->wr_rate = 96; break;
2417 case 0x3: tap->wr_rate = 108; break;
2418 /* Unknown rate: should not happen. */
2419 default: tap->wr_rate = 0;
2425 /* Send the frame to the 802.11 layer. */
2427 if (ni->ni_flags & IEEE80211_NODE_HT)
2428 m->m_flags |= M_AMPDU;
2429 (void)ieee80211_input(ni, m, rssi - nf, nf);
2430 /* Node is no longer needed. */
2431 ieee80211_free_node(ni);
2433 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
2438 /* Process an incoming Compressed BlockAck. */
2440 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2441 struct iwn_rx_data *data)
2443 struct ifnet *ifp = sc->sc_ifp;
2444 struct iwn_node *wn;
2445 struct ieee80211_node *ni;
2446 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1);
2447 struct iwn_tx_ring *txq;
2448 struct ieee80211_tx_ampdu *tap;
2451 int ackfailcnt = 0, i, shift;
2453 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2455 txq = &sc->txq[le16toh(ba->qid)];
2456 tap = sc->qid2tap[le16toh(ba->qid)];
2457 tid = WME_AC_TO_TID(tap->txa_ac);
2461 if (wn->agg[tid].bitmap == 0)
2464 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff);
2468 if (wn->agg[tid].nframes > (64 - shift))
2471 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap;
2472 for (i = 0; bitmap; i++) {
2473 if ((bitmap & 1) == 0) {
2475 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
2476 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
2479 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
2480 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
2487 * Process a CALIBRATION_RESULT notification sent by the initialization
2488 * firmware on response to a CMD_CALIB_CONFIG command (5000 only).
2491 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2492 struct iwn_rx_data *data)
2494 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1);
2497 /* Runtime firmware should not send such a notification. */
2498 if (sc->sc_flags & IWN_FLAG_CALIB_DONE)
2501 len = (le32toh(desc->len) & 0x3fff) - 4;
2502 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2504 switch (calib->code) {
2505 case IWN5000_PHY_CALIB_DC:
2506 if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0 &&
2507 (sc->hw_type == IWN_HW_REV_TYPE_5150 ||
2508 sc->hw_type >= IWN_HW_REV_TYPE_6000))
2511 case IWN5000_PHY_CALIB_LO:
2514 case IWN5000_PHY_CALIB_TX_IQ:
2517 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC:
2518 if (sc->hw_type < IWN_HW_REV_TYPE_6000 &&
2519 sc->hw_type != IWN_HW_REV_TYPE_5150)
2522 case IWN5000_PHY_CALIB_BASE_BAND:
2526 if (idx == -1) /* Ignore other results. */
2529 /* Save calibration result. */
2530 if (sc->calibcmd[idx].buf != NULL)
2531 free(sc->calibcmd[idx].buf, M_DEVBUF);
2532 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT);
2533 if (sc->calibcmd[idx].buf == NULL) {
2534 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2535 "not enough memory for calibration result %d\n",
2539 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2540 "saving calibration result code=%d len=%d\n", calib->code, len);
2541 sc->calibcmd[idx].len = len;
2542 memcpy(sc->calibcmd[idx].buf, calib, len);
2546 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification.
2547 * The latter is sent by the firmware after each received beacon.
2550 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2551 struct iwn_rx_data *data)
2553 struct iwn_ops *ops = &sc->ops;
2554 struct ifnet *ifp = sc->sc_ifp;
2555 struct ieee80211com *ic = ifp->if_l2com;
2556 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2557 struct iwn_calib_state *calib = &sc->calib;
2558 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1);
2561 /* Ignore statistics received during a scan. */
2562 if (vap->iv_state != IEEE80211_S_RUN ||
2563 (ic->ic_flags & IEEE80211_F_SCAN))
2566 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2568 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received statistics, cmd %d\n",
2569 __func__, desc->type);
2570 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */
2572 /* Test if temperature has changed. */
2573 if (stats->general.temp != sc->rawtemp) {
2574 /* Convert "raw" temperature to degC. */
2575 sc->rawtemp = stats->general.temp;
2576 temp = ops->get_temperature(sc);
2577 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n",
2580 /* Update TX power if need be (4965AGN only). */
2581 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
2582 iwn4965_power_calibration(sc, temp);
2585 if (desc->type != IWN_BEACON_STATISTICS)
2586 return; /* Reply to a statistics request. */
2588 sc->noise = iwn_get_noise(&stats->rx.general);
2589 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise);
2591 /* Test that RSSI and noise are present in stats report. */
2592 if (le32toh(stats->rx.general.flags) != 1) {
2593 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
2594 "received statistics without RSSI");
2598 if (calib->state == IWN_CALIB_STATE_ASSOC)
2599 iwn_collect_noise(sc, &stats->rx.general);
2600 else if (calib->state == IWN_CALIB_STATE_RUN)
2601 iwn_tune_sensitivity(sc, &stats->rx);
2605 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN
2606 * and 5000 adapters have different incompatible TX status formats.
2609 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2610 struct iwn_rx_data *data)
2612 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1);
2613 struct iwn_tx_ring *ring;
2616 qid = desc->qid & 0xf;
2617 ring = &sc->txq[qid];
2619 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2620 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2621 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2622 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2623 le32toh(stat->status));
2625 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2626 if (qid >= sc->firstaggqueue) {
2627 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes,
2630 iwn_tx_done(sc, desc, stat->ackfailcnt,
2631 le32toh(stat->status) & 0xff);
2636 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2637 struct iwn_rx_data *data)
2639 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1);
2640 struct iwn_tx_ring *ring;
2643 qid = desc->qid & 0xf;
2644 ring = &sc->txq[qid];
2646 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2647 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2648 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2649 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2650 le32toh(stat->status));
2653 /* Reset TX scheduler slot. */
2654 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx);
2657 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2658 if (qid >= sc->firstaggqueue) {
2659 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes,
2662 iwn_tx_done(sc, desc, stat->ackfailcnt,
2663 le16toh(stat->status) & 0xff);
2668 * Adapter-independent backend for TX_DONE firmware notifications.
2671 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt,
2674 struct ifnet *ifp = sc->sc_ifp;
2675 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2676 struct iwn_tx_data *data = &ring->data[desc->idx];
2678 struct ieee80211_node *ni;
2679 struct ieee80211vap *vap;
2681 KASSERT(data->ni != NULL, ("no node"));
2683 /* Unmap and free mbuf. */
2684 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
2685 bus_dmamap_unload(ring->data_dmat, data->map);
2686 m = data->m, data->m = NULL;
2687 ni = data->ni, data->ni = NULL;
2690 if (m->m_flags & M_TXCB) {
2692 * Channels marked for "radar" require traffic to be received
2693 * to unlock before we can transmit. Until traffic is seen
2694 * any attempt to transmit is returned immediately with status
2695 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily
2696 * happen on first authenticate after scanning. To workaround
2697 * this we ignore a failure of this sort in AUTH state so the
2698 * 802.11 layer will fall back to using a timeout to wait for
2699 * the AUTH reply. This allows the firmware time to see
2700 * traffic so a subsequent retry of AUTH succeeds. It's
2701 * unclear why the firmware does not maintain state for
2702 * channels recently visited as this would allow immediate
2703 * use of the channel after a scan (where we see traffic).
2705 if (status == IWN_TX_FAIL_TX_LOCKED &&
2706 ni->ni_vap->iv_state == IEEE80211_S_AUTH)
2707 ieee80211_process_callback(ni, m, 0);
2709 ieee80211_process_callback(ni, m,
2710 (status & IWN_TX_FAIL) != 0);
2714 * Update rate control statistics for the node.
2716 if (status & IWN_TX_FAIL) {
2718 ieee80211_ratectl_tx_complete(vap, ni,
2719 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
2722 ieee80211_ratectl_tx_complete(vap, ni,
2723 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
2726 ieee80211_free_node(ni);
2728 sc->sc_tx_timer = 0;
2729 if (--ring->queued < IWN_TX_RING_LOMARK) {
2730 sc->qfullmsk &= ~(1 << ring->qid);
2731 if (sc->qfullmsk == 0 &&
2732 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
2733 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2734 iwn_start_locked(ifp);
2740 * Process a "command done" firmware notification. This is where we wakeup
2741 * processes waiting for a synchronous command completion.
2744 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc)
2746 struct iwn_tx_ring *ring = &sc->txq[4];
2747 struct iwn_tx_data *data;
2749 if ((desc->qid & 0xf) != 4)
2750 return; /* Not a command ack. */
2752 data = &ring->data[desc->idx];
2754 /* If the command was mapped in an mbuf, free it. */
2755 if (data->m != NULL) {
2756 bus_dmamap_sync(ring->data_dmat, data->map,
2757 BUS_DMASYNC_POSTWRITE);
2758 bus_dmamap_unload(ring->data_dmat, data->map);
2762 wakeup(&ring->desc[desc->idx]);
2766 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes,
2769 struct ifnet *ifp = sc->sc_ifp;
2770 struct iwn_tx_ring *ring = &sc->txq[qid];
2771 struct iwn_tx_data *data;
2773 struct iwn_node *wn;
2774 struct ieee80211_node *ni;
2775 struct ieee80211vap *vap;
2776 struct ieee80211_tx_ampdu *tap;
2778 uint32_t *status = stat;
2779 uint16_t *aggstatus = stat;
2781 int bit, i, lastidx, seqno, shift, start;
2785 if ((*status & 0xff) != 1 && (*status & 0xff) != 2)
2786 printf("ieee80211_send_bar()\n");
2792 for (i = 0; i < nframes; i++) {
2793 if (le16toh(aggstatus[i * 2]) & 0xc)
2796 idx = le16toh(aggstatus[2*i + 1]) & 0xff;
2800 shift = 0x100 - idx + start;
2803 } else if (bit <= -64)
2804 bit = 0x100 - start + idx;
2806 shift = start - idx;
2810 bitmap = bitmap << shift;
2811 bitmap |= 1ULL << bit;
2813 tap = sc->qid2tap[qid];
2814 tid = WME_AC_TO_TID(tap->txa_ac);
2815 wn = (void *)tap->txa_ni;
2816 wn->agg[tid].bitmap = bitmap;
2817 wn->agg[tid].startidx = start;
2818 wn->agg[tid].nframes = nframes;
2820 seqno = le32toh(*(status + nframes)) & 0xfff;
2821 for (lastidx = (seqno & 0xff); ring->read != lastidx;) {
2822 data = &ring->data[ring->read];
2824 KASSERT(data->ni != NULL, ("no node"));
2826 /* Unmap and free mbuf. */
2827 bus_dmamap_sync(ring->data_dmat, data->map,
2828 BUS_DMASYNC_POSTWRITE);
2829 bus_dmamap_unload(ring->data_dmat, data->map);
2830 m = data->m, data->m = NULL;
2831 ni = data->ni, data->ni = NULL;
2834 if (m->m_flags & M_TXCB)
2835 ieee80211_process_callback(ni, m, 1);
2838 ieee80211_free_node(ni);
2841 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT;
2844 sc->sc_tx_timer = 0;
2845 if (ring->queued < IWN_TX_RING_LOMARK) {
2846 sc->qfullmsk &= ~(1 << ring->qid);
2847 if (sc->qfullmsk == 0 &&
2848 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
2849 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2850 iwn_start_locked(ifp);
2856 * Process an INT_FH_RX or INT_SW_RX interrupt.
2859 iwn_notif_intr(struct iwn_softc *sc)
2861 struct iwn_ops *ops = &sc->ops;
2862 struct ifnet *ifp = sc->sc_ifp;
2863 struct ieee80211com *ic = ifp->if_l2com;
2864 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2867 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map,
2868 BUS_DMASYNC_POSTREAD);
2870 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
2871 while (sc->rxq.cur != hw) {
2872 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
2873 struct iwn_rx_desc *desc;
2875 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2876 BUS_DMASYNC_POSTREAD);
2877 desc = mtod(data->m, struct iwn_rx_desc *);
2879 DPRINTF(sc, IWN_DEBUG_RECV,
2880 "%s: qid %x idx %d flags %x type %d(%s) len %d\n",
2881 __func__, desc->qid & 0xf, desc->idx, desc->flags,
2882 desc->type, iwn_intr_str(desc->type),
2883 le16toh(desc->len));
2885 if (!(desc->qid & 0x80)) /* Reply to a command. */
2886 iwn_cmd_done(sc, desc);
2888 switch (desc->type) {
2890 iwn_rx_phy(sc, desc, data);
2893 case IWN_RX_DONE: /* 4965AGN only. */
2894 case IWN_MPDU_RX_DONE:
2895 /* An 802.11 frame has been received. */
2896 iwn_rx_done(sc, desc, data);
2899 case IWN_RX_COMPRESSED_BA:
2900 /* A Compressed BlockAck has been received. */
2901 iwn_rx_compressed_ba(sc, desc, data);
2905 /* An 802.11 frame has been transmitted. */
2906 ops->tx_done(sc, desc, data);
2909 case IWN_RX_STATISTICS:
2910 case IWN_BEACON_STATISTICS:
2911 iwn_rx_statistics(sc, desc, data);
2914 case IWN_BEACON_MISSED:
2916 struct iwn_beacon_missed *miss =
2917 (struct iwn_beacon_missed *)(desc + 1);
2920 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2921 BUS_DMASYNC_POSTREAD);
2922 misses = le32toh(miss->consecutive);
2924 DPRINTF(sc, IWN_DEBUG_STATE,
2925 "%s: beacons missed %d/%d\n", __func__,
2926 misses, le32toh(miss->total));
2928 * If more than 5 consecutive beacons are missed,
2929 * reinitialize the sensitivity state machine.
2931 if (vap->iv_state == IEEE80211_S_RUN &&
2932 (ic->ic_flags & IEEE80211_F_SCAN) == 0) {
2934 (void)iwn_init_sensitivity(sc);
2935 if (misses >= vap->iv_bmissthreshold) {
2937 ieee80211_beacon_miss(ic);
2945 struct iwn_ucode_info *uc =
2946 (struct iwn_ucode_info *)(desc + 1);
2948 /* The microcontroller is ready. */
2949 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2950 BUS_DMASYNC_POSTREAD);
2951 DPRINTF(sc, IWN_DEBUG_RESET,
2952 "microcode alive notification version=%d.%d "
2953 "subtype=%x alive=%x\n", uc->major, uc->minor,
2954 uc->subtype, le32toh(uc->valid));
2956 if (le32toh(uc->valid) != 1) {
2957 device_printf(sc->sc_dev,
2958 "microcontroller initialization failed");
2961 if (uc->subtype == IWN_UCODE_INIT) {
2962 /* Save microcontroller report. */
2963 memcpy(&sc->ucode_info, uc, sizeof (*uc));
2965 /* Save the address of the error log in SRAM. */
2966 sc->errptr = le32toh(uc->errptr);
2969 case IWN_STATE_CHANGED:
2971 uint32_t *status = (uint32_t *)(desc + 1);
2974 * State change allows hardware switch change to be
2975 * noted. However, we handle this in iwn_intr as we
2976 * get both the enable/disble intr.
2978 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2979 BUS_DMASYNC_POSTREAD);
2980 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n",
2984 case IWN_START_SCAN:
2986 struct iwn_start_scan *scan =
2987 (struct iwn_start_scan *)(desc + 1);
2989 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2990 BUS_DMASYNC_POSTREAD);
2991 DPRINTF(sc, IWN_DEBUG_ANY,
2992 "%s: scanning channel %d status %x\n",
2993 __func__, scan->chan, le32toh(scan->status));
2998 struct iwn_stop_scan *scan =
2999 (struct iwn_stop_scan *)(desc + 1);
3001 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3002 BUS_DMASYNC_POSTREAD);
3003 DPRINTF(sc, IWN_DEBUG_STATE,
3004 "scan finished nchan=%d status=%d chan=%d\n",
3005 scan->nchan, scan->status, scan->chan);
3008 ieee80211_scan_next(vap);
3012 case IWN5000_CALIBRATION_RESULT:
3013 iwn5000_rx_calib_results(sc, desc, data);
3016 case IWN5000_CALIBRATION_DONE:
3017 sc->sc_flags |= IWN_FLAG_CALIB_DONE;
3022 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
3025 /* Tell the firmware what we have processed. */
3026 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
3027 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
3031 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up
3032 * from power-down sleep mode.
3035 iwn_wakeup_intr(struct iwn_softc *sc)
3039 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n",
3042 /* Wakeup RX and TX rings. */
3043 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
3044 for (qid = 0; qid < sc->ntxqs; qid++) {
3045 struct iwn_tx_ring *ring = &sc->txq[qid];
3046 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
3051 iwn_rftoggle_intr(struct iwn_softc *sc)
3053 struct ifnet *ifp = sc->sc_ifp;
3054 struct ieee80211com *ic = ifp->if_l2com;
3055 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL);
3057 IWN_LOCK_ASSERT(sc);
3059 device_printf(sc->sc_dev, "RF switch: radio %s\n",
3060 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
3061 if (tmp & IWN_GP_CNTRL_RFKILL)
3062 ieee80211_runtask(ic, &sc->sc_radioon_task);
3064 ieee80211_runtask(ic, &sc->sc_radiooff_task);
3068 * Dump the error log of the firmware when a firmware panic occurs. Although
3069 * we can't debug the firmware because it is neither open source nor free, it
3070 * can help us to identify certain classes of problems.
3073 iwn_fatal_intr(struct iwn_softc *sc)
3075 struct iwn_fw_dump dump;
3078 IWN_LOCK_ASSERT(sc);
3080 /* Force a complete recalibration on next init. */
3081 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
3083 /* Check that the error log address is valid. */
3084 if (sc->errptr < IWN_FW_DATA_BASE ||
3085 sc->errptr + sizeof (dump) >
3086 IWN_FW_DATA_BASE + sc->fw_data_maxsz) {
3087 printf("%s: bad firmware error log address 0x%08x\n", __func__,
3091 if (iwn_nic_lock(sc) != 0) {
3092 printf("%s: could not read firmware error log\n", __func__);
3095 /* Read firmware error log from SRAM. */
3096 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
3097 sizeof (dump) / sizeof (uint32_t));
3100 if (dump.valid == 0) {
3101 printf("%s: firmware error log is empty\n", __func__);
3104 printf("firmware error log:\n");
3105 printf(" error type = \"%s\" (0x%08X)\n",
3106 (dump.id < nitems(iwn_fw_errmsg)) ?
3107 iwn_fw_errmsg[dump.id] : "UNKNOWN",
3109 printf(" program counter = 0x%08X\n", dump.pc);
3110 printf(" source line = 0x%08X\n", dump.src_line);
3111 printf(" error data = 0x%08X%08X\n",
3112 dump.error_data[0], dump.error_data[1]);
3113 printf(" branch link = 0x%08X%08X\n",
3114 dump.branch_link[0], dump.branch_link[1]);
3115 printf(" interrupt link = 0x%08X%08X\n",
3116 dump.interrupt_link[0], dump.interrupt_link[1]);
3117 printf(" time = %u\n", dump.time[0]);
3119 /* Dump driver status (TX and RX rings) while we're here. */
3120 printf("driver status:\n");
3121 for (i = 0; i < sc->ntxqs; i++) {
3122 struct iwn_tx_ring *ring = &sc->txq[i];
3123 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
3124 i, ring->qid, ring->cur, ring->queued);
3126 printf(" rx ring: cur=%d\n", sc->rxq.cur);
3132 struct iwn_softc *sc = arg;
3133 struct ifnet *ifp = sc->sc_ifp;
3134 uint32_t r1, r2, tmp;
3138 /* Disable interrupts. */
3139 IWN_WRITE(sc, IWN_INT_MASK, 0);
3141 /* Read interrupts from ICT (fast) or from registers (slow). */
3142 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
3144 while (sc->ict[sc->ict_cur] != 0) {
3145 tmp |= sc->ict[sc->ict_cur];
3146 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
3147 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
3150 if (tmp == 0xffffffff) /* Shouldn't happen. */
3152 else if (tmp & 0xc0000) /* Workaround a HW bug. */
3154 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
3155 r2 = 0; /* Unused. */
3157 r1 = IWN_READ(sc, IWN_INT);
3158 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
3159 return; /* Hardware gone! */
3160 r2 = IWN_READ(sc, IWN_FH_INT);
3163 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2);
3165 if (r1 == 0 && r2 == 0)
3166 goto done; /* Interrupt not for us. */
3168 /* Acknowledge interrupts. */
3169 IWN_WRITE(sc, IWN_INT, r1);
3170 if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
3171 IWN_WRITE(sc, IWN_FH_INT, r2);
3173 if (r1 & IWN_INT_RF_TOGGLED) {
3174 iwn_rftoggle_intr(sc);
3177 if (r1 & IWN_INT_CT_REACHED) {
3178 device_printf(sc->sc_dev, "%s: critical temperature reached!\n",
3181 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
3182 device_printf(sc->sc_dev, "%s: fatal firmware error\n",
3184 /* Dump firmware error log and stop. */
3186 ifp->if_flags &= ~IFF_UP;
3187 iwn_stop_locked(sc);
3190 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) ||
3191 (r2 & IWN_FH_INT_RX)) {
3192 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
3193 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX))
3194 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX);
3195 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
3196 IWN_INT_PERIODIC_DIS);
3198 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) {
3199 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
3200 IWN_INT_PERIODIC_ENA);
3206 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) {
3207 if (sc->sc_flags & IWN_FLAG_USE_ICT)
3208 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX);
3209 wakeup(sc); /* FH DMA transfer completed. */
3212 if (r1 & IWN_INT_ALIVE)
3213 wakeup(sc); /* Firmware is alive. */
3215 if (r1 & IWN_INT_WAKEUP)
3216 iwn_wakeup_intr(sc);
3219 /* Re-enable interrupts. */
3220 if (ifp->if_flags & IFF_UP)
3221 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
3227 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and
3228 * 5000 adapters use a slightly different format).
3231 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
3234 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
3236 *w = htole16(len + 8);
3237 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3238 BUS_DMASYNC_PREWRITE);
3239 if (idx < IWN_SCHED_WINSZ) {
3240 *(w + IWN_TX_RING_COUNT) = *w;
3241 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3242 BUS_DMASYNC_PREWRITE);
3247 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
3250 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
3252 *w = htole16(id << 12 | (len + 8));
3253 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3254 BUS_DMASYNC_PREWRITE);
3255 if (idx < IWN_SCHED_WINSZ) {
3256 *(w + IWN_TX_RING_COUNT) = *w;
3257 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3258 BUS_DMASYNC_PREWRITE);
3264 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx)
3266 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
3268 *w = (*w & htole16(0xf000)) | htole16(1);
3269 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3270 BUS_DMASYNC_PREWRITE);
3271 if (idx < IWN_SCHED_WINSZ) {
3272 *(w + IWN_TX_RING_COUNT) = *w;
3273 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3274 BUS_DMASYNC_PREWRITE);
3280 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
3282 struct iwn_ops *ops = &sc->ops;
3283 const struct ieee80211_txparam *tp;
3284 struct ieee80211vap *vap = ni->ni_vap;
3285 struct ieee80211com *ic = ni->ni_ic;
3286 struct iwn_node *wn = (void *)ni;
3287 struct iwn_tx_ring *ring;
3288 struct iwn_tx_desc *desc;
3289 struct iwn_tx_data *data;
3290 struct iwn_tx_cmd *cmd;
3291 struct iwn_cmd_data *tx;
3292 struct ieee80211_frame *wh;
3293 struct ieee80211_key *k = NULL;
3298 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
3299 uint8_t tid, ridx, txant, type;
3300 int ac, i, totlen, error, pad, nsegs = 0, rate;
3302 IWN_LOCK_ASSERT(sc);
3304 wh = mtod(m, struct ieee80211_frame *);
3305 hdrlen = ieee80211_anyhdrsize(wh);
3306 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3308 /* Select EDCA Access Category and TX ring for this frame. */
3309 if (IEEE80211_QOS_HAS_SEQ(wh)) {
3310 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
3311 tid = qos & IEEE80211_QOS_TID;
3316 ac = M_WME_GETAC(m);
3318 if (IEEE80211_QOS_HAS_SEQ(wh) &&
3319 IEEE80211_AMPDU_RUNNING(&ni->ni_tx_ampdu[ac])) {
3320 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac];
3322 ring = &sc->txq[*(int *)tap->txa_private];
3323 *(uint16_t *)wh->i_seq =
3324 htole16(ni->ni_txseqs[tid] << IEEE80211_SEQ_SEQ_SHIFT);
3325 ni->ni_txseqs[tid]++;
3327 ring = &sc->txq[ac];
3329 desc = &ring->desc[ring->cur];
3330 data = &ring->data[ring->cur];
3332 /* Choose a TX rate index. */
3333 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
3334 if (type == IEEE80211_FC0_TYPE_MGT)
3335 rate = tp->mgmtrate;
3336 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
3337 rate = tp->mcastrate;
3338 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
3339 rate = tp->ucastrate;
3341 /* XXX pass pktlen */
3342 (void) ieee80211_ratectl_rate(ni, NULL, 0);
3343 rate = ni->ni_txrate;
3345 ridx = ic->ic_rt->rateCodeToIndex[rate];
3347 /* Encrypt the frame if need be. */
3348 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
3349 /* Retrieve key for TX. */
3350 k = ieee80211_crypto_encap(ni, m);
3355 /* 802.11 header may have moved. */
3356 wh = mtod(m, struct ieee80211_frame *);
3358 totlen = m->m_pkthdr.len;
3360 if (ieee80211_radiotap_active_vap(vap)) {
3361 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
3364 tap->wt_rate = rate;
3366 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3368 ieee80211_radiotap_tx(vap, m);
3371 /* Prepare TX firmware command. */
3372 cmd = &ring->cmd[ring->cur];
3373 cmd->code = IWN_CMD_TX_DATA;
3375 cmd->qid = ring->qid;
3376 cmd->idx = ring->cur;
3378 tx = (struct iwn_cmd_data *)cmd->data;
3379 /* NB: No need to clear tx, all fields are reinitialized here. */
3380 tx->scratch = 0; /* clear "scratch" area */
3383 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3384 /* Unicast frame, check if an ACK is expected. */
3385 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
3386 IEEE80211_QOS_ACKPOLICY_NOACK)
3387 flags |= IWN_TX_NEED_ACK;
3390 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
3391 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR))
3392 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */
3394 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
3395 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */
3397 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
3398 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3399 /* NB: Group frames are sent using CCK in 802.11b/g. */
3400 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) {
3401 flags |= IWN_TX_NEED_RTS;
3402 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3403 ridx >= IWN_RIDX_OFDM6) {
3404 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3405 flags |= IWN_TX_NEED_CTS;
3406 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3407 flags |= IWN_TX_NEED_RTS;
3409 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) {
3410 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3411 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3412 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS);
3413 flags |= IWN_TX_NEED_PROTECTION;
3415 flags |= IWN_TX_FULL_TXOP;
3419 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
3420 type != IEEE80211_FC0_TYPE_DATA)
3421 tx->id = sc->broadcast_id;
3425 if (type == IEEE80211_FC0_TYPE_MGT) {
3426 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3428 /* Tell HW to set timestamp in probe responses. */
3429 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3430 flags |= IWN_TX_INSERT_TSTAMP;
3431 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3432 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3433 tx->timeout = htole16(3);
3435 tx->timeout = htole16(2);
3437 tx->timeout = htole16(0);
3440 /* First segment length must be a multiple of 4. */
3441 flags |= IWN_TX_NEED_PADDING;
3442 pad = 4 - (hdrlen & 3);
3446 tx->len = htole16(totlen);
3448 tx->rts_ntries = 60;
3449 tx->data_ntries = 15;
3450 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3451 tx->rate = wn->ridx[rate];
3452 if (tx->id == sc->broadcast_id) {
3453 /* Group or management frame. */
3455 /* XXX Alternate between antenna A and B? */
3456 txant = IWN_LSB(sc->txchainmask);
3457 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
3459 tx->linkq = ni->ni_rates.rs_nrates - ridx - 1;
3460 flags |= IWN_TX_LINKQ; /* enable MRR */
3462 /* Set physical address of "scratch area". */
3463 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
3464 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
3466 /* Copy 802.11 header in TX command. */
3467 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3469 /* Trim 802.11 header. */
3472 tx->flags = htole32(flags);
3474 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
3475 &nsegs, BUS_DMA_NOWAIT);
3477 if (error != EFBIG) {
3478 device_printf(sc->sc_dev,
3479 "%s: can't map mbuf (error %d)\n", __func__, error);
3483 /* Too many DMA segments, linearize mbuf. */
3484 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER);
3486 device_printf(sc->sc_dev,
3487 "%s: could not defrag mbuf\n", __func__);
3493 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
3494 segs, &nsegs, BUS_DMA_NOWAIT);
3496 device_printf(sc->sc_dev,
3497 "%s: can't map mbuf (error %d)\n", __func__, error);
3506 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3507 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3509 /* Fill TX descriptor. */
3512 desc->nsegs += nsegs;
3513 /* First DMA segment is used by the TX command. */
3514 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3515 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3516 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3517 /* Other DMA segments are for data payload. */
3519 for (i = 1; i <= nsegs; i++) {
3520 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
3521 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
3526 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3527 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3528 BUS_DMASYNC_PREWRITE);
3529 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3530 BUS_DMASYNC_PREWRITE);
3532 /* Update TX scheduler. */
3533 if (ring->qid >= sc->firstaggqueue)
3534 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3537 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3538 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3540 /* Mark TX ring as full if we reach a certain threshold. */
3541 if (++ring->queued > IWN_TX_RING_HIMARK)
3542 sc->qfullmsk |= 1 << ring->qid;
3548 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m,
3549 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3551 struct iwn_ops *ops = &sc->ops;
3552 struct ifnet *ifp = sc->sc_ifp;
3553 struct ieee80211vap *vap = ni->ni_vap;
3554 struct ieee80211com *ic = ifp->if_l2com;
3555 struct iwn_tx_cmd *cmd;
3556 struct iwn_cmd_data *tx;
3557 struct ieee80211_frame *wh;
3558 struct iwn_tx_ring *ring;
3559 struct iwn_tx_desc *desc;
3560 struct iwn_tx_data *data;
3562 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
3565 int ac, totlen, error, pad, nsegs = 0, i, rate;
3566 uint8_t ridx, type, txant;
3568 IWN_LOCK_ASSERT(sc);
3570 wh = mtod(m, struct ieee80211_frame *);
3571 hdrlen = ieee80211_anyhdrsize(wh);
3572 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3574 ac = params->ibp_pri & 3;
3576 ring = &sc->txq[ac];
3577 desc = &ring->desc[ring->cur];
3578 data = &ring->data[ring->cur];
3580 /* Choose a TX rate index. */
3581 rate = params->ibp_rate0;
3582 ridx = ic->ic_rt->rateCodeToIndex[rate];
3583 if (ridx == (uint8_t)-1) {
3584 /* XXX fall back to mcast/mgmt rate? */
3589 totlen = m->m_pkthdr.len;
3591 /* Prepare TX firmware command. */
3592 cmd = &ring->cmd[ring->cur];
3593 cmd->code = IWN_CMD_TX_DATA;
3595 cmd->qid = ring->qid;
3596 cmd->idx = ring->cur;
3598 tx = (struct iwn_cmd_data *)cmd->data;
3599 /* NB: No need to clear tx, all fields are reinitialized here. */
3600 tx->scratch = 0; /* clear "scratch" area */
3603 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
3604 flags |= IWN_TX_NEED_ACK;
3605 if (params->ibp_flags & IEEE80211_BPF_RTS) {
3606 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3607 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3608 flags &= ~IWN_TX_NEED_RTS;
3609 flags |= IWN_TX_NEED_PROTECTION;
3611 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP;
3613 if (params->ibp_flags & IEEE80211_BPF_CTS) {
3614 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3615 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3616 flags &= ~IWN_TX_NEED_CTS;
3617 flags |= IWN_TX_NEED_PROTECTION;
3619 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP;
3621 if (type == IEEE80211_FC0_TYPE_MGT) {
3622 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3624 /* Tell HW to set timestamp in probe responses. */
3625 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3626 flags |= IWN_TX_INSERT_TSTAMP;
3628 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3629 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3630 tx->timeout = htole16(3);
3632 tx->timeout = htole16(2);
3634 tx->timeout = htole16(0);
3637 /* First segment length must be a multiple of 4. */
3638 flags |= IWN_TX_NEED_PADDING;
3639 pad = 4 - (hdrlen & 3);
3643 if (ieee80211_radiotap_active_vap(vap)) {
3644 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
3647 tap->wt_rate = rate;
3649 ieee80211_radiotap_tx(vap, m);
3652 tx->len = htole16(totlen);
3654 tx->id = sc->broadcast_id;
3655 tx->rts_ntries = params->ibp_try1;
3656 tx->data_ntries = params->ibp_try0;
3657 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3658 tx->rate = htole32(rate2plcp(rate));
3659 if (ridx < IWN_RIDX_OFDM6 &&
3660 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
3661 tx->rate |= htole32(IWN_RFLAG_CCK);
3662 /* Group or management frame. */
3664 txant = IWN_LSB(sc->txchainmask);
3665 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
3666 /* Set physical address of "scratch area". */
3667 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
3668 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
3670 /* Copy 802.11 header in TX command. */
3671 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3673 /* Trim 802.11 header. */
3676 tx->flags = htole32(flags);
3678 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
3679 &nsegs, BUS_DMA_NOWAIT);
3681 if (error != EFBIG) {
3682 device_printf(sc->sc_dev,
3683 "%s: can't map mbuf (error %d)\n", __func__, error);
3687 /* Too many DMA segments, linearize mbuf. */
3688 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER);
3690 device_printf(sc->sc_dev,
3691 "%s: could not defrag mbuf\n", __func__);
3697 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
3698 segs, &nsegs, BUS_DMA_NOWAIT);
3700 device_printf(sc->sc_dev,
3701 "%s: can't map mbuf (error %d)\n", __func__, error);
3710 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3711 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3713 /* Fill TX descriptor. */
3716 desc->nsegs += nsegs;
3717 /* First DMA segment is used by the TX command. */
3718 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3719 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3720 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3721 /* Other DMA segments are for data payload. */
3723 for (i = 1; i <= nsegs; i++) {
3724 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
3725 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
3730 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3731 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3732 BUS_DMASYNC_PREWRITE);
3733 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3734 BUS_DMASYNC_PREWRITE);
3736 /* Update TX scheduler. */
3737 if (ring->qid >= sc->firstaggqueue)
3738 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3741 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3742 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3744 /* Mark TX ring as full if we reach a certain threshold. */
3745 if (++ring->queued > IWN_TX_RING_HIMARK)
3746 sc->qfullmsk |= 1 << ring->qid;
3752 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
3753 const struct ieee80211_bpf_params *params)
3755 struct ieee80211com *ic = ni->ni_ic;
3756 struct ifnet *ifp = ic->ic_ifp;
3757 struct iwn_softc *sc = ifp->if_softc;
3760 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3761 ieee80211_free_node(ni);
3767 if (params == NULL) {
3769 * Legacy path; interpret frame contents to decide
3770 * precisely how to send the frame.
3772 error = iwn_tx_data(sc, m, ni);
3775 * Caller supplied explicit parameters to use in
3776 * sending the frame.
3778 error = iwn_tx_data_raw(sc, m, ni, params);
3781 /* NB: m is reclaimed on tx failure */
3782 ieee80211_free_node(ni);
3785 sc->sc_tx_timer = 5;
3792 iwn_start(struct ifnet *ifp)
3794 struct iwn_softc *sc = ifp->if_softc;
3797 iwn_start_locked(ifp);
3802 iwn_start_locked(struct ifnet *ifp)
3804 struct iwn_softc *sc = ifp->if_softc;
3805 struct ieee80211_node *ni;
3808 IWN_LOCK_ASSERT(sc);
3810 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
3811 (ifp->if_drv_flags & IFF_DRV_OACTIVE))
3815 if (sc->qfullmsk != 0) {
3816 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3819 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
3822 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3823 if (iwn_tx_data(sc, m, ni) != 0) {
3824 ieee80211_free_node(ni);
3828 sc->sc_tx_timer = 5;
3833 iwn_watchdog(void *arg)
3835 struct iwn_softc *sc = arg;
3836 struct ifnet *ifp = sc->sc_ifp;
3837 struct ieee80211com *ic = ifp->if_l2com;
3839 IWN_LOCK_ASSERT(sc);
3841 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running"));
3843 if (sc->sc_tx_timer > 0) {
3844 if (--sc->sc_tx_timer == 0) {
3845 if_printf(ifp, "device timeout\n");
3846 ieee80211_runtask(ic, &sc->sc_reinit_task);
3850 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
3854 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
3856 struct iwn_softc *sc = ifp->if_softc;
3857 struct ieee80211com *ic = ifp->if_l2com;
3858 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3859 struct ifreq *ifr = (struct ifreq *) data;
3860 int error = 0, startall = 0, stop = 0;
3864 error = ether_ioctl(ifp, cmd, data);
3868 if (ifp->if_flags & IFF_UP) {
3869 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3870 iwn_init_locked(sc);
3871 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)
3877 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3878 iwn_stop_locked(sc);
3882 ieee80211_start_all(ic);
3883 else if (vap != NULL && stop)
3884 ieee80211_stop(vap);
3887 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
3897 * Send a command to the firmware.
3900 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
3902 struct iwn_tx_ring *ring = &sc->txq[4];
3903 struct iwn_tx_desc *desc;
3904 struct iwn_tx_data *data;
3905 struct iwn_tx_cmd *cmd;
3911 IWN_LOCK_ASSERT(sc);
3913 desc = &ring->desc[ring->cur];
3914 data = &ring->data[ring->cur];
3917 if (size > sizeof cmd->data) {
3918 /* Command is too large to fit in a descriptor. */
3919 if (totlen > MCLBYTES)
3921 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE);
3924 cmd = mtod(m, struct iwn_tx_cmd *);
3925 error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
3926 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
3933 cmd = &ring->cmd[ring->cur];
3934 paddr = data->cmd_paddr;
3939 cmd->qid = ring->qid;
3940 cmd->idx = ring->cur;
3941 memcpy(cmd->data, buf, size);
3944 desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
3945 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4);
3947 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n",
3948 __func__, iwn_intr_str(cmd->code), cmd->code,
3949 cmd->flags, cmd->qid, cmd->idx);
3951 if (size > sizeof cmd->data) {
3952 bus_dmamap_sync(ring->data_dmat, data->map,
3953 BUS_DMASYNC_PREWRITE);
3955 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3956 BUS_DMASYNC_PREWRITE);
3958 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3959 BUS_DMASYNC_PREWRITE);
3961 /* Kick command ring. */
3962 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3963 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3965 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz);
3969 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3971 struct iwn4965_node_info hnode;
3975 * We use the node structure for 5000 Series internally (it is
3976 * a superset of the one for 4965AGN). We thus copy the common
3977 * fields before sending the command.
3979 src = (caddr_t)node;
3980 dst = (caddr_t)&hnode;
3981 memcpy(dst, src, 48);
3982 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */
3983 memcpy(dst + 48, src + 72, 20);
3984 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async);
3988 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3990 /* Direct mapping. */
3991 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async);
3995 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni)
3997 #define RV(v) ((v) & IEEE80211_RATE_VAL)
3998 struct iwn_node *wn = (void *)ni;
3999 struct ieee80211_rateset *rs = &ni->ni_rates;
4000 struct iwn_cmd_link_quality linkq;
4002 int i, rate, txrate;
4004 /* Use the first valid TX antenna. */
4005 txant = IWN_LSB(sc->txchainmask);
4007 memset(&linkq, 0, sizeof linkq);
4009 linkq.antmsk_1stream = txant;
4010 linkq.antmsk_2stream = IWN_ANT_AB;
4011 linkq.ampdu_max = 64;
4012 linkq.ampdu_threshold = 3;
4013 linkq.ampdu_limit = htole16(4000); /* 4ms */
4015 /* Start at highest available bit-rate. */
4016 if (IEEE80211_IS_CHAN_HT(ni->ni_chan))
4017 txrate = ni->ni_htrates.rs_nrates - 1;
4019 txrate = rs->rs_nrates - 1;
4020 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) {
4021 if (IEEE80211_IS_CHAN_HT(ni->ni_chan))
4022 rate = IEEE80211_RATE_MCS | txrate;
4024 rate = RV(rs->rs_rates[txrate]);
4025 linkq.retry[i] = wn->ridx[rate];
4027 if ((le32toh(wn->ridx[rate]) & IWN_RFLAG_MCS) &&
4028 RV(le32toh(wn->ridx[rate])) > 7)
4031 /* Next retry at immediate lower bit-rate. */
4035 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1);
4040 * Broadcast node is used to send group-addressed and management frames.
4043 iwn_add_broadcast_node(struct iwn_softc *sc, int async)
4045 struct iwn_ops *ops = &sc->ops;
4046 struct ifnet *ifp = sc->sc_ifp;
4047 struct ieee80211com *ic = ifp->if_l2com;
4048 struct iwn_node_info node;
4049 struct iwn_cmd_link_quality linkq;
4053 memset(&node, 0, sizeof node);
4054 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr);
4055 node.id = sc->broadcast_id;
4056 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__);
4057 if ((error = ops->add_node(sc, &node, async)) != 0)
4060 /* Use the first valid TX antenna. */
4061 txant = IWN_LSB(sc->txchainmask);
4063 memset(&linkq, 0, sizeof linkq);
4064 linkq.id = sc->broadcast_id;
4065 linkq.antmsk_1stream = txant;
4066 linkq.antmsk_2stream = IWN_ANT_AB;
4067 linkq.ampdu_max = 64;
4068 linkq.ampdu_threshold = 3;
4069 linkq.ampdu_limit = htole16(4000); /* 4ms */
4071 /* Use lowest mandatory bit-rate. */
4072 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
4073 linkq.retry[0] = htole32(0xd);
4075 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK);
4076 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant));
4077 /* Use same bit-rate for all TX retries. */
4078 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) {
4079 linkq.retry[i] = linkq.retry[0];
4081 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async);
4085 iwn_updateedca(struct ieee80211com *ic)
4087 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
4088 struct iwn_softc *sc = ic->ic_ifp->if_softc;
4089 struct iwn_edca_params cmd;
4092 memset(&cmd, 0, sizeof cmd);
4093 cmd.flags = htole32(IWN_EDCA_UPDATE);
4094 for (aci = 0; aci < WME_NUM_AC; aci++) {
4095 const struct wmeParams *ac =
4096 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci];
4097 cmd.ac[aci].aifsn = ac->wmep_aifsn;
4098 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin));
4099 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax));
4100 cmd.ac[aci].txoplimit =
4101 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit));
4103 IEEE80211_UNLOCK(ic);
4105 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1);
4113 iwn_update_mcast(struct ifnet *ifp)
4119 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on)
4121 struct iwn_cmd_led led;
4123 /* Clear microcode LED ownership. */
4124 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL);
4127 led.unit = htole32(10000); /* on/off in unit of 100ms */
4130 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
4134 * Set the critical temperature at which the firmware will stop the radio
4138 iwn_set_critical_temp(struct iwn_softc *sc)
4140 struct iwn_critical_temp crit;
4143 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF);
4145 if (sc->hw_type == IWN_HW_REV_TYPE_5150)
4146 temp = (IWN_CTOK(110) - sc->temp_off) * -5;
4147 else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
4148 temp = IWN_CTOK(110);
4151 memset(&crit, 0, sizeof crit);
4152 crit.tempR = htole32(temp);
4153 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp);
4154 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0);
4158 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni)
4160 struct iwn_cmd_timing cmd;
4163 memset(&cmd, 0, sizeof cmd);
4164 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
4165 cmd.bintval = htole16(ni->ni_intval);
4166 cmd.lintval = htole16(10);
4168 /* Compute remaining time until next beacon. */
4169 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU;
4170 mod = le64toh(cmd.tstamp) % val;
4171 cmd.binitval = htole32((uint32_t)(val - mod));
4173 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n",
4174 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
4176 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
4180 iwn4965_power_calibration(struct iwn_softc *sc, int temp)
4182 struct ifnet *ifp = sc->sc_ifp;
4183 struct ieee80211com *ic = ifp->if_l2com;
4185 /* Adjust TX power if need be (delta >= 3 degC). */
4186 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
4187 __func__, sc->temp, temp);
4188 if (abs(temp - sc->temp) >= 3) {
4189 /* Record temperature of last calibration. */
4191 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1);
4196 * Set TX power for current channel (each rate has its own power settings).
4197 * This function takes into account the regulatory information from EEPROM,
4198 * the current temperature and the current voltage.
4201 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
4204 /* Fixed-point arithmetic division using a n-bit fractional part. */
4205 #define fdivround(a, b, n) \
4206 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n))
4207 /* Linear interpolation. */
4208 #define interpolate(x, x1, y1, x2, y2, n) \
4209 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
4211 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 };
4212 struct iwn_ucode_info *uc = &sc->ucode_info;
4213 struct iwn4965_cmd_txpower cmd;
4214 struct iwn4965_eeprom_chan_samples *chans;
4215 const uint8_t *rf_gain, *dsp_gain;
4216 int32_t vdiff, tdiff;
4217 int i, c, grp, maxpwr;
4220 /* Retrieve current channel from last RXON. */
4221 chan = sc->rxon.chan;
4222 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n",
4225 memset(&cmd, 0, sizeof cmd);
4226 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1;
4229 if (IEEE80211_IS_CHAN_5GHZ(ch)) {
4230 maxpwr = sc->maxpwr5GHz;
4231 rf_gain = iwn4965_rf_gain_5ghz;
4232 dsp_gain = iwn4965_dsp_gain_5ghz;
4234 maxpwr = sc->maxpwr2GHz;
4235 rf_gain = iwn4965_rf_gain_2ghz;
4236 dsp_gain = iwn4965_dsp_gain_2ghz;
4239 /* Compute voltage compensation. */
4240 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
4245 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4246 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n",
4247 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage);
4249 /* Get channel attenuation group. */
4250 if (chan <= 20) /* 1-20 */
4252 else if (chan <= 43) /* 34-43 */
4254 else if (chan <= 70) /* 44-70 */
4256 else if (chan <= 124) /* 71-124 */
4260 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4261 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp);
4263 /* Get channel sub-band. */
4264 for (i = 0; i < IWN_NBANDS; i++)
4265 if (sc->bands[i].lo != 0 &&
4266 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
4268 if (i == IWN_NBANDS) /* Can't happen in real-life. */
4270 chans = sc->bands[i].chans;
4271 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4272 "%s: chan %d sub-band=%d\n", __func__, chan, i);
4274 for (c = 0; c < 2; c++) {
4275 uint8_t power, gain, temp;
4276 int maxchpwr, pwr, ridx, idx;
4278 power = interpolate(chan,
4279 chans[0].num, chans[0].samples[c][1].power,
4280 chans[1].num, chans[1].samples[c][1].power, 1);
4281 gain = interpolate(chan,
4282 chans[0].num, chans[0].samples[c][1].gain,
4283 chans[1].num, chans[1].samples[c][1].gain, 1);
4284 temp = interpolate(chan,
4285 chans[0].num, chans[0].samples[c][1].temp,
4286 chans[1].num, chans[1].samples[c][1].temp, 1);
4287 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4288 "%s: Tx chain %d: power=%d gain=%d temp=%d\n",
4289 __func__, c, power, gain, temp);
4291 /* Compute temperature compensation. */
4292 tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
4293 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4294 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n",
4295 __func__, tdiff, sc->temp, temp);
4297 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) {
4298 /* Convert dBm to half-dBm. */
4299 maxchpwr = sc->maxpwr[chan] * 2;
4301 maxchpwr -= 6; /* MIMO 2T: -3dB */
4305 /* Adjust TX power based on rate. */
4306 if ((ridx % 8) == 5)
4307 pwr -= 15; /* OFDM48: -7.5dB */
4308 else if ((ridx % 8) == 6)
4309 pwr -= 17; /* OFDM54: -8.5dB */
4310 else if ((ridx % 8) == 7)
4311 pwr -= 20; /* OFDM60: -10dB */
4313 pwr -= 10; /* Others: -5dB */
4315 /* Do not exceed channel max TX power. */
4319 idx = gain - (pwr - power) - tdiff - vdiff;
4320 if ((ridx / 8) & 1) /* MIMO */
4321 idx += (int32_t)le32toh(uc->atten[grp][c]);
4324 idx += 9; /* 5GHz */
4325 if (ridx == IWN_RIDX_MAX)
4328 /* Make sure idx stays in a valid range. */
4331 else if (idx > IWN4965_MAX_PWR_INDEX)
4332 idx = IWN4965_MAX_PWR_INDEX;
4334 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4335 "%s: Tx chain %d, rate idx %d: power=%d\n",
4336 __func__, c, ridx, idx);
4337 cmd.power[ridx].rf_gain[c] = rf_gain[idx];
4338 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
4342 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4343 "%s: set tx power for chan %d\n", __func__, chan);
4344 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
4351 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
4354 struct iwn5000_cmd_txpower cmd;
4357 * TX power calibration is handled automatically by the firmware
4360 memset(&cmd, 0, sizeof cmd);
4361 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */
4362 cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
4363 cmd.srv_limit = IWN5000_TXPOWER_AUTO;
4364 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__);
4365 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async);
4369 * Retrieve the maximum RSSI (in dBm) among receivers.
4372 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
4374 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;
4378 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
4379 agc = (le16toh(phy->agc) >> 7) & 0x7f;
4382 if (mask & IWN_ANT_A)
4383 rssi = MAX(rssi, phy->rssi[0]);
4384 if (mask & IWN_ANT_B)
4385 rssi = MAX(rssi, phy->rssi[2]);
4386 if (mask & IWN_ANT_C)
4387 rssi = MAX(rssi, phy->rssi[4]);
4389 DPRINTF(sc, IWN_DEBUG_RECV,
4390 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc,
4391 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4],
4392 rssi - agc - IWN_RSSI_TO_DBM);
4393 return rssi - agc - IWN_RSSI_TO_DBM;
4397 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
4399 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;
4403 agc = (le32toh(phy->agc) >> 9) & 0x7f;
4405 rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
4406 le16toh(phy->rssi[1]) & 0xff);
4407 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
4409 DPRINTF(sc, IWN_DEBUG_RECV,
4410 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc,
4411 phy->rssi[0], phy->rssi[1], phy->rssi[2],
4412 rssi - agc - IWN_RSSI_TO_DBM);
4413 return rssi - agc - IWN_RSSI_TO_DBM;
4417 * Retrieve the average noise (in dBm) among receivers.
4420 iwn_get_noise(const struct iwn_rx_general_stats *stats)
4422 int i, total, nbant, noise;
4425 for (i = 0; i < 3; i++) {
4426 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
4431 /* There should be at least one antenna but check anyway. */
4432 return (nbant == 0) ? -127 : (total / nbant) - 107;
4436 * Compute temperature (in degC) from last received statistics.
4439 iwn4965_get_temperature(struct iwn_softc *sc)
4441 struct iwn_ucode_info *uc = &sc->ucode_info;
4442 int32_t r1, r2, r3, r4, temp;
4444 r1 = le32toh(uc->temp[0].chan20MHz);
4445 r2 = le32toh(uc->temp[1].chan20MHz);
4446 r3 = le32toh(uc->temp[2].chan20MHz);
4447 r4 = le32toh(sc->rawtemp);
4449 if (r1 == r3) /* Prevents division by 0 (should not happen). */
4452 /* Sign-extend 23-bit R4 value to 32-bit. */
4453 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000;
4454 /* Compute temperature in Kelvin. */
4455 temp = (259 * (r4 - r2)) / (r3 - r1);
4456 temp = (temp * 97) / 100 + 8;
4458 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp,
4460 return IWN_KTOC(temp);
4464 iwn5000_get_temperature(struct iwn_softc *sc)
4469 * Temperature is not used by the driver for 5000 Series because
4470 * TX power calibration is handled by firmware.
4472 temp = le32toh(sc->rawtemp);
4473 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
4474 temp = (temp / -5) + sc->temp_off;
4475 temp = IWN_KTOC(temp);
4481 * Initialize sensitivity calibration state machine.
4484 iwn_init_sensitivity(struct iwn_softc *sc)
4486 struct iwn_ops *ops = &sc->ops;
4487 struct iwn_calib_state *calib = &sc->calib;
4491 /* Reset calibration state machine. */
4492 memset(calib, 0, sizeof (*calib));
4493 calib->state = IWN_CALIB_STATE_INIT;
4494 calib->cck_state = IWN_CCK_STATE_HIFA;
4495 /* Set initial correlation values. */
4496 calib->ofdm_x1 = sc->limits->min_ofdm_x1;
4497 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;
4498 calib->ofdm_x4 = sc->limits->min_ofdm_x4;
4499 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;
4500 calib->cck_x4 = 125;
4501 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4;
4502 calib->energy_cck = sc->limits->energy_cck;
4504 /* Write initial sensitivity. */
4505 if ((error = iwn_send_sensitivity(sc)) != 0)
4508 /* Write initial gains. */
4509 if ((error = ops->init_gains(sc)) != 0)
4512 /* Request statistics at each beacon interval. */
4514 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n",
4516 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1);
4520 * Collect noise and RSSI statistics for the first 20 beacons received
4521 * after association and use them to determine connected antennas and
4522 * to set differential gains.
4525 iwn_collect_noise(struct iwn_softc *sc,
4526 const struct iwn_rx_general_stats *stats)
4528 struct iwn_ops *ops = &sc->ops;
4529 struct iwn_calib_state *calib = &sc->calib;
4533 /* Accumulate RSSI and noise for all 3 antennas. */
4534 for (i = 0; i < 3; i++) {
4535 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff;
4536 calib->noise[i] += le32toh(stats->noise[i]) & 0xff;
4538 /* NB: We update differential gains only once after 20 beacons. */
4539 if (++calib->nbeacons < 20)
4542 /* Determine highest average RSSI. */
4543 val = MAX(calib->rssi[0], calib->rssi[1]);
4544 val = MAX(calib->rssi[2], val);
4546 /* Determine which antennas are connected. */
4547 sc->chainmask = sc->rxchainmask;
4548 for (i = 0; i < 3; i++)
4549 if (val - calib->rssi[i] > 15 * 20)
4550 sc->chainmask &= ~(1 << i);
4551 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4552 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n",
4553 __func__, sc->rxchainmask, sc->chainmask);
4555 /* If none of the TX antennas are connected, keep at least one. */
4556 if ((sc->chainmask & sc->txchainmask) == 0)
4557 sc->chainmask |= IWN_LSB(sc->txchainmask);
4559 (void)ops->set_gains(sc);
4560 calib->state = IWN_CALIB_STATE_RUN;
4563 /* XXX Disable RX chains with no antennas connected. */
4564 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));
4565 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
4570 /* Enable power-saving mode if requested by user. */
4571 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON)
4572 (void)iwn_set_pslevel(sc, 0, 3, 1);
4577 iwn4965_init_gains(struct iwn_softc *sc)
4579 struct iwn_phy_calib_gain cmd;
4581 memset(&cmd, 0, sizeof cmd);
4582 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4583 /* Differential gains initially set to 0 for all 3 antennas. */
4584 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4585 "%s: setting initial differential gains\n", __func__);
4586 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4590 iwn5000_init_gains(struct iwn_softc *sc)
4592 struct iwn_phy_calib cmd;
4594 memset(&cmd, 0, sizeof cmd);
4595 cmd.code = sc->reset_noise_gain;
4598 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4599 "%s: setting initial differential gains\n", __func__);
4600 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4604 iwn4965_set_gains(struct iwn_softc *sc)
4606 struct iwn_calib_state *calib = &sc->calib;
4607 struct iwn_phy_calib_gain cmd;
4608 int i, delta, noise;
4610 /* Get minimal noise among connected antennas. */
4611 noise = INT_MAX; /* NB: There's at least one antenna. */
4612 for (i = 0; i < 3; i++)
4613 if (sc->chainmask & (1 << i))
4614 noise = MIN(calib->noise[i], noise);
4616 memset(&cmd, 0, sizeof cmd);
4617 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4618 /* Set differential gains for connected antennas. */
4619 for (i = 0; i < 3; i++) {
4620 if (sc->chainmask & (1 << i)) {
4621 /* Compute attenuation (in unit of 1.5dB). */
4622 delta = (noise - (int32_t)calib->noise[i]) / 30;
4623 /* NB: delta <= 0 */
4624 /* Limit to [-4.5dB,0]. */
4625 cmd.gain[i] = MIN(abs(delta), 3);
4627 cmd.gain[i] |= 1 << 2; /* sign bit */
4630 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4631 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n",
4632 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask);
4633 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4637 iwn5000_set_gains(struct iwn_softc *sc)
4639 struct iwn_calib_state *calib = &sc->calib;
4640 struct iwn_phy_calib_gain cmd;
4641 int i, ant, div, delta;
4643 /* We collected 20 beacons and !=6050 need a 1.5 factor. */
4644 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
4646 memset(&cmd, 0, sizeof cmd);
4647 cmd.code = sc->noise_gain;
4650 /* Get first available RX antenna as referential. */
4651 ant = IWN_LSB(sc->rxchainmask);
4652 /* Set differential gains for other antennas. */
4653 for (i = ant + 1; i < 3; i++) {
4654 if (sc->chainmask & (1 << i)) {
4655 /* The delta is relative to antenna "ant". */
4656 delta = ((int32_t)calib->noise[ant] -
4657 (int32_t)calib->noise[i]) / div;
4658 /* Limit to [-4.5dB,+4.5dB]. */
4659 cmd.gain[i - 1] = MIN(abs(delta), 3);
4661 cmd.gain[i - 1] |= 1 << 2; /* sign bit */
4664 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4665 "setting differential gains Ant B/C: %x/%x (%x)\n",
4666 cmd.gain[0], cmd.gain[1], sc->chainmask);
4667 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4671 * Tune RF RX sensitivity based on the number of false alarms detected
4672 * during the last beacon period.
4675 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats)
4677 #define inc(val, inc, max) \
4678 if ((val) < (max)) { \
4679 if ((val) < (max) - (inc)) \
4685 #define dec(val, dec, min) \
4686 if ((val) > (min)) { \
4687 if ((val) > (min) + (dec)) \
4694 const struct iwn_sensitivity_limits *limits = sc->limits;
4695 struct iwn_calib_state *calib = &sc->calib;
4696 uint32_t val, rxena, fa;
4697 uint32_t energy[3], energy_min;
4698 uint8_t noise[3], noise_ref;
4699 int i, needs_update = 0;
4701 /* Check that we've been enabled long enough. */
4702 if ((rxena = le32toh(stats->general.load)) == 0)
4705 /* Compute number of false alarms since last call for OFDM. */
4706 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm;
4707 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm;
4708 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */
4710 /* Save counters values for next call. */
4711 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp);
4712 calib->fa_ofdm = le32toh(stats->ofdm.fa);
4714 if (fa > 50 * rxena) {
4715 /* High false alarm count, decrease sensitivity. */
4716 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4717 "%s: OFDM high false alarm count: %u\n", __func__, fa);
4718 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1);
4719 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);
4720 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4);
4721 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);
4723 } else if (fa < 5 * rxena) {
4724 /* Low false alarm count, increase sensitivity. */
4725 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4726 "%s: OFDM low false alarm count: %u\n", __func__, fa);
4727 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1);
4728 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);
4729 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4);
4730 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);
4733 /* Compute maximum noise among 3 receivers. */
4734 for (i = 0; i < 3; i++)
4735 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff;
4736 val = MAX(noise[0], noise[1]);
4737 val = MAX(noise[2], val);
4738 /* Insert it into our samples table. */
4739 calib->noise_samples[calib->cur_noise_sample] = val;
4740 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20;
4742 /* Compute maximum noise among last 20 samples. */
4743 noise_ref = calib->noise_samples[0];
4744 for (i = 1; i < 20; i++)
4745 noise_ref = MAX(noise_ref, calib->noise_samples[i]);
4747 /* Compute maximum energy among 3 receivers. */
4748 for (i = 0; i < 3; i++)
4749 energy[i] = le32toh(stats->general.energy[i]);
4750 val = MIN(energy[0], energy[1]);
4751 val = MIN(energy[2], val);
4752 /* Insert it into our samples table. */
4753 calib->energy_samples[calib->cur_energy_sample] = val;
4754 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10;
4756 /* Compute minimum energy among last 10 samples. */
4757 energy_min = calib->energy_samples[0];
4758 for (i = 1; i < 10; i++)
4759 energy_min = MAX(energy_min, calib->energy_samples[i]);
4762 /* Compute number of false alarms since last call for CCK. */
4763 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck;
4764 fa += le32toh(stats->cck.fa) - calib->fa_cck;
4765 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */
4767 /* Save counters values for next call. */
4768 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp);
4769 calib->fa_cck = le32toh(stats->cck.fa);
4771 if (fa > 50 * rxena) {
4772 /* High false alarm count, decrease sensitivity. */
4773 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4774 "%s: CCK high false alarm count: %u\n", __func__, fa);
4775 calib->cck_state = IWN_CCK_STATE_HIFA;
4778 if (calib->cck_x4 > 160) {
4779 calib->noise_ref = noise_ref;
4780 if (calib->energy_cck > 2)
4781 dec(calib->energy_cck, 2, energy_min);
4783 if (calib->cck_x4 < 160) {
4784 calib->cck_x4 = 161;
4787 inc(calib->cck_x4, 3, limits->max_cck_x4);
4789 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);
4791 } else if (fa < 5 * rxena) {
4792 /* Low false alarm count, increase sensitivity. */
4793 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4794 "%s: CCK low false alarm count: %u\n", __func__, fa);
4795 calib->cck_state = IWN_CCK_STATE_LOFA;
4798 if (calib->cck_state != IWN_CCK_STATE_INIT &&
4799 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 ||
4800 calib->low_fa > 100)) {
4801 inc(calib->energy_cck, 2, limits->min_energy_cck);
4802 dec(calib->cck_x4, 3, limits->min_cck_x4);
4803 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);
4806 /* Not worth to increase or decrease sensitivity. */
4807 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4808 "%s: CCK normal false alarm count: %u\n", __func__, fa);
4810 calib->noise_ref = noise_ref;
4812 if (calib->cck_state == IWN_CCK_STATE_HIFA) {
4813 /* Previous interval had many false alarms. */
4814 dec(calib->energy_cck, 8, energy_min);
4816 calib->cck_state = IWN_CCK_STATE_INIT;
4820 (void)iwn_send_sensitivity(sc);
4826 iwn_send_sensitivity(struct iwn_softc *sc)
4828 struct iwn_calib_state *calib = &sc->calib;
4829 struct iwn_enhanced_sensitivity_cmd cmd;
4832 memset(&cmd, 0, sizeof cmd);
4833 len = sizeof (struct iwn_sensitivity_cmd);
4834 cmd.which = IWN_SENSITIVITY_WORKTBL;
4835 /* OFDM modulation. */
4836 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1);
4837 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1);
4838 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4);
4839 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4);
4840 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);
4841 cmd.energy_ofdm_th = htole16(62);
4842 /* CCK modulation. */
4843 cmd.corr_cck_x4 = htole16(calib->cck_x4);
4844 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4);
4845 cmd.energy_cck = htole16(calib->energy_cck);
4846 /* Barker modulation: use default values. */
4847 cmd.corr_barker = htole16(190);
4848 cmd.corr_barker_mrc = htole16(390);
4850 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4851 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
4852 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4,
4853 calib->ofdm_mrc_x4, calib->cck_x4,
4854 calib->cck_mrc_x4, calib->energy_cck);
4856 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS))
4858 /* Enhanced sensitivity settings. */
4859 len = sizeof (struct iwn_enhanced_sensitivity_cmd);
4860 cmd.ofdm_det_slope_mrc = htole16(668);
4861 cmd.ofdm_det_icept_mrc = htole16(4);
4862 cmd.ofdm_det_slope = htole16(486);
4863 cmd.ofdm_det_icept = htole16(37);
4864 cmd.cck_det_slope_mrc = htole16(853);
4865 cmd.cck_det_icept_mrc = htole16(4);
4866 cmd.cck_det_slope = htole16(476);
4867 cmd.cck_det_icept = htole16(99);
4869 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1);
4873 * Set STA mode power saving level (between 0 and 5).
4874 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving.
4877 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async)
4879 struct iwn_pmgt_cmd cmd;
4880 const struct iwn_pmgt *pmgt;
4881 uint32_t max, skip_dtim;
4885 /* Select which PS parameters to use. */
4887 pmgt = &iwn_pmgt[0][level];
4888 else if (dtim <= 10)
4889 pmgt = &iwn_pmgt[1][level];
4891 pmgt = &iwn_pmgt[2][level];
4893 memset(&cmd, 0, sizeof cmd);
4894 if (level != 0) /* not CAM */
4895 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP);
4897 cmd.flags |= htole16(IWN_PS_FAST_PD);
4898 /* Retrieve PCIe Active State Power Management (ASPM). */
4899 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
4900 if (!(reg & 0x1)) /* L0s Entry disabled. */
4901 cmd.flags |= htole16(IWN_PS_PCI_PMGT);
4902 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
4903 cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
4909 skip_dtim = pmgt->skip_dtim;
4910 if (skip_dtim != 0) {
4911 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM);
4912 max = pmgt->intval[4];
4913 if (max == (uint32_t)-1)
4914 max = dtim * (skip_dtim + 1);
4915 else if (max > dtim)
4916 max = (max / dtim) * dtim;
4919 for (i = 0; i < 5; i++)
4920 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i]));
4922 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n",
4924 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async);
4928 iwn_send_btcoex(struct iwn_softc *sc)
4930 struct iwn_bluetooth cmd;
4932 memset(&cmd, 0, sizeof cmd);
4933 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO;
4934 cmd.lead_time = IWN_BT_LEAD_TIME_DEF;
4935 cmd.max_kill = IWN_BT_MAX_KILL_DEF;
4936 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n",
4938 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0);
4942 iwn_send_advanced_btcoex(struct iwn_softc *sc)
4944 static const uint32_t btcoex_3wire[12] = {
4945 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa,
4946 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa,
4947 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000,
4949 struct iwn6000_btcoex_config btconfig;
4950 struct iwn_btcoex_priotable btprio;
4951 struct iwn_btcoex_prot btprot;
4954 memset(&btconfig, 0, sizeof btconfig);
4955 btconfig.flags = 145;
4956 btconfig.max_kill = 5;
4957 btconfig.bt3_t7_timer = 1;
4958 btconfig.kill_ack = htole32(0xffff0000);
4959 btconfig.kill_cts = htole32(0xffff0000);
4960 btconfig.sample_time = 2;
4961 btconfig.bt3_t2_timer = 0xc;
4962 for (i = 0; i < 12; i++)
4963 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]);
4964 btconfig.valid = htole16(0xff);
4965 btconfig.prio_boost = 0xf0;
4966 DPRINTF(sc, IWN_DEBUG_RESET,
4967 "%s: configuring advanced bluetooth coexistence\n", __func__);
4968 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, sizeof(btconfig), 1);
4972 memset(&btprio, 0, sizeof btprio);
4973 btprio.calib_init1 = 0x6;
4974 btprio.calib_init2 = 0x7;
4975 btprio.calib_periodic_low1 = 0x2;
4976 btprio.calib_periodic_low2 = 0x3;
4977 btprio.calib_periodic_high1 = 0x4;
4978 btprio.calib_periodic_high2 = 0x5;
4980 btprio.scan52 = 0x8;
4981 btprio.scan24 = 0xa;
4982 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio),
4987 /* Force BT state machine change. */
4988 memset(&btprot, 0, sizeof btprio);
4991 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
4995 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
4999 iwn_config(struct iwn_softc *sc)
5001 struct iwn_ops *ops = &sc->ops;
5002 struct ifnet *ifp = sc->sc_ifp;
5003 struct ieee80211com *ic = ifp->if_l2com;
5008 if (sc->hw_type == IWN_HW_REV_TYPE_6005) {
5009 /* Set radio temperature sensor offset. */
5010 error = iwn5000_temp_offset_calib(sc);
5012 device_printf(sc->sc_dev,
5013 "%s: could not set temperature offset\n", __func__);
5018 /* Configure valid TX chains for >=5000 Series. */
5019 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
5020 txmask = htole32(sc->txchainmask);
5021 DPRINTF(sc, IWN_DEBUG_RESET,
5022 "%s: configuring valid TX chains 0x%x\n", __func__, txmask);
5023 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask,
5026 device_printf(sc->sc_dev,
5027 "%s: could not configure valid TX chains, "
5028 "error %d\n", __func__, error);
5033 /* Configure bluetooth coexistence. */
5034 if (sc->sc_flags & IWN_FLAG_ADV_BTCOEX)
5035 error = iwn_send_advanced_btcoex(sc);
5037 error = iwn_send_btcoex(sc);
5039 device_printf(sc->sc_dev,
5040 "%s: could not configure bluetooth coexistence, error %d\n",
5045 /* Set mode, channel, RX filter and enable RX. */
5046 memset(&sc->rxon, 0, sizeof (struct iwn_rxon));
5047 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp));
5048 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp));
5049 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
5050 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
5051 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
5052 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
5053 switch (ic->ic_opmode) {
5054 case IEEE80211_M_STA:
5055 sc->rxon.mode = IWN_MODE_STA;
5056 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST);
5058 case IEEE80211_M_MONITOR:
5059 sc->rxon.mode = IWN_MODE_MONITOR;
5060 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST |
5061 IWN_FILTER_CTL | IWN_FILTER_PROMISC);
5064 /* Should not get there. */
5067 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */
5068 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */
5069 sc->rxon.ht_single_mask = 0xff;
5070 sc->rxon.ht_dual_mask = 0xff;
5071 sc->rxon.ht_triple_mask = 0xff;
5073 IWN_RXCHAIN_VALID(sc->rxchainmask) |
5074 IWN_RXCHAIN_MIMO_COUNT(2) |
5075 IWN_RXCHAIN_IDLE_COUNT(2);
5076 sc->rxon.rxchain = htole16(rxchain);
5077 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__);
5078 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0);
5080 device_printf(sc->sc_dev, "%s: RXON command failed\n",
5085 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) {
5086 device_printf(sc->sc_dev, "%s: could not add broadcast node\n",
5091 /* Configuration has changed, set TX power accordingly. */
5092 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) {
5093 device_printf(sc->sc_dev, "%s: could not set TX power\n",
5098 if ((error = iwn_set_critical_temp(sc)) != 0) {
5099 device_printf(sc->sc_dev,
5100 "%s: could not set critical temperature\n", __func__);
5104 /* Set power saving level to CAM during initialization. */
5105 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) {
5106 device_printf(sc->sc_dev,
5107 "%s: could not set power saving level\n", __func__);
5114 * Add an ssid element to a frame.
5117 ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len)
5119 *frm++ = IEEE80211_ELEMID_SSID;
5121 memcpy(frm, ssid, len);
5126 iwn_scan(struct iwn_softc *sc)
5128 struct ifnet *ifp = sc->sc_ifp;
5129 struct ieee80211com *ic = ifp->if_l2com;
5130 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/
5131 struct ieee80211_node *ni = ss->ss_vap->iv_bss;
5132 struct iwn_scan_hdr *hdr;
5133 struct iwn_cmd_data *tx;
5134 struct iwn_scan_essid *essid;
5135 struct iwn_scan_chan *chan;
5136 struct ieee80211_frame *wh;
5137 struct ieee80211_rateset *rs;
5138 struct ieee80211_channel *c;
5144 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO);
5146 device_printf(sc->sc_dev,
5147 "%s: could not allocate buffer for scan command\n",
5151 hdr = (struct iwn_scan_hdr *)buf;
5153 * Move to the next channel if no frames are received within 10ms
5154 * after sending the probe request.
5156 hdr->quiet_time = htole16(10); /* timeout in milliseconds */
5157 hdr->quiet_threshold = htole16(1); /* min # of packets */
5159 /* Select antennas for scanning. */
5161 IWN_RXCHAIN_VALID(sc->rxchainmask) |
5162 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) |
5163 IWN_RXCHAIN_DRIVER_FORCE;
5164 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) &&
5165 sc->hw_type == IWN_HW_REV_TYPE_4965) {
5166 /* Ant A must be avoided in 5GHz because of an HW bug. */
5167 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B);
5168 } else /* Use all available RX antennas. */
5169 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask);
5170 hdr->rxchain = htole16(rxchain);
5171 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON);
5173 tx = (struct iwn_cmd_data *)(hdr + 1);
5174 tx->flags = htole32(IWN_TX_AUTO_SEQ);
5175 tx->id = sc->broadcast_id;
5176 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
5178 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) {
5179 /* Send probe requests at 6Mbps. */
5180 tx->rate = htole32(0xd);
5181 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A];
5183 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO);
5184 if (sc->hw_type == IWN_HW_REV_TYPE_4965 &&
5185 sc->rxon.associd && sc->rxon.chan > 14)
5186 tx->rate = htole32(0xd);
5188 /* Send probe requests at 1Mbps. */
5189 tx->rate = htole32(10 | IWN_RFLAG_CCK);
5191 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G];
5193 /* Use the first valid TX antenna. */
5194 txant = IWN_LSB(sc->txchainmask);
5195 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
5197 essid = (struct iwn_scan_essid *)(tx + 1);
5198 if (ss->ss_ssid[0].len != 0) {
5199 essid[0].id = IEEE80211_ELEMID_SSID;
5200 essid[0].len = ss->ss_ssid[0].len;
5201 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
5204 * Build a probe request frame. Most of the following code is a
5205 * copy & paste of what is done in net80211.
5207 wh = (struct ieee80211_frame *)(essid + 20);
5208 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
5209 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
5210 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
5211 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr);
5212 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp));
5213 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr);
5214 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */
5215 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */
5217 frm = (uint8_t *)(wh + 1);
5218 frm = ieee80211_add_ssid(frm, NULL, 0);
5219 frm = ieee80211_add_rates(frm, rs);
5220 if (rs->rs_nrates > IEEE80211_RATE_SIZE)
5221 frm = ieee80211_add_xrates(frm, rs);
5222 if (ic->ic_htcaps & IEEE80211_HTC_HT)
5223 frm = ieee80211_add_htcap(frm, ni);
5225 /* Set length of probe request. */
5226 tx->len = htole16(frm - (uint8_t *)wh);
5229 chan = (struct iwn_scan_chan *)frm;
5230 chan->chan = htole16(ieee80211_chan2ieee(ic, c));
5232 if (ss->ss_nssid > 0)
5233 chan->flags |= htole32(IWN_CHAN_NPBREQS(1));
5234 chan->dsp_gain = 0x6e;
5235 if (IEEE80211_IS_CHAN_5GHZ(c) &&
5236 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
5237 chan->rf_gain = 0x3b;
5238 chan->active = htole16(24);
5239 chan->passive = htole16(110);
5240 chan->flags |= htole32(IWN_CHAN_ACTIVE);
5241 } else if (IEEE80211_IS_CHAN_5GHZ(c)) {
5242 chan->rf_gain = 0x3b;
5243 chan->active = htole16(24);
5244 if (sc->rxon.associd)
5245 chan->passive = htole16(78);
5247 chan->passive = htole16(110);
5248 hdr->crc_threshold = 0xffff;
5249 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
5250 chan->rf_gain = 0x28;
5251 chan->active = htole16(36);
5252 chan->passive = htole16(120);
5253 chan->flags |= htole32(IWN_CHAN_ACTIVE);
5255 chan->rf_gain = 0x28;
5256 chan->active = htole16(36);
5257 if (sc->rxon.associd)
5258 chan->passive = htole16(88);
5260 chan->passive = htole16(120);
5261 hdr->crc_threshold = 0xffff;
5264 DPRINTF(sc, IWN_DEBUG_STATE,
5265 "%s: chan %u flags 0x%x rf_gain 0x%x "
5266 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__,
5267 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain,
5268 chan->active, chan->passive);
5272 buflen = (uint8_t *)chan - buf;
5273 hdr->len = htole16(buflen);
5275 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n",
5277 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1);
5278 free(buf, M_DEVBUF);
5283 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap)
5285 struct iwn_ops *ops = &sc->ops;
5286 struct ifnet *ifp = sc->sc_ifp;
5287 struct ieee80211com *ic = ifp->if_l2com;
5288 struct ieee80211_node *ni = vap->iv_bss;
5291 /* Update adapter configuration. */
5292 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
5293 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan);
5294 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
5295 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
5296 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
5297 if (ic->ic_flags & IEEE80211_F_SHSLOT)
5298 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
5299 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
5300 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
5301 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
5302 sc->rxon.cck_mask = 0;
5303 sc->rxon.ofdm_mask = 0x15;
5304 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
5305 sc->rxon.cck_mask = 0x03;
5306 sc->rxon.ofdm_mask = 0;
5308 /* Assume 802.11b/g. */
5309 sc->rxon.cck_mask = 0x0f;
5310 sc->rxon.ofdm_mask = 0x15;
5312 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n",
5313 sc->rxon.chan, sc->rxon.flags, sc->rxon.cck_mask,
5314 sc->rxon.ofdm_mask);
5315 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
5317 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n",
5322 /* Configuration has changed, set TX power accordingly. */
5323 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) {
5324 device_printf(sc->sc_dev,
5325 "%s: could not set TX power, error %d\n", __func__, error);
5329 * Reconfiguring RXON clears the firmware nodes table so we must
5330 * add the broadcast node again.
5332 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) {
5333 device_printf(sc->sc_dev,
5334 "%s: could not add broadcast node, error %d\n", __func__,
5342 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap)
5344 struct iwn_ops *ops = &sc->ops;
5345 struct ifnet *ifp = sc->sc_ifp;
5346 struct ieee80211com *ic = ifp->if_l2com;
5347 struct ieee80211_node *ni = vap->iv_bss;
5348 struct iwn_node_info node;
5349 uint32_t htflags = 0;
5352 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
5353 /* Link LED blinks while monitoring. */
5354 iwn_set_led(sc, IWN_LED_LINK, 5, 5);
5357 if ((error = iwn_set_timing(sc, ni)) != 0) {
5358 device_printf(sc->sc_dev,
5359 "%s: could not set timing, error %d\n", __func__, error);
5363 /* Update adapter configuration. */
5364 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
5365 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd));
5366 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan);
5367 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
5368 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
5369 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
5370 if (ic->ic_flags & IEEE80211_F_SHSLOT)
5371 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
5372 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
5373 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
5374 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
5375 sc->rxon.cck_mask = 0;
5376 sc->rxon.ofdm_mask = 0x15;
5377 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
5378 sc->rxon.cck_mask = 0x03;
5379 sc->rxon.ofdm_mask = 0;
5381 /* Assume 802.11b/g. */
5382 sc->rxon.cck_mask = 0x0f;
5383 sc->rxon.ofdm_mask = 0x15;
5385 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
5386 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode);
5387 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
5388 switch (ic->ic_curhtprotmode) {
5389 case IEEE80211_HTINFO_OPMODE_HT20PR:
5390 htflags |= IWN_RXON_HT_MODEPURE40;
5393 htflags |= IWN_RXON_HT_MODEMIXED;
5397 if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan))
5398 htflags |= IWN_RXON_HT_HT40MINUS;
5400 sc->rxon.flags |= htole32(htflags);
5401 sc->rxon.filter |= htole32(IWN_FILTER_BSS);
5402 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n",
5403 sc->rxon.chan, sc->rxon.flags);
5404 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
5406 device_printf(sc->sc_dev,
5407 "%s: could not update configuration, error %d\n", __func__,
5412 /* Configuration has changed, set TX power accordingly. */
5413 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) {
5414 device_printf(sc->sc_dev,
5415 "%s: could not set TX power, error %d\n", __func__, error);
5419 /* Fake a join to initialize the TX rate. */
5420 ((struct iwn_node *)ni)->id = IWN_ID_BSS;
5421 iwn_newassoc(ni, 1);
5424 memset(&node, 0, sizeof node);
5425 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr);
5426 node.id = IWN_ID_BSS;
5427 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
5428 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) {
5429 case IEEE80211_HTCAP_SMPS_ENA:
5430 node.htflags |= htole32(IWN_SMPS_MIMO_DIS);
5432 case IEEE80211_HTCAP_SMPS_DYNAMIC:
5433 node.htflags |= htole32(IWN_SMPS_MIMO_PROT);
5436 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) |
5437 IWN_AMDPU_DENSITY(5)); /* 4us */
5438 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan))
5439 node.htflags |= htole32(IWN_NODE_HT40);
5441 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__);
5442 error = ops->add_node(sc, &node, 1);
5444 device_printf(sc->sc_dev,
5445 "%s: could not add BSS node, error %d\n", __func__, error);
5448 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n",
5450 if ((error = iwn_set_link_quality(sc, ni)) != 0) {
5451 device_printf(sc->sc_dev,
5452 "%s: could not setup link quality for node %d, error %d\n",
5453 __func__, node.id, error);
5457 if ((error = iwn_init_sensitivity(sc)) != 0) {
5458 device_printf(sc->sc_dev,
5459 "%s: could not set sensitivity, error %d\n", __func__,
5463 /* Start periodic calibration timer. */
5464 sc->calib.state = IWN_CALIB_STATE_ASSOC;
5466 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
5469 /* Link LED always on while associated. */
5470 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
5475 * This function is called by upper layer when an ADDBA request is received
5476 * from another STA and before the ADDBA response is sent.
5479 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap,
5480 int baparamset, int batimeout, int baseqctl)
5482 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
5483 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5484 struct iwn_ops *ops = &sc->ops;
5485 struct iwn_node *wn = (void *)ni;
5486 struct iwn_node_info node;
5491 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID);
5492 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START);
5494 memset(&node, 0, sizeof node);
5496 node.control = IWN_NODE_UPDATE;
5497 node.flags = IWN_FLAG_SET_ADDBA;
5498 node.addba_tid = tid;
5499 node.addba_ssn = htole16(ssn);
5500 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n",
5502 error = ops->add_node(sc, &node, 1);
5505 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl);
5510 * This function is called by upper layer on teardown of an HT-immediate
5511 * Block Ack agreement (eg. uppon receipt of a DELBA frame).
5514 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap)
5516 struct ieee80211com *ic = ni->ni_ic;
5517 struct iwn_softc *sc = ic->ic_ifp->if_softc;
5518 struct iwn_ops *ops = &sc->ops;
5519 struct iwn_node *wn = (void *)ni;
5520 struct iwn_node_info node;
5523 /* XXX: tid as an argument */
5524 for (tid = 0; tid < WME_NUM_TID; tid++) {
5525 if (&ni->ni_rx_ampdu[tid] == rap)
5529 memset(&node, 0, sizeof node);
5531 node.control = IWN_NODE_UPDATE;
5532 node.flags = IWN_FLAG_SET_DELBA;
5533 node.delba_tid = tid;
5534 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid);
5535 (void)ops->add_node(sc, &node, 1);
5536 sc->sc_ampdu_rx_stop(ni, rap);
5540 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
5541 int dialogtoken, int baparamset, int batimeout)
5543 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5546 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) {
5547 if (sc->qid2tap[qid] == NULL)
5550 if (qid == sc->ntxqs) {
5551 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n",
5555 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
5556 if (tap->txa_private == NULL) {
5557 device_printf(sc->sc_dev,
5558 "%s: failed to alloc TX aggregation structure\n", __func__);
5561 sc->qid2tap[qid] = tap;
5562 *(int *)tap->txa_private = qid;
5563 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
5568 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
5569 int code, int baparamset, int batimeout)
5571 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5572 int qid = *(int *)tap->txa_private;
5573 uint8_t tid = WME_AC_TO_TID(tap->txa_ac);
5576 if (code == IEEE80211_STATUS_SUCCESS) {
5577 ni->ni_txseqs[tid] = tap->txa_start & 0xfff;
5578 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid);
5582 sc->qid2tap[qid] = NULL;
5583 free(tap->txa_private, M_DEVBUF);
5584 tap->txa_private = NULL;
5586 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout);
5590 * This function is called by upper layer when an ADDBA response is received
5594 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
5597 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[TID_TO_WME_AC(tid)];
5598 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5599 struct iwn_ops *ops = &sc->ops;
5600 struct iwn_node *wn = (void *)ni;
5601 struct iwn_node_info node;
5604 /* Enable TX for the specified RA/TID. */
5605 wn->disable_tid &= ~(1 << tid);
5606 memset(&node, 0, sizeof node);
5608 node.control = IWN_NODE_UPDATE;
5609 node.flags = IWN_FLAG_SET_DISABLE_TID;
5610 node.disable_tid = htole16(wn->disable_tid);
5611 error = ops->add_node(sc, &node, 1);
5615 if ((error = iwn_nic_lock(sc)) != 0)
5617 qid = *(int *)tap->txa_private;
5618 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff);
5621 iwn_set_link_quality(sc, ni);
5626 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
5628 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5629 struct iwn_ops *ops = &sc->ops;
5630 uint8_t tid = WME_AC_TO_TID(tap->txa_ac);
5633 if (tap->txa_private == NULL)
5636 qid = *(int *)tap->txa_private;
5637 if (iwn_nic_lock(sc) != 0)
5639 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff);
5641 sc->qid2tap[qid] = NULL;
5642 free(tap->txa_private, M_DEVBUF);
5643 tap->txa_private = NULL;
5647 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5648 int qid, uint8_t tid, uint16_t ssn)
5650 struct iwn_node *wn = (void *)ni;
5652 /* Stop TX scheduler while we're changing its configuration. */
5653 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5654 IWN4965_TXQ_STATUS_CHGACT);
5656 /* Assign RA/TID translation to the queue. */
5657 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
5660 /* Enable chain-building mode for the queue. */
5661 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid);
5663 /* Set starting sequence number from the ADDBA request. */
5664 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
5665 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5666 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5668 /* Set scheduler window size. */
5669 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
5671 /* Set scheduler frame limit. */
5672 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5673 IWN_SCHED_LIMIT << 16);
5675 /* Enable interrupts for the queue. */
5676 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5678 /* Mark the queue as active. */
5679 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5680 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA |
5681 iwn_tid2fifo[tid] << 1);
5685 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
5687 /* Stop TX scheduler while we're changing its configuration. */
5688 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5689 IWN4965_TXQ_STATUS_CHGACT);
5691 /* Set starting sequence number from the ADDBA request. */
5692 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5693 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5695 /* Disable interrupts for the queue. */
5696 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5698 /* Mark the queue as inactive. */
5699 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5700 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1);
5704 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5705 int qid, uint8_t tid, uint16_t ssn)
5707 struct iwn_node *wn = (void *)ni;
5709 /* Stop TX scheduler while we're changing its configuration. */
5710 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5711 IWN5000_TXQ_STATUS_CHGACT);
5713 /* Assign RA/TID translation to the queue. */
5714 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
5717 /* Enable chain-building mode for the queue. */
5718 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid);
5720 /* Enable aggregation for the queue. */
5721 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5723 /* Set starting sequence number from the ADDBA request. */
5724 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
5725 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5726 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5728 /* Set scheduler window size and frame limit. */
5729 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5730 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5732 /* Enable interrupts for the queue. */
5733 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5735 /* Mark the queue as active. */
5736 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5737 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]);
5741 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
5743 /* Stop TX scheduler while we're changing its configuration. */
5744 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5745 IWN5000_TXQ_STATUS_CHGACT);
5747 /* Disable aggregation for the queue. */
5748 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5750 /* Set starting sequence number from the ADDBA request. */
5751 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5752 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5754 /* Disable interrupts for the queue. */
5755 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5757 /* Mark the queue as inactive. */
5758 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5759 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]);
5763 * Query calibration tables from the initialization firmware. We do this
5764 * only once at first boot. Called from a process context.
5767 iwn5000_query_calibration(struct iwn_softc *sc)
5769 struct iwn5000_calib_config cmd;
5772 memset(&cmd, 0, sizeof cmd);
5773 cmd.ucode.once.enable = 0xffffffff;
5774 cmd.ucode.once.start = 0xffffffff;
5775 cmd.ucode.once.send = 0xffffffff;
5776 cmd.ucode.flags = 0xffffffff;
5777 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n",
5779 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0);
5783 /* Wait at most two seconds for calibration to complete. */
5784 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE))
5785 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz);
5790 * Send calibration results to the runtime firmware. These results were
5791 * obtained on first boot from the initialization firmware.
5794 iwn5000_send_calibration(struct iwn_softc *sc)
5798 for (idx = 0; idx < 5; idx++) {
5799 if (sc->calibcmd[idx].buf == NULL)
5800 continue; /* No results available. */
5801 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5802 "send calibration result idx=%d len=%d\n", idx,
5803 sc->calibcmd[idx].len);
5804 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf,
5805 sc->calibcmd[idx].len, 0);
5807 device_printf(sc->sc_dev,
5808 "%s: could not send calibration result, error %d\n",
5817 iwn5000_send_wimax_coex(struct iwn_softc *sc)
5819 struct iwn5000_wimax_coex wimax;
5822 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
5823 /* Enable WiMAX coexistence for combo adapters. */
5825 IWN_WIMAX_COEX_ASSOC_WA_UNMASK |
5826 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK |
5827 IWN_WIMAX_COEX_STA_TABLE_VALID |
5828 IWN_WIMAX_COEX_ENABLE;
5829 memcpy(wimax.events, iwn6050_wimax_events,
5830 sizeof iwn6050_wimax_events);
5834 /* Disable WiMAX coexistence. */
5836 memset(wimax.events, 0, sizeof wimax.events);
5838 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n",
5840 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0);
5844 iwn5000_crystal_calib(struct iwn_softc *sc)
5846 struct iwn5000_phy_calib_crystal cmd;
5848 memset(&cmd, 0, sizeof cmd);
5849 cmd.code = IWN5000_PHY_CALIB_CRYSTAL;
5852 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
5853 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
5854 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n",
5855 cmd.cap_pin[0], cmd.cap_pin[1]);
5856 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5860 iwn5000_temp_offset_calib(struct iwn_softc *sc)
5862 struct iwn5000_phy_calib_temp_offset cmd;
5864 memset(&cmd, 0, sizeof cmd);
5865 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET;
5868 if (sc->eeprom_temp != 0)
5869 cmd.offset = htole16(sc->eeprom_temp);
5871 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET);
5872 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n",
5873 le16toh(cmd.offset));
5874 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5878 * This function is called after the runtime firmware notifies us of its
5879 * readiness (called in a process context).
5882 iwn4965_post_alive(struct iwn_softc *sc)
5886 if ((error = iwn_nic_lock(sc)) != 0)
5889 /* Clear TX scheduler state in SRAM. */
5890 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5891 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
5892 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t));
5894 /* Set physical address of TX scheduler rings (1KB aligned). */
5895 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5897 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5899 /* Disable chain mode for all our 16 queues. */
5900 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0);
5902 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) {
5903 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0);
5904 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5906 /* Set scheduler window size. */
5907 iwn_mem_write(sc, sc->sched_base +
5908 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ);
5909 /* Set scheduler frame limit. */
5910 iwn_mem_write(sc, sc->sched_base +
5911 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5912 IWN_SCHED_LIMIT << 16);
5915 /* Enable interrupts for all our 16 queues. */
5916 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff);
5917 /* Identify TX FIFO rings (0-7). */
5918 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff);
5920 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5921 for (qid = 0; qid < 7; qid++) {
5922 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
5923 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5924 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1);
5931 * This function is called after the initialization or runtime firmware
5932 * notifies us of its readiness (called in a process context).
5935 iwn5000_post_alive(struct iwn_softc *sc)
5939 /* Switch to using ICT interrupt mode. */
5940 iwn5000_ict_reset(sc);
5942 if ((error = iwn_nic_lock(sc)) != 0)
5945 /* Clear TX scheduler state in SRAM. */
5946 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5947 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
5948 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t));
5950 /* Set physical address of TX scheduler rings (1KB aligned). */
5951 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5953 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5955 /* Enable chain mode for all queues, except command queue. */
5956 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef);
5957 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0);
5959 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) {
5960 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0);
5961 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5963 iwn_mem_write(sc, sc->sched_base +
5964 IWN5000_SCHED_QUEUE_OFFSET(qid), 0);
5965 /* Set scheduler window size and frame limit. */
5966 iwn_mem_write(sc, sc->sched_base +
5967 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5968 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5971 /* Enable interrupts for all our 20 queues. */
5972 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff);
5973 /* Identify TX FIFO rings (0-7). */
5974 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff);
5976 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5977 for (qid = 0; qid < 7; qid++) {
5978 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
5979 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5980 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
5984 /* Configure WiMAX coexistence for combo adapters. */
5985 error = iwn5000_send_wimax_coex(sc);
5987 device_printf(sc->sc_dev,
5988 "%s: could not configure WiMAX coexistence, error %d\n",
5992 if (sc->hw_type != IWN_HW_REV_TYPE_5150) {
5993 /* Perform crystal calibration. */
5994 error = iwn5000_crystal_calib(sc);
5996 device_printf(sc->sc_dev,
5997 "%s: crystal calibration failed, error %d\n",
6002 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) {
6003 /* Query calibration from the initialization firmware. */
6004 if ((error = iwn5000_query_calibration(sc)) != 0) {
6005 device_printf(sc->sc_dev,
6006 "%s: could not query calibration, error %d\n",
6011 * We have the calibration results now, reboot with the
6012 * runtime firmware (call ourselves recursively!)
6015 error = iwn_hw_init(sc);
6017 /* Send calibration results to runtime firmware. */
6018 error = iwn5000_send_calibration(sc);
6024 * The firmware boot code is small and is intended to be copied directly into
6025 * the NIC internal memory (no DMA transfer).
6028 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size)
6032 size /= sizeof (uint32_t);
6034 if ((error = iwn_nic_lock(sc)) != 0)
6037 /* Copy microcode image into NIC memory. */
6038 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE,
6039 (const uint32_t *)ucode, size);
6041 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0);
6042 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE);
6043 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size);
6045 /* Start boot load now. */
6046 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START);
6048 /* Wait for transfer to complete. */
6049 for (ntries = 0; ntries < 1000; ntries++) {
6050 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) &
6051 IWN_BSM_WR_CTRL_START))
6055 if (ntries == 1000) {
6056 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
6062 /* Enable boot after power up. */
6063 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN);
6070 iwn4965_load_firmware(struct iwn_softc *sc)
6072 struct iwn_fw_info *fw = &sc->fw;
6073 struct iwn_dma_info *dma = &sc->fw_dma;
6076 /* Copy initialization sections into pre-allocated DMA-safe memory. */
6077 memcpy(dma->vaddr, fw->init.data, fw->init.datasz);
6078 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6079 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
6080 fw->init.text, fw->init.textsz);
6081 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6083 /* Tell adapter where to find initialization sections. */
6084 if ((error = iwn_nic_lock(sc)) != 0)
6086 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
6087 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz);
6088 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
6089 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
6090 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz);
6093 /* Load firmware boot code. */
6094 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz);
6096 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
6100 /* Now press "execute". */
6101 IWN_WRITE(sc, IWN_RESET, 0);
6103 /* Wait at most one second for first alive notification. */
6104 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
6105 device_printf(sc->sc_dev,
6106 "%s: timeout waiting for adapter to initialize, error %d\n",
6111 /* Retrieve current temperature for initial TX power calibration. */
6112 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz;
6113 sc->temp = iwn4965_get_temperature(sc);
6115 /* Copy runtime sections into pre-allocated DMA-safe memory. */
6116 memcpy(dma->vaddr, fw->main.data, fw->main.datasz);
6117 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6118 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
6119 fw->main.text, fw->main.textsz);
6120 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6122 /* Tell adapter where to find runtime sections. */
6123 if ((error = iwn_nic_lock(sc)) != 0)
6125 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
6126 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz);
6127 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
6128 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
6129 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE,
6130 IWN_FW_UPDATED | fw->main.textsz);
6137 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst,
6138 const uint8_t *section, int size)
6140 struct iwn_dma_info *dma = &sc->fw_dma;
6143 /* Copy firmware section into pre-allocated DMA-safe memory. */
6144 memcpy(dma->vaddr, section, size);
6145 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6147 if ((error = iwn_nic_lock(sc)) != 0)
6150 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
6151 IWN_FH_TX_CONFIG_DMA_PAUSE);
6153 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst);
6154 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL),
6155 IWN_LOADDR(dma->paddr));
6156 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL),
6157 IWN_HIADDR(dma->paddr) << 28 | size);
6158 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL),
6159 IWN_FH_TXBUF_STATUS_TBNUM(1) |
6160 IWN_FH_TXBUF_STATUS_TBIDX(1) |
6161 IWN_FH_TXBUF_STATUS_TFBD_VALID);
6163 /* Kick Flow Handler to start DMA transfer. */
6164 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
6165 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD);
6169 /* Wait at most five seconds for FH DMA transfer to complete. */
6170 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz);
6174 iwn5000_load_firmware(struct iwn_softc *sc)
6176 struct iwn_fw_part *fw;
6179 /* Load the initialization firmware on first boot only. */
6180 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ?
6181 &sc->fw.main : &sc->fw.init;
6183 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE,
6184 fw->text, fw->textsz);
6186 device_printf(sc->sc_dev,
6187 "%s: could not load firmware %s section, error %d\n",
6188 __func__, ".text", error);
6191 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE,
6192 fw->data, fw->datasz);
6194 device_printf(sc->sc_dev,
6195 "%s: could not load firmware %s section, error %d\n",
6196 __func__, ".data", error);
6200 /* Now press "execute". */
6201 IWN_WRITE(sc, IWN_RESET, 0);
6206 * Extract text and data sections from a legacy firmware image.
6209 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw)
6211 const uint32_t *ptr;
6215 ptr = (const uint32_t *)fw->data;
6216 rev = le32toh(*ptr++);
6218 /* Check firmware API version. */
6219 if (IWN_FW_API(rev) <= 1) {
6220 device_printf(sc->sc_dev,
6221 "%s: bad firmware, need API version >=2\n", __func__);
6224 if (IWN_FW_API(rev) >= 3) {
6225 /* Skip build number (version 2 header). */
6229 if (fw->size < hdrlen) {
6230 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6231 __func__, fw->size);
6234 fw->main.textsz = le32toh(*ptr++);
6235 fw->main.datasz = le32toh(*ptr++);
6236 fw->init.textsz = le32toh(*ptr++);
6237 fw->init.datasz = le32toh(*ptr++);
6238 fw->boot.textsz = le32toh(*ptr++);
6240 /* Check that all firmware sections fit. */
6241 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz +
6242 fw->init.textsz + fw->init.datasz + fw->boot.textsz) {
6243 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6244 __func__, fw->size);
6248 /* Get pointers to firmware sections. */
6249 fw->main.text = (const uint8_t *)ptr;
6250 fw->main.data = fw->main.text + fw->main.textsz;
6251 fw->init.text = fw->main.data + fw->main.datasz;
6252 fw->init.data = fw->init.text + fw->init.textsz;
6253 fw->boot.text = fw->init.data + fw->init.datasz;
6258 * Extract text and data sections from a TLV firmware image.
6261 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw,
6264 const struct iwn_fw_tlv_hdr *hdr;
6265 const struct iwn_fw_tlv *tlv;
6266 const uint8_t *ptr, *end;
6270 if (fw->size < sizeof (*hdr)) {
6271 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6272 __func__, fw->size);
6275 hdr = (const struct iwn_fw_tlv_hdr *)fw->data;
6276 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) {
6277 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n",
6278 __func__, le32toh(hdr->signature));
6281 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr,
6282 le32toh(hdr->build));
6285 * Select the closest supported alternative that is less than
6286 * or equal to the specified one.
6288 altmask = le64toh(hdr->altmask);
6289 while (alt > 0 && !(altmask & (1ULL << alt)))
6290 alt--; /* Downgrade. */
6291 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt);
6293 ptr = (const uint8_t *)(hdr + 1);
6294 end = (const uint8_t *)(fw->data + fw->size);
6296 /* Parse type-length-value fields. */
6297 while (ptr + sizeof (*tlv) <= end) {
6298 tlv = (const struct iwn_fw_tlv *)ptr;
6299 len = le32toh(tlv->len);
6301 ptr += sizeof (*tlv);
6302 if (ptr + len > end) {
6303 device_printf(sc->sc_dev,
6304 "%s: firmware too short: %zu bytes\n", __func__,
6308 /* Skip other alternatives. */
6309 if (tlv->alt != 0 && tlv->alt != htole16(alt))
6312 switch (le16toh(tlv->type)) {
6313 case IWN_FW_TLV_MAIN_TEXT:
6314 fw->main.text = ptr;
6315 fw->main.textsz = len;
6317 case IWN_FW_TLV_MAIN_DATA:
6318 fw->main.data = ptr;
6319 fw->main.datasz = len;
6321 case IWN_FW_TLV_INIT_TEXT:
6322 fw->init.text = ptr;
6323 fw->init.textsz = len;
6325 case IWN_FW_TLV_INIT_DATA:
6326 fw->init.data = ptr;
6327 fw->init.datasz = len;
6329 case IWN_FW_TLV_BOOT_TEXT:
6330 fw->boot.text = ptr;
6331 fw->boot.textsz = len;
6333 case IWN_FW_TLV_ENH_SENS:
6335 sc->sc_flags |= IWN_FLAG_ENH_SENS;
6337 case IWN_FW_TLV_PHY_CALIB:
6338 tmp = htole32(*ptr);
6340 sc->reset_noise_gain = tmp;
6341 sc->noise_gain = tmp + 1;
6345 DPRINTF(sc, IWN_DEBUG_RESET,
6346 "TLV type %d not handled\n", le16toh(tlv->type));
6349 next: /* TLV fields are 32-bit aligned. */
6350 ptr += (len + 3) & ~3;
6356 iwn_read_firmware(struct iwn_softc *sc)
6358 struct iwn_fw_info *fw = &sc->fw;
6363 memset(fw, 0, sizeof (*fw));
6365 /* Read firmware image from filesystem. */
6366 sc->fw_fp = firmware_get(sc->fwname);
6367 if (sc->fw_fp == NULL) {
6368 device_printf(sc->sc_dev, "%s: could not read firmware %s\n",
6369 __func__, sc->fwname);
6375 fw->size = sc->fw_fp->datasize;
6376 fw->data = (const uint8_t *)sc->fw_fp->data;
6377 if (fw->size < sizeof (uint32_t)) {
6378 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6379 __func__, fw->size);
6380 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6385 /* Retrieve text and data sections. */
6386 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */
6387 error = iwn_read_firmware_leg(sc, fw);
6389 error = iwn_read_firmware_tlv(sc, fw, 1);
6391 device_printf(sc->sc_dev,
6392 "%s: could not read firmware sections, error %d\n",
6394 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6399 /* Make sure text and data sections fit in hardware memory. */
6400 if (fw->main.textsz > sc->fw_text_maxsz ||
6401 fw->main.datasz > sc->fw_data_maxsz ||
6402 fw->init.textsz > sc->fw_text_maxsz ||
6403 fw->init.datasz > sc->fw_data_maxsz ||
6404 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ ||
6405 (fw->boot.textsz & 3) != 0) {
6406 device_printf(sc->sc_dev, "%s: firmware sections too large\n",
6408 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6413 /* We can proceed with loading the firmware. */
6418 iwn_clock_wait(struct iwn_softc *sc)
6422 /* Set "initialization complete" bit. */
6423 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
6425 /* Wait for clock stabilization. */
6426 for (ntries = 0; ntries < 2500; ntries++) {
6427 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY)
6431 device_printf(sc->sc_dev,
6432 "%s: timeout waiting for clock stabilization\n", __func__);
6437 iwn_apm_init(struct iwn_softc *sc)
6442 /* Disable L0s exit timer (NMI bug workaround). */
6443 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER);
6444 /* Don't wait for ICH L0s (ICH bug workaround). */
6445 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX);
6447 /* Set FH wait threshold to max (HW bug under stress workaround). */
6448 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000);
6450 /* Enable HAP INTA to move adapter from L1a to L0s. */
6451 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A);
6453 /* Retrieve PCIe Active State Power Management (ASPM). */
6454 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
6455 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
6456 if (reg & 0x02) /* L1 Entry enabled. */
6457 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
6459 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
6461 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
6462 sc->hw_type <= IWN_HW_REV_TYPE_1000)
6463 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT);
6465 /* Wait for clock stabilization before accessing prph. */
6466 if ((error = iwn_clock_wait(sc)) != 0)
6469 if ((error = iwn_nic_lock(sc)) != 0)
6471 if (sc->hw_type == IWN_HW_REV_TYPE_4965) {
6472 /* Enable DMA and BSM (Bootstrap State Machine). */
6473 iwn_prph_write(sc, IWN_APMG_CLK_EN,
6474 IWN_APMG_CLK_CTRL_DMA_CLK_RQT |
6475 IWN_APMG_CLK_CTRL_BSM_CLK_RQT);
6478 iwn_prph_write(sc, IWN_APMG_CLK_EN,
6479 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
6482 /* Disable L1-Active. */
6483 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS);
6490 iwn_apm_stop_master(struct iwn_softc *sc)
6494 /* Stop busmaster DMA activity. */
6495 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER);
6496 for (ntries = 0; ntries < 100; ntries++) {
6497 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED)
6501 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__);
6505 iwn_apm_stop(struct iwn_softc *sc)
6507 iwn_apm_stop_master(sc);
6509 /* Reset the entire device. */
6510 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW);
6512 /* Clear "initialization complete" bit. */
6513 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
6517 iwn4965_nic_config(struct iwn_softc *sc)
6519 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) {
6521 * I don't believe this to be correct but this is what the
6522 * vendor driver is doing. Probably the bits should not be
6523 * shifted in IWN_RFCFG_*.
6525 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6526 IWN_RFCFG_TYPE(sc->rfcfg) |
6527 IWN_RFCFG_STEP(sc->rfcfg) |
6528 IWN_RFCFG_DASH(sc->rfcfg));
6530 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6531 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
6536 iwn5000_nic_config(struct iwn_softc *sc)
6541 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) {
6542 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6543 IWN_RFCFG_TYPE(sc->rfcfg) |
6544 IWN_RFCFG_STEP(sc->rfcfg) |
6545 IWN_RFCFG_DASH(sc->rfcfg));
6547 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6548 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
6550 if ((error = iwn_nic_lock(sc)) != 0)
6552 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS);
6554 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
6556 * Select first Switching Voltage Regulator (1.32V) to
6557 * solve a stability issue related to noisy DC2DC line
6558 * in the silicon of 1000 Series.
6560 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
6561 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
6562 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
6563 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
6567 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) {
6568 /* Use internal power amplifier only. */
6569 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA);
6571 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 ||
6572 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) {
6573 /* Indicate that ROM calibration version is >=6. */
6574 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6);
6576 if (sc->hw_type == IWN_HW_REV_TYPE_6005)
6577 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2);
6582 * Take NIC ownership over Intel Active Management Technology (AMT).
6585 iwn_hw_prepare(struct iwn_softc *sc)
6589 /* Check if hardware is ready. */
6590 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
6591 for (ntries = 0; ntries < 5; ntries++) {
6592 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
6593 IWN_HW_IF_CONFIG_NIC_READY)
6598 /* Hardware not ready, force into ready state. */
6599 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE);
6600 for (ntries = 0; ntries < 15000; ntries++) {
6601 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) &
6602 IWN_HW_IF_CONFIG_PREPARE_DONE))
6606 if (ntries == 15000)
6609 /* Hardware should be ready now. */
6610 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
6611 for (ntries = 0; ntries < 5; ntries++) {
6612 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
6613 IWN_HW_IF_CONFIG_NIC_READY)
6621 iwn_hw_init(struct iwn_softc *sc)
6623 struct iwn_ops *ops = &sc->ops;
6624 int error, chnl, qid;
6626 /* Clear pending interrupts. */
6627 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6629 if ((error = iwn_apm_init(sc)) != 0) {
6630 device_printf(sc->sc_dev,
6631 "%s: could not power ON adapter, error %d\n", __func__,
6636 /* Select VMAIN power source. */
6637 if ((error = iwn_nic_lock(sc)) != 0)
6639 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK);
6642 /* Perform adapter-specific initialization. */
6643 if ((error = ops->nic_config(sc)) != 0)
6646 /* Initialize RX ring. */
6647 if ((error = iwn_nic_lock(sc)) != 0)
6649 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
6650 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0);
6651 /* Set physical address of RX ring (256-byte aligned). */
6652 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8);
6653 /* Set physical address of RX status (16-byte aligned). */
6654 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4);
6656 IWN_WRITE(sc, IWN_FH_RX_CONFIG,
6657 IWN_FH_RX_CONFIG_ENA |
6658 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */
6659 IWN_FH_RX_CONFIG_IRQ_DST_HOST |
6660 IWN_FH_RX_CONFIG_SINGLE_FRAME |
6661 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) |
6662 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG));
6664 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7);
6666 if ((error = iwn_nic_lock(sc)) != 0)
6669 /* Initialize TX scheduler. */
6670 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
6672 /* Set physical address of "keep warm" page (16-byte aligned). */
6673 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4);
6675 /* Initialize TX rings. */
6676 for (qid = 0; qid < sc->ntxqs; qid++) {
6677 struct iwn_tx_ring *txq = &sc->txq[qid];
6679 /* Set physical address of TX ring (256-byte aligned). */
6680 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid),
6681 txq->desc_dma.paddr >> 8);
6685 /* Enable DMA channels. */
6686 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
6687 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
6688 IWN_FH_TX_CONFIG_DMA_ENA |
6689 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA);
6692 /* Clear "radio off" and "commands blocked" bits. */
6693 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6694 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED);
6696 /* Clear pending interrupts. */
6697 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6698 /* Enable interrupt coalescing. */
6699 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8);
6700 /* Enable interrupts. */
6701 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6703 /* _Really_ make sure "radio off" bit is cleared! */
6704 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6705 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6707 /* Enable shadow registers. */
6708 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
6709 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff);
6711 if ((error = ops->load_firmware(sc)) != 0) {
6712 device_printf(sc->sc_dev,
6713 "%s: could not load firmware, error %d\n", __func__,
6717 /* Wait at most one second for firmware alive notification. */
6718 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
6719 device_printf(sc->sc_dev,
6720 "%s: timeout waiting for adapter to initialize, error %d\n",
6724 /* Do post-firmware initialization. */
6725 return ops->post_alive(sc);
6729 iwn_hw_stop(struct iwn_softc *sc)
6731 int chnl, qid, ntries;
6733 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO);
6735 /* Disable interrupts. */
6736 IWN_WRITE(sc, IWN_INT_MASK, 0);
6737 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6738 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff);
6739 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6741 /* Make sure we no longer hold the NIC lock. */
6744 /* Stop TX scheduler. */
6745 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
6747 /* Stop all DMA channels. */
6748 if (iwn_nic_lock(sc) == 0) {
6749 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
6750 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0);
6751 for (ntries = 0; ntries < 200; ntries++) {
6752 if (IWN_READ(sc, IWN_FH_TX_STATUS) &
6753 IWN_FH_TX_STATUS_IDLE(chnl))
6762 iwn_reset_rx_ring(sc, &sc->rxq);
6764 /* Reset all TX rings. */
6765 for (qid = 0; qid < sc->ntxqs; qid++)
6766 iwn_reset_tx_ring(sc, &sc->txq[qid]);
6768 if (iwn_nic_lock(sc) == 0) {
6769 iwn_prph_write(sc, IWN_APMG_CLK_DIS,
6770 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
6774 /* Power OFF adapter. */
6779 iwn_radio_on(void *arg0, int pending)
6781 struct iwn_softc *sc = arg0;
6782 struct ifnet *ifp = sc->sc_ifp;
6783 struct ieee80211com *ic = ifp->if_l2com;
6784 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6788 ieee80211_init(vap);
6793 iwn_radio_off(void *arg0, int pending)
6795 struct iwn_softc *sc = arg0;
6796 struct ifnet *ifp = sc->sc_ifp;
6797 struct ieee80211com *ic = ifp->if_l2com;
6798 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6802 ieee80211_stop(vap);
6804 /* Enable interrupts to get RF toggle notification. */
6806 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6807 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6812 iwn_init_locked(struct iwn_softc *sc)
6814 struct ifnet *ifp = sc->sc_ifp;
6817 IWN_LOCK_ASSERT(sc);
6819 if ((error = iwn_hw_prepare(sc)) != 0) {
6820 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n",
6825 /* Initialize interrupt mask to default value. */
6826 sc->int_mask = IWN_INT_MASK_DEF;
6827 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6829 /* Check that the radio is not disabled by hardware switch. */
6830 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) {
6831 device_printf(sc->sc_dev,
6832 "radio is disabled by hardware switch\n");
6833 /* Enable interrupts to get RF toggle notifications. */
6834 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6835 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6839 /* Read firmware images from the filesystem. */
6840 if ((error = iwn_read_firmware(sc)) != 0) {
6841 device_printf(sc->sc_dev,
6842 "%s: could not read firmware, error %d\n", __func__,
6847 /* Initialize hardware and upload firmware. */
6848 error = iwn_hw_init(sc);
6849 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6852 device_printf(sc->sc_dev,
6853 "%s: could not initialize hardware, error %d\n", __func__,
6858 /* Configure adapter now that it is ready. */
6859 if ((error = iwn_config(sc)) != 0) {
6860 device_printf(sc->sc_dev,
6861 "%s: could not configure device, error %d\n", __func__,
6866 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6867 ifp->if_drv_flags |= IFF_DRV_RUNNING;
6869 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
6872 fail: iwn_stop_locked(sc);
6878 struct iwn_softc *sc = arg;
6879 struct ifnet *ifp = sc->sc_ifp;
6880 struct ieee80211com *ic = ifp->if_l2com;
6883 iwn_init_locked(sc);
6886 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6887 ieee80211_start_all(ic);
6891 iwn_stop_locked(struct iwn_softc *sc)
6893 struct ifnet *ifp = sc->sc_ifp;
6895 IWN_LOCK_ASSERT(sc);
6897 sc->sc_tx_timer = 0;
6898 callout_stop(&sc->watchdog_to);
6899 callout_stop(&sc->calib_to);
6900 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
6902 /* Power OFF hardware. */
6907 iwn_stop(struct iwn_softc *sc)
6910 iwn_stop_locked(sc);
6915 * Callback from net80211 to start a scan.
6918 iwn_scan_start(struct ieee80211com *ic)
6920 struct ifnet *ifp = ic->ic_ifp;
6921 struct iwn_softc *sc = ifp->if_softc;
6924 /* make the link LED blink while we're scanning */
6925 iwn_set_led(sc, IWN_LED_LINK, 20, 2);
6930 * Callback from net80211 to terminate a scan.
6933 iwn_scan_end(struct ieee80211com *ic)
6935 struct ifnet *ifp = ic->ic_ifp;
6936 struct iwn_softc *sc = ifp->if_softc;
6937 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6940 if (vap->iv_state == IEEE80211_S_RUN) {
6941 /* Set link LED to ON status if we are associated */
6942 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
6948 * Callback from net80211 to force a channel change.
6951 iwn_set_channel(struct ieee80211com *ic)
6953 const struct ieee80211_channel *c = ic->ic_curchan;
6954 struct ifnet *ifp = ic->ic_ifp;
6955 struct iwn_softc *sc = ifp->if_softc;
6959 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq);
6960 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags);
6961 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq);
6962 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags);
6965 * Only need to set the channel in Monitor mode. AP scanning and auth
6966 * are already taken care of by their respective firmware commands.
6968 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
6969 error = iwn_config(sc);
6971 device_printf(sc->sc_dev,
6972 "%s: error %d settting channel\n", __func__, error);
6978 * Callback from net80211 to start scanning of the current channel.
6981 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell)
6983 struct ieee80211vap *vap = ss->ss_vap;
6984 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6988 error = iwn_scan(sc);
6991 ieee80211_cancel_scan(vap);
6995 * Callback from net80211 to handle the minimum dwell time being met.
6996 * The intent is to terminate the scan but we just let the firmware
6997 * notify us when it's finished as we have no safe way to abort it.
7000 iwn_scan_mindwell(struct ieee80211_scan_state *ss)
7002 /* NB: don't try to abort scan; wait for firmware to finish */
7006 iwn_hw_reset(void *arg0, int pending)
7008 struct iwn_softc *sc = arg0;
7009 struct ifnet *ifp = sc->sc_ifp;
7010 struct ieee80211com *ic = ifp->if_l2com;
7014 ieee80211_notify_radio(ic, 1);