2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44 * are three supported methods for data transfer between host and
45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46 * Propulsion Technology (tm) DMA. The latter mechanism is a form
47 * of double buffer DMA where the packet data is copied to a
48 * pre-allocated DMA buffer who's physical address has been loaded
49 * into a table at device initialization time. The rationale is that
50 * the virtual to physical address translation needed for normal
51 * scatter/gather DMA is more expensive than the data copy needed
52 * for double buffering. This may be true in Windows NT and the like,
53 * but it isn't true for us, at least on the x86 arch. This driver
54 * uses the scatter/gather I/O method for both TX and RX.
56 * The LXT1001 only supports TCP/IP checksum offload on receive.
57 * Also, the VLAN tagging is done using a 16-entry table which allows
58 * the chip to perform hardware filtering based on VLAN tags. Sadly,
59 * our vlan support doesn't currently play well with this kind of
63 * - Jeff James at Intel, for arranging to have the LXT1001 manual
64 * released (at long last)
65 * - Beny Chen at D-Link, for actually sending it to me
66 * - Brad Short and Keith Alexis at SMC, for sending me sample
67 * SMC9462SX and SMC9462TX adapters for testing
68 * - Paul Saab at Y!, for not killing me (though it remains to be seen
69 * if in fact he did me much of a favor)
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/sockio.h>
76 #include <sys/malloc.h>
77 #include <sys/kernel.h>
78 #include <sys/module.h>
79 #include <sys/socket.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_dl.h>
85 #include <net/if_media.h>
86 #include <net/if_types.h>
90 #include <vm/vm.h> /* for vtophys */
91 #include <vm/pmap.h> /* for vtophys */
92 #include <machine/bus.h>
93 #include <machine/resource.h>
97 #include <dev/mii/mii.h>
98 #include <dev/mii/miivar.h>
100 #include <dev/pci/pcireg.h>
101 #include <dev/pci/pcivar.h>
103 #define LGE_USEIOSPACE
105 #include <dev/lge/if_lgereg.h>
107 /* "device miibus" required. See GENERIC if you get errors here. */
108 #include "miibus_if.h"
111 * Various supported device vendors/types and their names.
113 static struct lge_type lge_devs[] = {
114 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
118 static int lge_probe(device_t);
119 static int lge_attach(device_t);
120 static int lge_detach(device_t);
122 static int lge_alloc_jumbo_mem(struct lge_softc *);
123 static void lge_free_jumbo_mem(struct lge_softc *);
124 static void *lge_jalloc(struct lge_softc *);
125 static void lge_jfree(void *, void *);
127 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
128 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
129 static void lge_rxeof(struct lge_softc *, int);
130 static void lge_rxeoc(struct lge_softc *);
131 static void lge_txeof(struct lge_softc *);
132 static void lge_intr(void *);
133 static void lge_tick(void *);
134 static void lge_start(struct ifnet *);
135 static void lge_start_locked(struct ifnet *);
136 static int lge_ioctl(struct ifnet *, u_long, caddr_t);
137 static void lge_init(void *);
138 static void lge_init_locked(struct lge_softc *);
139 static void lge_stop(struct lge_softc *);
140 static void lge_watchdog(struct lge_softc *);
141 static int lge_shutdown(device_t);
142 static int lge_ifmedia_upd(struct ifnet *);
143 static void lge_ifmedia_upd_locked(struct ifnet *);
144 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
146 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
147 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
149 static int lge_miibus_readreg(device_t, int, int);
150 static int lge_miibus_writereg(device_t, int, int, int);
151 static void lge_miibus_statchg(device_t);
153 static void lge_setmulti(struct lge_softc *);
154 static void lge_reset(struct lge_softc *);
155 static int lge_list_rx_init(struct lge_softc *);
156 static int lge_list_tx_init(struct lge_softc *);
158 #ifdef LGE_USEIOSPACE
159 #define LGE_RES SYS_RES_IOPORT
160 #define LGE_RID LGE_PCI_LOIO
162 #define LGE_RES SYS_RES_MEMORY
163 #define LGE_RID LGE_PCI_LOMEM
166 static device_method_t lge_methods[] = {
167 /* Device interface */
168 DEVMETHOD(device_probe, lge_probe),
169 DEVMETHOD(device_attach, lge_attach),
170 DEVMETHOD(device_detach, lge_detach),
171 DEVMETHOD(device_shutdown, lge_shutdown),
174 DEVMETHOD(bus_print_child, bus_generic_print_child),
175 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
178 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
179 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
180 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
185 static driver_t lge_driver = {
188 sizeof(struct lge_softc)
191 static devclass_t lge_devclass;
193 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0);
194 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
195 MODULE_DEPEND(lge, pci, 1, 1, 1);
196 MODULE_DEPEND(lge, ether, 1, 1, 1);
197 MODULE_DEPEND(lge, miibus, 1, 1, 1);
199 #define LGE_SETBIT(sc, reg, x) \
200 CSR_WRITE_4(sc, reg, \
201 CSR_READ_4(sc, reg) | (x))
203 #define LGE_CLRBIT(sc, reg, x) \
204 CSR_WRITE_4(sc, reg, \
205 CSR_READ_4(sc, reg) & ~(x))
208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
211 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
214 * Read a word of data stored in the EEPROM at address 'addr.'
217 lge_eeprom_getword(sc, addr, dest)
218 struct lge_softc *sc;
225 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
226 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
228 for (i = 0; i < LGE_TIMEOUT; i++)
229 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
232 if (i == LGE_TIMEOUT) {
233 device_printf(sc->lge_dev, "EEPROM read timed out\n");
237 val = CSR_READ_4(sc, LGE_EEDATA);
240 *dest = (val >> 16) & 0xFFFF;
242 *dest = val & 0xFFFF;
248 * Read a sequence of words from the EEPROM.
251 lge_read_eeprom(sc, dest, off, cnt, swap)
252 struct lge_softc *sc;
259 u_int16_t word = 0, *ptr;
261 for (i = 0; i < cnt; i++) {
262 lge_eeprom_getword(sc, off + i, &word);
263 ptr = (u_int16_t *)(dest + (i * 2));
274 lge_miibus_readreg(dev, phy, reg)
278 struct lge_softc *sc;
281 sc = device_get_softc(dev);
284 * If we have a non-PCS PHY, pretend that the internal
285 * autoneg stuff at PHY address 0 isn't there so that
286 * the miibus code will find only the GMII PHY.
288 if (sc->lge_pcs == 0 && phy == 0)
291 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
293 for (i = 0; i < LGE_TIMEOUT; i++)
294 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
297 if (i == LGE_TIMEOUT) {
298 device_printf(sc->lge_dev, "PHY read timed out\n");
302 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
306 lge_miibus_writereg(dev, phy, reg, data)
310 struct lge_softc *sc;
313 sc = device_get_softc(dev);
315 CSR_WRITE_4(sc, LGE_GMIICTL,
316 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
318 for (i = 0; i < LGE_TIMEOUT; i++)
319 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
322 if (i == LGE_TIMEOUT) {
323 device_printf(sc->lge_dev, "PHY write timed out\n");
331 lge_miibus_statchg(dev)
334 struct lge_softc *sc;
335 struct mii_data *mii;
337 sc = device_get_softc(dev);
338 mii = device_get_softc(sc->lge_miibus);
340 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
341 switch (IFM_SUBTYPE(mii->mii_media_active)) {
344 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
347 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
350 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
354 * Choose something, even if it's wrong. Clearing
355 * all the bits will hose autoneg on the internal
358 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
362 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
363 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
365 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
373 struct lge_softc *sc;
376 struct ifmultiaddr *ifma;
377 u_int32_t h = 0, hashes[2] = { 0, 0 };
382 /* Make sure multicast hash table is enabled. */
383 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
385 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
386 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
387 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
391 /* first, zot all the existing hash bits */
392 CSR_WRITE_4(sc, LGE_MAR0, 0);
393 CSR_WRITE_4(sc, LGE_MAR1, 0);
395 /* now program new ones */
397 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
398 if (ifma->ifma_addr->sa_family != AF_LINK)
400 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
401 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
403 hashes[0] |= (1 << h);
405 hashes[1] |= (1 << (h - 32));
407 if_maddr_runlock(ifp);
409 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
410 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
417 struct lge_softc *sc;
421 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
423 for (i = 0; i < LGE_TIMEOUT; i++) {
424 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
428 if (i == LGE_TIMEOUT)
429 device_printf(sc->lge_dev, "reset never completed\n");
431 /* Wait a little while for the chip to get its brains in order. */
438 * Probe for a Level 1 chip. Check the PCI vendor and device
439 * IDs against our list and return a device name if we find a match.
449 while(t->lge_name != NULL) {
450 if ((pci_get_vendor(dev) == t->lge_vid) &&
451 (pci_get_device(dev) == t->lge_did)) {
452 device_set_desc(dev, t->lge_name);
453 return(BUS_PROBE_DEFAULT);
462 * Attach the interface. Allocate softc structures, do ifmedia
463 * setup and ethernet/BPF attach.
469 u_char eaddr[ETHER_ADDR_LEN];
470 struct lge_softc *sc;
471 struct ifnet *ifp = NULL;
474 sc = device_get_softc(dev);
477 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
479 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0);
482 * Map control/status registers.
484 pci_enable_busmaster(dev);
487 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
489 if (sc->lge_res == NULL) {
490 device_printf(dev, "couldn't map ports/memory\n");
495 sc->lge_btag = rman_get_bustag(sc->lge_res);
496 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
498 /* Allocate interrupt */
500 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
501 RF_SHAREABLE | RF_ACTIVE);
503 if (sc->lge_irq == NULL) {
504 device_printf(dev, "couldn't map interrupt\n");
509 /* Reset the adapter. */
513 * Get station address from the EEPROM.
515 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
516 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
517 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
519 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
520 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
522 if (sc->lge_ldata == NULL) {
523 device_printf(dev, "no memory for list buffers!\n");
528 /* Try to allocate memory for jumbo buffers. */
529 if (lge_alloc_jumbo_mem(sc)) {
530 device_printf(dev, "jumbo buffer allocation failed\n");
535 ifp = sc->lge_ifp = if_alloc(IFT_ETHER);
537 device_printf(dev, "can not if_alloc()\n");
542 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
543 ifp->if_mtu = ETHERMTU;
544 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
545 ifp->if_ioctl = lge_ioctl;
546 ifp->if_start = lge_start;
547 ifp->if_init = lge_init;
548 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
549 ifp->if_capabilities = IFCAP_RXCSUM;
550 ifp->if_capenable = ifp->if_capabilities;
552 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
560 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd,
561 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
563 device_printf(dev, "attaching PHYs failed\n");
568 * Call MI attach routine.
570 ether_ifattach(ifp, eaddr);
572 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE,
573 NULL, lge_intr, sc, &sc->lge_intrhand);
577 device_printf(dev, "couldn't set up irq\n");
583 lge_free_jumbo_mem(sc);
585 contigfree(sc->lge_ldata,
586 sizeof(struct lge_list_data), M_DEVBUF);
590 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
592 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
593 mtx_destroy(&sc->lge_mtx);
601 struct lge_softc *sc;
604 sc = device_get_softc(dev);
611 callout_drain(&sc->lge_stat_callout);
614 bus_generic_detach(dev);
615 device_delete_child(dev, sc->lge_miibus);
617 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
618 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
619 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
621 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
623 lge_free_jumbo_mem(sc);
624 mtx_destroy(&sc->lge_mtx);
630 * Initialize the transmit descriptors.
634 struct lge_softc *sc;
636 struct lge_list_data *ld;
637 struct lge_ring_data *cd;
642 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
643 ld->lge_tx_list[i].lge_mbuf = NULL;
644 ld->lge_tx_list[i].lge_ctl = 0;
647 cd->lge_tx_prod = cd->lge_tx_cons = 0;
654 * Initialize the RX descriptors and allocate mbufs for them. Note that
655 * we arralge the descriptors in a closed ring, so that the last descriptor
656 * points back to the first.
660 struct lge_softc *sc;
662 struct lge_list_data *ld;
663 struct lge_ring_data *cd;
669 cd->lge_rx_prod = cd->lge_rx_cons = 0;
671 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
673 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
674 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
676 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
680 /* Clear possible 'rx command queue empty' interrupt. */
681 CSR_READ_4(sc, LGE_ISR);
687 * Initialize an RX descriptor and attach an MBUF cluster.
691 struct lge_softc *sc;
692 struct lge_rx_desc *c;
695 struct mbuf *m_new = NULL;
699 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
701 device_printf(sc->lge_dev, "no memory for rx list "
702 "-- packet dropped!\n");
706 /* Allocate the jumbo buffer */
707 buf = lge_jalloc(sc);
710 device_printf(sc->lge_dev, "jumbo allocation failed "
711 "-- packet dropped!\n");
716 /* Attach the buffer to the mbuf */
717 m_new->m_data = (void *)buf;
718 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
719 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
720 buf, (struct lge_softc *)sc, 0, EXT_NET_DRV);
723 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
724 m_new->m_data = m_new->m_ext.ext_buf;
728 * Adjust alignment so packet payload begins on a
729 * longword boundary. Mandatory for Alpha, useful on
732 m_adj(m_new, ETHER_ALIGN);
735 c->lge_fragptr_hi = 0;
736 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
737 c->lge_fraglen = m_new->m_len;
738 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
742 * Put this buffer in the RX command FIFO. To do this,
743 * we just write the physical address of the descriptor
744 * into the RX descriptor address registers. Note that
745 * there are two registers, one high DWORD and one low
746 * DWORD, which lets us specify a 64-bit address if
747 * desired. We only use a 32-bit address for now.
748 * Writing to the low DWORD register is what actually
749 * causes the command to be issued, so we do that
752 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
753 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
759 lge_alloc_jumbo_mem(sc)
760 struct lge_softc *sc;
764 struct lge_jpool_entry *entry;
766 /* Grab a big chunk o' storage. */
767 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
768 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
770 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
771 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n");
775 SLIST_INIT(&sc->lge_jfree_listhead);
776 SLIST_INIT(&sc->lge_jinuse_listhead);
779 * Now divide it up into 9K pieces and save the addresses
782 ptr = sc->lge_cdata.lge_jumbo_buf;
783 for (i = 0; i < LGE_JSLOTS; i++) {
784 sc->lge_cdata.lge_jslots[i] = ptr;
786 entry = malloc(sizeof(struct lge_jpool_entry),
789 device_printf(sc->lge_dev, "no memory for jumbo "
794 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
795 entry, jpool_entries);
802 lge_free_jumbo_mem(sc)
803 struct lge_softc *sc;
805 struct lge_jpool_entry *entry;
807 if (sc->lge_cdata.lge_jumbo_buf == NULL)
810 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) {
811 device_printf(sc->lge_dev,
812 "asked to free buffer that is in use!\n");
813 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
814 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry,
817 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) {
818 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
819 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
820 free(entry, M_DEVBUF);
823 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
829 * Allocate a jumbo buffer.
833 struct lge_softc *sc;
835 struct lge_jpool_entry *entry;
837 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
841 device_printf(sc->lge_dev, "no free jumbo buffers\n");
846 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
847 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
848 return(sc->lge_cdata.lge_jslots[entry->slot]);
852 * Release a jumbo buffer.
859 struct lge_softc *sc;
861 struct lge_jpool_entry *entry;
863 /* Extract the softc struct pointer. */
867 panic("lge_jfree: can't find softc pointer!");
869 /* calculate the slot this buffer belongs to */
870 i = ((vm_offset_t)buf
871 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
873 if ((i < 0) || (i >= LGE_JSLOTS))
874 panic("lge_jfree: asked to free buffer that we don't manage!");
876 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
878 panic("lge_jfree: buffer not in use!");
880 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
881 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
887 * A frame has been uploaded: pass the resulting mbuf chain up to
888 * the higher level protocols.
892 struct lge_softc *sc;
897 struct lge_rx_desc *cur_rx;
898 int c, i, total_len = 0;
899 u_int32_t rxsts, rxctl;
903 /* Find out how many frames were processed. */
905 i = sc->lge_cdata.lge_rx_cons;
909 struct mbuf *m0 = NULL;
911 cur_rx = &sc->lge_ldata->lge_rx_list[i];
912 rxctl = cur_rx->lge_ctl;
913 rxsts = cur_rx->lge_sts;
914 m = cur_rx->lge_mbuf;
915 cur_rx->lge_mbuf = NULL;
916 total_len = LGE_RXBYTES(cur_rx);
917 LGE_INC(i, LGE_RX_LIST_CNT);
921 * If an error occurs, update stats, clear the
922 * status word and leave the mbuf cluster in place:
923 * it should simply get re-used next time this descriptor
924 * comes up in the ring.
926 if (rxctl & LGE_RXCTL_ERRMASK) {
928 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
932 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
933 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
935 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
937 device_printf(sc->lge_dev, "no receive buffers "
938 "available -- packet dropped!\n");
944 m->m_pkthdr.rcvif = ifp;
945 m->m_pkthdr.len = m->m_len = total_len;
950 /* Do IP checksum checking. */
951 if (rxsts & LGE_RXSTS_ISIP)
952 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
953 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
954 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
955 if ((rxsts & LGE_RXSTS_ISTCP &&
956 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
957 (rxsts & LGE_RXSTS_ISUDP &&
958 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
959 m->m_pkthdr.csum_flags |=
960 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
961 m->m_pkthdr.csum_data = 0xffff;
965 (*ifp->if_input)(ifp, m);
969 sc->lge_cdata.lge_rx_cons = i;
976 struct lge_softc *sc;
981 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
987 * A frame was downloaded to the chip. It's safe for us to clean up
993 struct lge_softc *sc;
995 struct lge_tx_desc *cur_tx = NULL;
997 u_int32_t idx, txdone;
1001 /* Clear the timeout timer. */
1005 * Go through our tx list and free mbufs for those
1006 * frames that have been transmitted.
1008 idx = sc->lge_cdata.lge_tx_cons;
1009 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1011 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1012 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1015 if (cur_tx->lge_mbuf != NULL) {
1016 m_freem(cur_tx->lge_mbuf);
1017 cur_tx->lge_mbuf = NULL;
1019 cur_tx->lge_ctl = 0;
1022 LGE_INC(idx, LGE_TX_LIST_CNT);
1026 sc->lge_cdata.lge_tx_cons = idx;
1029 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1038 struct lge_softc *sc;
1039 struct mii_data *mii;
1044 LGE_LOCK_ASSERT(sc);
1046 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1047 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1048 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1049 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1051 if (!sc->lge_link) {
1052 mii = device_get_softc(sc->lge_miibus);
1054 if (mii->mii_media_status & IFM_ACTIVE &&
1055 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1058 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1059 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T))
1060 device_printf(sc->lge_dev, "gigabit link up\n");
1061 if (ifp->if_snd.ifq_head != NULL)
1062 lge_start_locked(ifp);
1066 if (sc->lge_timer != 0 && --sc->lge_timer == 0)
1068 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1077 struct lge_softc *sc;
1085 /* Supress unwanted interrupts */
1086 if (!(ifp->if_flags & IFF_UP)) {
1094 * Reading the ISR register clears all interrupts, and
1095 * clears the 'interrupts enabled' bit in the IMR
1098 status = CSR_READ_4(sc, LGE_ISR);
1100 if ((status & LGE_INTRS) == 0)
1103 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1106 if (status & LGE_ISR_RXDMA_DONE)
1107 lge_rxeof(sc, LGE_RX_DMACNT(status));
1109 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1112 if (status & LGE_ISR_PHY_INTR) {
1114 callout_stop(&sc->lge_stat_callout);
1119 /* Re-enable interrupts. */
1120 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1122 if (ifp->if_snd.ifq_head != NULL)
1123 lge_start_locked(ifp);
1130 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1131 * pointers to the fragment pointers.
1134 lge_encap(sc, m_head, txidx)
1135 struct lge_softc *sc;
1136 struct mbuf *m_head;
1139 struct lge_frag *f = NULL;
1140 struct lge_tx_desc *cur_tx;
1142 int frag = 0, tot_len = 0;
1145 * Start packing the mbufs in this chain into
1146 * the fragment pointers. Stop when we run out
1147 * of fragments or hit the end of the mbuf chain.
1150 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1153 for (m = m_head; m != NULL; m = m->m_next) {
1154 if (m->m_len != 0) {
1155 tot_len += m->m_len;
1156 f = &cur_tx->lge_frags[frag];
1157 f->lge_fraglen = m->m_len;
1158 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1159 f->lge_fragptr_hi = 0;
1167 cur_tx->lge_mbuf = m_head;
1168 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1169 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1171 /* Queue for transmit */
1172 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1178 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1179 * to the mbuf data regions directly in the transmit lists. We also save a
1180 * copy of the pointers since the transmit list fragment pointers are
1181 * physical addresses.
1188 struct lge_softc *sc;
1192 lge_start_locked(ifp);
1197 lge_start_locked(ifp)
1200 struct lge_softc *sc;
1201 struct mbuf *m_head = NULL;
1209 idx = sc->lge_cdata.lge_tx_prod;
1211 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1214 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1215 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1218 IF_DEQUEUE(&ifp->if_snd, m_head);
1222 if (lge_encap(sc, m_head, &idx)) {
1223 IF_PREPEND(&ifp->if_snd, m_head);
1224 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1229 * If there's a BPF listener, bounce a copy of this frame
1232 BPF_MTAP(ifp, m_head);
1235 sc->lge_cdata.lge_tx_prod = idx;
1238 * Set a timeout in case the chip goes out to lunch.
1249 struct lge_softc *sc = xsc;
1252 lge_init_locked(sc);
1258 struct lge_softc *sc;
1260 struct ifnet *ifp = sc->lge_ifp;
1262 LGE_LOCK_ASSERT(sc);
1263 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1267 * Cancel pending I/O and free all RX/TX buffers.
1272 /* Set MAC address */
1273 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0]));
1274 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4]));
1276 /* Init circular RX list. */
1277 if (lge_list_rx_init(sc) == ENOBUFS) {
1278 device_printf(sc->lge_dev, "initialization failed: no "
1279 "memory for rx buffers\n");
1285 * Init tx descriptors.
1287 lge_list_tx_init(sc);
1289 /* Set initial value for MODE1 register. */
1290 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1291 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1292 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1293 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1295 /* If we want promiscuous mode, set the allframes bit. */
1296 if (ifp->if_flags & IFF_PROMISC) {
1297 CSR_WRITE_4(sc, LGE_MODE1,
1298 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1300 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1304 * Set the capture broadcast bit to capture broadcast frames.
1306 if (ifp->if_flags & IFF_BROADCAST) {
1307 CSR_WRITE_4(sc, LGE_MODE1,
1308 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1313 /* Packet padding workaround? */
1314 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1316 /* No error frames */
1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1319 /* Receive large frames */
1320 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1322 /* Workaround: disable RX/TX flow control */
1323 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1324 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1326 /* Make sure to strip CRC from received frames */
1327 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1329 /* Turn off magic packet mode */
1330 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1332 /* Turn off all VLAN stuff */
1333 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1334 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1336 /* Workarond: FIFO overflow */
1337 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1338 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1341 * Load the multicast filter.
1346 * Enable hardware checksum validation for all received IPv4
1347 * packets, do not reject packets with bad checksums.
1349 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1350 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1351 LGE_MODE2_RX_ERRCSUM);
1354 * Enable the delivery of PHY interrupts based on
1355 * link/speed/duplex status chalges.
1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1359 /* Enable receiver and transmitter. */
1360 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1361 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1363 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1364 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1367 * Enable interrupts.
1369 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1370 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1372 lge_ifmedia_upd_locked(ifp);
1374 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1375 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1377 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1383 * Set media options.
1386 lge_ifmedia_upd(ifp)
1389 struct lge_softc *sc;
1393 lge_ifmedia_upd_locked(ifp);
1400 lge_ifmedia_upd_locked(ifp)
1403 struct lge_softc *sc;
1404 struct mii_data *mii;
1405 struct mii_softc *miisc;
1409 LGE_LOCK_ASSERT(sc);
1410 mii = device_get_softc(sc->lge_miibus);
1412 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1418 * Report current media status.
1421 lge_ifmedia_sts(ifp, ifmr)
1423 struct ifmediareq *ifmr;
1425 struct lge_softc *sc;
1426 struct mii_data *mii;
1431 mii = device_get_softc(sc->lge_miibus);
1434 ifmr->ifm_active = mii->mii_media_active;
1435 ifmr->ifm_status = mii->mii_media_status;
1441 lge_ioctl(ifp, command, data)
1446 struct lge_softc *sc = ifp->if_softc;
1447 struct ifreq *ifr = (struct ifreq *) data;
1448 struct mii_data *mii;
1454 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1457 ifp->if_mtu = ifr->ifr_mtu;
1462 if (ifp->if_flags & IFF_UP) {
1463 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1464 ifp->if_flags & IFF_PROMISC &&
1465 !(sc->lge_if_flags & IFF_PROMISC)) {
1466 CSR_WRITE_4(sc, LGE_MODE1,
1467 LGE_MODE1_SETRST_CTL1|
1468 LGE_MODE1_RX_PROMISC);
1469 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1470 !(ifp->if_flags & IFF_PROMISC) &&
1471 sc->lge_if_flags & IFF_PROMISC) {
1472 CSR_WRITE_4(sc, LGE_MODE1,
1473 LGE_MODE1_RX_PROMISC);
1475 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1476 lge_init_locked(sc);
1479 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1482 sc->lge_if_flags = ifp->if_flags;
1495 mii = device_get_softc(sc->lge_miibus);
1496 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1499 error = ether_ioctl(ifp, command, data);
1508 struct lge_softc *sc;
1512 LGE_LOCK_ASSERT(sc);
1516 if_printf(ifp, "watchdog timeout\n");
1520 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1521 lge_init_locked(sc);
1523 if (ifp->if_snd.ifq_head != NULL)
1524 lge_start_locked(ifp);
1528 * Stop the adapter and free any mbufs allocated to the
1533 struct lge_softc *sc;
1538 LGE_LOCK_ASSERT(sc);
1541 callout_stop(&sc->lge_stat_callout);
1542 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1544 /* Disable receiver and transmitter. */
1545 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1549 * Free data in the RX lists.
1551 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1552 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1553 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1554 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1557 bzero((char *)&sc->lge_ldata->lge_rx_list,
1558 sizeof(sc->lge_ldata->lge_rx_list));
1561 * Free the TX list buffers.
1563 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1564 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1565 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1566 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1570 bzero((char *)&sc->lge_ldata->lge_tx_list,
1571 sizeof(sc->lge_ldata->lge_tx_list));
1573 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1579 * Stop all chip I/O so that the kernel's probe routines don't
1580 * get confused by errant DMAs when rebooting.
1586 struct lge_softc *sc;
1588 sc = device_get_softc(dev);