2 * Copyright (c) 2006 IronPort Systems
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Copyright (c) 2007 LSI Corp.
28 * Copyright (c) 2007 Rajesh Prabhakaran.
29 * All rights reserved.
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
34 * 1. Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * 2. Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in the
38 * documentation and/or other materials provided with the distribution.
40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 #include <sys/cdefs.h>
57 __FBSDID("$FreeBSD$");
60 * MegaRAID SAS MFI firmware definitions
62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely
63 * new firmware interface from the old AMI MegaRAID one, and there is no
64 * reason why this interface should be limited to just SAS. In any case, LSI
65 * seems to also call this interface 'MFI', so that will be used here.
69 * Start with the register set. All registers are 32 bits wide.
70 * The usual Intel IOP style setup.
72 #define MFI_IMSG0 0x10 /* Inbound message 0 */
73 #define MFI_IMSG1 0x14 /* Inbound message 1 */
74 #define MFI_OMSG0 0x18 /* Outbound message 0 */
75 #define MFI_OMSG1 0x1c /* Outbound message 1 */
76 #define MFI_IDB 0x20 /* Inbound doorbell */
77 #define MFI_ISTS 0x24 /* Inbound interrupt status */
78 #define MFI_IMSK 0x28 /* Inbound interrupt mask */
79 #define MFI_ODB 0x2c /* Outbound doorbell */
80 #define MFI_OSTS 0x30 /* Outbound interrupt status */
81 #define MFI_OMSK 0x34 /* Outbound interrupt mask */
82 #define MFI_IQP 0x40 /* Inbound queue port */
83 #define MFI_OQP 0x44 /* Outbound queue port */
86 * 1078 specific related register
88 #define MFI_ODR0 0x9c /* outbound doorbell register0 */
89 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */
90 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */
91 #define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */
92 #define MFI_RMI 0x2 /* reply message interrupt */
93 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */
94 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */
97 * GEN2 specific changes
99 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */
100 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */
102 /* Bits for MFI_OSTS */
103 #define MFI_OSTS_INTR_VALID 0x00000002
106 * Firmware state values. Found in OMSG0 during initialization.
108 #define MFI_FWSTATE_MASK 0xf0000000
109 #define MFI_FWSTATE_UNDEFINED 0x00000000
110 #define MFI_FWSTATE_BB_INIT 0x10000000
111 #define MFI_FWSTATE_FW_INIT 0x40000000
112 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000
113 #define MFI_FWSTATE_FW_INIT_2 0x70000000
114 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000
115 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000
116 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000
117 #define MFI_FWSTATE_READY 0xb0000000
118 #define MFI_FWSTATE_OPERATIONAL 0xc0000000
119 #define MFI_FWSTATE_FAULT 0xf0000000
120 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000
121 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff
124 * Control bits to drive the card to ready state. These go into the IDB
127 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */
128 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */
129 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */
130 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
131 #define MFI_FWINIT_HOTPLUG 0x00000010
146 /* Direct commands */
148 MFI_DCMD_CTRL_GETINFO = 0x01010000,
149 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201,
150 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202,
151 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000,
152 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000,
153 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100,
154 MFI_DCMD_CTRL_EVENT_GET = 0x01040300,
155 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500,
156 MFI_DCMD_PR_GET_STATUS = 0x01070100,
157 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200,
158 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300,
159 MFI_DCMD_PR_START = 0x01070400,
160 MFI_DCMD_PR_STOP = 0x01070500,
161 MFI_DCMD_TIME_SECS_GET = 0x01080201,
162 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100,
163 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200,
164 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300,
165 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400,
166 MFI_DCMD_PD_GET_LIST = 0x02010000,
167 MFI_DCMD_PD_GET_INFO = 0x02020000,
168 MFI_DCMD_PD_STATE_SET = 0x02030100,
169 MFI_DCMD_PD_REBUILD_START = 0x02040100,
170 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200,
171 MFI_DCMD_PD_CLEAR_START = 0x02050100,
172 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200,
173 MFI_DCMD_PD_GET_PROGRESS = 0x02060000,
174 MFI_DCMD_PD_LOCATE_START = 0x02070100,
175 MFI_DCMD_PD_LOCATE_STOP = 0x02070200,
176 MFI_DCMD_LD_GET_LIST = 0x03010000,
177 MFI_DCMD_LD_GET_INFO = 0x03020000,
178 MFI_DCMD_LD_GET_PROP = 0x03030000,
179 MFI_DCMD_LD_SET_PROP = 0x03040000,
180 MFI_DCMD_LD_INIT_START = 0x03060100,
181 MFI_DCMD_LD_DELETE = 0x03090000,
182 MFI_DCMD_CFG_READ = 0x04010000,
183 MFI_DCMD_CFG_ADD = 0x04020000,
184 MFI_DCMD_CFG_CLEAR = 0x04030000,
185 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000,
186 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000,
187 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400,
188 MFI_DCMD_BBU_GET_STATUS = 0x05010000,
189 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000,
190 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000,
191 MFI_DCMD_CLUSTER = 0x08000000,
192 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100,
193 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200
196 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
197 #define MFI_FLUSHCACHE_CTRL 0x01
198 #define MFI_FLUSHCACHE_DISK 0x02
200 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */
201 #define MFI_SHUTDOWN_SPINDOWN 0x01
206 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
207 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
208 #define MFI_FRAME_SGL32 0x0000
209 #define MFI_FRAME_SGL64 0x0002
210 #define MFI_FRAME_SENSE32 0x0000
211 #define MFI_FRAME_SENSE64 0x0004
212 #define MFI_FRAME_DIR_NONE 0x0000
213 #define MFI_FRAME_DIR_WRITE 0x0008
214 #define MFI_FRAME_DIR_READ 0x0010
215 #define MFI_FRAME_DIR_BOTH 0x0018
217 /* MFI Status codes */
220 MFI_STAT_INVALID_CMD,
221 MFI_STAT_INVALID_DCMD,
222 MFI_STAT_INVALID_PARAMETER,
223 MFI_STAT_INVALID_SEQUENCE_NUMBER,
224 MFI_STAT_ABORT_NOT_POSSIBLE,
225 MFI_STAT_APP_HOST_CODE_NOT_FOUND,
227 MFI_STAT_APP_NOT_INITIALIZED,
228 MFI_STAT_ARRAY_INDEX_INVALID,
229 MFI_STAT_ARRAY_ROW_NOT_EMPTY,
230 MFI_STAT_CONFIG_RESOURCE_CONFLICT,
231 MFI_STAT_DEVICE_NOT_FOUND,
232 MFI_STAT_DRIVE_TOO_SMALL,
233 MFI_STAT_FLASH_ALLOC_FAIL,
235 MFI_STAT_FLASH_ERROR = 0x10,
236 MFI_STAT_FLASH_IMAGE_BAD,
237 MFI_STAT_FLASH_IMAGE_INCOMPLETE,
238 MFI_STAT_FLASH_NOT_OPEN,
239 MFI_STAT_FLASH_NOT_STARTED,
240 MFI_STAT_FLUSH_FAILED,
241 MFI_STAT_HOST_CODE_NOT_FOUNT,
242 MFI_STAT_LD_CC_IN_PROGRESS,
243 MFI_STAT_LD_INIT_IN_PROGRESS,
244 MFI_STAT_LD_LBA_OUT_OF_RANGE,
245 MFI_STAT_LD_MAX_CONFIGURED,
246 MFI_STAT_LD_NOT_OPTIMAL,
247 MFI_STAT_LD_RBLD_IN_PROGRESS,
248 MFI_STAT_LD_RECON_IN_PROGRESS,
249 MFI_STAT_LD_WRONG_RAID_LEVEL,
250 MFI_STAT_MAX_SPARES_EXCEEDED,
251 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
252 MFI_STAT_MFC_HW_ERROR,
253 MFI_STAT_NO_HW_PRESENT,
255 MFI_STAT_NOT_IN_ENCL,
256 MFI_STAT_PD_CLEAR_IN_PROGRESS,
257 MFI_STAT_PD_TYPE_WRONG,
258 MFI_STAT_PR_DISABLED,
259 MFI_STAT_ROW_INDEX_INVALID,
260 MFI_STAT_SAS_CONFIG_INVALID_ACTION,
261 MFI_STAT_SAS_CONFIG_INVALID_DATA,
262 MFI_STAT_SAS_CONFIG_INVALID_PAGE,
263 MFI_STAT_SAS_CONFIG_INVALID_TYPE,
264 MFI_STAT_SCSI_DONE_WITH_ERROR,
265 MFI_STAT_SCSI_IO_FAILED,
266 MFI_STAT_SCSI_RESERVATION_CONFLICT,
267 MFI_STAT_SHUTDOWN_FAILED = 0x30,
268 MFI_STAT_TIME_NOT_SET,
269 MFI_STAT_WRONG_STATE,
271 MFI_STAT_PEER_NOTIFICATION_REJECTED,
272 MFI_STAT_PEER_NOTIFICATION_FAILED,
273 MFI_STAT_RESERVATION_IN_PROGRESS,
274 MFI_STAT_I2C_ERRORS_DETECTED,
275 MFI_STAT_PCI_ERRORS_DETECTED,
276 MFI_STAT_DIAG_FAILED,
277 MFI_STAT_BOOT_MSG_PENDING,
278 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE,
279 MFI_STAT_INVALID_STATUS = 0xFF
283 MFI_EVT_CLASS_DEBUG = -2,
284 MFI_EVT_CLASS_PROGRESS = -1,
285 MFI_EVT_CLASS_INFO = 0,
286 MFI_EVT_CLASS_WARNING = 1,
287 MFI_EVT_CLASS_CRITICAL = 2,
288 MFI_EVT_CLASS_FATAL = 3,
289 MFI_EVT_CLASS_DEAD = 4
293 MFI_EVT_LOCALE_LD = 0x0001,
294 MFI_EVT_LOCALE_PD = 0x0002,
295 MFI_EVT_LOCALE_ENCL = 0x0004,
296 MFI_EVT_LOCALE_BBU = 0x0008,
297 MFI_EVT_LOCALE_SAS = 0x0010,
298 MFI_EVT_LOCALE_CTRL = 0x0020,
299 MFI_EVT_LOCALE_CONFIG = 0x0040,
300 MFI_EVT_LOCALE_CLUSTER = 0x0080,
301 MFI_EVT_LOCALE_ALL = 0xffff
305 MR_EVT_ARGS_NONE = 0x00,
306 MR_EVT_ARGS_CDB_SENSE,
308 MR_EVT_ARGS_LD_COUNT,
310 MR_EVT_ARGS_LD_OWNER,
311 MR_EVT_ARGS_LD_LBA_PD_LBA,
313 MR_EVT_ARGS_LD_STATE,
314 MR_EVT_ARGS_LD_STRIP,
318 MR_EVT_ARGS_PD_LBA_LD,
320 MR_EVT_ARGS_PD_STATE,
329 MR_LD_CACHE_WRITE_BACK = 0x01,
330 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02,
331 MR_LD_CACHE_READ_AHEAD = 0x04,
332 MR_LD_CACHE_READ_ADAPTIVE = 0x08,
333 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10,
334 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
335 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40
337 #define MR_LD_CACHE_MASK 0x7f
339 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0
340 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD
341 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \
342 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE)
343 #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0
344 #define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK
345 #define MR_LD_CACHE_POLICY_IO_CACHED \
346 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE)
347 #define MR_LD_CACHE_POLICY_IO_DIRECT 0
350 MR_PD_CACHE_UNCHANGED = 0,
351 MR_PD_CACHE_ENABLE = 1,
352 MR_PD_CACHE_DISABLE = 2
356 * Other propertities and definitions
358 #define MFI_MAX_PD_CHANNELS 2
359 #define MFI_MAX_LD_CHANNELS 2
360 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
361 #define MFI_MAX_CHANNEL_DEVS 128
362 #define MFI_DEFAULT_ID -1
363 #define MFI_MAX_LUN 8
364 #define MFI_MAX_LD 64
365 #define MFI_MAX_PD 256
367 #define MFI_FRAME_SIZE 64
368 #define MFI_MBOX_SIZE 12
370 /* Firmware flashing can take 40s */
371 #define MFI_POLL_TIMEOUT_SECS 50
373 /* Allow for speedier math calculations */
374 #define MFI_SECTOR_LEN 512
376 /* Scatter Gather elements */
388 struct mfi_sg32 sg32[1];
389 struct mfi_sg64 sg64[1];
392 /* Message frames. All messages have a common header */
393 struct mfi_frame_header {
405 #define MFI_FRAME_DATAOUT 0x08
406 #define MFI_FRAME_DATAIN 0x10
411 struct mfi_init_frame {
412 struct mfi_frame_header header;
413 uint32_t qinfo_new_addr_lo;
414 uint32_t qinfo_new_addr_hi;
415 uint32_t qinfo_old_addr_lo;
416 uint32_t qinfo_old_addr_hi;
417 uint32_t reserved[6];
420 #define MFI_IO_FRAME_SIZE 40
421 struct mfi_io_frame {
422 struct mfi_frame_header header;
423 uint32_t sense_addr_lo;
424 uint32_t sense_addr_hi;
430 #define MFI_PASS_FRAME_SIZE 48
431 struct mfi_pass_frame {
432 struct mfi_frame_header header;
433 uint32_t sense_addr_lo;
434 uint32_t sense_addr_hi;
439 #define MFI_DCMD_FRAME_SIZE 40
440 struct mfi_dcmd_frame {
441 struct mfi_frame_header header;
443 uint8_t mbox[MFI_MBOX_SIZE];
447 struct mfi_abort_frame {
448 struct mfi_frame_header header;
449 uint32_t abort_context;
451 uint32_t abort_mfi_addr_lo;
452 uint32_t abort_mfi_addr_hi;
453 uint32_t reserved[6];
456 struct mfi_smp_frame {
457 struct mfi_frame_header header;
460 struct mfi_sg32 sg32[2];
461 struct mfi_sg64 sg64[2];
465 struct mfi_stp_frame {
466 struct mfi_frame_header header;
470 struct mfi_sg32 sg32[2];
471 struct mfi_sg64 sg64[2];
476 struct mfi_frame_header header;
477 struct mfi_init_frame init;
478 struct mfi_io_frame io;
479 struct mfi_pass_frame pass;
480 struct mfi_dcmd_frame dcmd;
481 struct mfi_abort_frame abort;
482 struct mfi_smp_frame smp;
483 struct mfi_stp_frame stp;
484 uint8_t bytes[MFI_FRAME_SIZE];
487 #define MFI_SENSE_LEN 128
489 uint8_t data[MFI_SENSE_LEN];
492 /* The queue init structure that is passed with the init message */
493 struct mfi_init_qinfo {
504 /* SAS (?) controller properties, part of mfi_ctrl_info */
505 struct mfi_ctrl_props {
507 uint16_t pred_fail_poll_interval;
508 uint16_t intr_throttle_cnt;
509 uint16_t intr_throttle_timeout;
510 uint8_t rebuild_rate;
511 uint8_t patrol_read_rate;
515 uint8_t cache_flush_interval;
516 uint8_t spinup_drv_cnt;
517 uint8_t spinup_delay;
518 uint8_t cluster_enable;
519 uint8_t coercion_mode;
520 uint8_t alarm_enable;
521 uint8_t disable_auto_rebuild;
522 uint8_t disable_battery_warn;
523 uint8_t ecc_bucket_size;
524 uint16_t ecc_bucket_leak_rate;
525 uint8_t restore_hotspare_on_insertion;
526 uint8_t expose_encl_devices;
527 uint8_t reserved[38];
530 /* PCI information about the card. */
531 struct mfi_info_pci {
536 uint8_t reserved[24];
539 /* Host (front end) interface information */
540 struct mfi_info_host {
542 #define MFI_INFO_HOST_PCIX 0x01
543 #define MFI_INFO_HOST_PCIE 0x02
544 #define MFI_INFO_HOST_ISCSI 0x04
545 #define MFI_INFO_HOST_SAS3G 0x08
548 uint64_t port_addr[8];
551 /* Device (back end) interface information */
552 struct mfi_info_device {
554 #define MFI_INFO_DEV_SPI 0x01
555 #define MFI_INFO_DEV_SAS3G 0x02
556 #define MFI_INFO_DEV_SATA1 0x04
557 #define MFI_INFO_DEV_SATA3G 0x08
560 uint64_t port_addr[8];
563 /* Firmware component information */
564 struct mfi_info_component {
571 /* Controller default settings */
572 struct mfi_defaults {
574 uint8_t phy_polarity;
575 uint8_t background_rate;
580 uint8_t cache_when_bbu_bad;
583 uint8_t alarm_disable;
586 uint8_t dirty_led_shows_drive_activity;
587 uint8_t bios_continue_on_error;
588 uint8_t spindown_mode;
589 uint8_t allowed_device_types;
590 uint8_t allow_mix_in_enclosure;
591 uint8_t allow_mix_in_ld;
592 uint8_t allow_sata_in_cluster;
593 uint8_t max_chained_enclosures;
594 uint8_t disable_ctrl_r;
595 uint8_t enabel_web_bios;
596 uint8_t phy_polarity_split;
597 uint8_t direct_pd_mapping;
598 uint8_t bios_enumerate_lds;
599 uint8_t restored_hot_spare_on_insertion;
600 uint8_t expose_enclosure_devices;
601 uint8_t maintain_pd_fail_history;
605 /* Controller default settings */
606 struct mfi_bios_data {
607 uint16_t boot_target_id;
608 uint8_t do_not_int_13;
609 uint8_t continue_on_error;
612 uint8_t expose_all_drives;
613 uint8_t reserved[56];
617 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */
618 struct mfi_ctrl_info {
619 struct mfi_info_pci pci;
620 struct mfi_info_host host;
621 struct mfi_info_device device;
623 /* Firmware components that are present and active. */
624 uint32_t image_check_word;
625 uint32_t image_component_count;
626 struct mfi_info_component image_component[8];
628 /* Firmware components that have been flashed but are inactive */
629 uint32_t pending_image_component_count;
630 struct mfi_info_component pending_image_component[8];
636 char product_name[80];
637 char serial_number[32];
639 #define MFI_INFO_HW_BBU 0x01
640 #define MFI_INFO_HW_ALARM 0x02
641 #define MFI_INFO_HW_NVRAM 0x04
642 #define MFI_INFO_HW_UART 0x08
643 uint32_t current_fw_time;
645 uint16_t max_sg_elements;
646 uint32_t max_request_size;
647 uint16_t lds_present;
648 uint16_t lds_degraded;
649 uint16_t lds_offline;
651 uint16_t pd_disks_present;
652 uint16_t pd_disks_pred_failure;
653 uint16_t pd_disks_failed;
655 uint16_t memory_size;
657 uint16_t ram_correctable_errors;
658 uint16_t ram_uncorrectable_errors;
659 uint8_t cluster_allowed;
660 uint8_t cluster_active;
661 uint16_t max_strips_per_io;
663 uint32_t raid_levels;
664 #define MFI_INFO_RAID_0 0x01
665 #define MFI_INFO_RAID_1 0x02
666 #define MFI_INFO_RAID_5 0x04
667 #define MFI_INFO_RAID_1E 0x08
668 #define MFI_INFO_RAID_6 0x10
670 uint32_t adapter_ops;
671 #define MFI_INFO_AOPS_RBLD_RATE 0x0001
672 #define MFI_INFO_AOPS_CC_RATE 0x0002
673 #define MFI_INFO_AOPS_BGI_RATE 0x0004
674 #define MFI_INFO_AOPS_RECON_RATE 0x0008
675 #define MFI_INFO_AOPS_PATROL_RATE 0x0010
676 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020
677 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
678 #define MFI_INFO_AOPS_BBU 0x0080
679 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100
680 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200
681 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
682 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800
683 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000
684 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000
685 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000
688 #define MFI_INFO_LDOPS_READ_POLICY 0x01
689 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02
690 #define MFI_INFO_LDOPS_IO_POLICY 0x04
691 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08
692 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
698 } __packed stripe_sz_ops;
701 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01
702 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02
703 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04
705 uint32_t pd_mix_support;
706 #define MFI_INFO_PDMIX_SAS 0x01
707 #define MFI_INFO_PDMIX_SATA 0x02
708 #define MFI_INFO_PDMIX_ENCL 0x04
709 #define MFI_INFO_PDMIX_LD 0x08
710 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10
712 uint8_t ecc_bucket_count;
713 uint8_t reserved2[11];
714 struct mfi_ctrl_props properties;
715 char package_version[0x60];
716 uint8_t pad[0x800 - 0x6a0];
719 /* keep track of an event. */
729 /* event log state. */
730 struct mfi_evt_log_state {
731 uint32_t newest_seq_num;
732 uint32_t oldest_seq_num;
733 uint32_t clear_seq_num;
734 uint32_t shutdown_seq_num;
735 uint32_t boot_seq_num;
738 struct mfi_progress {
740 uint16_t elapsed_seconds;
751 uint8_t enclosure_index;
755 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */
756 struct mfi_evt_detail {
760 union mfi_evt evt_class;
762 uint8_t reserved1[15];
766 struct mfi_evt_pd pd;
774 struct mfi_evt_ld ld;
777 struct mfi_evt_ld ld;
783 struct mfi_evt_ld ld;
787 struct mfi_evt_ld ld;
795 struct mfi_evt_ld ld;
796 struct mfi_evt_pd pd;
800 struct mfi_evt_ld ld;
801 struct mfi_progress prog;
805 struct mfi_evt_ld ld;
812 struct mfi_evt_ld ld;
815 struct mfi_evt_pd pd;
818 struct mfi_evt_pd pd;
824 struct mfi_evt_pd pd;
829 struct mfi_evt_pd pd;
830 struct mfi_evt_ld ld;
834 struct mfi_evt_pd pd;
835 struct mfi_progress prog;
839 struct mfi_evt_pd ld;
847 uint16_t subVenderId;
848 uint16_t subDeviceId;
857 uint16_t elapsedSeconds;
872 char description[128];
875 struct mfi_evt_list {
878 struct mfi_evt_detail event[1];
889 union mfi_pd_ddf_type {
893 uint16_t forced_pd_guid : 1;
895 uint16_t is_global_spare : 1;
896 uint16_t is_spare : 1;
897 uint16_t is_foreign : 1;
898 uint16_t reserved : 7;
911 struct mfi_pd_progress {
913 #define MFI_PD_PROGRESS_REBUILD (1<<0)
914 #define MFI_PD_PROGRESS_PATROL (1<<1)
915 #define MFI_PD_PROGRESS_CLEAR (1<<2)
916 struct mfi_progress rbld;
917 struct mfi_progress patrol;
918 struct mfi_progress clear;
919 struct mfi_progress reserved[4];
923 union mfi_pd_ref ref;
924 uint8_t inquiry_data[96];
925 uint8_t vpd_page83[64];
926 uint8_t not_supported;
927 uint8_t scsi_dev_type;
928 uint8_t connected_port_bitmap;
929 uint8_t device_speed;
930 uint32_t media_err_count;
931 uint32_t other_err_count;
932 uint32_t pred_fail_count;
933 uint32_t last_pred_fail_event_seq_num;
934 uint16_t fw_state; /* MFI_PD_STATE_* */
935 uint8_t disabled_for_removal;
937 union mfi_pd_ddf_type state;
940 uint8_t is_path_broken;
942 uint64_t sas_addr[4];
945 uint64_t non_coerced_size;
946 uint64_t coerced_size;
947 uint16_t encl_device_id;
950 struct mfi_pd_progress prog_info;
951 uint8_t bad_block_table_full;
952 uint8_t unusable_in_current_config;
953 uint8_t vpd_page83_ext[64];
954 uint8_t reserved[512-358];
957 struct mfi_pd_address {
959 uint16_t encl_device_id;
962 uint8_t scsi_dev_type; /* 0 = disk */
963 uint8_t connect_port_bitmap;
964 uint64_t sas_addr[2];
970 struct mfi_pd_address addr[0];
974 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00,
975 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01,
976 MFI_PD_STATE_HOT_SPARE = 0x02,
977 MFI_PD_STATE_OFFLINE = 0x10,
978 MFI_PD_STATE_FAILED = 0x11,
979 MFI_PD_STATE_REBUILD = 0x14,
980 MFI_PD_STATE_ONLINE = 0x18,
981 MFI_PD_STATE_COPYBACK = 0x20,
982 MFI_PD_STATE_SYSTEM = 0x40
1000 uint8_t reserved2[3];
1002 } ld_list[MFI_MAX_LD];
1005 enum mfi_ld_access {
1006 MFI_LD_ACCESS_RW = 0,
1007 MFI_LD_ACCSSS_RO = 2,
1008 MFI_LD_ACCESS_BLOCKED = 3,
1010 #define MFI_LD_ACCESS_MASK 3
1013 MFI_LD_STATE_OFFLINE = 0,
1014 MFI_LD_STATE_PARTIALLY_DEGRADED = 1,
1015 MFI_LD_STATE_DEGRADED = 2,
1016 MFI_LD_STATE_OPTIMAL = 3
1019 struct mfi_ld_props {
1020 union mfi_ld_ref ld;
1022 uint8_t default_cache_policy;
1023 uint8_t access_policy;
1024 uint8_t disk_cache_policy;
1025 uint8_t current_cache_policy;
1027 uint8_t reserved[7];
1030 struct mfi_ld_params {
1031 uint8_t primary_raid_level;
1032 uint8_t raid_level_qualifier;
1033 uint8_t secondary_raid_level;
1034 uint8_t stripe_size;
1039 #define MFI_LD_PARAMS_INIT_NO 0
1040 #define MFI_LD_PARAMS_INIT_QUICK 1
1041 #define MFI_LD_PARAMS_INIT_FULL 2
1042 uint8_t is_consistent;
1043 uint8_t reserved[23];
1046 struct mfi_ld_progress {
1048 #define MFI_LD_PROGRESS_CC (1<<0)
1049 #define MFI_LD_PROGRESS_BGI (1<<1)
1050 #define MFI_LD_PROGRESS_FGI (1<<2)
1051 #define MFI_LD_PROGRESS_RECON (1<<3)
1052 struct mfi_progress cc;
1053 struct mfi_progress bgi;
1054 struct mfi_progress fgi;
1055 struct mfi_progress recon;
1056 struct mfi_progress reserved[4];
1060 uint64_t start_block;
1061 uint64_t num_blocks;
1063 uint8_t reserved[6];
1066 #define MFI_MAX_SPAN_DEPTH 8
1067 struct mfi_ld_config {
1068 struct mfi_ld_props properties;
1069 struct mfi_ld_params params;
1070 struct mfi_span span[MFI_MAX_SPAN_DEPTH];
1073 struct mfi_ld_info {
1074 struct mfi_ld_config ld_config;
1076 struct mfi_ld_progress progress;
1077 uint16_t cluster_owner;
1078 uint8_t reconstruct_active;
1079 uint8_t reserved1[1];
1080 uint8_t vpd_page83[64];
1081 uint8_t reserved2[16];
1084 #define MAX_ARRAYS 16
1086 union mfi_pd_ref ref;
1088 #define MFI_SPARE_DEDICATED (1 << 0)
1089 #define MFI_SPARE_REVERTIBLE (1 << 1)
1090 #define MFI_SPARE_ENCL_AFFINITY (1 << 2)
1091 uint8_t reserved[2];
1092 uint8_t array_count;
1093 uint16_t array_ref[MAX_ARRAYS];
1103 union mfi_pd_ref ref; /* 0xffff == missing drive */
1104 uint16_t fw_state; /* MFI_PD_STATE_* */
1112 struct mfi_config_data {
1114 uint16_t array_count;
1115 uint16_t array_size;
1116 uint16_t log_drv_count;
1117 uint16_t log_drv_size;
1118 uint16_t spares_count;
1119 uint16_t spares_size;
1120 uint8_t reserved[16];
1121 struct mfi_array array[0];
1122 struct mfi_ld_config ld[0];
1123 struct mfi_spare spare[0];
1126 struct mfi_bbu_capacity_info {
1127 uint16_t relative_charge;
1128 uint16_t absolute_charge;
1129 uint16_t remaining_capacity;
1130 uint16_t full_charge_capacity;
1131 uint16_t run_time_to_empty;
1132 uint16_t average_time_to_empty;
1133 uint16_t average_time_to_full;
1134 uint16_t cycle_count;
1136 uint16_t remaining_capacity_alarm;
1137 uint16_t remaining_time_alarm;
1138 uint8_t reserved[26];
1141 struct mfi_bbu_design_info {
1143 uint16_t design_capacity;
1144 uint16_t design_voltage;
1146 uint16_t serial_number;
1147 uint16_t pack_stat_config;
1148 uint8_t mfg_name[12];
1149 uint8_t device_name[8];
1150 uint8_t device_chemistry[8];
1151 uint8_t mfg_data[8];
1152 uint8_t reserved[17];
1155 struct mfi_ibbu_state {
1156 uint16_t gas_guage_status;
1157 uint16_t relative_charge;
1158 uint16_t charger_system_state;
1159 uint16_t charger_system_ctrl;
1160 uint16_t charging_current;
1161 uint16_t absolute_charge;
1163 uint8_t reserved[18];
1166 struct mfi_bbu_state {
1167 uint16_t gas_guage_status;
1168 uint16_t relative_charge;
1169 uint16_t charger_status;
1170 uint16_t remaining_capacity;
1171 uint16_t full_charge_capacity;
1172 uint8_t is_SOH_good;
1173 uint8_t reserved[21];
1176 union mfi_bbu_status_detail {
1177 struct mfi_ibbu_state ibbu;
1178 struct mfi_bbu_state bbu;
1181 struct mfi_bbu_status {
1182 uint8_t battery_type;
1183 #define MFI_BBU_TYPE_NONE 0
1184 #define MFI_BBU_TYPE_IBBU 1
1185 #define MFI_BBU_TYPE_BBU 2
1189 uint16_t temperature;
1191 #define MFI_BBU_STATE_PACK_MISSING (1 << 0)
1192 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1)
1193 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2)
1194 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 0)
1195 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 0)
1197 union mfi_bbu_status_detail detail;
1201 MFI_PR_STATE_STOPPED = 0,
1202 MFI_PR_STATE_READY = 1,
1203 MFI_PR_STATE_ACTIVE = 2,
1204 MFI_PR_STATE_ABORTED = 0xff
1207 struct mfi_pr_status {
1208 uint32_t num_iteration;
1210 uint8_t num_pd_done;
1211 uint8_t reserved[10];
1214 enum mfi_pr_opmode {
1215 MFI_PR_OPMODE_AUTO = 0,
1216 MFI_PR_OPMODE_MANUAL = 1,
1217 MFI_PR_OPMODE_DISABLED = 2
1220 struct mfi_pr_properties {
1224 uint8_t exclude_ld_count;
1225 uint16_t excluded_ld[MFI_MAX_LD];
1226 uint8_t cur_pd_map[MFI_MAX_PD / 8];
1227 uint8_t last_pd_map[MFI_MAX_PD / 8];
1230 uint32_t clear_freq;
1233 #define MFI_SCSI_MAX_TARGETS 128
1234 #define MFI_SCSI_MAX_LUNS 8
1235 #define MFI_SCSI_INITIATOR_ID 255
1236 #define MFI_SCSI_MAX_CMDS 8
1237 #define MFI_SCSI_MAX_CDB_LEN 16
1239 #endif /* _MFIREG_H */