sys/dev/mii/brgphy.c

   1 /*-
   2  * Copyright (c) 2000
   3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  38  */
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/socket.h>
  45 #include <sys/bus.h>
  46
  47 #include <net/if.h>
  48 #include <net/ethernet.h>
  49 #include <net/if_media.h>
  50
  51 #include <dev/mii/mii.h>
  52 #include <dev/mii/miivar.h>
  53 #include "miidevs.h"
  54
  55 #include <dev/mii/brgphyreg.h>
  56 #include <net/if_arp.h>
  57 #include <machine/bus.h>
  58 #include <dev/bge/if_bgereg.h>
  59 #include <dev/bce/if_bcereg.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include "miibus_if.h"
  65
  66 static int brgphy_probe(device_t);
  67 static int brgphy_attach(device_t);
  68
  69 struct brgphy_softc {
  70         struct mii_softc mii_sc;
  71         int serdes_flags;       /* Keeps track of the serdes type used */
  72 #define BRGPHY_5706S            0x0001
  73 #define BRGPHY_5708S            0x0002
  74 #define BRGPHY_NOANWAIT         0x0004
  75 #define BRGPHY_5709S            0x0008
  76         int bce_phy_flags;      /* PHY flags transferred from the MAC driver */
  77 };
  78
  79 static device_method_t brgphy_methods[] = {
  80         /* device interface */
  81         DEVMETHOD(device_probe,         brgphy_probe),
  82         DEVMETHOD(device_attach,        brgphy_attach),
  83         DEVMETHOD(device_detach,        mii_phy_detach),
  84         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  85         { 0, 0 }
  86 };
  87
  88 static devclass_t brgphy_devclass;
  89
  90 static driver_t brgphy_driver = {
  91         "brgphy",
  92         brgphy_methods,
  93         sizeof(struct brgphy_softc)
  94 };
  95
  96 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
  97
  98 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
  99 static void     brgphy_setmedia(struct mii_softc *, int);
 100 static void     brgphy_status(struct mii_softc *);
 101 static void     brgphy_mii_phy_auto(struct mii_softc *, int);
 102 static void     brgphy_reset(struct mii_softc *);
 103 static void     brgphy_enable_loopback(struct mii_softc *);
 104 static void     bcm5401_load_dspcode(struct mii_softc *);
 105 static void     bcm5411_load_dspcode(struct mii_softc *);
 106 static void     bcm54k2_load_dspcode(struct mii_softc *);
 107 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 108 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 109 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 110 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 111 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 112 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 113 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 114 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 115
 116 static const struct mii_phydesc brgphys[] = {
 117         MII_PHY_DESC(BROADCOM, BCM5400),
 118         MII_PHY_DESC(BROADCOM, BCM5401),
 119         MII_PHY_DESC(BROADCOM, BCM5411),
 120         MII_PHY_DESC(BROADCOM, BCM54K2),
 121         MII_PHY_DESC(BROADCOM, BCM5701),
 122         MII_PHY_DESC(BROADCOM, BCM5703),
 123         MII_PHY_DESC(BROADCOM, BCM5704),
 124         MII_PHY_DESC(BROADCOM, BCM5705),
 125         MII_PHY_DESC(BROADCOM, BCM5706),
 126         MII_PHY_DESC(BROADCOM, BCM5714),
 127         MII_PHY_DESC(BROADCOM, BCM5421),
 128         MII_PHY_DESC(BROADCOM, BCM5750),
 129         MII_PHY_DESC(BROADCOM, BCM5752),
 130         MII_PHY_DESC(BROADCOM, BCM5780),
 131         MII_PHY_DESC(BROADCOM, BCM5708C),
 132         MII_PHY_DESC(BROADCOM2, BCM5482),
 133         MII_PHY_DESC(BROADCOM2, BCM5708S),
 134         MII_PHY_DESC(BROADCOM2, BCM5709C),
 135         MII_PHY_DESC(BROADCOM2, BCM5709S),
 136         MII_PHY_DESC(BROADCOM2, BCM5709CAX),
 137         MII_PHY_DESC(BROADCOM2, BCM5722),
 138         MII_PHY_DESC(BROADCOM2, BCM5755),
 139         MII_PHY_DESC(BROADCOM2, BCM5754),
 140         MII_PHY_DESC(BROADCOM2, BCM5761),
 141         MII_PHY_DESC(BROADCOM2, BCM5784),
 142         MII_PHY_DESC(BROADCOM3, BCM5717C),
 143         MII_PHY_DESC(BROADCOM3, BCM5719C),
 144         MII_PHY_DESC(BROADCOM3, BCM57765),
 145         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
 146         MII_PHY_END
 147 };
 148
 149 static const struct mii_phy_funcs brgphy_funcs = {
 150         brgphy_service,
 151         brgphy_status,
 152         brgphy_reset
 153 };
 154
 155 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21"
 156 #define HS21_BCM_CHIPID 0x57081021
 157
 158 static int
 159 detect_hs21(struct bce_softc *bce_sc)
 160 {
 161         char *sysenv;
 162         int found;
 163
 164         found = 0;
 165         if (bce_sc->bce_chipid == HS21_BCM_CHIPID) {
 166                 sysenv = getenv("smbios.system.product");
 167                 if (sysenv != NULL) {
 168                         if (strncmp(sysenv, HS21_PRODUCT_ID,
 169                             strlen(HS21_PRODUCT_ID)) == 0)
 170                                 found = 1;
 171                         freeenv(sysenv);
 172                 }
 173         }
 174         return (found);
 175 }
 176
 177 /* Search for our PHY in the list of known PHYs */
 178 static int
 179 brgphy_probe(device_t dev)
 180 {
 181
 182         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 183 }
 184
 185 /* Attach the PHY to the MII bus */
 186 static int
 187 brgphy_attach(device_t dev)
 188 {
 189         struct brgphy_softc *bsc;
 190         struct bge_softc *bge_sc = NULL;
 191         struct bce_softc *bce_sc = NULL;
 192         struct mii_softc *sc;
 193         struct ifnet *ifp;
 194
 195         bsc = device_get_softc(dev);
 196         sc = &bsc->mii_sc;
 197
 198         mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
 199             &brgphy_funcs, 0);
 200
 201         bsc->serdes_flags = 0;
 202
 203         /* Handle any special cases based on the PHY ID */
 204         switch (sc->mii_mpd_oui) {
 205         case MII_OUI_BROADCOM:
 206                 switch (sc->mii_mpd_model) {
 207                 case MII_MODEL_BROADCOM_BCM5706:
 208                 case MII_MODEL_BROADCOM_BCM5714:
 209                         /*
 210                          * The 5464 PHY used in the 5706 supports both copper
 211                          * and fiber interfaces over GMII.  Need to check the
 212                          * shadow registers to see which mode is actually
 213                          * in effect, and therefore whether we have 5706C or
 214                          * 5706S.
 215                          */
 216                         PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 217                                 BRGPHY_SHADOW_1C_MODE_CTRL);
 218                         if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 219                                 BRGPHY_SHADOW_1C_ENA_1000X) {
 220                                 bsc->serdes_flags |= BRGPHY_5706S;
 221                                 sc->mii_flags |= MIIF_HAVEFIBER;
 222                         }
 223                         break;
 224                 } break;
 225         case MII_OUI_BROADCOM2:
 226                 switch (sc->mii_mpd_model) {
 227                 case MII_MODEL_BROADCOM2_BCM5708S:
 228                         bsc->serdes_flags |= BRGPHY_5708S;
 229                         sc->mii_flags |= MIIF_HAVEFIBER;
 230                         break;
 231                 case MII_MODEL_BROADCOM2_BCM5709S:
 232                         bsc->serdes_flags |= BRGPHY_5709S;
 233                         sc->mii_flags |= MIIF_HAVEFIBER;
 234                         break;
 235                 }
 236                 break;
 237         }
 238
 239         ifp = sc->mii_pdata->mii_ifp;
 240
 241         /* Find the MAC driver associated with this PHY. */
 242         if (strcmp(ifp->if_dname, "bge") == 0)  {
 243                 bge_sc = ifp->if_softc;
 244         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 245                 bce_sc = ifp->if_softc;
 246         }
 247
 248         PHY_RESET(sc);
 249
 250         /* Read the PHY's capabilities. */
 251         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
 252         if (sc->mii_capabilities & BMSR_EXTSTAT)
 253                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 254         device_printf(dev, " ");
 255
 256 #define ADD(m, c)       ifmedia_add(&sc->mii_pdata->mii_media, (m), (c), NULL)
 257
 258         /* Add the supported media types */
 259         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 260                 mii_phy_add_media(sc);
 261                 printf("\n");
 262         } else {
 263                 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 264                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 265                         BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 266                 printf("1000baseSX-FDX, ");
 267                 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */
 268                 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 269                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
 270                         printf("2500baseSX-FDX, ");
 271                 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
 272                     (detect_hs21(bce_sc) != 0)) {
 273                         /*
 274                          * There appears to be certain silicon revision
 275                          * in IBM HS21 blades that is having issues with
 276                          * this driver wating for the auto-negotiation to
 277                          * complete. This happens with a specific chip id
 278                          * only and when the 1000baseSX-FDX is the only
 279                          * mode. Workaround this issue since it's unlikely
 280                          * to be ever addressed.
 281                          */
 282                         printf("auto-neg workaround, ");
 283                         bsc->serdes_flags |= BRGPHY_NOANWAIT;
 284                 }
 285                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
 286                 printf("auto\n");
 287         }
 288
 289 #undef ADD
 290         MIIBUS_MEDIAINIT(sc->mii_dev);
 291         return (0);
 292 }
 293
 294 static int
 295 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 296 {
 297         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 298         int val;
 299
 300         switch (cmd) {
 301         case MII_POLLSTAT:
 302                 break;
 303         case MII_MEDIACHG:
 304                 /* If the interface is not up, don't do anything. */
 305                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 306                         break;
 307
 308                 /* Todo: Why is this here?  Is it really needed? */
 309                 PHY_RESET(sc);  /* XXX hardware bug work-around */
 310
 311                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 312                 case IFM_AUTO:
 313                         brgphy_mii_phy_auto(sc, ife->ifm_media);
 314                         break;
 315                 case IFM_2500_SX:
 316                 case IFM_1000_SX:
 317                 case IFM_1000_T:
 318                 case IFM_100_TX:
 319                 case IFM_10_T:
 320                         brgphy_setmedia(sc, ife->ifm_media);
 321                         break;
 322                 default:
 323                         return (EINVAL);
 324                 }
 325                 break;
 326         case MII_TICK:
 327                 /* Bail if the interface isn't up. */
 328                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 329                         return (0);
 330
 331
 332                 /* Bail if autoneg isn't in process. */
 333                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 334                         sc->mii_ticks = 0;
 335                         break;
 336                 }
 337
 338                 /*
 339                  * Check to see if we have link.  If we do, we don't
 340                  * need to restart the autonegotiation process.
 341                  */
 342                 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 343                 if (val & BMSR_LINK) {
 344                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 345                         break;
 346                 }
 347
 348                 /* Announce link loss right after it happens. */
 349                 if (sc->mii_ticks++ == 0)
 350                         break;
 351
 352                 /* Only retry autonegotiation every mii_anegticks seconds. */
 353                 if (sc->mii_ticks <= sc->mii_anegticks)
 354                         break;
 355
 356
 357                 /* Retry autonegotiation */
 358                 sc->mii_ticks = 0;
 359                 brgphy_mii_phy_auto(sc, ife->ifm_media);
 360                 break;
 361         }
 362
 363         /* Update the media status. */
 364         PHY_STATUS(sc);
 365
 366         /*
 367          * Callback if something changed. Note that we need to poke
 368          * the DSP on the Broadcom PHYs if the media changes.
 369          */
 370         if (sc->mii_media_active != mii->mii_media_active ||
 371             sc->mii_media_status != mii->mii_media_status ||
 372             cmd == MII_MEDIACHG) {
 373                 switch (sc->mii_mpd_oui) {
 374                 case MII_OUI_BROADCOM:
 375                         switch (sc->mii_mpd_model) {
 376                         case MII_MODEL_BROADCOM_BCM5400:
 377                                 bcm5401_load_dspcode(sc);
 378                                 break;
 379                         case MII_MODEL_BROADCOM_BCM5401:
 380                                 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
 381                                         bcm5401_load_dspcode(sc);
 382                                 break;
 383                         case MII_MODEL_BROADCOM_BCM5411:
 384                                 bcm5411_load_dspcode(sc);
 385                                 break;
 386                         case MII_MODEL_BROADCOM_BCM54K2:
 387                                 bcm54k2_load_dspcode(sc);
 388                                 break;
 389                         }
 390                         break;
 391                 }
 392         }
 393         mii_phy_update(sc, cmd);
 394         return (0);
 395 }
 396
 397 /****************************************************************************/
 398 /* Sets the PHY link speed.                                                 */
 399 /*                                                                          */
 400 /* Returns:                                                                 */
 401 /*   None                                                                   */
 402 /****************************************************************************/
 403 static void
 404 brgphy_setmedia(struct mii_softc *sc, int media)
 405 {
 406         int bmcr = 0, gig;
 407
 408         switch (IFM_SUBTYPE(media)) {
 409         case IFM_2500_SX:
 410                 break;
 411         case IFM_1000_SX:
 412         case IFM_1000_T:
 413                 bmcr = BRGPHY_S1000;
 414                 break;
 415         case IFM_100_TX:
 416                 bmcr = BRGPHY_S100;
 417                 break;
 418         case IFM_10_T:
 419         default:
 420                 bmcr = BRGPHY_S10;
 421                 break;
 422         }
 423
 424         if ((media & IFM_FDX) != 0) {
 425                 bmcr |= BRGPHY_BMCR_FDX;
 426                 gig = BRGPHY_1000CTL_AFD;
 427         } else {
 428                 gig = BRGPHY_1000CTL_AHD;
 429         }
 430
 431         /* Force loopback to disconnect PHY from Ethernet medium. */
 432         brgphy_enable_loopback(sc);
 433
 434         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 435         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 436
 437         if (IFM_SUBTYPE(media) != IFM_1000_T &&
 438             IFM_SUBTYPE(media) != IFM_1000_SX) {
 439                 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 440                 return;
 441         }
 442
 443         if (IFM_SUBTYPE(media) == IFM_1000_T) {
 444                 gig |= BRGPHY_1000CTL_MSE;
 445                 if ((media & IFM_ETH_MASTER) != 0)
 446                         gig |= BRGPHY_1000CTL_MSC;
 447         }
 448         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 449         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 450             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 451 }
 452
 453 /****************************************************************************/
 454 /* Set the media status based on the PHY settings.                          */
 455 /*                                                                          */
 456 /* Returns:                                                                 */
 457 /*   None                                                                   */
 458 /****************************************************************************/
 459 static void
 460 brgphy_status(struct mii_softc *sc)
 461 {
 462         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 463         struct mii_data *mii = sc->mii_pdata;
 464         int aux, bmcr, bmsr, val, xstat;
 465         u_int flowstat;
 466
 467         mii->mii_media_status = IFM_AVALID;
 468         mii->mii_media_active = IFM_ETHER;
 469
 470         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 471         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 472
 473         if (bmcr & BRGPHY_BMCR_LOOP) {
 474                 mii->mii_media_active |= IFM_LOOP;
 475         }
 476
 477         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 478             (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
 479             (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
 480                 /* Erg, still trying, I guess... */
 481                 mii->mii_media_active |= IFM_NONE;
 482                 return;
 483         }
 484
 485         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 486                 /*
 487                  * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
 488                  * wedges at least the PHY of BCM5704 (but not others).
 489                  */
 490                 flowstat = mii_phy_flowstatus(sc);
 491                 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
 492                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 493
 494                 /* If copper link is up, get the negotiated speed/duplex. */
 495                 if (aux & BRGPHY_AUXSTS_LINK) {
 496                         mii->mii_media_status |= IFM_ACTIVE;
 497                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 498                         case BRGPHY_RES_1000FD:
 499                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 500                         case BRGPHY_RES_1000HD:
 501                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 502                         case BRGPHY_RES_100FD:
 503                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 504                         case BRGPHY_RES_100T4:
 505                                 mii->mii_media_active |= IFM_100_T4; break;
 506                         case BRGPHY_RES_100HD:
 507                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 508                         case BRGPHY_RES_10FD:
 509                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 510                         case BRGPHY_RES_10HD:
 511                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 512                         default:
 513                                 mii->mii_media_active |= IFM_NONE; break;
 514                         }
 515
 516                         if ((mii->mii_media_active & IFM_FDX) != 0)
 517                                 mii->mii_media_active |= flowstat;
 518
 519                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
 520                             (xstat & BRGPHY_1000STS_MSR) != 0)
 521                                 mii->mii_media_active |= IFM_ETH_MASTER;
 522                 }
 523         } else {
 524                 /* Todo: Add support for flow control. */
 525                 /* If serdes link is up, get the negotiated speed/duplex. */
 526                 if (bmsr & BRGPHY_BMSR_LINK) {
 527                         mii->mii_media_status |= IFM_ACTIVE;
 528                 }
 529
 530                 /* Check the link speed/duplex based on the PHY type. */
 531                 if (bsc->serdes_flags & BRGPHY_5706S) {
 532                         mii->mii_media_active |= IFM_1000_SX;
 533
 534                         /* If autoneg enabled, read negotiated duplex settings */
 535                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 536                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 537                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 538                                         mii->mii_media_active |= IFM_FDX;
 539                                 else
 540                                         mii->mii_media_active |= IFM_HDX;
 541                         }
 542                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 543                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 544                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 545
 546                         /* Check for MRBE auto-negotiated speed results. */
 547                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 548                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 549                                 mii->mii_media_active |= IFM_10_FL; break;
 550                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 551                                 mii->mii_media_active |= IFM_100_FX; break;
 552                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 553                                 mii->mii_media_active |= IFM_1000_SX; break;
 554                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 555                                 mii->mii_media_active |= IFM_2500_SX; break;
 556                         }
 557
 558                         /* Check for MRBE auto-negotiated duplex results. */
 559                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 560                                 mii->mii_media_active |= IFM_FDX;
 561                         else
 562                                 mii->mii_media_active |= IFM_HDX;
 563                 } else if (bsc->serdes_flags & BRGPHY_5709S) {
 564                         /* Select GP Status Block of the AN MMD, get autoneg results. */
 565                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
 566                         xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
 567
 568                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
 569                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
 570
 571                         /* Check for MRBE auto-negotiated speed results. */
 572                         switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
 573                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
 574                                         mii->mii_media_active |= IFM_10_FL; break;
 575                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
 576                                         mii->mii_media_active |= IFM_100_FX; break;
 577                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
 578                                         mii->mii_media_active |= IFM_1000_SX; break;
 579                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
 580                                         mii->mii_media_active |= IFM_2500_SX; break;
 581                         }
 582
 583                         /* Check for MRBE auto-negotiated duplex results. */
 584                         if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
 585                                 mii->mii_media_active |= IFM_FDX;
 586                         else
 587                                 mii->mii_media_active |= IFM_HDX;
 588                 }
 589         }
 590 }
 591
 592 static void
 593 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
 594 {
 595         int anar, ktcr = 0;
 596
 597         PHY_RESET(sc);
 598
 599         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 600                 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
 601                 if ((media & IFM_FLOW) != 0 ||
 602                     (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 603                         anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
 604                 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
 605         } else {
 606                 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
 607                 if ((media & IFM_FLOW) != 0 ||
 608                     (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 609                         anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
 610                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
 611         }
 612
 613         ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 614         if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
 615                 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 616         PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 617         ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
 618
 619         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
 620             BRGPHY_BMCR_STARTNEG);
 621         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 622 }
 623
 624 /* Enable loopback to force the link down. */
 625 static void
 626 brgphy_enable_loopback(struct mii_softc *sc)
 627 {
 628         int i;
 629
 630         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 631         for (i = 0; i < 15000; i++) {
 632                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 633                         break;
 634                 DELAY(10);
 635         }
 636 }
 637
 638 /* Turn off tap power management on 5401. */
 639 static void
 640 bcm5401_load_dspcode(struct mii_softc *sc)
 641 {
 642         static const struct {
 643                 int             reg;
 644                 uint16_t        val;
 645         } dspcode[] = {
 646                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 647                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 648                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 649                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 650                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 651                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 652                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 653                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 654                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 655                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 656                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 657                 { 0,                            0 },
 658         };
 659         int i;
 660
 661         for (i = 0; dspcode[i].reg != 0; i++)
 662                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 663         DELAY(40);
 664 }
 665
 666 static void
 667 bcm5411_load_dspcode(struct mii_softc *sc)
 668 {
 669         static const struct {
 670                 int             reg;
 671                 uint16_t        val;
 672         } dspcode[] = {
 673                 { 0x1c,                         0x8c23 },
 674                 { 0x1c,                         0x8ca3 },
 675                 { 0x1c,                         0x8c23 },
 676                 { 0,                            0 },
 677         };
 678         int i;
 679
 680         for (i = 0; dspcode[i].reg != 0; i++)
 681                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 682 }
 683
 684 void
 685 bcm54k2_load_dspcode(struct mii_softc *sc)
 686 {
 687         static const struct {
 688                 int             reg;
 689                 uint16_t        val;
 690         } dspcode[] = {
 691                 { 4,                            0x01e1 },
 692                 { 9,                            0x0300 },
 693                 { 0,                            0 },
 694         };
 695         int i;
 696
 697         for (i = 0; dspcode[i].reg != 0; i++)
 698                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 699
 700 }
 701
 702 static void
 703 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 704 {
 705         static const struct {
 706                 int             reg;
 707                 uint16_t        val;
 708         } dspcode[] = {
 709                 { 0x1c,                         0x8d68 },
 710                 { 0x1c,                         0x8d68 },
 711                 { 0,                            0 },
 712         };
 713         int i;
 714
 715         for (i = 0; dspcode[i].reg != 0; i++)
 716                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 717 }
 718
 719 static void
 720 brgphy_fixup_adc_bug(struct mii_softc *sc)
 721 {
 722         static const struct {
 723                 int             reg;
 724                 uint16_t        val;
 725         } dspcode[] = {
 726                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 727                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 728                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 729                 { 0,                            0 },
 730         };
 731         int i;
 732
 733         for (i = 0; dspcode[i].reg != 0; i++)
 734                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 735 }
 736
 737 static void
 738 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 739 {
 740         static const struct {
 741                 int             reg;
 742                 uint16_t        val;
 743         } dspcode[] = {
 744                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 745                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 746                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 747                 { BRGPHY_MII_TEST1,                     0x0014 },
 748                 { BRGPHY_MII_AUXCTL,            0x0400 },
 749                 { 0,                            0 },
 750         };
 751         int i;
 752
 753         for (i = 0; dspcode[i].reg != 0; i++)
 754                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 755 }
 756
 757 static void
 758 brgphy_fixup_ber_bug(struct mii_softc *sc)
 759 {
 760         static const struct {
 761                 int             reg;
 762                 uint16_t        val;
 763         } dspcode[] = {
 764                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 765                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 766                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 767                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 768                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 769                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 770                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 771                 { BRGPHY_MII_AUXCTL,            0x0400 },
 772                 { 0,                            0 },
 773         };
 774         int i;
 775
 776         for (i = 0; dspcode[i].reg != 0; i++)
 777                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 778 }
 779
 780 static void
 781 brgphy_fixup_crc_bug(struct mii_softc *sc)
 782 {
 783         static const struct {
 784                 int             reg;
 785                 uint16_t        val;
 786         } dspcode[] = {
 787                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 788                 { 0x1c,                         0x8c68 },
 789                 { 0x1c,                         0x8d68 },
 790                 { 0x1c,                         0x8c68 },
 791                 { 0,                            0 },
 792         };
 793         int i;
 794
 795         for (i = 0; dspcode[i].reg != 0; i++)
 796                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 797 }
 798
 799 static void
 800 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 801 {
 802         static const struct {
 803                 int             reg;
 804                 uint16_t        val;
 805         } dspcode[] = {
 806                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 807                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 808                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 809                 { BRGPHY_MII_AUXCTL,            0x0400 },
 810                 { 0,                            0 },
 811         };
 812         int i;
 813
 814         for (i = 0; dspcode[i].reg != 0; i++)
 815                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 816 }
 817
 818 static void
 819 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
 820 {
 821         uint32_t val;
 822
 823         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
 824         val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 825         val &= ~(1 << 8);
 826         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
 827
 828 }
 829
 830 static void
 831 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 832 {
 833         uint32_t        val;
 834
 835         /* Enable Ethernet@WireSpeed. */
 836         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 837         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 838         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 839 }
 840
 841 static void
 842 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 843 {
 844         uint32_t        val;
 845
 846         /* Set or clear jumbo frame settings in the PHY. */
 847         if (mtu > ETHER_MAX_LEN) {
 848                 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
 849                         /* BCM5401 PHY cannot read-modify-write. */
 850                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 851                 } else {
 852                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 853                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 854                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 855                             val | BRGPHY_AUXCTL_LONG_PKT);
 856                 }
 857
 858                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 859                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 860                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 861         } else {
 862                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 863                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 864                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 865                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 866
 867                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 868                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 869                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 870         }
 871 }
 872
 873 static void
 874 brgphy_reset(struct mii_softc *sc)
 875 {
 876         struct bge_softc *bge_sc = NULL;
 877         struct bce_softc *bce_sc = NULL;
 878         struct ifnet *ifp;
 879         int i, val;
 880
 881         /*
 882          * Perform a reset.  Note that at least some Broadcom PHYs default to
 883          * being powered down as well as isolated after a reset but don't work
 884          * if one or both of these bits are cleared.  However, they just work
 885          * fine if both bits remain set, so we don't use mii_phy_reset() here.
 886          */
 887         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
 888
 889         /* Wait 100ms for it to complete. */
 890         for (i = 0; i < 100; i++) {
 891                 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
 892                         break;
 893                 DELAY(1000);
 894         }
 895
 896         /* Handle any PHY specific procedures following the reset. */
 897         switch (sc->mii_mpd_oui) {
 898         case MII_OUI_BROADCOM:
 899                 switch (sc->mii_mpd_model) {
 900                 case MII_MODEL_BROADCOM_BCM5400:
 901                         bcm5401_load_dspcode(sc);
 902                         break;
 903                 case MII_MODEL_BROADCOM_BCM5401:
 904                         if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
 905                                 bcm5401_load_dspcode(sc);
 906                         break;
 907                 case MII_MODEL_BROADCOM_BCM5411:
 908                         bcm5411_load_dspcode(sc);
 909                         break;
 910                 case MII_MODEL_BROADCOM_BCM54K2:
 911                         bcm54k2_load_dspcode(sc);
 912                         break;
 913                 }
 914                 break;
 915         }
 916
 917         ifp = sc->mii_pdata->mii_ifp;
 918
 919         /* Find the driver associated with this PHY. */
 920         if (strcmp(ifp->if_dname, "bge") == 0)  {
 921                 bge_sc = ifp->if_softc;
 922         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 923                 bce_sc = ifp->if_softc;
 924         }
 925
 926         if (bge_sc) {
 927                 /* Fix up various bugs */
 928                 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
 929                         brgphy_fixup_5704_a0_bug(sc);
 930                 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
 931                         brgphy_fixup_adc_bug(sc);
 932                 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
 933                         brgphy_fixup_adjust_trim(sc);
 934                 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
 935                         brgphy_fixup_ber_bug(sc);
 936                 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
 937                         brgphy_fixup_crc_bug(sc);
 938                 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
 939                         brgphy_fixup_jitter_bug(sc);
 940
 941                 brgphy_jumbo_settings(sc, ifp->if_mtu);
 942
 943                 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
 944                         brgphy_ethernet_wirespeed(sc);
 945
 946                 /* Enable Link LED on Dell boxes */
 947                 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
 948                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 949                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
 950                             ~BRGPHY_PHY_EXTCTL_3_LED);
 951                 }
 952
 953                 /* Adjust output voltage (From Linux driver) */
 954                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
 955                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
 956         } else if (bce_sc) {
 957                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
 958                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
 959
 960                         /* Store autoneg capabilities/results in digital block (Page 0) */
 961                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
 962                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
 963                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
 964                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 965
 966                         /* Enable fiber mode and autodetection */
 967                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
 968                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
 969                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
 970                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
 971
 972                         /* Enable parallel detection */
 973                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
 974                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
 975                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
 976
 977                         /* Advertise 2.5G support through next page during autoneg */
 978                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 979                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
 980                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
 981                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
 982
 983                         /* Increase TX signal amplitude */
 984                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
 985                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
 986                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
 987                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 988                                         BRGPHY_5708S_TX_MISC_PG5);
 989                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
 990                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
 991                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 992                                         BRGPHY_5708S_DIG_PG0);
 993                         }
 994
 995                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
 996                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
 997                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
 998                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 999                                                 BRGPHY_5708S_TX_MISC_PG5);
1000                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1001                                                 bce_sc->bce_port_hw_cfg &
1002                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1003                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1004                                                 BRGPHY_5708S_DIG_PG0);
1005                         }
1006                 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1007                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1008
1009                         /* Select the SerDes Digital block of the AN MMD. */
1010                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1011                         val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1012                         val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1013                         val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1014                         PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1015
1016                         /* Select the Over 1G block of the AN MMD. */
1017                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1018
1019                         /* Enable autoneg "Next Page" to advertise 2.5G support. */
1020                         val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1021                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1022                                 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1023                         else
1024                                 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1025                         PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1026
1027                         /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1028                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1029
1030                         /* Enable MRBE speed autoneg. */
1031                         val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1032                         val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1033                             BRGPHY_MRBE_MSG_PG5_NP_T2;
1034                         PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1035
1036                         /* Select the Clause 73 User B0 block of the AN MMD. */
1037                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1038
1039                         /* Enable MRBE speed autoneg. */
1040                         PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1041                             BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1042                             BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1043                             BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1044
1045                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1046                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1047         } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1048                         if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1049                                 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1050                                 brgphy_fixup_disable_early_dac(sc);
1051
1052                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1053                         brgphy_ethernet_wirespeed(sc);
1054                 } else {
1055                         brgphy_fixup_ber_bug(sc);
1056                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1057                         brgphy_ethernet_wirespeed(sc);
1058                 }
1059         }
1060 }