2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/sysctl.h>
127 #include <sys/taskqueue.h>
130 #include <net/if_arp.h>
131 #include <net/ethernet.h>
132 #include <net/if_dl.h>
133 #include <net/if_media.h>
134 #include <net/if_types.h>
135 #include <net/if_vlan_var.h>
139 #include <machine/bus.h>
140 #include <machine/resource.h>
142 #include <sys/rman.h>
144 #include <dev/mii/mii.h>
145 #include <dev/mii/miivar.h>
147 #include <dev/pci/pcireg.h>
148 #include <dev/pci/pcivar.h>
150 #include <pci/if_rlreg.h>
152 MODULE_DEPEND(re, pci, 1, 1, 1);
153 MODULE_DEPEND(re, ether, 1, 1, 1);
154 MODULE_DEPEND(re, miibus, 1, 1, 1);
156 /* "device miibus" required. See GENERIC if you get errors here. */
157 #include "miibus_if.h"
160 static int intr_filter = 0;
161 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
162 static int msi_disable = 0;
163 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
164 static int msix_disable = 0;
165 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
166 static int prefer_iomap = 0;
167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
172 * Various supported device vendors/types and their names.
174 static struct rl_type re_devs[] = {
175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
179 { RT_VENDORID, RT_DEVICEID_8139, 0,
180 "RealTek 8139C+ 10/100BaseTX" },
181 { RT_VENDORID, RT_DEVICEID_8101E, 0,
182 "RealTek 810xE PCIe 10/100baseTX" },
183 { RT_VENDORID, RT_DEVICEID_8168, 0,
184 "RealTek 8168/8111 B/C/CP/D/DP/E PCIe Gigabit Ethernet" },
185 { RT_VENDORID, RT_DEVICEID_8169, 0,
186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
193 { USR_VENDORID, USR_DEVICEID_997902, 0,
194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
197 static struct rl_hwrev re_hwrevs[] = {
198 { RL_HWREV_8139, RL_8139, "", RL_MTU },
199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU },
200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU },
202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU },
203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU },
204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU },
215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU },
216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
223 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
224 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
225 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
226 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
227 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
228 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
229 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
230 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
231 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
232 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
236 static int re_probe (device_t);
237 static int re_attach (device_t);
238 static int re_detach (device_t);
240 static int re_encap (struct rl_softc *, struct mbuf **);
242 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
243 static int re_allocmem (device_t, struct rl_softc *);
244 static __inline void re_discard_rxbuf
245 (struct rl_softc *, int);
246 static int re_newbuf (struct rl_softc *, int);
247 static int re_jumbo_newbuf (struct rl_softc *, int);
248 static int re_rx_list_init (struct rl_softc *);
249 static int re_jrx_list_init (struct rl_softc *);
250 static int re_tx_list_init (struct rl_softc *);
252 static __inline void re_fixup_rx
255 static int re_rxeof (struct rl_softc *, int *);
256 static void re_txeof (struct rl_softc *);
257 #ifdef DEVICE_POLLING
258 static int re_poll (struct ifnet *, enum poll_cmd, int);
259 static int re_poll_locked (struct ifnet *, enum poll_cmd, int);
261 static int re_intr (void *);
262 static void re_intr_msi (void *);
263 static void re_tick (void *);
264 static void re_int_task (void *, int);
265 static void re_start (struct ifnet *);
266 static void re_start_locked (struct ifnet *);
267 static int re_ioctl (struct ifnet *, u_long, caddr_t);
268 static void re_init (void *);
269 static void re_init_locked (struct rl_softc *);
270 static void re_stop (struct rl_softc *);
271 static void re_watchdog (struct rl_softc *);
272 static int re_suspend (device_t);
273 static int re_resume (device_t);
274 static int re_shutdown (device_t);
275 static int re_ifmedia_upd (struct ifnet *);
276 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
278 static void re_eeprom_putbyte (struct rl_softc *, int);
279 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
280 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
281 static int re_gmii_readreg (device_t, int, int);
282 static int re_gmii_writereg (device_t, int, int, int);
284 static int re_miibus_readreg (device_t, int, int);
285 static int re_miibus_writereg (device_t, int, int, int);
286 static void re_miibus_statchg (device_t);
288 static void re_set_jumbo (struct rl_softc *, int);
289 static void re_set_rxmode (struct rl_softc *);
290 static void re_reset (struct rl_softc *);
291 static void re_setwol (struct rl_softc *);
292 static void re_clrwol (struct rl_softc *);
295 static int re_diag (struct rl_softc *);
298 static void re_add_sysctls (struct rl_softc *);
299 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS);
300 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int);
301 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS);
303 static device_method_t re_methods[] = {
304 /* Device interface */
305 DEVMETHOD(device_probe, re_probe),
306 DEVMETHOD(device_attach, re_attach),
307 DEVMETHOD(device_detach, re_detach),
308 DEVMETHOD(device_suspend, re_suspend),
309 DEVMETHOD(device_resume, re_resume),
310 DEVMETHOD(device_shutdown, re_shutdown),
313 DEVMETHOD(bus_print_child, bus_generic_print_child),
314 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
317 DEVMETHOD(miibus_readreg, re_miibus_readreg),
318 DEVMETHOD(miibus_writereg, re_miibus_writereg),
319 DEVMETHOD(miibus_statchg, re_miibus_statchg),
324 static driver_t re_driver = {
327 sizeof(struct rl_softc)
330 static devclass_t re_devclass;
332 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
333 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
336 CSR_WRITE_1(sc, RL_EECMD, \
337 CSR_READ_1(sc, RL_EECMD) | x)
340 CSR_WRITE_1(sc, RL_EECMD, \
341 CSR_READ_1(sc, RL_EECMD) & ~x)
344 * Send a read command and address to the EEPROM, check for ACK.
347 re_eeprom_putbyte(struct rl_softc *sc, int addr)
351 d = addr | (RL_9346_READ << sc->rl_eewidth);
354 * Feed in each bit and strobe the clock.
357 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
359 EE_SET(RL_EE_DATAIN);
361 EE_CLR(RL_EE_DATAIN);
372 * Read a word of data stored in the EEPROM at address 'addr.'
375 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
381 * Send address of word we want to read.
383 re_eeprom_putbyte(sc, addr);
386 * Start reading bits from EEPROM.
388 for (i = 0x8000; i; i >>= 1) {
391 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
401 * Read a sequence of words from the EEPROM.
404 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
407 u_int16_t word = 0, *ptr;
409 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
413 for (i = 0; i < cnt; i++) {
414 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
415 re_eeprom_getword(sc, off + i, &word);
416 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
417 ptr = (u_int16_t *)(dest + (i * 2));
421 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
425 re_gmii_readreg(device_t dev, int phy, int reg)
431 sc = device_get_softc(dev);
433 /* Let the rgephy driver read the GMEDIASTAT register */
435 if (reg == RL_GMEDIASTAT) {
436 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
440 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
442 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
443 rval = CSR_READ_4(sc, RL_PHYAR);
444 if (rval & RL_PHYAR_BUSY)
449 if (i == RL_PHY_TIMEOUT) {
450 device_printf(sc->rl_dev, "PHY read failed\n");
455 * Controller requires a 20us delay to process next MDIO request.
459 return (rval & RL_PHYAR_PHYDATA);
463 re_gmii_writereg(device_t dev, int phy, int reg, int data)
469 sc = device_get_softc(dev);
471 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
472 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
474 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
475 rval = CSR_READ_4(sc, RL_PHYAR);
476 if (!(rval & RL_PHYAR_BUSY))
481 if (i == RL_PHY_TIMEOUT) {
482 device_printf(sc->rl_dev, "PHY write failed\n");
487 * Controller requires a 20us delay to process next MDIO request.
495 re_miibus_readreg(device_t dev, int phy, int reg)
499 u_int16_t re8139_reg = 0;
501 sc = device_get_softc(dev);
503 if (sc->rl_type == RL_8169) {
504 rval = re_gmii_readreg(dev, phy, reg);
510 re8139_reg = RL_BMCR;
513 re8139_reg = RL_BMSR;
516 re8139_reg = RL_ANAR;
519 re8139_reg = RL_ANER;
522 re8139_reg = RL_LPAR;
528 * Allow the rlphy driver to read the media status
529 * register. If we have a link partner which does not
530 * support NWAY, this is the register which will tell
531 * us the results of parallel detection.
534 rval = CSR_READ_1(sc, RL_MEDIASTAT);
537 device_printf(sc->rl_dev, "bad phy register\n");
540 rval = CSR_READ_2(sc, re8139_reg);
541 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
542 /* 8139C+ has different bit layout. */
543 rval &= ~(BMCR_LOOP | BMCR_ISO);
549 re_miibus_writereg(device_t dev, int phy, int reg, int data)
552 u_int16_t re8139_reg = 0;
555 sc = device_get_softc(dev);
557 if (sc->rl_type == RL_8169) {
558 rval = re_gmii_writereg(dev, phy, reg, data);
564 re8139_reg = RL_BMCR;
565 if (sc->rl_type == RL_8139CPLUS) {
566 /* 8139C+ has different bit layout. */
567 data &= ~(BMCR_LOOP | BMCR_ISO);
571 re8139_reg = RL_BMSR;
574 re8139_reg = RL_ANAR;
577 re8139_reg = RL_ANER;
580 re8139_reg = RL_LPAR;
587 device_printf(sc->rl_dev, "bad phy register\n");
590 CSR_WRITE_2(sc, re8139_reg, data);
595 re_miibus_statchg(device_t dev)
599 struct mii_data *mii;
601 sc = device_get_softc(dev);
602 mii = device_get_softc(sc->rl_miibus);
604 if (mii == NULL || ifp == NULL ||
605 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
608 sc->rl_flags &= ~RL_FLAG_LINK;
609 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
610 (IFM_ACTIVE | IFM_AVALID)) {
611 switch (IFM_SUBTYPE(mii->mii_media_active)) {
614 sc->rl_flags |= RL_FLAG_LINK;
617 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
619 sc->rl_flags |= RL_FLAG_LINK;
626 * RealTek controllers does not provide any interface to
627 * Tx/Rx MACs for resolved speed, duplex and flow-control
633 * Set the RX configuration and 64-bit multicast hash filter.
636 re_set_rxmode(struct rl_softc *sc)
639 struct ifmultiaddr *ifma;
640 uint32_t hashes[2] = { 0, 0 };
647 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
649 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
650 if (ifp->if_flags & IFF_PROMISC)
651 rxfilt |= RL_RXCFG_RX_ALLPHYS;
653 * Unlike other hardwares, we have to explicitly set
654 * RL_RXCFG_RX_MULTI to receive multicast frames in
657 rxfilt |= RL_RXCFG_RX_MULTI;
658 hashes[0] = hashes[1] = 0xffffffff;
663 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
664 if (ifma->ifma_addr->sa_family != AF_LINK)
666 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
667 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
669 hashes[0] |= (1 << h);
671 hashes[1] |= (1 << (h - 32));
673 if_maddr_runlock(ifp);
675 if (hashes[0] != 0 || hashes[1] != 0) {
677 * For some unfathomable reason, RealTek decided to
678 * reverse the order of the multicast hash registers
679 * in the PCI Express parts. This means we have to
680 * write the hash pattern in reverse order for those
683 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
684 h = bswap32(hashes[0]);
685 hashes[0] = bswap32(hashes[1]);
688 rxfilt |= RL_RXCFG_RX_MULTI;
692 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
693 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
694 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
698 re_reset(struct rl_softc *sc)
704 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
706 for (i = 0; i < RL_TIMEOUT; i++) {
708 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
712 device_printf(sc->rl_dev, "reset never completed!\n");
714 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
715 CSR_WRITE_1(sc, 0x82, 1);
716 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
717 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
723 * The following routine is designed to test for a defect on some
724 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
725 * lines connected to the bus, however for a 32-bit only card, they
726 * should be pulled high. The result of this defect is that the
727 * NIC will not work right if you plug it into a 64-bit slot: DMA
728 * operations will be done with 64-bit transfers, which will fail
729 * because the 64-bit data lines aren't connected.
731 * There's no way to work around this (short of talking a soldering
732 * iron to the board), however we can detect it. The method we use
733 * here is to put the NIC into digital loopback mode, set the receiver
734 * to promiscuous mode, and then try to send a frame. We then compare
735 * the frame data we sent to what was received. If the data matches,
736 * then the NIC is working correctly, otherwise we know the user has
737 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
738 * slot. In the latter case, there's no way the NIC can work correctly,
739 * so we print out a message on the console and abort the device attach.
743 re_diag(struct rl_softc *sc)
745 struct ifnet *ifp = sc->rl_ifp;
747 struct ether_header *eh;
748 struct rl_desc *cur_rx;
751 int total_len, i, error = 0, phyaddr;
752 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
753 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
755 /* Allocate a single mbuf */
756 MGETHDR(m0, M_DONTWAIT, MT_DATA);
763 * Initialize the NIC in test mode. This sets the chip up
764 * so that it can send and receive frames, but performs the
765 * following special functions:
766 * - Puts receiver in promiscuous mode
767 * - Enables digital loopback mode
768 * - Leaves interrupts turned off
771 ifp->if_flags |= IFF_PROMISC;
773 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
775 sc->rl_flags |= RL_FLAG_LINK;
776 if (sc->rl_type == RL_8169)
781 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
782 for (i = 0; i < RL_TIMEOUT; i++) {
783 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
784 if (!(status & BMCR_RESET))
788 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
789 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
793 /* Put some data in the mbuf */
795 eh = mtod(m0, struct ether_header *);
796 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
797 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
798 eh->ether_type = htons(ETHERTYPE_IP);
799 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
802 * Queue the packet, start transmission.
803 * Note: IF_HANDOFF() ultimately calls re_start() for us.
806 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
808 /* XXX: re_diag must not be called when in ALTQ mode */
809 IF_HANDOFF(&ifp->if_snd, m0, ifp);
813 /* Wait for it to propagate through the chip */
816 for (i = 0; i < RL_TIMEOUT; i++) {
817 status = CSR_READ_2(sc, RL_ISR);
818 CSR_WRITE_2(sc, RL_ISR, status);
819 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
820 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
825 if (i == RL_TIMEOUT) {
826 device_printf(sc->rl_dev,
827 "diagnostic failed, failed to receive packet in"
834 * The packet should have been dumped into the first
835 * entry in the RX DMA ring. Grab it from there.
838 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
839 sc->rl_ldata.rl_rx_list_map,
840 BUS_DMASYNC_POSTREAD);
841 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
842 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
843 BUS_DMASYNC_POSTREAD);
844 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
845 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
847 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
848 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
849 eh = mtod(m0, struct ether_header *);
851 cur_rx = &sc->rl_ldata.rl_rx_list[0];
852 total_len = RL_RXBYTES(cur_rx);
853 rxstat = le32toh(cur_rx->rl_cmdstat);
855 if (total_len != ETHER_MIN_LEN) {
856 device_printf(sc->rl_dev,
857 "diagnostic failed, received short packet\n");
862 /* Test that the received packet data matches what we sent. */
864 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
865 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
866 ntohs(eh->ether_type) != ETHERTYPE_IP) {
867 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
868 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
869 dst, ":", src, ":", ETHERTYPE_IP);
870 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
871 eh->ether_dhost, ":", eh->ether_shost, ":",
872 ntohs(eh->ether_type));
873 device_printf(sc->rl_dev, "You may have a defective 32-bit "
874 "NIC plugged into a 64-bit PCI slot.\n");
875 device_printf(sc->rl_dev, "Please re-install the NIC in a "
876 "32-bit slot for proper operation.\n");
877 device_printf(sc->rl_dev, "Read the re(4) man page for more "
883 /* Turn interface off, release resources */
886 sc->rl_flags &= ~RL_FLAG_LINK;
887 ifp->if_flags &= ~IFF_PROMISC;
900 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
901 * IDs against our list and return a device name if we find a match.
904 re_probe(device_t dev)
907 uint16_t devid, vendor;
908 uint16_t revid, sdevid;
911 vendor = pci_get_vendor(dev);
912 devid = pci_get_device(dev);
913 revid = pci_get_revid(dev);
914 sdevid = pci_get_subdevice(dev);
916 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
917 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
919 * Only attach to rev. 3 of the Linksys EG1032 adapter.
920 * Rev. 2 is supported by sk(4).
926 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
928 /* 8139, let rl(4) take care of this device. */
934 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
935 if (vendor == t->rl_vid && devid == t->rl_did) {
936 device_set_desc(dev, t->rl_name);
937 return (BUS_PROBE_DEFAULT);
945 * Map a single buffer address.
949 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
956 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
958 *addr = segs->ds_addr;
962 re_allocmem(device_t dev, struct rl_softc *sc)
965 bus_size_t rx_list_size, tx_list_size;
969 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
970 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
973 * Allocate the parent bus DMA tag appropriate for PCI.
974 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
975 * register should be set. However some RealTek chips are known
976 * to be buggy on DAC handling, therefore disable DAC by limiting
977 * DMA address space to 32bit. PCIe variants of RealTek chips
978 * may not have the limitation.
980 lowaddr = BUS_SPACE_MAXADDR;
981 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
982 lowaddr = BUS_SPACE_MAXADDR_32BIT;
983 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
984 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
985 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
986 NULL, NULL, &sc->rl_parent_tag);
988 device_printf(dev, "could not allocate parent DMA tag\n");
993 * Allocate map for TX mbufs.
995 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
996 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
997 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
998 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1000 device_printf(dev, "could not allocate TX DMA tag\n");
1005 * Allocate map for RX mbufs.
1008 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1009 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1010 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1011 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
1012 &sc->rl_ldata.rl_jrx_mtag);
1015 "could not allocate jumbo RX DMA tag\n");
1019 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1020 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1021 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1023 device_printf(dev, "could not allocate RX DMA tag\n");
1028 * Allocate map for TX descriptor list.
1030 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1031 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1032 NULL, tx_list_size, 1, tx_list_size, 0,
1033 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1035 device_printf(dev, "could not allocate TX DMA ring tag\n");
1039 /* Allocate DMA'able memory for the TX ring */
1041 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1042 (void **)&sc->rl_ldata.rl_tx_list,
1043 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1044 &sc->rl_ldata.rl_tx_list_map);
1046 device_printf(dev, "could not allocate TX DMA ring\n");
1050 /* Load the map for the TX ring. */
1052 sc->rl_ldata.rl_tx_list_addr = 0;
1053 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1054 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1055 tx_list_size, re_dma_map_addr,
1056 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1057 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1058 device_printf(dev, "could not load TX DMA ring\n");
1062 /* Create DMA maps for TX buffers */
1064 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1065 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1066 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1068 device_printf(dev, "could not create DMA map for TX\n");
1074 * Allocate map for RX descriptor list.
1076 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1077 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1078 NULL, rx_list_size, 1, rx_list_size, 0,
1079 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1081 device_printf(dev, "could not create RX DMA ring tag\n");
1085 /* Allocate DMA'able memory for the RX ring */
1087 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1088 (void **)&sc->rl_ldata.rl_rx_list,
1089 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1090 &sc->rl_ldata.rl_rx_list_map);
1092 device_printf(dev, "could not allocate RX DMA ring\n");
1096 /* Load the map for the RX ring. */
1098 sc->rl_ldata.rl_rx_list_addr = 0;
1099 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1100 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1101 rx_list_size, re_dma_map_addr,
1102 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1103 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1104 device_printf(dev, "could not load RX DMA ring\n");
1108 /* Create DMA maps for RX buffers */
1110 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1111 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1112 &sc->rl_ldata.rl_jrx_sparemap);
1115 "could not create spare DMA map for jumbo RX\n");
1118 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1119 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1120 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1123 "could not create DMA map for jumbo RX\n");
1128 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1129 &sc->rl_ldata.rl_rx_sparemap);
1131 device_printf(dev, "could not create spare DMA map for RX\n");
1134 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1135 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1136 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1138 device_printf(dev, "could not create DMA map for RX\n");
1143 /* Create DMA map for statistics. */
1144 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1145 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1146 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1147 &sc->rl_ldata.rl_stag);
1149 device_printf(dev, "could not create statistics DMA tag\n");
1152 /* Allocate DMA'able memory for statistics. */
1153 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1154 (void **)&sc->rl_ldata.rl_stats,
1155 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1156 &sc->rl_ldata.rl_smap);
1159 "could not allocate statistics DMA memory\n");
1162 /* Load the map for statistics. */
1163 sc->rl_ldata.rl_stats_addr = 0;
1164 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1165 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1166 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1167 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1168 device_printf(dev, "could not load statistics DMA memory\n");
1176 * Attach the interface. Allocate softc structures, do ifmedia
1177 * setup and ethernet/BPF attach.
1180 re_attach(device_t dev)
1182 u_char eaddr[ETHER_ADDR_LEN];
1183 u_int16_t as[ETHER_ADDR_LEN / 2];
1184 struct rl_softc *sc;
1186 struct rl_hwrev *hw_rev;
1188 u_int16_t devid, re_did = 0;
1189 int error = 0, i, phy, rid;
1190 int msic, msixc, reg;
1193 sc = device_get_softc(dev);
1196 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1198 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1201 * Map control/status registers.
1203 pci_enable_busmaster(dev);
1205 devid = pci_get_device(dev);
1207 * Prefer memory space register mapping over IO space.
1208 * Because RTL8169SC does not seem to work when memory mapping
1209 * is used always activate io mapping.
1211 if (devid == RT_DEVICEID_8169SC)
1213 if (prefer_iomap == 0) {
1214 sc->rl_res_id = PCIR_BAR(1);
1215 sc->rl_res_type = SYS_RES_MEMORY;
1216 /* RTL8168/8101E seems to use different BARs. */
1217 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1218 sc->rl_res_id = PCIR_BAR(2);
1220 sc->rl_res_id = PCIR_BAR(0);
1221 sc->rl_res_type = SYS_RES_IOPORT;
1223 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1224 &sc->rl_res_id, RF_ACTIVE);
1225 if (sc->rl_res == NULL && prefer_iomap == 0) {
1226 sc->rl_res_id = PCIR_BAR(0);
1227 sc->rl_res_type = SYS_RES_IOPORT;
1228 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1229 &sc->rl_res_id, RF_ACTIVE);
1231 if (sc->rl_res == NULL) {
1232 device_printf(dev, "couldn't map ports/memory\n");
1237 sc->rl_btag = rman_get_bustag(sc->rl_res);
1238 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1240 msic = pci_msi_count(dev);
1241 msixc = pci_msix_count(dev);
1242 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0)
1243 sc->rl_flags |= RL_FLAG_PCIE;
1245 device_printf(dev, "MSI count : %d\n", msic);
1246 device_printf(dev, "MSI-X count : %d\n", msixc);
1248 if (msix_disable > 0)
1250 if (msi_disable > 0)
1252 /* Prefer MSI-X to MSI. */
1256 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1258 if (sc->rl_res_pba == NULL) {
1259 device_printf(sc->rl_dev,
1260 "could not allocate MSI-X PBA resource\n");
1262 if (sc->rl_res_pba != NULL &&
1263 pci_alloc_msix(dev, &msixc) == 0) {
1265 device_printf(dev, "Using %d MSI-X message\n",
1267 sc->rl_flags |= RL_FLAG_MSIX;
1269 pci_release_msi(dev);
1271 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1272 if (sc->rl_res_pba != NULL)
1273 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1275 sc->rl_res_pba = NULL;
1279 /* Prefer MSI to INTx. */
1280 if (msixc == 0 && msic > 0) {
1282 if (pci_alloc_msi(dev, &msic) == 0) {
1283 if (msic == RL_MSI_MESSAGES) {
1284 device_printf(dev, "Using %d MSI message\n",
1286 sc->rl_flags |= RL_FLAG_MSI;
1287 /* Explicitly set MSI enable bit. */
1288 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1289 cfg = CSR_READ_1(sc, RL_CFG2);
1291 CSR_WRITE_1(sc, RL_CFG2, cfg);
1292 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1294 pci_release_msi(dev);
1296 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1300 /* Allocate interrupt */
1301 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1303 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1304 RF_SHAREABLE | RF_ACTIVE);
1305 if (sc->rl_irq[0] == NULL) {
1306 device_printf(dev, "couldn't allocate IRQ resources\n");
1311 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1312 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1313 SYS_RES_IRQ, &rid, RF_ACTIVE);
1314 if (sc->rl_irq[i] == NULL) {
1316 "couldn't llocate IRQ resources for "
1317 "message %d\n", rid);
1324 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1325 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1326 cfg = CSR_READ_1(sc, RL_CFG2);
1327 if ((cfg & RL_CFG2_MSI) != 0) {
1328 device_printf(dev, "turning off MSI enable bit.\n");
1329 cfg &= ~RL_CFG2_MSI;
1330 CSR_WRITE_1(sc, RL_CFG2, cfg);
1332 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1336 hwrev = CSR_READ_4(sc, RL_TXCFG);
1337 switch (hwrev & 0x70000000) {
1340 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1341 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1344 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1345 hwrev &= RL_TXCFG_HWREV;
1348 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000);
1349 while (hw_rev->rl_desc != NULL) {
1350 if (hw_rev->rl_rev == hwrev) {
1351 sc->rl_type = hw_rev->rl_type;
1352 sc->rl_hwrev = hw_rev;
1357 if (hw_rev->rl_desc == NULL) {
1358 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1363 switch (hw_rev->rl_rev) {
1364 case RL_HWREV_8139CPLUS:
1365 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1367 case RL_HWREV_8100E:
1368 case RL_HWREV_8101E:
1369 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1371 case RL_HWREV_8102E:
1372 case RL_HWREV_8102EL:
1373 case RL_HWREV_8102EL_SPIN1:
1374 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1375 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1378 case RL_HWREV_8103E:
1379 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1380 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1381 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
1383 case RL_HWREV_8401E:
1384 case RL_HWREV_8105E:
1385 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1386 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1387 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1389 case RL_HWREV_8168B_SPIN1:
1390 case RL_HWREV_8168B_SPIN2:
1391 sc->rl_flags |= RL_FLAG_WOLRXENB;
1393 case RL_HWREV_8168B_SPIN3:
1394 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1396 case RL_HWREV_8168C_SPIN2:
1397 sc->rl_flags |= RL_FLAG_MACSLEEP;
1399 case RL_HWREV_8168C:
1400 if ((hwrev & 0x00700000) == 0x00200000)
1401 sc->rl_flags |= RL_FLAG_MACSLEEP;
1403 case RL_HWREV_8168CP:
1404 case RL_HWREV_8168D:
1405 case RL_HWREV_8168DP:
1406 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1407 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1408 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2;
1410 case RL_HWREV_8168E:
1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1412 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1413 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2;
1415 case RL_HWREV_8168E_VL:
1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1417 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1418 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2;
1420 case RL_HWREV_8169_8110SB:
1421 case RL_HWREV_8169_8110SBL:
1422 case RL_HWREV_8169_8110SC:
1423 case RL_HWREV_8169_8110SCE:
1424 sc->rl_flags |= RL_FLAG_PHYWAKE;
1427 case RL_HWREV_8169S:
1428 case RL_HWREV_8110S:
1429 sc->rl_flags |= RL_FLAG_MACRESET;
1435 /* Reset the adapter. */
1441 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1442 cfg = CSR_READ_1(sc, RL_CFG1);
1444 CSR_WRITE_1(sc, RL_CFG1, cfg);
1445 cfg = CSR_READ_1(sc, RL_CFG5);
1446 cfg &= RL_CFG5_PME_STS;
1447 CSR_WRITE_1(sc, RL_CFG5, cfg);
1448 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1450 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1452 * XXX Should have a better way to extract station
1453 * address from EEPROM.
1455 for (i = 0; i < ETHER_ADDR_LEN; i++)
1456 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1458 sc->rl_eewidth = RL_9356_ADDR_LEN;
1459 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1460 if (re_did != 0x8129)
1461 sc->rl_eewidth = RL_9346_ADDR_LEN;
1464 * Get station address from the EEPROM.
1466 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1467 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1468 as[i] = le16toh(as[i]);
1469 bcopy(as, eaddr, sizeof(eaddr));
1472 if (sc->rl_type == RL_8169) {
1473 /* Set RX length mask and number of descriptors. */
1474 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1475 sc->rl_txstart = RL_GTXSTART;
1476 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1477 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1479 /* Set RX length mask and number of descriptors. */
1480 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1481 sc->rl_txstart = RL_TXSTART;
1482 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1483 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1486 error = re_allocmem(dev, sc);
1491 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1493 device_printf(dev, "can not if_alloc()\n");
1498 /* Take controller out of deep sleep mode. */
1499 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1500 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1501 CSR_WRITE_1(sc, RL_GPIO,
1502 CSR_READ_1(sc, RL_GPIO) | 0x01);
1504 CSR_WRITE_1(sc, RL_GPIO,
1505 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1508 /* Take PHY out of power down mode. */
1509 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1510 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1511 if (hw_rev->rl_rev == RL_HWREV_8401E)
1512 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1514 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1515 re_gmii_writereg(dev, 1, 0x1f, 0);
1516 re_gmii_writereg(dev, 1, 0x0e, 0);
1519 #define RE_PHYAD_INTERNAL 0
1522 phy = RE_PHYAD_INTERNAL;
1523 if (sc->rl_type == RL_8169)
1525 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1526 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1528 device_printf(dev, "attaching PHYs failed\n");
1533 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1534 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1535 ifp->if_ioctl = re_ioctl;
1536 ifp->if_start = re_start;
1538 * RTL8168/8111C generates wrong IP checksummed frame if the
1539 * packet has IP options so disable TX IP checksum offloading.
1541 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1542 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2)
1543 ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
1545 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1546 ifp->if_hwassist |= CSUM_TSO;
1547 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1548 ifp->if_capenable = ifp->if_capabilities;
1549 ifp->if_init = re_init;
1550 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1551 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1552 IFQ_SET_READY(&ifp->if_snd);
1554 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1557 * Call MI attach routine.
1559 ether_ifattach(ifp, eaddr);
1561 /* VLAN capability setup */
1562 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1563 if (ifp->if_capabilities & IFCAP_HWCSUM)
1564 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1565 /* Enable WOL if PM is supported. */
1566 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0)
1567 ifp->if_capabilities |= IFCAP_WOL;
1568 ifp->if_capenable = ifp->if_capabilities;
1570 * Don't enable TSO by default. It is known to generate
1571 * corrupted TCP segments(bad TCP options) under certain
1574 ifp->if_hwassist &= ~CSUM_TSO;
1575 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1576 #ifdef DEVICE_POLLING
1577 ifp->if_capabilities |= IFCAP_POLLING;
1580 * Tell the upper layer(s) we support long frames.
1581 * Must appear after the call to ether_ifattach() because
1582 * ether_ifattach() sets ifi_hdrlen to the default value.
1584 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1588 * Perform hardware diagnostic on the original RTL8169.
1589 * Some 32-bit cards were incorrectly wired and would
1590 * malfunction if plugged into a 64-bit slot.
1593 if (hwrev == RL_HWREV_8169) {
1594 error = re_diag(sc);
1597 "attach aborted due to hardware diag failure\n");
1598 ether_ifdetach(ifp);
1604 #ifdef RE_TX_MODERATION
1607 /* Hook interrupt last to avoid having to lock softc */
1608 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1610 error = bus_setup_intr(dev, sc->rl_irq[0],
1611 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1612 &sc->rl_intrhand[0]);
1614 error = bus_setup_intr(dev, sc->rl_irq[0],
1615 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1616 &sc->rl_intrhand[0]);
1619 device_printf(dev, "couldn't set up irq\n");
1620 ether_ifdetach(ifp);
1632 * Shutdown hardware and free up resources. This can be called any
1633 * time after the mutex has been initialized. It is called in both
1634 * the error case in attach and the normal detach case so it needs
1635 * to be careful about only freeing resources that have actually been
1639 re_detach(device_t dev)
1641 struct rl_softc *sc;
1645 sc = device_get_softc(dev);
1647 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1649 /* These should only be active if attach succeeded */
1650 if (device_is_attached(dev)) {
1651 #ifdef DEVICE_POLLING
1652 if (ifp->if_capenable & IFCAP_POLLING)
1653 ether_poll_deregister(ifp);
1661 callout_drain(&sc->rl_stat_callout);
1662 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1664 * Force off the IFF_UP flag here, in case someone
1665 * still had a BPF descriptor attached to this
1666 * interface. If they do, ether_ifdetach() will cause
1667 * the BPF code to try and clear the promisc mode
1668 * flag, which will bubble down to re_ioctl(),
1669 * which will try to call re_init() again. This will
1670 * turn the NIC back on and restart the MII ticker,
1671 * which will panic the system when the kernel tries
1672 * to invoke the re_tick() function that isn't there
1675 ifp->if_flags &= ~IFF_UP;
1676 ether_ifdetach(ifp);
1679 device_delete_child(dev, sc->rl_miibus);
1680 bus_generic_detach(dev);
1683 * The rest is resource deallocation, so we should already be
1687 if (sc->rl_intrhand[0] != NULL) {
1688 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1689 sc->rl_intrhand[0] = NULL;
1693 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1697 if (sc->rl_irq[0] != NULL) {
1698 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1699 sc->rl_irq[0] = NULL;
1701 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1702 pci_release_msi(dev);
1703 if (sc->rl_res_pba) {
1705 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1708 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1711 /* Unload and free the RX DMA ring memory and map */
1713 if (sc->rl_ldata.rl_rx_list_tag) {
1714 if (sc->rl_ldata.rl_rx_list_map)
1715 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1716 sc->rl_ldata.rl_rx_list_map);
1717 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list)
1718 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1719 sc->rl_ldata.rl_rx_list,
1720 sc->rl_ldata.rl_rx_list_map);
1721 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1724 /* Unload and free the TX DMA ring memory and map */
1726 if (sc->rl_ldata.rl_tx_list_tag) {
1727 if (sc->rl_ldata.rl_tx_list_map)
1728 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1729 sc->rl_ldata.rl_tx_list_map);
1730 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list)
1731 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1732 sc->rl_ldata.rl_tx_list,
1733 sc->rl_ldata.rl_tx_list_map);
1734 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1737 /* Destroy all the RX and TX buffer maps */
1739 if (sc->rl_ldata.rl_tx_mtag) {
1740 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1741 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1742 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1743 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1745 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1747 if (sc->rl_ldata.rl_rx_mtag) {
1748 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1749 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1750 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1751 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1753 if (sc->rl_ldata.rl_rx_sparemap)
1754 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1755 sc->rl_ldata.rl_rx_sparemap);
1756 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1758 if (sc->rl_ldata.rl_jrx_mtag) {
1759 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1760 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1761 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1762 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1764 if (sc->rl_ldata.rl_jrx_sparemap)
1765 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1766 sc->rl_ldata.rl_jrx_sparemap);
1767 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1769 /* Unload and free the stats buffer and map */
1771 if (sc->rl_ldata.rl_stag) {
1772 if (sc->rl_ldata.rl_smap)
1773 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1774 sc->rl_ldata.rl_smap);
1775 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats)
1776 bus_dmamem_free(sc->rl_ldata.rl_stag,
1777 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1778 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1781 if (sc->rl_parent_tag)
1782 bus_dma_tag_destroy(sc->rl_parent_tag);
1784 mtx_destroy(&sc->rl_mtx);
1789 static __inline void
1790 re_discard_rxbuf(struct rl_softc *sc, int idx)
1792 struct rl_desc *desc;
1793 struct rl_rxdesc *rxd;
1796 if (sc->rl_ifp->if_mtu > RL_MTU &&
1797 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1798 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1800 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1801 desc = &sc->rl_ldata.rl_rx_list[idx];
1802 desc->rl_vlanctl = 0;
1803 cmdstat = rxd->rx_size;
1804 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1805 cmdstat |= RL_RDESC_CMD_EOR;
1806 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1810 re_newbuf(struct rl_softc *sc, int idx)
1813 struct rl_rxdesc *rxd;
1814 bus_dma_segment_t segs[1];
1816 struct rl_desc *desc;
1820 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1824 m->m_len = m->m_pkthdr.len = MCLBYTES;
1827 * This is part of an evil trick to deal with non-x86 platforms.
1828 * The RealTek chip requires RX buffers to be aligned on 64-bit
1829 * boundaries, but that will hose non-x86 machines. To get around
1830 * this, we leave some empty space at the start of each buffer
1831 * and for non-x86 hosts, we copy the buffer back six bytes
1832 * to achieve word alignment. This is slightly more efficient
1833 * than allocating a new buffer, copying the contents, and
1834 * discarding the old buffer.
1836 m_adj(m, RE_ETHER_ALIGN);
1838 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1839 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1844 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1846 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1847 if (rxd->rx_m != NULL) {
1848 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1849 BUS_DMASYNC_POSTREAD);
1850 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1854 map = rxd->rx_dmamap;
1855 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1856 rxd->rx_size = segs[0].ds_len;
1857 sc->rl_ldata.rl_rx_sparemap = map;
1858 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1859 BUS_DMASYNC_PREREAD);
1861 desc = &sc->rl_ldata.rl_rx_list[idx];
1862 desc->rl_vlanctl = 0;
1863 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1864 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1865 cmdstat = segs[0].ds_len;
1866 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1867 cmdstat |= RL_RDESC_CMD_EOR;
1868 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1874 re_jumbo_newbuf(struct rl_softc *sc, int idx)
1877 struct rl_rxdesc *rxd;
1878 bus_dma_segment_t segs[1];
1880 struct rl_desc *desc;
1884 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1887 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1889 m_adj(m, RE_ETHER_ALIGN);
1891 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
1892 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1897 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1899 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1900 if (rxd->rx_m != NULL) {
1901 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1902 BUS_DMASYNC_POSTREAD);
1903 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
1907 map = rxd->rx_dmamap;
1908 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
1909 rxd->rx_size = segs[0].ds_len;
1910 sc->rl_ldata.rl_jrx_sparemap = map;
1911 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1912 BUS_DMASYNC_PREREAD);
1914 desc = &sc->rl_ldata.rl_rx_list[idx];
1915 desc->rl_vlanctl = 0;
1916 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1917 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1918 cmdstat = segs[0].ds_len;
1919 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1920 cmdstat |= RL_RDESC_CMD_EOR;
1921 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1927 static __inline void
1928 re_fixup_rx(struct mbuf *m)
1931 uint16_t *src, *dst;
1933 src = mtod(m, uint16_t *);
1934 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1936 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1939 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1944 re_tx_list_init(struct rl_softc *sc)
1946 struct rl_desc *desc;
1951 bzero(sc->rl_ldata.rl_tx_list,
1952 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
1953 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
1954 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
1956 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
1957 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
1959 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1960 sc->rl_ldata.rl_tx_list_map,
1961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1963 sc->rl_ldata.rl_tx_prodidx = 0;
1964 sc->rl_ldata.rl_tx_considx = 0;
1965 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
1971 re_rx_list_init(struct rl_softc *sc)
1975 bzero(sc->rl_ldata.rl_rx_list,
1976 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
1977 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1978 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
1979 if ((error = re_newbuf(sc, i)) != 0)
1983 /* Flush the RX descriptors */
1985 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1986 sc->rl_ldata.rl_rx_list_map,
1987 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1989 sc->rl_ldata.rl_rx_prodidx = 0;
1990 sc->rl_head = sc->rl_tail = NULL;
1991 sc->rl_int_rx_act = 0;
1997 re_jrx_list_init(struct rl_softc *sc)
2001 bzero(sc->rl_ldata.rl_rx_list,
2002 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2003 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2004 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2005 if ((error = re_jumbo_newbuf(sc, i)) != 0)
2009 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2010 sc->rl_ldata.rl_rx_list_map,
2011 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2013 sc->rl_ldata.rl_rx_prodidx = 0;
2014 sc->rl_head = sc->rl_tail = NULL;
2015 sc->rl_int_rx_act = 0;
2021 * RX handler for C+ and 8169. For the gigE chips, we support
2022 * the reception of jumbo frames that have been fragmented
2023 * across multiple 2K mbuf cluster buffers.
2026 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2030 int i, rxerr, total_len;
2031 struct rl_desc *cur_rx;
2032 u_int32_t rxstat, rxvlan;
2033 int jumbo, maxpkt = 16, rx_npkts = 0;
2038 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2043 /* Invalidate the descriptor memory */
2045 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2046 sc->rl_ldata.rl_rx_list_map,
2047 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2049 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2050 i = RL_RX_DESC_NXT(sc, i)) {
2051 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2053 cur_rx = &sc->rl_ldata.rl_rx_list[i];
2054 rxstat = le32toh(cur_rx->rl_cmdstat);
2055 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2057 total_len = rxstat & sc->rl_rxlenmask;
2058 rxvlan = le32toh(cur_rx->rl_vlanctl);
2060 m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2062 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2064 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2065 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
2066 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
2068 * RTL8168C or later controllers do not
2069 * support multi-fragment packet.
2071 re_discard_rxbuf(sc, i);
2073 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2074 if (re_newbuf(sc, i) != 0) {
2076 * If this is part of a multi-fragment packet,
2077 * discard all the pieces.
2079 if (sc->rl_head != NULL) {
2080 m_freem(sc->rl_head);
2081 sc->rl_head = sc->rl_tail = NULL;
2083 re_discard_rxbuf(sc, i);
2086 m->m_len = RE_RX_DESC_BUFLEN;
2087 if (sc->rl_head == NULL)
2088 sc->rl_head = sc->rl_tail = m;
2090 m->m_flags &= ~M_PKTHDR;
2091 sc->rl_tail->m_next = m;
2098 * NOTE: for the 8139C+, the frame length field
2099 * is always 12 bits in size, but for the gigE chips,
2100 * it is 13 bits (since the max RX frame length is 16K).
2101 * Unfortunately, all 32 bits in the status word
2102 * were already used, so to make room for the extra
2103 * length bit, RealTek took out the 'frame alignment
2104 * error' bit and shifted the other status bits
2105 * over one slot. The OWN, EOR, FS and LS bits are
2106 * still in the same places. We have already extracted
2107 * the frame length and checked the OWN bit, so rather
2108 * than using an alternate bit mapping, we shift the
2109 * status bits one space to the right so we can evaluate
2110 * them using the 8169 status as though it was in the
2111 * same format as that of the 8139C+.
2113 if (sc->rl_type == RL_8169)
2117 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2118 * set, but if CRC is clear, it will still be a valid frame.
2120 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
2122 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2124 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
2129 * If this is part of a multi-fragment packet,
2130 * discard all the pieces.
2132 if (sc->rl_head != NULL) {
2133 m_freem(sc->rl_head);
2134 sc->rl_head = sc->rl_tail = NULL;
2136 re_discard_rxbuf(sc, i);
2142 * If allocating a replacement mbuf fails,
2143 * reload the current one.
2146 rxerr = re_jumbo_newbuf(sc, i);
2148 rxerr = re_newbuf(sc, i);
2151 if (sc->rl_head != NULL) {
2152 m_freem(sc->rl_head);
2153 sc->rl_head = sc->rl_tail = NULL;
2155 re_discard_rxbuf(sc, i);
2159 if (sc->rl_head != NULL) {
2161 m->m_len = total_len;
2163 m->m_len = total_len % RE_RX_DESC_BUFLEN;
2165 m->m_len = RE_RX_DESC_BUFLEN;
2168 * Special case: if there's 4 bytes or less
2169 * in this buffer, the mbuf can be discarded:
2170 * the last 4 bytes is the CRC, which we don't
2171 * care about anyway.
2173 if (m->m_len <= ETHER_CRC_LEN) {
2174 sc->rl_tail->m_len -=
2175 (ETHER_CRC_LEN - m->m_len);
2178 m->m_len -= ETHER_CRC_LEN;
2179 m->m_flags &= ~M_PKTHDR;
2180 sc->rl_tail->m_next = m;
2183 sc->rl_head = sc->rl_tail = NULL;
2184 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2186 m->m_pkthdr.len = m->m_len =
2187 (total_len - ETHER_CRC_LEN);
2193 m->m_pkthdr.rcvif = ifp;
2195 /* Do RX checksumming if enabled */
2197 if (ifp->if_capenable & IFCAP_RXCSUM) {
2198 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2199 /* Check IP header checksum */
2200 if (rxstat & RL_RDESC_STAT_PROTOID)
2201 m->m_pkthdr.csum_flags |=
2203 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2204 m->m_pkthdr.csum_flags |=
2207 /* Check TCP/UDP checksum */
2208 if ((RL_TCPPKT(rxstat) &&
2209 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2210 (RL_UDPPKT(rxstat) &&
2211 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2212 m->m_pkthdr.csum_flags |=
2213 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2214 m->m_pkthdr.csum_data = 0xffff;
2218 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2220 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2221 (rxvlan & RL_RDESC_IPV4))
2222 m->m_pkthdr.csum_flags |=
2224 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2225 (rxvlan & RL_RDESC_IPV4))
2226 m->m_pkthdr.csum_flags |=
2228 if (((rxstat & RL_RDESC_STAT_TCP) &&
2229 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2230 ((rxstat & RL_RDESC_STAT_UDP) &&
2231 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2232 m->m_pkthdr.csum_flags |=
2233 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2234 m->m_pkthdr.csum_data = 0xffff;
2239 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2240 m->m_pkthdr.ether_vtag =
2241 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2242 m->m_flags |= M_VLANTAG;
2245 (*ifp->if_input)(ifp, m);
2250 /* Flush the RX DMA ring */
2252 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2253 sc->rl_ldata.rl_rx_list_map,
2254 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2256 sc->rl_ldata.rl_rx_prodidx = i;
2258 if (rx_npktsp != NULL)
2259 *rx_npktsp = rx_npkts;
2267 re_txeof(struct rl_softc *sc)
2270 struct rl_txdesc *txd;
2274 cons = sc->rl_ldata.rl_tx_considx;
2275 if (cons == sc->rl_ldata.rl_tx_prodidx)
2279 /* Invalidate the TX descriptor list */
2280 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2281 sc->rl_ldata.rl_tx_list_map,
2282 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2284 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2285 cons = RL_TX_DESC_NXT(sc, cons)) {
2286 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2287 if (txstat & RL_TDESC_STAT_OWN)
2290 * We only stash mbufs in the last descriptor
2291 * in a fragment chain, which also happens to
2292 * be the only place where the TX status bits
2295 if (txstat & RL_TDESC_CMD_EOF) {
2296 txd = &sc->rl_ldata.rl_tx_desc[cons];
2297 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2298 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2299 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2301 KASSERT(txd->tx_m != NULL,
2302 ("%s: freeing NULL mbufs!", __func__));
2305 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2306 RL_TDESC_STAT_COLCNT))
2307 ifp->if_collisions++;
2308 if (txstat & RL_TDESC_STAT_TXERRSUM)
2313 sc->rl_ldata.rl_tx_free++;
2314 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2316 sc->rl_ldata.rl_tx_considx = cons;
2318 /* No changes made to the TX ring, so no flush needed */
2320 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2321 #ifdef RE_TX_MODERATION
2323 * If not all descriptors have been reaped yet, reload
2324 * the timer so that we will eventually get another
2325 * interrupt that will cause us to re-enter this routine.
2326 * This is done in case the transmitter has gone idle.
2328 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2331 sc->rl_watchdog_timer = 0;
2337 struct rl_softc *sc;
2338 struct mii_data *mii;
2344 mii = device_get_softc(sc->rl_miibus);
2346 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2347 re_miibus_statchg(sc->rl_dev);
2349 * Reclaim transmitted frames here. Technically it is not
2350 * necessary to do here but it ensures periodic reclamation
2351 * regardless of Tx completion interrupt which seems to be
2352 * lost on PCIe based controllers under certain situations.
2356 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2359 #ifdef DEVICE_POLLING
2361 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2363 struct rl_softc *sc = ifp->if_softc;
2367 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2368 rx_npkts = re_poll_locked(ifp, cmd, count);
2374 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2376 struct rl_softc *sc = ifp->if_softc;
2381 sc->rxcycles = count;
2382 re_rxeof(sc, &rx_npkts);
2385 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2386 re_start_locked(ifp);
2388 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2391 status = CSR_READ_2(sc, RL_ISR);
2392 if (status == 0xffff)
2395 CSR_WRITE_2(sc, RL_ISR, status);
2396 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2397 (sc->rl_flags & RL_FLAG_PCIE))
2398 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2401 * XXX check behaviour on receiver stalls.
2404 if (status & RL_ISR_SYSTEM_ERR) {
2405 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2411 #endif /* DEVICE_POLLING */
2416 struct rl_softc *sc;
2421 status = CSR_READ_2(sc, RL_ISR);
2422 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2423 return (FILTER_STRAY);
2424 CSR_WRITE_2(sc, RL_IMR, 0);
2426 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2428 return (FILTER_HANDLED);
2432 re_int_task(void *arg, int npending)
2434 struct rl_softc *sc;
2444 status = CSR_READ_2(sc, RL_ISR);
2445 CSR_WRITE_2(sc, RL_ISR, status);
2447 if (sc->suspended ||
2448 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2453 #ifdef DEVICE_POLLING
2454 if (ifp->if_capenable & IFCAP_POLLING) {
2460 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2461 rval = re_rxeof(sc, NULL);
2464 * Some chips will ignore a second TX request issued
2465 * while an existing transmission is in progress. If
2466 * the transmitter goes idle but there are still
2467 * packets waiting to be sent, we need to restart the
2468 * channel here to flush them out. This only seems to
2469 * be required with the PCIe devices.
2471 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2472 (sc->rl_flags & RL_FLAG_PCIE))
2473 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2475 #ifdef RE_TX_MODERATION
2476 RL_ISR_TIMEOUT_EXPIRED|
2480 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2483 if (status & RL_ISR_SYSTEM_ERR) {
2484 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2488 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2489 re_start_locked(ifp);
2493 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2494 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2498 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2502 re_intr_msi(void *xsc)
2504 struct rl_softc *sc;
2506 uint16_t intrs, status;
2512 #ifdef DEVICE_POLLING
2513 if (ifp->if_capenable & IFCAP_POLLING) {
2518 /* Disable interrupts. */
2519 CSR_WRITE_2(sc, RL_IMR, 0);
2520 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2525 intrs = RL_INTRS_CPLUS;
2526 status = CSR_READ_2(sc, RL_ISR);
2527 CSR_WRITE_2(sc, RL_ISR, status);
2528 if (sc->rl_int_rx_act > 0) {
2529 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2531 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2535 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2536 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2538 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2539 if (sc->rl_int_rx_mod != 0 &&
2540 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2541 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2542 /* Rearm one-shot timer. */
2543 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2544 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2545 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2546 sc->rl_int_rx_act = 1;
2548 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2549 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2550 sc->rl_int_rx_act = 0;
2556 * Some chips will ignore a second TX request issued
2557 * while an existing transmission is in progress. If
2558 * the transmitter goes idle but there are still
2559 * packets waiting to be sent, we need to restart the
2560 * channel here to flush them out. This only seems to
2561 * be required with the PCIe devices.
2563 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2564 (sc->rl_flags & RL_FLAG_PCIE))
2565 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2566 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2569 if (status & RL_ISR_SYSTEM_ERR) {
2570 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2574 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2575 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2576 re_start_locked(ifp);
2577 CSR_WRITE_2(sc, RL_IMR, intrs);
2583 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2585 struct rl_txdesc *txd, *txd_last;
2586 bus_dma_segment_t segs[RL_NTXSEGS];
2589 struct rl_desc *desc;
2591 int i, error, ei, si;
2593 uint32_t cmdstat, csum_flags, vlanctl;
2596 M_ASSERTPKTHDR((*m_head));
2599 * With some of the RealTek chips, using the checksum offload
2600 * support in conjunction with the autopadding feature results
2601 * in the transmission of corrupt frames. For example, if we
2602 * need to send a really small IP fragment that's less than 60
2603 * bytes in size, and IP header checksumming is enabled, the
2604 * resulting ethernet frame that appears on the wire will
2605 * have garbled payload. To work around this, if TX IP checksum
2606 * offload is enabled, we always manually pad short frames out
2607 * to the minimum ethernet frame size.
2609 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2610 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2611 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2612 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2613 if (M_WRITABLE(*m_head) == 0) {
2614 /* Get a writable copy. */
2615 m_new = m_dup(*m_head, M_DONTWAIT);
2617 if (m_new == NULL) {
2623 if ((*m_head)->m_next != NULL ||
2624 M_TRAILINGSPACE(*m_head) < padlen) {
2625 m_new = m_defrag(*m_head, M_DONTWAIT);
2626 if (m_new == NULL) {
2635 * Manually pad short frames, and zero the pad space
2636 * to avoid leaking data.
2638 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2639 m_new->m_pkthdr.len += padlen;
2640 m_new->m_len = m_new->m_pkthdr.len;
2644 prod = sc->rl_ldata.rl_tx_prodidx;
2645 txd = &sc->rl_ldata.rl_tx_desc[prod];
2646 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2647 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2648 if (error == EFBIG) {
2649 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS);
2650 if (m_new == NULL) {
2656 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2657 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2663 } else if (error != 0)
2671 /* Check for number of available descriptors. */
2672 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2673 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2677 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2678 BUS_DMASYNC_PREWRITE);
2681 * Set up checksum offload. Note: checksum offload bits must
2682 * appear in all descriptors of a multi-descriptor transmit
2683 * attempt. This is according to testing done with an 8169
2684 * chip. This is a requirement.
2688 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2689 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2690 csum_flags |= RL_TDESC_CMD_LGSEND;
2691 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2692 RL_TDESC_CMD_MSSVALV2_SHIFT);
2694 csum_flags |= RL_TDESC_CMD_LGSEND |
2695 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2696 RL_TDESC_CMD_MSSVAL_SHIFT);
2700 * Unconditionally enable IP checksum if TCP or UDP
2701 * checksum is required. Otherwise, TCP/UDP checksum
2702 * does't make effects.
2704 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2705 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2706 csum_flags |= RL_TDESC_CMD_IPCSUM;
2707 if (((*m_head)->m_pkthdr.csum_flags &
2709 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2710 if (((*m_head)->m_pkthdr.csum_flags &
2712 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2714 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2715 if (((*m_head)->m_pkthdr.csum_flags &
2717 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2718 if (((*m_head)->m_pkthdr.csum_flags &
2720 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2726 * Set up hardware VLAN tagging. Note: vlan tag info must
2727 * appear in all descriptors of a multi-descriptor
2728 * transmission attempt.
2730 if ((*m_head)->m_flags & M_VLANTAG)
2731 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2732 RL_TDESC_VLANCTL_TAG;
2735 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2736 desc = &sc->rl_ldata.rl_tx_list[prod];
2737 desc->rl_vlanctl = htole32(vlanctl);
2738 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2739 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2740 cmdstat = segs[i].ds_len;
2742 cmdstat |= RL_TDESC_CMD_OWN;
2743 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2744 cmdstat |= RL_TDESC_CMD_EOR;
2745 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2746 sc->rl_ldata.rl_tx_free--;
2748 /* Update producer index. */
2749 sc->rl_ldata.rl_tx_prodidx = prod;
2751 /* Set EOF on the last descriptor. */
2752 ei = RL_TX_DESC_PRV(sc, prod);
2753 desc = &sc->rl_ldata.rl_tx_list[ei];
2754 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2756 desc = &sc->rl_ldata.rl_tx_list[si];
2757 /* Set SOF and transfer ownership of packet to the chip. */
2758 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2761 * Insure that the map for this transmission
2762 * is placed at the array index of the last descriptor
2763 * in this chain. (Swap last and first dmamaps.)
2765 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2766 map = txd->tx_dmamap;
2767 txd->tx_dmamap = txd_last->tx_dmamap;
2768 txd_last->tx_dmamap = map;
2769 txd_last->tx_m = *m_head;
2775 re_start(struct ifnet *ifp)
2777 struct rl_softc *sc;
2781 re_start_locked(ifp);
2786 * Main transmit routine for C+ and gigE NICs.
2789 re_start_locked(struct ifnet *ifp)
2791 struct rl_softc *sc;
2792 struct mbuf *m_head;
2797 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2798 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2801 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2802 sc->rl_ldata.rl_tx_free > 1;) {
2803 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2807 if (re_encap(sc, &m_head) != 0) {
2810 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2811 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2816 * If there's a BPF listener, bounce a copy of this frame
2819 ETHER_BPF_MTAP(ifp, m_head);
2825 #ifdef RE_TX_MODERATION
2826 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2827 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2832 /* Flush the TX descriptors */
2834 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2835 sc->rl_ldata.rl_tx_list_map,
2836 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2838 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2840 #ifdef RE_TX_MODERATION
2842 * Use the countdown timer for interrupt moderation.
2843 * 'TX done' interrupts are disabled. Instead, we reset the
2844 * countdown timer, which will begin counting until it hits
2845 * the value in the TIMERINT register, and then trigger an
2846 * interrupt. Each time we write to the TIMERCNT register,
2847 * the timer count is reset to 0.
2849 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2853 * Set a timeout in case the chip goes out to lunch.
2855 sc->rl_watchdog_timer = 5;
2859 re_set_jumbo(struct rl_softc *sc, int jumbo)
2862 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
2863 pci_set_max_read_req(sc->rl_dev, 4096);
2867 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2869 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) |
2871 switch (sc->rl_hwrev->rl_rev) {
2872 case RL_HWREV_8168DP:
2874 case RL_HWREV_8168E:
2875 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
2879 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
2883 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) &
2884 ~RL_CFG3_JUMBO_EN0);
2885 switch (sc->rl_hwrev->rl_rev) {
2886 case RL_HWREV_8168DP:
2888 case RL_HWREV_8168E:
2889 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) &
2893 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) &
2894 ~RL_CFG4_JUMBO_EN1);
2897 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2899 switch (sc->rl_hwrev->rl_rev) {
2900 case RL_HWREV_8168DP:
2901 pci_set_max_read_req(sc->rl_dev, 4096);
2905 pci_set_max_read_req(sc->rl_dev, 512);
2907 pci_set_max_read_req(sc->rl_dev, 4096);
2914 struct rl_softc *sc = xsc;
2922 re_init_locked(struct rl_softc *sc)
2924 struct ifnet *ifp = sc->rl_ifp;
2925 struct mii_data *mii;
2929 uint32_t align_dummy;
2930 u_char eaddr[ETHER_ADDR_LEN];
2935 mii = device_get_softc(sc->rl_miibus);
2937 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2941 * Cancel pending I/O and free all RX/TX buffers.
2945 /* Put controller into known state. */
2949 * For C+ mode, initialize the RX descriptors and mbufs.
2951 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
2952 if (ifp->if_mtu > RL_MTU) {
2953 if (re_jrx_list_init(sc) != 0) {
2954 device_printf(sc->rl_dev,
2955 "no memory for jumbo RX buffers\n");
2959 /* Disable checksum offloading for jumbo frames. */
2960 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
2961 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
2963 if (re_rx_list_init(sc) != 0) {
2964 device_printf(sc->rl_dev,
2965 "no memory for RX buffers\n");
2970 re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
2972 if (re_rx_list_init(sc) != 0) {
2973 device_printf(sc->rl_dev, "no memory for RX buffers\n");
2977 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
2978 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
2979 if (ifp->if_mtu > RL_MTU)
2980 pci_set_max_read_req(sc->rl_dev, 512);
2982 pci_set_max_read_req(sc->rl_dev, 4096);
2985 re_tx_list_init(sc);
2988 * Enable C+ RX and TX mode, as well as VLAN stripping and
2989 * RX checksum offload. We must configure the C+ register
2990 * before all others.
2992 cfg = RL_CPLUSCMD_PCI_MRW;
2993 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2994 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
2995 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2996 cfg |= RL_CPLUSCMD_VLANSTRIP;
2997 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
2998 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3002 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3003 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3004 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3005 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3007 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0)
3009 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3011 CSR_WRITE_4(sc, 0x7c, reg);
3012 /* Disable interrupt mitigation. */
3013 CSR_WRITE_2(sc, 0xe2, 0);
3016 * Disable TSO if interface MTU size is greater than MSS
3017 * allowed in controller.
3019 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3020 ifp->if_capenable &= ~IFCAP_TSO4;
3021 ifp->if_hwassist &= ~CSUM_TSO;
3025 * Init our MAC address. Even though the chipset
3026 * documentation doesn't mention it, we need to enter "Config
3027 * register write enable" mode to modify the ID registers.
3029 /* Copy MAC address on stack to align. */
3030 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3031 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3032 CSR_WRITE_4(sc, RL_IDR0,
3033 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3034 CSR_WRITE_4(sc, RL_IDR4,
3035 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3036 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3039 * Load the addresses of the RX and TX lists into the chip.
3042 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3043 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3044 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3045 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3047 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3048 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3049 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3050 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3053 * Enable transmit and receive.
3055 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3058 * Set the initial TX configuration.
3060 if (sc->rl_testmode) {
3061 if (sc->rl_type == RL_8169)
3062 CSR_WRITE_4(sc, RL_TXCFG,
3063 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3065 CSR_WRITE_4(sc, RL_TXCFG,
3066 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3068 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3070 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3073 * Set the initial RX configuration.
3077 /* Configure interrupt moderation. */
3078 if (sc->rl_type == RL_8169) {
3079 /* Magic from vendor. */
3080 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3083 #ifdef DEVICE_POLLING
3085 * Disable interrupts if we are polling.
3087 if (ifp->if_capenable & IFCAP_POLLING)
3088 CSR_WRITE_2(sc, RL_IMR, 0);
3089 else /* otherwise ... */
3093 * Enable interrupts.
3095 if (sc->rl_testmode)
3096 CSR_WRITE_2(sc, RL_IMR, 0);
3098 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3099 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3101 /* Set initial TX threshold */
3102 sc->rl_txthresh = RL_TX_THRESH_INIT;
3104 /* Start RX/TX process. */
3105 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3107 /* Enable receiver and transmitter. */
3108 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3112 * Initialize the timer interrupt register so that
3113 * a timer interrupt will be generated once the timer
3114 * reaches a certain number of ticks. The timer is
3115 * reloaded on each transmit.
3117 #ifdef RE_TX_MODERATION
3119 * Use timer interrupt register to moderate TX interrupt
3120 * moderation, which dramatically improves TX frame rate.
3122 if (sc->rl_type == RL_8169)
3123 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3125 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3128 * Use timer interrupt register to moderate RX interrupt
3131 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3133 if (sc->rl_type == RL_8169)
3134 CSR_WRITE_4(sc, RL_TIMERINT_8169,
3135 RL_USECS(sc->rl_int_rx_mod));
3137 if (sc->rl_type == RL_8169)
3138 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3143 * For 8169 gigE NICs, set the max allowed RX packet
3144 * size so we can receive jumbo frames.
3146 if (sc->rl_type == RL_8169) {
3147 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3149 * For controllers that use new jumbo frame scheme,
3150 * set maximum size of jumbo frame depedning on
3151 * controller revisions.
3153 if (ifp->if_mtu > RL_MTU)
3154 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3155 sc->rl_hwrev->rl_max_mtu +
3156 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
3159 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3161 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3162 sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3163 /* RTL810x has no jumbo frame support. */
3164 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3166 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3169 if (sc->rl_testmode)
3174 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
3176 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3177 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3179 sc->rl_flags &= ~RL_FLAG_LINK;
3180 sc->rl_watchdog_timer = 0;
3181 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3185 * Set media options.
3188 re_ifmedia_upd(struct ifnet *ifp)
3190 struct rl_softc *sc;
3191 struct mii_data *mii;
3195 mii = device_get_softc(sc->rl_miibus);
3197 error = mii_mediachg(mii);
3204 * Report current media status.
3207 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3209 struct rl_softc *sc;
3210 struct mii_data *mii;
3213 mii = device_get_softc(sc->rl_miibus);
3218 ifmr->ifm_active = mii->mii_media_active;
3219 ifmr->ifm_status = mii->mii_media_status;
3223 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3225 struct rl_softc *sc = ifp->if_softc;
3226 struct ifreq *ifr = (struct ifreq *) data;
3227 struct mii_data *mii;
3233 if (ifr->ifr_mtu < ETHERMIN ||
3234 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) {
3239 if (ifp->if_mtu != ifr->ifr_mtu) {
3240 ifp->if_mtu = ifr->ifr_mtu;
3241 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3242 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3243 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3246 if (ifp->if_mtu > RL_TSO_MTU &&
3247 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3248 ifp->if_capenable &= ~(IFCAP_TSO4 |
3250 ifp->if_hwassist &= ~CSUM_TSO;
3252 VLAN_CAPABILITIES(ifp);
3258 if ((ifp->if_flags & IFF_UP) != 0) {
3259 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3260 if (((ifp->if_flags ^ sc->rl_if_flags)
3261 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3266 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3269 sc->rl_if_flags = ifp->if_flags;
3275 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3281 mii = device_get_softc(sc->rl_miibus);
3282 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3288 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3290 #ifdef DEVICE_POLLING
3291 if (mask & IFCAP_POLLING) {
3292 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3293 error = ether_poll_register(re_poll, ifp);
3297 /* Disable interrupts */
3298 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3299 ifp->if_capenable |= IFCAP_POLLING;
3302 error = ether_poll_deregister(ifp);
3303 /* Enable interrupts. */
3305 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3306 ifp->if_capenable &= ~IFCAP_POLLING;
3310 #endif /* DEVICE_POLLING */
3311 if ((mask & IFCAP_TXCSUM) != 0 &&
3312 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3313 ifp->if_capenable ^= IFCAP_TXCSUM;
3314 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) {
3315 rev = sc->rl_hwrev->rl_rev;
3316 if (rev == RL_HWREV_8168C ||
3317 rev == RL_HWREV_8168C_SPIN2)
3318 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
3320 ifp->if_hwassist |= RE_CSUM_FEATURES;
3322 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3325 if ((mask & IFCAP_RXCSUM) != 0 &&
3326 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3327 ifp->if_capenable ^= IFCAP_RXCSUM;
3330 if ((mask & IFCAP_TSO4) != 0 &&
3331 (ifp->if_capabilities & IFCAP_TSO) != 0) {
3332 ifp->if_capenable ^= IFCAP_TSO4;
3333 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3334 ifp->if_hwassist |= CSUM_TSO;
3336 ifp->if_hwassist &= ~CSUM_TSO;
3337 if (ifp->if_mtu > RL_TSO_MTU &&
3338 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3339 ifp->if_capenable &= ~IFCAP_TSO4;
3340 ifp->if_hwassist &= ~CSUM_TSO;
3343 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3344 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3345 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3346 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3347 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3348 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3349 /* TSO over VLAN requires VLAN hardware tagging. */
3350 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3351 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3354 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3355 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
3356 IFCAP_VLAN_HWTSO)) != 0)
3358 if ((mask & IFCAP_WOL) != 0 &&
3359 (ifp->if_capabilities & IFCAP_WOL) != 0) {
3360 if ((mask & IFCAP_WOL_UCAST) != 0)
3361 ifp->if_capenable ^= IFCAP_WOL_UCAST;
3362 if ((mask & IFCAP_WOL_MCAST) != 0)
3363 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3364 if ((mask & IFCAP_WOL_MAGIC) != 0)
3365 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3367 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
3368 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3371 VLAN_CAPABILITIES(ifp);
3375 error = ether_ioctl(ifp, command, data);
3383 re_watchdog(struct rl_softc *sc)
3389 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3394 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3395 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3397 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3398 re_start_locked(ifp);
3402 if_printf(ifp, "watchdog timeout\n");
3406 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3408 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3409 re_start_locked(ifp);
3413 * Stop the adapter and free any mbufs allocated to the
3417 re_stop(struct rl_softc *sc)
3421 struct rl_txdesc *txd;
3422 struct rl_rxdesc *rxd;
3428 sc->rl_watchdog_timer = 0;
3429 callout_stop(&sc->rl_stat_callout);
3430 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3432 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0)
3433 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3436 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3438 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3439 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3441 if (sc->rl_head != NULL) {
3442 m_freem(sc->rl_head);
3443 sc->rl_head = sc->rl_tail = NULL;
3446 /* Free the TX list buffers. */
3448 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3449 txd = &sc->rl_ldata.rl_tx_desc[i];
3450 if (txd->tx_m != NULL) {
3451 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3452 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3453 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3460 /* Free the RX list buffers. */
3462 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3463 rxd = &sc->rl_ldata.rl_rx_desc[i];
3464 if (rxd->rx_m != NULL) {
3465 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3466 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3467 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3476 * Device suspend routine. Stop the interface and save some PCI
3477 * settings in case the BIOS doesn't restore them properly on
3481 re_suspend(device_t dev)
3483 struct rl_softc *sc;
3485 sc = device_get_softc(dev);
3497 * Device resume routine. Restore some PCI settings in case the BIOS
3498 * doesn't, re-enable busmastering, and restart the interface if
3502 re_resume(device_t dev)
3504 struct rl_softc *sc;
3507 sc = device_get_softc(dev);
3512 /* Take controller out of sleep mode. */
3513 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3514 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3515 CSR_WRITE_1(sc, RL_GPIO,
3516 CSR_READ_1(sc, RL_GPIO) | 0x01);
3520 * Clear WOL matching such that normal Rx filtering
3521 * wouldn't interfere with WOL patterns.
3525 /* reinitialize interface if necessary */
3526 if (ifp->if_flags & IFF_UP)
3536 * Stop all chip I/O so that the kernel's probe routines don't
3537 * get confused by errant DMAs when rebooting.
3540 re_shutdown(device_t dev)
3542 struct rl_softc *sc;
3544 sc = device_get_softc(dev);
3549 * Mark interface as down since otherwise we will panic if
3550 * interrupt comes in later on, which can happen in some
3553 sc->rl_ifp->if_flags &= ~IFF_UP;
3561 re_setwol(struct rl_softc *sc)
3570 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3574 /* Put controller into sleep mode. */
3575 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3576 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3577 CSR_WRITE_1(sc, RL_GPIO,
3578 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3580 if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
3581 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3582 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3583 /* Enable config register write. */
3584 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3587 v = CSR_READ_1(sc, RL_CFG1);
3589 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3591 CSR_WRITE_1(sc, RL_CFG1, v);
3593 v = CSR_READ_1(sc, RL_CFG3);
3594 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3595 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3596 v |= RL_CFG3_WOL_MAGIC;
3597 CSR_WRITE_1(sc, RL_CFG3, v);
3599 /* Config register write done. */
3600 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3602 v = CSR_READ_1(sc, RL_CFG5);
3603 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3604 v &= ~RL_CFG5_WOL_LANWAKE;
3605 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3606 v |= RL_CFG5_WOL_UCAST;
3607 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3608 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3609 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3610 v |= RL_CFG5_WOL_LANWAKE;
3611 CSR_WRITE_1(sc, RL_CFG5, v);
3613 if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
3614 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3615 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3617 * It seems that hardware resets its link speed to 100Mbps in
3618 * power down mode so switching to 100Mbps in driver is not
3622 /* Request PME if WOL is requested. */
3623 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3624 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3625 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3626 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3627 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3631 re_clrwol(struct rl_softc *sc)
3638 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3641 /* Enable config register write. */
3642 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3644 v = CSR_READ_1(sc, RL_CFG3);
3645 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3646 CSR_WRITE_1(sc, RL_CFG3, v);
3648 /* Config register write done. */
3649 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3651 v = CSR_READ_1(sc, RL_CFG5);
3652 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3653 v &= ~RL_CFG5_WOL_LANWAKE;
3654 CSR_WRITE_1(sc, RL_CFG5, v);
3658 re_add_sysctls(struct rl_softc *sc)
3660 struct sysctl_ctx_list *ctx;
3661 struct sysctl_oid_list *children;
3664 ctx = device_get_sysctl_ctx(sc->rl_dev);
3665 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3667 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3668 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3669 "Statistics Information");
3670 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3674 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3675 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3676 /* Pull in device tunables. */
3677 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3678 error = resource_int_value(device_get_name(sc->rl_dev),
3679 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3681 if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3682 sc->rl_int_rx_mod > RL_TIMER_MAX) {
3683 device_printf(sc->rl_dev, "int_rx_mod value out of "
3684 "range; using default: %d\n",
3686 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3693 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3695 struct rl_softc *sc;
3696 struct rl_stats *stats;
3697 int error, i, result;
3700 error = sysctl_handle_int(oidp, &result, 0, req);
3701 if (error || req->newptr == NULL)
3705 sc = (struct rl_softc *)arg1;
3707 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3711 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3712 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
3713 CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
3714 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
3715 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3716 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
3717 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3718 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
3719 RL_DUMPSTATS_START));
3720 for (i = RL_TIMEOUT; i > 0; i--) {
3721 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
3722 RL_DUMPSTATS_START) == 0)
3726 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3727 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
3730 device_printf(sc->rl_dev,
3731 "DUMP statistics request timedout\n");
3735 stats = sc->rl_ldata.rl_stats;
3736 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
3737 printf("Tx frames : %ju\n",
3738 (uintmax_t)le64toh(stats->rl_tx_pkts));
3739 printf("Rx frames : %ju\n",
3740 (uintmax_t)le64toh(stats->rl_rx_pkts));
3741 printf("Tx errors : %ju\n",
3742 (uintmax_t)le64toh(stats->rl_tx_errs));
3743 printf("Rx errors : %u\n",
3744 le32toh(stats->rl_rx_errs));
3745 printf("Rx missed frames : %u\n",
3746 (uint32_t)le16toh(stats->rl_missed_pkts));
3747 printf("Rx frame alignment errs : %u\n",
3748 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
3749 printf("Tx single collisions : %u\n",
3750 le32toh(stats->rl_tx_onecoll));
3751 printf("Tx multiple collisions : %u\n",
3752 le32toh(stats->rl_tx_multicolls));
3753 printf("Rx unicast frames : %ju\n",
3754 (uintmax_t)le64toh(stats->rl_rx_ucasts));
3755 printf("Rx broadcast frames : %ju\n",
3756 (uintmax_t)le64toh(stats->rl_rx_bcasts));
3757 printf("Rx multicast frames : %u\n",
3758 le32toh(stats->rl_rx_mcasts));
3759 printf("Tx aborts : %u\n",
3760 (uint32_t)le16toh(stats->rl_tx_aborts));
3761 printf("Tx underruns : %u\n",
3762 (uint32_t)le16toh(stats->rl_rx_underruns));
3769 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3775 value = *(int *)arg1;
3776 error = sysctl_handle_int(oidp, &value, 0, req);
3777 if (error || req->newptr == NULL)
3779 if (value < low || value > high)
3781 *(int *)arg1 = value;
3787 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
3790 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,