2 * Copyright (C) 2008-2009 Semihalf, Piotr Ziecik
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * Freescale integrated Security Engine (SEC) driver. Currently SEC 2.0 and
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/endian.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/random.h>
47 #include <machine/bus.h>
48 #include <machine/resource.h>
50 #include <opencrypto/cryptodev.h>
51 #include "cryptodev_if.h"
53 #include <dev/ofw/ofw_bus_subr.h>
54 #include <dev/sec/sec.h>
56 static int sec_probe(device_t dev);
57 static int sec_attach(device_t dev);
58 static int sec_detach(device_t dev);
59 static int sec_suspend(device_t dev);
60 static int sec_resume(device_t dev);
61 static int sec_shutdown(device_t dev);
62 static void sec_primary_intr(void *arg);
63 static void sec_secondary_intr(void *arg);
64 static int sec_setup_intr(struct sec_softc *sc, struct resource **ires,
65 void **ihand, int *irid, driver_intr_t handler, const char *iname);
66 static void sec_release_intr(struct sec_softc *sc, struct resource *ires,
67 void *ihand, int irid, const char *iname);
68 static int sec_controller_reset(struct sec_softc *sc);
69 static int sec_channel_reset(struct sec_softc *sc, int channel, int full);
70 static int sec_init(struct sec_softc *sc);
71 static int sec_alloc_dma_mem(struct sec_softc *sc,
72 struct sec_dma_mem *dma_mem, bus_size_t size);
73 static int sec_desc_map_dma(struct sec_softc *sc,
74 struct sec_dma_mem *dma_mem, void *mem, bus_size_t size, int type,
75 struct sec_desc_map_info *sdmi);
76 static void sec_free_dma_mem(struct sec_dma_mem *dma_mem);
77 static void sec_enqueue(struct sec_softc *sc);
78 static int sec_enqueue_desc(struct sec_softc *sc, struct sec_desc *desc,
80 static int sec_eu_channel(struct sec_softc *sc, int eu);
81 static int sec_make_pointer(struct sec_softc *sc, struct sec_desc *desc,
82 u_int n, void *data, bus_size_t doffset, bus_size_t dsize, int dtype);
83 static int sec_make_pointer_direct(struct sec_softc *sc,
84 struct sec_desc *desc, u_int n, bus_addr_t data, bus_size_t dsize);
85 static int sec_alloc_session(struct sec_softc *sc);
86 static int sec_newsession(device_t dev, u_int32_t *sidp,
87 struct cryptoini *cri);
88 static int sec_freesession(device_t dev, uint64_t tid);
89 static int sec_process(device_t dev, struct cryptop *crp, int hint);
90 static int sec_split_cri(struct cryptoini *cri, struct cryptoini **enc,
91 struct cryptoini **mac);
92 static int sec_split_crp(struct cryptop *crp, struct cryptodesc **enc,
93 struct cryptodesc **mac);
94 static int sec_build_common_ns_desc(struct sec_softc *sc,
95 struct sec_desc *desc, struct sec_session *ses, struct cryptop *crp,
96 struct cryptodesc *enc, int buftype);
97 static int sec_build_common_s_desc(struct sec_softc *sc,
98 struct sec_desc *desc, struct sec_session *ses, struct cryptop *crp,
99 struct cryptodesc *enc, struct cryptodesc *mac, int buftype);
101 static struct sec_session *sec_get_session(struct sec_softc *sc, u_int sid);
102 static struct sec_desc *sec_find_desc(struct sec_softc *sc, bus_addr_t paddr);
105 static int sec_aesu_newsession(struct sec_softc *sc,
106 struct sec_session *ses, struct cryptoini *enc, struct cryptoini *mac);
107 static int sec_aesu_make_desc(struct sec_softc *sc,
108 struct sec_session *ses, struct sec_desc *desc, struct cryptop *crp,
112 static int sec_deu_newsession(struct sec_softc *sc,
113 struct sec_session *ses, struct cryptoini *enc, struct cryptoini *mac);
114 static int sec_deu_make_desc(struct sec_softc *sc,
115 struct sec_session *ses, struct sec_desc *desc, struct cryptop *crp,
119 static int sec_mdeu_can_handle(u_int alg);
120 static int sec_mdeu_config(struct cryptodesc *crd,
121 u_int *eu, u_int *mode, u_int *hashlen);
122 static int sec_mdeu_newsession(struct sec_softc *sc,
123 struct sec_session *ses, struct cryptoini *enc, struct cryptoini *mac);
124 static int sec_mdeu_make_desc(struct sec_softc *sc,
125 struct sec_session *ses, struct sec_desc *desc, struct cryptop *crp,
128 static device_method_t sec_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_probe, sec_probe),
131 DEVMETHOD(device_attach, sec_attach),
132 DEVMETHOD(device_detach, sec_detach),
134 DEVMETHOD(device_suspend, sec_suspend),
135 DEVMETHOD(device_resume, sec_resume),
136 DEVMETHOD(device_shutdown, sec_shutdown),
139 DEVMETHOD(bus_print_child, bus_generic_print_child),
140 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
143 DEVMETHOD(cryptodev_newsession, sec_newsession),
144 DEVMETHOD(cryptodev_freesession,sec_freesession),
145 DEVMETHOD(cryptodev_process, sec_process),
149 static driver_t sec_driver = {
152 sizeof(struct sec_softc),
155 static devclass_t sec_devclass;
156 DRIVER_MODULE(sec, simplebus, sec_driver, sec_devclass, 0, 0);
157 MODULE_DEPEND(sec, crypto, 1, 1, 1);
159 static struct sec_eu_methods sec_eus[] = {
176 sec_sync_dma_mem(struct sec_dma_mem *dma_mem, bus_dmasync_op_t op)
179 /* Sync only if dma memory is valid */
180 if (dma_mem->dma_vaddr != NULL)
181 bus_dmamap_sync(dma_mem->dma_tag, dma_mem->dma_map, op);
185 sec_free_session(struct sec_softc *sc, struct sec_session *ses)
188 SEC_LOCK(sc, sessions);
190 SEC_UNLOCK(sc, sessions);
194 sec_get_pointer_data(struct sec_desc *desc, u_int n)
197 return (desc->sd_ptr_dmem[n].dma_vaddr);
201 sec_probe(device_t dev)
203 struct sec_softc *sc;
206 if (!ofw_bus_is_compatible(dev, "fsl,sec2.0"))
209 sc = device_get_softc(dev);
212 sc->sc_rres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rrid,
215 if (sc->sc_rres == NULL)
218 sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
219 sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
221 id = SEC_READ(sc, SEC_ID);
223 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid, sc->sc_rres);
227 device_set_desc(dev, "Freescale Security Engine 2.0");
231 device_set_desc(dev, "Freescale Security Engine 3.0");
235 device_printf(dev, "unknown SEC ID 0x%016llx!\n", id);
243 sec_attach(device_t dev)
245 struct sec_softc *sc;
246 struct sec_hw_lt *lt;
250 sc = device_get_softc(dev);
255 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
256 if (sc->sc_cid < 0) {
257 device_printf(dev, "could not get crypto driver ID!\n");
262 mtx_init(&sc->sc_controller_lock, device_get_nameunit(dev),
263 "SEC Controller lock", MTX_DEF);
264 mtx_init(&sc->sc_descriptors_lock, device_get_nameunit(dev),
265 "SEC Descriptors lock", MTX_DEF);
266 mtx_init(&sc->sc_sessions_lock, device_get_nameunit(dev),
267 "SEC Sessions lock", MTX_DEF);
269 /* Allocate I/O memory for SEC registers */
271 sc->sc_rres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rrid,
274 if (sc->sc_rres == NULL) {
275 device_printf(dev, "could not allocate I/O memory!\n");
279 sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
280 sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
282 /* Setup interrupts */
284 error = sec_setup_intr(sc, &sc->sc_pri_ires, &sc->sc_pri_ihand,
285 &sc->sc_pri_irid, sec_primary_intr, "primary");
291 if (sc->sc_version == 3) {
293 error = sec_setup_intr(sc, &sc->sc_sec_ires, &sc->sc_sec_ihand,
294 &sc->sc_sec_irid, sec_secondary_intr, "secondary");
300 /* Alloc DMA memory for descriptors and link tables */
301 error = sec_alloc_dma_mem(sc, &(sc->sc_desc_dmem),
302 SEC_DESCRIPTORS * sizeof(struct sec_hw_desc));
307 error = sec_alloc_dma_mem(sc, &(sc->sc_lt_dmem),
308 (SEC_LT_ENTRIES + 1) * sizeof(struct sec_hw_lt));
313 /* Fill in descriptors and link tables */
314 for (i = 0; i < SEC_DESCRIPTORS; i++) {
315 sc->sc_desc[i].sd_desc =
316 (struct sec_hw_desc*)(sc->sc_desc_dmem.dma_vaddr) + i;
317 sc->sc_desc[i].sd_desc_paddr = sc->sc_desc_dmem.dma_paddr +
318 (i * sizeof(struct sec_hw_desc));
321 for (i = 0; i < SEC_LT_ENTRIES + 1; i++) {
323 (struct sec_hw_lt*)(sc->sc_lt_dmem.dma_vaddr) + i;
324 sc->sc_lt[i].sl_lt_paddr = sc->sc_lt_dmem.dma_paddr +
325 (i * sizeof(struct sec_hw_lt));
328 /* Last entry in link table is used to create a circle */
329 lt = sc->sc_lt[SEC_LT_ENTRIES].sl_lt;
333 lt->shl_ptr = sc->sc_lt[0].sl_lt_paddr;
335 /* Init descriptor and link table queues pointers */
336 SEC_CNT_INIT(sc, sc_free_desc_get_cnt, SEC_DESCRIPTORS);
337 SEC_CNT_INIT(sc, sc_free_desc_put_cnt, SEC_DESCRIPTORS);
338 SEC_CNT_INIT(sc, sc_ready_desc_get_cnt, SEC_DESCRIPTORS);
339 SEC_CNT_INIT(sc, sc_ready_desc_put_cnt, SEC_DESCRIPTORS);
340 SEC_CNT_INIT(sc, sc_queued_desc_get_cnt, SEC_DESCRIPTORS);
341 SEC_CNT_INIT(sc, sc_queued_desc_put_cnt, SEC_DESCRIPTORS);
342 SEC_CNT_INIT(sc, sc_lt_alloc_cnt, SEC_LT_ENTRIES);
343 SEC_CNT_INIT(sc, sc_lt_free_cnt, SEC_LT_ENTRIES);
345 /* Create masks for fast checks */
346 sc->sc_int_error_mask = 0;
347 for (i = 0; i < SEC_CHANNELS; i++)
348 sc->sc_int_error_mask |= (~0ULL & SEC_INT_CH_ERR(i));
350 switch (sc->sc_version) {
352 sc->sc_channel_idle_mask =
353 (SEC_CHAN_CSR2_FFLVL_M << SEC_CHAN_CSR2_FFLVL_S) |
354 (SEC_CHAN_CSR2_MSTATE_M << SEC_CHAN_CSR2_MSTATE_S) |
355 (SEC_CHAN_CSR2_PSTATE_M << SEC_CHAN_CSR2_PSTATE_S) |
356 (SEC_CHAN_CSR2_GSTATE_M << SEC_CHAN_CSR2_GSTATE_S);
359 sc->sc_channel_idle_mask =
360 (SEC_CHAN_CSR3_FFLVL_M << SEC_CHAN_CSR3_FFLVL_S) |
361 (SEC_CHAN_CSR3_MSTATE_M << SEC_CHAN_CSR3_MSTATE_S) |
362 (SEC_CHAN_CSR3_PSTATE_M << SEC_CHAN_CSR3_PSTATE_S) |
363 (SEC_CHAN_CSR3_GSTATE_M << SEC_CHAN_CSR3_GSTATE_S);
368 error = sec_init(sc);
373 /* Register in OCF (AESU) */
374 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
376 /* Register in OCF (DEU) */
377 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
378 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
380 /* Register in OCF (MDEU) */
381 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0);
382 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
383 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
384 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
385 crypto_register(sc->sc_cid, CRYPTO_SHA2_256_HMAC, 0, 0);
386 if (sc->sc_version >= 3) {
387 crypto_register(sc->sc_cid, CRYPTO_SHA2_384_HMAC, 0, 0);
388 crypto_register(sc->sc_cid, CRYPTO_SHA2_512_HMAC, 0, 0);
394 sec_free_dma_mem(&(sc->sc_lt_dmem));
396 sec_free_dma_mem(&(sc->sc_desc_dmem));
398 sec_release_intr(sc, sc->sc_sec_ires, sc->sc_sec_ihand,
399 sc->sc_sec_irid, "secondary");
401 sec_release_intr(sc, sc->sc_pri_ires, sc->sc_pri_ihand,
402 sc->sc_pri_irid, "primary");
404 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid, sc->sc_rres);
406 mtx_destroy(&sc->sc_controller_lock);
407 mtx_destroy(&sc->sc_descriptors_lock);
408 mtx_destroy(&sc->sc_sessions_lock);
414 sec_detach(device_t dev)
416 struct sec_softc *sc = device_get_softc(dev);
417 int i, error, timeout = SEC_TIMEOUT;
419 /* Prepare driver to shutdown */
420 SEC_LOCK(sc, descriptors);
422 SEC_UNLOCK(sc, descriptors);
424 /* Wait until all queued processing finishes */
426 SEC_LOCK(sc, descriptors);
427 i = SEC_READY_DESC_CNT(sc) + SEC_QUEUED_DESC_CNT(sc);
428 SEC_UNLOCK(sc, descriptors);
434 device_printf(dev, "queue flush timeout!\n");
436 /* DMA can be still active - stop it */
437 for (i = 0; i < SEC_CHANNELS; i++)
438 sec_channel_reset(sc, i, 1);
447 /* Disable interrupts */
448 SEC_WRITE(sc, SEC_IER, 0);
450 /* Unregister from OCF */
451 crypto_unregister_all(sc->sc_cid);
453 /* Free DMA memory */
454 for (i = 0; i < SEC_DESCRIPTORS; i++)
455 SEC_DESC_FREE_POINTERS(&(sc->sc_desc[i]));
457 sec_free_dma_mem(&(sc->sc_lt_dmem));
458 sec_free_dma_mem(&(sc->sc_desc_dmem));
460 /* Release interrupts */
461 sec_release_intr(sc, sc->sc_pri_ires, sc->sc_pri_ihand,
462 sc->sc_pri_irid, "primary");
463 sec_release_intr(sc, sc->sc_sec_ires, sc->sc_sec_ihand,
464 sc->sc_sec_irid, "secondary");
468 error = bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid,
471 device_printf(dev, "bus_release_resource() failed for"
472 " I/O memory, error %d\n", error);
477 mtx_destroy(&sc->sc_controller_lock);
478 mtx_destroy(&sc->sc_descriptors_lock);
479 mtx_destroy(&sc->sc_sessions_lock);
485 sec_suspend(device_t dev)
492 sec_resume(device_t dev)
499 sec_shutdown(device_t dev)
506 sec_setup_intr(struct sec_softc *sc, struct resource **ires, void **ihand,
507 int *irid, driver_intr_t handler, const char *iname)
511 (*ires) = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, irid,
514 if ((*ires) == NULL) {
515 device_printf(sc->sc_dev, "could not allocate %s IRQ\n", iname);
519 error = bus_setup_intr(sc->sc_dev, *ires, INTR_MPSAFE | INTR_TYPE_NET,
520 NULL, handler, sc, ihand);
523 device_printf(sc->sc_dev, "failed to set up %s IRQ\n", iname);
524 if (bus_release_resource(sc->sc_dev, SYS_RES_IRQ, *irid, *ires))
525 device_printf(sc->sc_dev, "could not release %s IRQ\n",
536 sec_release_intr(struct sec_softc *sc, struct resource *ires, void *ihand,
537 int irid, const char *iname)
544 error = bus_teardown_intr(sc->sc_dev, ires, ihand);
546 device_printf(sc->sc_dev, "bus_teardown_intr() failed for %s"
547 " IRQ, error %d\n", iname, error);
549 error = bus_release_resource(sc->sc_dev, SYS_RES_IRQ, irid, ires);
551 device_printf(sc->sc_dev, "bus_release_resource() failed for %s"
552 " IRQ, error %d\n", iname, error);
556 sec_primary_intr(void *arg)
558 struct sec_softc *sc = arg;
559 struct sec_desc *desc;
563 SEC_LOCK(sc, controller);
565 /* Check for errors */
566 isr = SEC_READ(sc, SEC_ISR);
567 if (isr & sc->sc_int_error_mask) {
568 /* Check each channel for error */
569 for (i = 0; i < SEC_CHANNELS; i++) {
570 if ((isr & SEC_INT_CH_ERR(i)) == 0)
573 device_printf(sc->sc_dev,
574 "I/O error on channel %i!\n", i);
576 /* Find and mark problematic descriptor */
577 desc = sec_find_desc(sc, SEC_READ(sc,
581 desc->sd_error = EIO;
583 /* Do partial channel reset */
584 sec_channel_reset(sc, i, 0);
589 SEC_WRITE(sc, SEC_ICR, 0xFFFFFFFFFFFFFFFFULL);
591 SEC_UNLOCK(sc, controller);
592 SEC_LOCK(sc, descriptors);
594 /* Handle processed descriptors */
595 SEC_DESC_SYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
597 while (SEC_QUEUED_DESC_CNT(sc) > 0) {
598 desc = SEC_GET_QUEUED_DESC(sc);
600 if (desc->sd_desc->shd_done != 0xFF && desc->sd_error == 0) {
601 SEC_PUT_BACK_QUEUED_DESC(sc);
605 SEC_DESC_SYNC_POINTERS(desc, BUS_DMASYNC_PREREAD |
606 BUS_DMASYNC_PREWRITE);
608 desc->sd_crp->crp_etype = desc->sd_error;
609 crypto_done(desc->sd_crp);
611 SEC_DESC_FREE_POINTERS(desc);
612 SEC_DESC_FREE_LT(sc, desc);
613 SEC_DESC_QUEUED2FREE(sc);
616 SEC_DESC_SYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
618 if (!sc->sc_shutdown) {
619 wakeup = sc->sc_blocked;
623 SEC_UNLOCK(sc, descriptors);
625 /* Enqueue ready descriptors in hardware */
629 crypto_unblock(sc->sc_cid, wakeup);
633 sec_secondary_intr(void *arg)
635 struct sec_softc *sc = arg;
637 device_printf(sc->sc_dev, "spurious secondary interrupt!\n");
638 sec_primary_intr(arg);
642 sec_controller_reset(struct sec_softc *sc)
644 int timeout = SEC_TIMEOUT;
646 /* Reset Controller */
647 SEC_WRITE(sc, SEC_MCR, SEC_MCR_SWR);
649 while (SEC_READ(sc, SEC_MCR) & SEC_MCR_SWR) {
654 device_printf(sc->sc_dev, "timeout while waiting for "
664 sec_channel_reset(struct sec_softc *sc, int channel, int full)
666 int timeout = SEC_TIMEOUT;
667 uint64_t bit = (full) ? SEC_CHAN_CCR_R : SEC_CHAN_CCR_CON;
671 reg = SEC_READ(sc, SEC_CHAN_CCR(channel));
672 SEC_WRITE(sc, SEC_CHAN_CCR(channel), reg | bit);
674 while (SEC_READ(sc, SEC_CHAN_CCR(channel)) & bit) {
679 device_printf(sc->sc_dev, "timeout while waiting for "
686 reg = SEC_CHAN_CCR_CDIE | SEC_CHAN_CCR_NT | SEC_CHAN_CCR_BS;
688 switch(sc->sc_version) {
690 reg |= SEC_CHAN_CCR_CDWE;
693 reg |= SEC_CHAN_CCR_AWSE | SEC_CHAN_CCR_WGN;
697 SEC_WRITE(sc, SEC_CHAN_CCR(channel), reg);
704 sec_init(struct sec_softc *sc)
709 /* Reset controller twice to clear all pending interrupts */
710 error = sec_controller_reset(sc);
714 error = sec_controller_reset(sc);
719 for (i = 0; i < SEC_CHANNELS; i++) {
720 error = sec_channel_reset(sc, i, 1);
725 /* Enable Interrupts */
727 for (i = 0; i < SEC_CHANNELS; i++)
728 reg |= SEC_INT_CH_DN(i) | SEC_INT_CH_ERR(i);
730 SEC_WRITE(sc, SEC_IER, reg);
736 sec_alloc_dma_mem_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
738 struct sec_dma_mem *dma_mem = arg;
743 KASSERT(nseg == 1, ("Wrong number of segments, should be 1"));
744 dma_mem->dma_paddr = segs->ds_addr;
748 sec_dma_map_desc_cb(void *arg, bus_dma_segment_t *segs, int nseg,
751 struct sec_desc_map_info *sdmi = arg;
752 struct sec_softc *sc = sdmi->sdmi_sc;
753 struct sec_lt *lt = NULL;
758 SEC_LOCK_ASSERT(sc, descriptors);
763 for (i = 0; i < nseg; i++) {
764 addr = segs[i].ds_addr;
765 size = segs[i].ds_len;
767 /* Skip requested offset */
768 if (sdmi->sdmi_offset >= size) {
769 sdmi->sdmi_offset -= size;
773 addr += sdmi->sdmi_offset;
774 size -= sdmi->sdmi_offset;
775 sdmi->sdmi_offset = 0;
777 /* Do not link more than requested */
778 if (sdmi->sdmi_size < size)
779 size = sdmi->sdmi_size;
781 lt = SEC_ALLOC_LT_ENTRY(sc);
782 lt->sl_lt->shl_length = size;
783 lt->sl_lt->shl_r = 0;
784 lt->sl_lt->shl_n = 0;
785 lt->sl_lt->shl_ptr = addr;
787 if (sdmi->sdmi_lt_first == NULL)
788 sdmi->sdmi_lt_first = lt;
790 sdmi->sdmi_lt_used += 1;
792 if ((sdmi->sdmi_size -= size) == 0)
796 sdmi->sdmi_lt_last = lt;
800 sec_dma_map_desc_cb2(void *arg, bus_dma_segment_t *segs, int nseg,
801 bus_size_t size, int error)
804 sec_dma_map_desc_cb(arg, segs, nseg, error);
808 sec_alloc_dma_mem(struct sec_softc *sc, struct sec_dma_mem *dma_mem,
813 if (dma_mem->dma_vaddr != NULL)
816 error = bus_dma_tag_create(NULL, /* parent */
817 SEC_DMA_ALIGNMENT, 0, /* alignment, boundary */
818 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
819 BUS_SPACE_MAXADDR, /* highaddr */
820 NULL, NULL, /* filtfunc, filtfuncarg */
821 size, 1, /* maxsize, nsegments */
822 size, 0, /* maxsegsz, flags */
823 NULL, NULL, /* lockfunc, lockfuncarg */
824 &(dma_mem->dma_tag)); /* dmat */
827 device_printf(sc->sc_dev, "failed to allocate busdma tag, error"
832 error = bus_dmamem_alloc(dma_mem->dma_tag, &(dma_mem->dma_vaddr),
833 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &(dma_mem->dma_map));
836 device_printf(sc->sc_dev, "failed to allocate DMA safe"
837 " memory, error %i!\n", error);
841 error = bus_dmamap_load(dma_mem->dma_tag, dma_mem->dma_map,
842 dma_mem->dma_vaddr, size, sec_alloc_dma_mem_cb, dma_mem,
846 device_printf(sc->sc_dev, "cannot get address of the DMA"
847 " memory, error %i\n", error);
851 dma_mem->dma_is_map = 0;
855 bus_dmamem_free(dma_mem->dma_tag, dma_mem->dma_vaddr, dma_mem->dma_map);
857 bus_dma_tag_destroy(dma_mem->dma_tag);
859 dma_mem->dma_vaddr = NULL;
864 sec_desc_map_dma(struct sec_softc *sc, struct sec_dma_mem *dma_mem, void *mem,
865 bus_size_t size, int type, struct sec_desc_map_info *sdmi)
869 if (dma_mem->dma_vaddr != NULL)
876 size = SEC_FREE_LT_CNT(sc) * SEC_MAX_DMA_BLOCK_SIZE;
879 size = m_length((struct mbuf*)mem, NULL);
885 error = bus_dma_tag_create(NULL, /* parent */
886 SEC_DMA_ALIGNMENT, 0, /* alignment, boundary */
887 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
888 BUS_SPACE_MAXADDR, /* highaddr */
889 NULL, NULL, /* filtfunc, filtfuncarg */
891 SEC_FREE_LT_CNT(sc), /* nsegments */
892 SEC_MAX_DMA_BLOCK_SIZE, 0, /* maxsegsz, flags */
893 NULL, NULL, /* lockfunc, lockfuncarg */
894 &(dma_mem->dma_tag)); /* dmat */
897 device_printf(sc->sc_dev, "failed to allocate busdma tag, error"
899 dma_mem->dma_vaddr = NULL;
903 error = bus_dmamap_create(dma_mem->dma_tag, 0, &(dma_mem->dma_map));
906 device_printf(sc->sc_dev, "failed to create DMA map, error %i!"
908 bus_dma_tag_destroy(dma_mem->dma_tag);
914 error = bus_dmamap_load(dma_mem->dma_tag, dma_mem->dma_map,
915 mem, size, sec_dma_map_desc_cb, sdmi, BUS_DMA_NOWAIT);
918 error = bus_dmamap_load_uio(dma_mem->dma_tag, dma_mem->dma_map,
919 mem, sec_dma_map_desc_cb2, sdmi, BUS_DMA_NOWAIT);
922 error = bus_dmamap_load_mbuf(dma_mem->dma_tag, dma_mem->dma_map,
923 mem, sec_dma_map_desc_cb2, sdmi, BUS_DMA_NOWAIT);
928 device_printf(sc->sc_dev, "cannot get address of the DMA"
929 " memory, error %i!\n", error);
930 bus_dmamap_destroy(dma_mem->dma_tag, dma_mem->dma_map);
931 bus_dma_tag_destroy(dma_mem->dma_tag);
935 dma_mem->dma_is_map = 1;
936 dma_mem->dma_vaddr = mem;
942 sec_free_dma_mem(struct sec_dma_mem *dma_mem)
945 /* Check for double free */
946 if (dma_mem->dma_vaddr == NULL)
949 bus_dmamap_unload(dma_mem->dma_tag, dma_mem->dma_map);
951 if (dma_mem->dma_is_map)
952 bus_dmamap_destroy(dma_mem->dma_tag, dma_mem->dma_map);
954 bus_dmamem_free(dma_mem->dma_tag, dma_mem->dma_vaddr,
957 bus_dma_tag_destroy(dma_mem->dma_tag);
958 dma_mem->dma_vaddr = NULL;
962 sec_eu_channel(struct sec_softc *sc, int eu)
967 SEC_LOCK_ASSERT(sc, controller);
969 reg = SEC_READ(sc, SEC_EUASR);
973 channel = SEC_EUASR_AFEU(reg);
976 channel = SEC_EUASR_DEU(reg);
980 channel = SEC_EUASR_MDEU(reg);
983 channel = SEC_EUASR_RNGU(reg);
986 channel = SEC_EUASR_PKEU(reg);
989 channel = SEC_EUASR_AESU(reg);
992 channel = SEC_EUASR_KEU(reg);
995 channel = SEC_EUASR_CRCU(reg);
999 return (channel - 1);
1003 sec_enqueue_desc(struct sec_softc *sc, struct sec_desc *desc, int channel)
1005 u_int fflvl = SEC_MAX_FIFO_LEVEL;
1009 SEC_LOCK_ASSERT(sc, controller);
1011 /* Find free channel if have not got one */
1013 for (i = 0; i < SEC_CHANNELS; i++) {
1014 reg = SEC_READ(sc, SEC_CHAN_CSR(channel));
1016 if ((reg & sc->sc_channel_idle_mask) == 0) {
1023 /* There is no free channel */
1027 /* Check FIFO level on selected channel */
1028 reg = SEC_READ(sc, SEC_CHAN_CSR(channel));
1030 switch(sc->sc_version) {
1032 fflvl = (reg >> SEC_CHAN_CSR2_FFLVL_S) & SEC_CHAN_CSR2_FFLVL_M;
1035 fflvl = (reg >> SEC_CHAN_CSR3_FFLVL_S) & SEC_CHAN_CSR3_FFLVL_M;
1039 if (fflvl >= SEC_MAX_FIFO_LEVEL)
1042 /* Enqueue descriptor in channel */
1043 SEC_WRITE(sc, SEC_CHAN_FF(channel), desc->sd_desc_paddr);
1049 sec_enqueue(struct sec_softc *sc)
1051 struct sec_desc *desc;
1054 SEC_LOCK(sc, descriptors);
1055 SEC_LOCK(sc, controller);
1057 while (SEC_READY_DESC_CNT(sc) > 0) {
1058 desc = SEC_GET_READY_DESC(sc);
1060 ch0 = sec_eu_channel(sc, desc->sd_desc->shd_eu_sel0);
1061 ch1 = sec_eu_channel(sc, desc->sd_desc->shd_eu_sel1);
1064 * Both EU are used by the same channel.
1065 * Enqueue descriptor in channel used by busy EUs.
1067 if (ch0 >= 0 && ch0 == ch1) {
1068 if (sec_enqueue_desc(sc, desc, ch0) >= 0) {
1069 SEC_DESC_READY2QUEUED(sc);
1075 * Only one EU is free.
1076 * Enqueue descriptor in channel used by busy EU.
1078 if ((ch0 >= 0 && ch1 < 0) || (ch1 >= 0 && ch0 < 0)) {
1079 if (sec_enqueue_desc(sc, desc, (ch0 >= 0) ? ch0 : ch1)
1081 SEC_DESC_READY2QUEUED(sc);
1088 * Enqueue descriptor in first free channel.
1090 if (ch0 < 0 && ch1 < 0) {
1091 if (sec_enqueue_desc(sc, desc, -1) >= 0) {
1092 SEC_DESC_READY2QUEUED(sc);
1097 /* Current descriptor can not be queued at the moment */
1098 SEC_PUT_BACK_READY_DESC(sc);
1102 SEC_UNLOCK(sc, controller);
1103 SEC_UNLOCK(sc, descriptors);
1106 static struct sec_desc *
1107 sec_find_desc(struct sec_softc *sc, bus_addr_t paddr)
1109 struct sec_desc *desc = NULL;
1112 SEC_LOCK_ASSERT(sc, descriptors);
1114 for (i = 0; i < SEC_CHANNELS; i++) {
1115 if (sc->sc_desc[i].sd_desc_paddr == paddr) {
1116 desc = &(sc->sc_desc[i]);
1125 sec_make_pointer_direct(struct sec_softc *sc, struct sec_desc *desc, u_int n,
1126 bus_addr_t data, bus_size_t dsize)
1128 struct sec_hw_desc_ptr *ptr;
1130 SEC_LOCK_ASSERT(sc, descriptors);
1132 ptr = &(desc->sd_desc->shd_pointer[n]);
1133 ptr->shdp_length = dsize;
1134 ptr->shdp_extent = 0;
1136 ptr->shdp_ptr = data;
1142 sec_make_pointer(struct sec_softc *sc, struct sec_desc *desc,
1143 u_int n, void *data, bus_size_t doffset, bus_size_t dsize, int dtype)
1145 struct sec_desc_map_info sdmi = { sc, dsize, doffset, NULL, NULL, 0 };
1146 struct sec_hw_desc_ptr *ptr;
1149 SEC_LOCK_ASSERT(sc, descriptors);
1151 /* For flat memory map only requested region */
1152 if (dtype == SEC_MEMORY) {
1153 data = (uint8_t*)(data) + doffset;
1154 sdmi.sdmi_offset = 0;
1157 error = sec_desc_map_dma(sc, &(desc->sd_ptr_dmem[n]), data, dsize,
1163 sdmi.sdmi_lt_last->sl_lt->shl_r = 1;
1164 desc->sd_lt_used += sdmi.sdmi_lt_used;
1166 ptr = &(desc->sd_desc->shd_pointer[n]);
1167 ptr->shdp_length = dsize;
1168 ptr->shdp_extent = 0;
1170 ptr->shdp_ptr = sdmi.sdmi_lt_first->sl_lt_paddr;
1176 sec_split_cri(struct cryptoini *cri, struct cryptoini **enc,
1177 struct cryptoini **mac)
1179 struct cryptoini *e, *m;
1184 /* We can haldle only two operations */
1185 if (m && m->cri_next)
1188 if (sec_mdeu_can_handle(e->cri_alg)) {
1194 if (m && !sec_mdeu_can_handle(m->cri_alg))
1204 sec_split_crp(struct cryptop *crp, struct cryptodesc **enc,
1205 struct cryptodesc **mac)
1207 struct cryptodesc *e, *m, *t;
1212 /* We can haldle only two operations */
1213 if (m && m->crd_next)
1216 if (sec_mdeu_can_handle(e->crd_alg)) {
1222 if (m && !sec_mdeu_can_handle(m->crd_alg))
1232 sec_alloc_session(struct sec_softc *sc)
1234 struct sec_session *ses = NULL;
1238 SEC_LOCK(sc, sessions);
1240 for (i = 0; i < SEC_MAX_SESSIONS; i++) {
1241 if (sc->sc_sessions[i].ss_used == 0) {
1242 ses = &(sc->sc_sessions[i]);
1252 SEC_UNLOCK(sc, sessions);
1257 static struct sec_session *
1258 sec_get_session(struct sec_softc *sc, u_int sid)
1260 struct sec_session *ses;
1262 if (sid >= SEC_MAX_SESSIONS)
1265 SEC_LOCK(sc, sessions);
1267 ses = &(sc->sc_sessions[sid]);
1269 if (ses->ss_used == 0)
1272 SEC_UNLOCK(sc, sessions);
1278 sec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
1280 struct sec_softc *sc = device_get_softc(dev);
1281 struct sec_eu_methods *eu = sec_eus;
1282 struct cryptoini *enc = NULL;
1283 struct cryptoini *mac = NULL;
1284 struct sec_session *ses;
1288 error = sec_split_cri(cri, &enc, &mac);
1292 /* Check key lengths */
1293 if (enc && enc->cri_key && (enc->cri_klen / 8) > SEC_MAX_KEY_LEN)
1296 if (mac && mac->cri_key && (mac->cri_klen / 8) > SEC_MAX_KEY_LEN)
1299 /* Only SEC 3.0 supports digests larger than 256 bits */
1300 if (sc->sc_version < 3 && mac && mac->cri_klen > 256)
1303 sid = sec_alloc_session(sc);
1307 ses = sec_get_session(sc, sid);
1309 /* Find EU for this session */
1310 while (eu->sem_make_desc != NULL) {
1311 error = eu->sem_newsession(sc, ses, enc, mac);
1318 /* If not found, return EINVAL */
1320 sec_free_session(sc, ses);
1324 /* Save cipher key */
1325 if (enc && enc->cri_key) {
1326 ses->ss_klen = enc->cri_klen / 8;
1327 memcpy(ses->ss_key, enc->cri_key, ses->ss_klen);
1330 /* Save digest key */
1331 if (mac && mac->cri_key) {
1332 ses->ss_mklen = mac->cri_klen / 8;
1333 memcpy(ses->ss_mkey, mac->cri_key, ses->ss_mklen);
1343 sec_freesession(device_t dev, uint64_t tid)
1345 struct sec_softc *sc = device_get_softc(dev);
1346 struct sec_session *ses;
1349 ses = sec_get_session(sc, CRYPTO_SESID2LID(tid));
1353 sec_free_session(sc, ses);
1359 sec_process(device_t dev, struct cryptop *crp, int hint)
1361 struct sec_softc *sc = device_get_softc(dev);
1362 struct sec_desc *desc = NULL;
1363 struct cryptodesc *mac, *enc;
1364 struct sec_session *ses;
1365 int buftype, error = 0;
1367 /* Check Session ID */
1368 ses = sec_get_session(sc, CRYPTO_SESID2LID(crp->crp_sid));
1370 crp->crp_etype = EINVAL;
1375 /* Check for input length */
1376 if (crp->crp_ilen > SEC_MAX_DMA_BLOCK_SIZE) {
1377 crp->crp_etype = E2BIG;
1382 /* Get descriptors */
1383 if (sec_split_crp(crp, &enc, &mac)) {
1384 crp->crp_etype = EINVAL;
1389 SEC_LOCK(sc, descriptors);
1390 SEC_DESC_SYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1392 /* Block driver if there is no free descriptors or we are going down */
1393 if (SEC_FREE_DESC_CNT(sc) == 0 || sc->sc_shutdown) {
1394 sc->sc_blocked |= CRYPTO_SYMQ;
1395 SEC_UNLOCK(sc, descriptors);
1399 /* Prepare descriptor */
1400 desc = SEC_GET_FREE_DESC(sc);
1401 desc->sd_lt_used = 0;
1405 if (crp->crp_flags & CRYPTO_F_IOV)
1407 else if (crp->crp_flags & CRYPTO_F_IMBUF)
1410 buftype = SEC_MEMORY;
1412 if (enc && enc->crd_flags & CRD_F_ENCRYPT) {
1413 if (enc->crd_flags & CRD_F_IV_EXPLICIT)
1414 memcpy(desc->sd_desc->shd_iv, enc->crd_iv,
1417 arc4rand(desc->sd_desc->shd_iv, ses->ss_ivlen, 0);
1419 if ((enc->crd_flags & CRD_F_IV_PRESENT) == 0)
1420 crypto_copyback(crp->crp_flags, crp->crp_buf,
1421 enc->crd_inject, ses->ss_ivlen,
1422 desc->sd_desc->shd_iv);
1424 if (enc->crd_flags & CRD_F_IV_EXPLICIT)
1425 memcpy(desc->sd_desc->shd_iv, enc->crd_iv,
1428 crypto_copydata(crp->crp_flags, crp->crp_buf,
1429 enc->crd_inject, ses->ss_ivlen,
1430 desc->sd_desc->shd_iv);
1433 if (enc && enc->crd_flags & CRD_F_KEY_EXPLICIT) {
1434 if ((enc->crd_klen / 8) <= SEC_MAX_KEY_LEN) {
1435 ses->ss_klen = enc->crd_klen / 8;
1436 memcpy(ses->ss_key, enc->crd_key, ses->ss_klen);
1441 if (!error && mac && mac->crd_flags & CRD_F_KEY_EXPLICIT) {
1442 if ((mac->crd_klen / 8) <= SEC_MAX_KEY_LEN) {
1443 ses->ss_mklen = mac->crd_klen / 8;
1444 memcpy(ses->ss_mkey, mac->crd_key, ses->ss_mklen);
1450 memcpy(desc->sd_desc->shd_key, ses->ss_key, ses->ss_klen);
1451 memcpy(desc->sd_desc->shd_mkey, ses->ss_mkey, ses->ss_mklen);
1453 error = ses->ss_eu->sem_make_desc(sc, ses, desc, crp, buftype);
1457 SEC_DESC_FREE_POINTERS(desc);
1458 SEC_DESC_PUT_BACK_LT(sc, desc);
1459 SEC_PUT_BACK_FREE_DESC(sc);
1460 SEC_UNLOCK(sc, descriptors);
1461 crp->crp_etype = error;
1467 * Skip DONE interrupt if this is not last request in burst, but only
1468 * if we are running on SEC 3.X. On SEC 2.X we have to enable DONE
1469 * signaling on each descriptor.
1471 if ((hint & CRYPTO_HINT_MORE) && sc->sc_version == 3)
1472 desc->sd_desc->shd_dn = 0;
1474 desc->sd_desc->shd_dn = 1;
1476 SEC_DESC_SYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1477 SEC_DESC_SYNC_POINTERS(desc, BUS_DMASYNC_POSTREAD |
1478 BUS_DMASYNC_POSTWRITE);
1479 SEC_DESC_FREE2READY(sc);
1480 SEC_UNLOCK(sc, descriptors);
1482 /* Enqueue ready descriptors in hardware */
1489 sec_build_common_ns_desc(struct sec_softc *sc, struct sec_desc *desc,
1490 struct sec_session *ses, struct cryptop *crp, struct cryptodesc *enc,
1493 struct sec_hw_desc *hd = desc->sd_desc;
1496 hd->shd_desc_type = SEC_DT_COMMON_NONSNOOP;
1497 hd->shd_eu_sel1 = SEC_EU_NONE;
1500 /* Pointer 0: NULL */
1501 error = sec_make_pointer_direct(sc, desc, 0, 0, 0);
1505 /* Pointer 1: IV IN */
1506 error = sec_make_pointer_direct(sc, desc, 1, desc->sd_desc_paddr +
1507 offsetof(struct sec_hw_desc, shd_iv), ses->ss_ivlen);
1511 /* Pointer 2: Cipher Key */
1512 error = sec_make_pointer_direct(sc, desc, 2, desc->sd_desc_paddr +
1513 offsetof(struct sec_hw_desc, shd_key), ses->ss_klen);
1517 /* Pointer 3: Data IN */
1518 error = sec_make_pointer(sc, desc, 3, crp->crp_buf, enc->crd_skip,
1519 enc->crd_len, buftype);
1523 /* Pointer 4: Data OUT */
1524 error = sec_make_pointer(sc, desc, 4, crp->crp_buf, enc->crd_skip,
1525 enc->crd_len, buftype);
1529 /* Pointer 5: IV OUT (Not used: NULL) */
1530 error = sec_make_pointer_direct(sc, desc, 5, 0, 0);
1534 /* Pointer 6: NULL */
1535 error = sec_make_pointer_direct(sc, desc, 6, 0, 0);
1541 sec_build_common_s_desc(struct sec_softc *sc, struct sec_desc *desc,
1542 struct sec_session *ses, struct cryptop *crp, struct cryptodesc *enc,
1543 struct cryptodesc *mac, int buftype)
1545 struct sec_hw_desc *hd = desc->sd_desc;
1546 u_int eu, mode, hashlen;
1549 if (mac->crd_len < enc->crd_len)
1552 if (mac->crd_skip + mac->crd_len != enc->crd_skip + enc->crd_len)
1555 error = sec_mdeu_config(mac, &eu, &mode, &hashlen);
1559 hd->shd_desc_type = SEC_DT_HMAC_SNOOP;
1560 hd->shd_eu_sel1 = eu;
1561 hd->shd_mode1 = mode;
1563 /* Pointer 0: HMAC Key */
1564 error = sec_make_pointer_direct(sc, desc, 0, desc->sd_desc_paddr +
1565 offsetof(struct sec_hw_desc, shd_mkey), ses->ss_mklen);
1569 /* Pointer 1: HMAC-Only Data IN */
1570 error = sec_make_pointer(sc, desc, 1, crp->crp_buf, mac->crd_skip,
1571 mac->crd_len - enc->crd_len, buftype);
1575 /* Pointer 2: Cipher Key */
1576 error = sec_make_pointer_direct(sc, desc, 2, desc->sd_desc_paddr +
1577 offsetof(struct sec_hw_desc, shd_key), ses->ss_klen);
1581 /* Pointer 3: IV IN */
1582 error = sec_make_pointer_direct(sc, desc, 3, desc->sd_desc_paddr +
1583 offsetof(struct sec_hw_desc, shd_iv), ses->ss_ivlen);
1587 /* Pointer 4: Data IN */
1588 error = sec_make_pointer(sc, desc, 4, crp->crp_buf, enc->crd_skip,
1589 enc->crd_len, buftype);
1593 /* Pointer 5: Data OUT */
1594 error = sec_make_pointer(sc, desc, 5, crp->crp_buf, enc->crd_skip,
1595 enc->crd_len, buftype);
1599 /* Pointer 6: HMAC OUT */
1600 error = sec_make_pointer(sc, desc, 6, crp->crp_buf, mac->crd_inject,
1609 sec_aesu_newsession(struct sec_softc *sc, struct sec_session *ses,
1610 struct cryptoini *enc, struct cryptoini *mac)
1616 if (enc->cri_alg != CRYPTO_AES_CBC)
1619 ses->ss_ivlen = AES_BLOCK_LEN;
1625 sec_aesu_make_desc(struct sec_softc *sc, struct sec_session *ses,
1626 struct sec_desc *desc, struct cryptop *crp, int buftype)
1628 struct sec_hw_desc *hd = desc->sd_desc;
1629 struct cryptodesc *enc, *mac;
1632 error = sec_split_crp(crp, &enc, &mac);
1639 hd->shd_eu_sel0 = SEC_EU_AESU;
1640 hd->shd_mode0 = SEC_AESU_MODE_CBC;
1642 if (enc->crd_alg != CRYPTO_AES_CBC)
1645 if (enc->crd_flags & CRD_F_ENCRYPT) {
1646 hd->shd_mode0 |= SEC_AESU_MODE_ED;
1652 error = sec_build_common_s_desc(sc, desc, ses, crp, enc, mac,
1655 error = sec_build_common_ns_desc(sc, desc, ses, crp, enc,
1664 sec_deu_newsession(struct sec_softc *sc, struct sec_session *ses,
1665 struct cryptoini *enc, struct cryptoini *mac)
1671 switch (enc->cri_alg) {
1672 case CRYPTO_DES_CBC:
1673 case CRYPTO_3DES_CBC:
1679 ses->ss_ivlen = DES_BLOCK_LEN;
1685 sec_deu_make_desc(struct sec_softc *sc, struct sec_session *ses,
1686 struct sec_desc *desc, struct cryptop *crp, int buftype)
1688 struct sec_hw_desc *hd = desc->sd_desc;
1689 struct cryptodesc *enc, *mac;
1692 error = sec_split_crp(crp, &enc, &mac);
1699 hd->shd_eu_sel0 = SEC_EU_DEU;
1700 hd->shd_mode0 = SEC_DEU_MODE_CBC;
1702 switch (enc->crd_alg) {
1703 case CRYPTO_3DES_CBC:
1704 hd->shd_mode0 |= SEC_DEU_MODE_TS;
1706 case CRYPTO_DES_CBC:
1712 if (enc->crd_flags & CRD_F_ENCRYPT) {
1713 hd->shd_mode0 |= SEC_DEU_MODE_ED;
1719 error = sec_build_common_s_desc(sc, desc, ses, crp, enc, mac,
1722 error = sec_build_common_ns_desc(sc, desc, ses, crp, enc,
1731 sec_mdeu_can_handle(u_int alg)
1736 case CRYPTO_MD5_HMAC:
1737 case CRYPTO_SHA1_HMAC:
1738 case CRYPTO_SHA2_256_HMAC:
1739 case CRYPTO_SHA2_384_HMAC:
1740 case CRYPTO_SHA2_512_HMAC:
1748 sec_mdeu_config(struct cryptodesc *crd, u_int *eu, u_int *mode, u_int *hashlen)
1751 *mode = SEC_MDEU_MODE_PD | SEC_MDEU_MODE_INIT;
1754 switch (crd->crd_alg) {
1755 case CRYPTO_MD5_HMAC:
1756 *mode |= SEC_MDEU_MODE_HMAC;
1759 *eu = SEC_EU_MDEU_A;
1760 *mode |= SEC_MDEU_MODE_MD5;
1761 *hashlen = MD5_HASH_LEN;
1763 case CRYPTO_SHA1_HMAC:
1764 *mode |= SEC_MDEU_MODE_HMAC;
1767 *eu = SEC_EU_MDEU_A;
1768 *mode |= SEC_MDEU_MODE_SHA1;
1769 *hashlen = SHA1_HASH_LEN;
1771 case CRYPTO_SHA2_256_HMAC:
1772 *mode |= SEC_MDEU_MODE_HMAC | SEC_MDEU_MODE_SHA256;
1773 *eu = SEC_EU_MDEU_A;
1775 case CRYPTO_SHA2_384_HMAC:
1776 *mode |= SEC_MDEU_MODE_HMAC | SEC_MDEU_MODE_SHA384;
1777 *eu = SEC_EU_MDEU_B;
1779 case CRYPTO_SHA2_512_HMAC:
1780 *mode |= SEC_MDEU_MODE_HMAC | SEC_MDEU_MODE_SHA512;
1781 *eu = SEC_EU_MDEU_B;
1787 if (*mode & SEC_MDEU_MODE_HMAC)
1788 *hashlen = SEC_HMAC_HASH_LEN;
1794 sec_mdeu_newsession(struct sec_softc *sc, struct sec_session *ses,
1795 struct cryptoini *enc, struct cryptoini *mac)
1798 if (mac && sec_mdeu_can_handle(mac->cri_alg))
1805 sec_mdeu_make_desc(struct sec_softc *sc, struct sec_session *ses,
1806 struct sec_desc *desc, struct cryptop *crp, int buftype)
1808 struct cryptodesc *enc, *mac;
1809 struct sec_hw_desc *hd = desc->sd_desc;
1810 u_int eu, mode, hashlen;
1813 error = sec_split_crp(crp, &enc, &mac);
1820 error = sec_mdeu_config(mac, &eu, &mode, &hashlen);
1824 hd->shd_desc_type = SEC_DT_COMMON_NONSNOOP;
1825 hd->shd_eu_sel0 = eu;
1826 hd->shd_mode0 = mode;
1827 hd->shd_eu_sel1 = SEC_EU_NONE;
1830 /* Pointer 0: NULL */
1831 error = sec_make_pointer_direct(sc, desc, 0, 0, 0);
1835 /* Pointer 1: Context In (Not used: NULL) */
1836 error = sec_make_pointer_direct(sc, desc, 1, 0, 0);
1840 /* Pointer 2: HMAC Key (or NULL, depending on digest type) */
1841 if (hd->shd_mode0 & SEC_MDEU_MODE_HMAC)
1842 error = sec_make_pointer_direct(sc, desc, 2,
1843 desc->sd_desc_paddr + offsetof(struct sec_hw_desc,
1844 shd_mkey), ses->ss_mklen);
1846 error = sec_make_pointer_direct(sc, desc, 2, 0, 0);
1851 /* Pointer 3: Input Data */
1852 error = sec_make_pointer(sc, desc, 3, crp->crp_buf, mac->crd_skip,
1853 mac->crd_len, buftype);
1857 /* Pointer 4: NULL */
1858 error = sec_make_pointer_direct(sc, desc, 4, 0, 0);
1862 /* Pointer 5: Hash out */
1863 error = sec_make_pointer(sc, desc, 5, crp->crp_buf,
1864 mac->crd_inject, hashlen, buftype);
1868 /* Pointer 6: NULL */
1869 error = sec_make_pointer_direct(sc, desc, 6, 0, 0);