sys/dev/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34 /*-
  35  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  36  *
  37  * Permission to use, copy, modify, and distribute this software for any
  38  * purpose with or without fee is hereby granted, provided that the above
  39  * copyright notice and this permission notice appear in all copies.
  40  *
  41  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  42  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  43  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  44  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  45  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  46  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  47  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  48  */
  49
  50 #include <sys/cdefs.h>
  51 __FBSDID("$FreeBSD$");
  52
  53 /*
  54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  55  * the SK-984x series adapters, both single port and dual port.
  56  * References:
  57  *      The XaQti XMAC II datasheet,
  58  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  60  *
  61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  63  * convenience to others until Vitesse corrects this problem:
  64  *
  65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  66  *
  67  * Written by Bill Paul <wpaul@ee.columbia.edu>
  68  * Department of Electrical Engineering
  69  * Columbia University, New York City
  70  */
  71 /*
  72  * The SysKonnect gigabit ethernet adapters consist of two main
  73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  75  * components and a PHY while the GEnesis controller provides a PCI
  76  * interface with DMA support. Each card may have between 512K and
  77  * 2MB of SRAM on board depending on the configuration.
  78  *
  79  * The SysKonnect GEnesis controller can have either one or two XMAC
  80  * chips connected to it, allowing single or dual port NIC configurations.
  81  * SysKonnect has the distinction of being the only vendor on the market
  82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  84  * XMAC registers. This driver takes advantage of these features to allow
  85  * both XMACs to operate as independent interfaces.
  86  */
  87
  88 #include <sys/param.h>
  89 #include <sys/systm.h>
  90 #include <sys/bus.h>
  91 #include <sys/endian.h>
  92 #include <sys/mbuf.h>
  93 #include <sys/malloc.h>
  94 #include <sys/kernel.h>
  95 #include <sys/module.h>
  96 #include <sys/socket.h>
  97 #include <sys/sockio.h>
  98 #include <sys/queue.h>
  99 #include <sys/sysctl.h>
 100
 101 #include <net/bpf.h>
 102 #include <net/ethernet.h>
 103 #include <net/if.h>
 104 #include <net/if_arp.h>
 105 #include <net/if_dl.h>
 106 #include <net/if_media.h>
 107 #include <net/if_types.h>
 108 #include <net/if_vlan_var.h>
 109
 110 #include <netinet/in.h>
 111 #include <netinet/in_systm.h>
 112 #include <netinet/ip.h>
 113
 114 #include <machine/bus.h>
 115 #include <machine/in_cksum.h>
 116 #include <machine/resource.h>
 117 #include <sys/rman.h>
 118
 119 #include <dev/mii/mii.h>
 120 #include <dev/mii/miivar.h>
 121 #include <dev/mii/brgphyreg.h>
 122
 123 #include <dev/pci/pcireg.h>
 124 #include <dev/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include <dev/sk/if_skreg.h>
 131 #include <dev/sk/xmaciireg.h>
 132 #include <dev/sk/yukonreg.h>
 133
 134 MODULE_DEPEND(sk, pci, 1, 1, 1);
 135 MODULE_DEPEND(sk, ether, 1, 1, 1);
 136 MODULE_DEPEND(sk, miibus, 1, 1, 1);
 137
 138 /* "device miibus" required.  See GENERIC if you get errors here. */
 139 #include "miibus_if.h"
 140
 141 #ifndef lint
 142 static const char rcsid[] =
 143   "$FreeBSD$";
 144 #endif
 145
 146 static struct sk_type sk_devs[] = {
 147         {
 148                 VENDORID_SK,
 149                 DEVICEID_SK_V1,
 150                 "SysKonnect Gigabit Ethernet (V1.0)"
 151         },
 152         {
 153                 VENDORID_SK,
 154                 DEVICEID_SK_V2,
 155                 "SysKonnect Gigabit Ethernet (V2.0)"
 156         },
 157         {
 158                 VENDORID_MARVELL,
 159                 DEVICEID_SK_V2,
 160                 "Marvell Gigabit Ethernet"
 161         },
 162         {
 163                 VENDORID_MARVELL,
 164                 DEVICEID_BELKIN_5005,
 165                 "Belkin F5D5005 Gigabit Ethernet"
 166         },
 167         {
 168                 VENDORID_3COM,
 169                 DEVICEID_3COM_3C940,
 170                 "3Com 3C940 Gigabit Ethernet"
 171         },
 172         {
 173                 VENDORID_LINKSYS,
 174                 DEVICEID_LINKSYS_EG1032,
 175                 "Linksys EG1032 Gigabit Ethernet"
 176         },
 177         {
 178                 VENDORID_DLINK,
 179                 DEVICEID_DLINK_DGE530T_A1,
 180                 "D-Link DGE-530T Gigabit Ethernet"
 181         },
 182         {
 183                 VENDORID_DLINK,
 184                 DEVICEID_DLINK_DGE530T_B1,
 185                 "D-Link DGE-530T Gigabit Ethernet"
 186         },
 187         { 0, 0, NULL }
 188 };
 189
 190 static int skc_probe(device_t);
 191 static int skc_attach(device_t);
 192 static int skc_detach(device_t);
 193 static int skc_shutdown(device_t);
 194 static int skc_suspend(device_t);
 195 static int skc_resume(device_t);
 196 static int sk_detach(device_t);
 197 static int sk_probe(device_t);
 198 static int sk_attach(device_t);
 199 static void sk_tick(void *);
 200 static void sk_yukon_tick(void *);
 201 static void sk_intr(void *);
 202 static void sk_intr_xmac(struct sk_if_softc *);
 203 static void sk_intr_bcom(struct sk_if_softc *);
 204 static void sk_intr_yukon(struct sk_if_softc *);
 205 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
 206 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
 207 static void sk_rxeof(struct sk_if_softc *);
 208 static void sk_jumbo_rxeof(struct sk_if_softc *);
 209 static void sk_txeof(struct sk_if_softc *);
 210 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
 211 static int sk_encap(struct sk_if_softc *, struct mbuf **);
 212 static void sk_start(struct ifnet *);
 213 static void sk_start_locked(struct ifnet *);
 214 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
 215 static void sk_init(void *);
 216 static void sk_init_locked(struct sk_if_softc *);
 217 static void sk_init_xmac(struct sk_if_softc *);
 218 static void sk_init_yukon(struct sk_if_softc *);
 219 static void sk_stop(struct sk_if_softc *);
 220 static void sk_watchdog(void *);
 221 static int sk_ifmedia_upd(struct ifnet *);
 222 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 223 static void sk_reset(struct sk_softc *);
 224 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
 225 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
 226 static int sk_newbuf(struct sk_if_softc *, int);
 227 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
 228 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 229 static int sk_dma_alloc(struct sk_if_softc *);
 230 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
 231 static void sk_dma_free(struct sk_if_softc *);
 232 static void sk_dma_jumbo_free(struct sk_if_softc *);
 233 static int sk_init_rx_ring(struct sk_if_softc *);
 234 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
 235 static void sk_init_tx_ring(struct sk_if_softc *);
 236 static u_int32_t sk_win_read_4(struct sk_softc *, int);
 237 static u_int16_t sk_win_read_2(struct sk_softc *, int);
 238 static u_int8_t sk_win_read_1(struct sk_softc *, int);
 239 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
 240 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
 241 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
 242
 243 static int sk_miibus_readreg(device_t, int, int);
 244 static int sk_miibus_writereg(device_t, int, int, int);
 245 static void sk_miibus_statchg(device_t);
 246
 247 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 248 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
 249                                                 int);
 250 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
 251
 252 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 253 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
 254                                                 int);
 255 static void sk_marv_miibus_statchg(struct sk_if_softc *);
 256
 257 static uint32_t sk_xmchash(const uint8_t *);
 258 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
 259 static void sk_rxfilter(struct sk_if_softc *);
 260 static void sk_rxfilter_genesis(struct sk_if_softc *);
 261 static void sk_rxfilter_yukon(struct sk_if_softc *);
 262
 263 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
 264 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
 265
 266 /* Tunables. */
 267 static int jumbo_disable = 0;
 268 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
 269
 270 /*
 271  * It seems that SK-NET GENESIS supports very simple checksum offload
 272  * capability for Tx and I believe it can generate 0 checksum value for
 273  * UDP packets in Tx as the hardware can't differenciate UDP packets from
 274  * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
 275  * means sender didn't perforam checksum computation. For the safety I
 276  * disabled UDP checksum offload capability at the moment. Alternatively
 277  * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
 278  * offload routine.
 279  */
 280 #define SK_CSUM_FEATURES        (CSUM_TCP)
 281
 282 /*
 283  * Note that we have newbus methods for both the GEnesis controller
 284  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 285  * the miibus code is a child of the XMACs. We need to do it this way
 286  * so that the miibus drivers can access the PHY registers on the
 287  * right PHY. It's not quite what I had in mind, but it's the only
 288  * design that achieves the desired effect.
 289  */
 290 static device_method_t skc_methods[] = {
 291         /* Device interface */
 292         DEVMETHOD(device_probe,         skc_probe),
 293         DEVMETHOD(device_attach,        skc_attach),
 294         DEVMETHOD(device_detach,        skc_detach),
 295         DEVMETHOD(device_suspend,       skc_suspend),
 296         DEVMETHOD(device_resume,        skc_resume),
 297         DEVMETHOD(device_shutdown,      skc_shutdown),
 298
 299         /* bus interface */
 300         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 301         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 302
 303         { 0, 0 }
 304 };
 305
 306 static driver_t skc_driver = {
 307         "skc",
 308         skc_methods,
 309         sizeof(struct sk_softc)
 310 };
 311
 312 static devclass_t skc_devclass;
 313
 314 static device_method_t sk_methods[] = {
 315         /* Device interface */
 316         DEVMETHOD(device_probe,         sk_probe),
 317         DEVMETHOD(device_attach,        sk_attach),
 318         DEVMETHOD(device_detach,        sk_detach),
 319         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 320
 321         /* bus interface */
 322         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 323         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 324
 325         /* MII interface */
 326         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 327         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 328         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 329
 330         { 0, 0 }
 331 };
 332
 333 static driver_t sk_driver = {
 334         "sk",
 335         sk_methods,
 336         sizeof(struct sk_if_softc)
 337 };
 338
 339 static devclass_t sk_devclass;
 340
 341 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0);
 342 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
 343 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 344
 345 static struct resource_spec sk_res_spec_io[] = {
 346         { SYS_RES_IOPORT,       PCIR_BAR(1),    RF_ACTIVE },
 347         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 348         { -1,                   0,              0 }
 349 };
 350
 351 static struct resource_spec sk_res_spec_mem[] = {
 352         { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 353         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 354         { -1,                   0,              0 }
 355 };
 356
 357 #define SK_SETBIT(sc, reg, x)           \
 358         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 359
 360 #define SK_CLRBIT(sc, reg, x)           \
 361         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 362
 363 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 364         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 365
 366 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 367         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 368
 369 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 370         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 371
 372 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 373         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 374
 375 static u_int32_t
 376 sk_win_read_4(sc, reg)
 377         struct sk_softc         *sc;
 378         int                     reg;
 379 {
 380 #ifdef SK_USEIOSPACE
 381         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 382         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 383 #else
 384         return(CSR_READ_4(sc, reg));
 385 #endif
 386 }
 387
 388 static u_int16_t
 389 sk_win_read_2(sc, reg)
 390         struct sk_softc         *sc;
 391         int                     reg;
 392 {
 393 #ifdef SK_USEIOSPACE
 394         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 395         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 396 #else
 397         return(CSR_READ_2(sc, reg));
 398 #endif
 399 }
 400
 401 static u_int8_t
 402 sk_win_read_1(sc, reg)
 403         struct sk_softc         *sc;
 404         int                     reg;
 405 {
 406 #ifdef SK_USEIOSPACE
 407         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 408         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 409 #else
 410         return(CSR_READ_1(sc, reg));
 411 #endif
 412 }
 413
 414 static void
 415 sk_win_write_4(sc, reg, val)
 416         struct sk_softc         *sc;
 417         int                     reg;
 418         u_int32_t               val;
 419 {
 420 #ifdef SK_USEIOSPACE
 421         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 422         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 423 #else
 424         CSR_WRITE_4(sc, reg, val);
 425 #endif
 426         return;
 427 }
 428
 429 static void
 430 sk_win_write_2(sc, reg, val)
 431         struct sk_softc         *sc;
 432         int                     reg;
 433         u_int32_t               val;
 434 {
 435 #ifdef SK_USEIOSPACE
 436         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 437         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 438 #else
 439         CSR_WRITE_2(sc, reg, val);
 440 #endif
 441         return;
 442 }
 443
 444 static void
 445 sk_win_write_1(sc, reg, val)
 446         struct sk_softc         *sc;
 447         int                     reg;
 448         u_int32_t               val;
 449 {
 450 #ifdef SK_USEIOSPACE
 451         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 452         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 453 #else
 454         CSR_WRITE_1(sc, reg, val);
 455 #endif
 456         return;
 457 }
 458
 459 static int
 460 sk_miibus_readreg(dev, phy, reg)
 461         device_t                dev;
 462         int                     phy, reg;
 463 {
 464         struct sk_if_softc      *sc_if;
 465         int                     v;
 466
 467         sc_if = device_get_softc(dev);
 468
 469         SK_IF_MII_LOCK(sc_if);
 470         switch(sc_if->sk_softc->sk_type) {
 471         case SK_GENESIS:
 472                 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
 473                 break;
 474         case SK_YUKON:
 475         case SK_YUKON_LITE:
 476         case SK_YUKON_LP:
 477                 v = sk_marv_miibus_readreg(sc_if, phy, reg);
 478                 break;
 479         default:
 480                 v = 0;
 481                 break;
 482         }
 483         SK_IF_MII_UNLOCK(sc_if);
 484
 485         return (v);
 486 }
 487
 488 static int
 489 sk_miibus_writereg(dev, phy, reg, val)
 490         device_t                dev;
 491         int                     phy, reg, val;
 492 {
 493         struct sk_if_softc      *sc_if;
 494         int                     v;
 495
 496         sc_if = device_get_softc(dev);
 497
 498         SK_IF_MII_LOCK(sc_if);
 499         switch(sc_if->sk_softc->sk_type) {
 500         case SK_GENESIS:
 501                 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 502                 break;
 503         case SK_YUKON:
 504         case SK_YUKON_LITE:
 505         case SK_YUKON_LP:
 506                 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
 507                 break;
 508         default:
 509                 v = 0;
 510                 break;
 511         }
 512         SK_IF_MII_UNLOCK(sc_if);
 513
 514         return (v);
 515 }
 516
 517 static void
 518 sk_miibus_statchg(dev)
 519         device_t                dev;
 520 {
 521         struct sk_if_softc      *sc_if;
 522
 523         sc_if = device_get_softc(dev);
 524
 525         SK_IF_MII_LOCK(sc_if);
 526         switch(sc_if->sk_softc->sk_type) {
 527         case SK_GENESIS:
 528                 sk_xmac_miibus_statchg(sc_if);
 529                 break;
 530         case SK_YUKON:
 531         case SK_YUKON_LITE:
 532         case SK_YUKON_LP:
 533                 sk_marv_miibus_statchg(sc_if);
 534                 break;
 535         }
 536         SK_IF_MII_UNLOCK(sc_if);
 537
 538         return;
 539 }
 540
 541 static int
 542 sk_xmac_miibus_readreg(sc_if, phy, reg)
 543         struct sk_if_softc      *sc_if;
 544         int                     phy, reg;
 545 {
 546         int                     i;
 547
 548         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 549         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 550         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 551                 for (i = 0; i < SK_TIMEOUT; i++) {
 552                         DELAY(1);
 553                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 554                             XM_MMUCMD_PHYDATARDY)
 555                                 break;
 556                 }
 557
 558                 if (i == SK_TIMEOUT) {
 559                         if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 560                         return(0);
 561                 }
 562         }
 563         DELAY(1);
 564         i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
 565
 566         return(i);
 567 }
 568
 569 static int
 570 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 571         struct sk_if_softc      *sc_if;
 572         int                     phy, reg, val;
 573 {
 574         int                     i;
 575
 576         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 577         for (i = 0; i < SK_TIMEOUT; i++) {
 578                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 579                         break;
 580         }
 581
 582         if (i == SK_TIMEOUT) {
 583                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 584                 return (ETIMEDOUT);
 585         }
 586
 587         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 588         for (i = 0; i < SK_TIMEOUT; i++) {
 589                 DELAY(1);
 590                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 591                         break;
 592         }
 593         if (i == SK_TIMEOUT)
 594                 if_printf(sc_if->sk_ifp, "phy write timed out\n");
 595
 596         return(0);
 597 }
 598
 599 static void
 600 sk_xmac_miibus_statchg(sc_if)
 601         struct sk_if_softc      *sc_if;
 602 {
 603         struct mii_data         *mii;
 604
 605         mii = device_get_softc(sc_if->sk_miibus);
 606
 607         /*
 608          * If this is a GMII PHY, manually set the XMAC's
 609          * duplex mode accordingly.
 610          */
 611         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 612                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 613                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 614                 } else {
 615                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 616                 }
 617         }
 618 }
 619
 620 static int
 621 sk_marv_miibus_readreg(sc_if, phy, reg)
 622         struct sk_if_softc      *sc_if;
 623         int                     phy, reg;
 624 {
 625         u_int16_t               val;
 626         int                     i;
 627
 628         if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 629             sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
 630                 return(0);
 631         }
 632
 633         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 634                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 635
 636         for (i = 0; i < SK_TIMEOUT; i++) {
 637                 DELAY(1);
 638                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 639                 if (val & YU_SMICR_READ_VALID)
 640                         break;
 641         }
 642
 643         if (i == SK_TIMEOUT) {
 644                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 645                 return(0);
 646         }
 647
 648         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 649
 650         return(val);
 651 }
 652
 653 static int
 654 sk_marv_miibus_writereg(sc_if, phy, reg, val)
 655         struct sk_if_softc      *sc_if;
 656         int                     phy, reg, val;
 657 {
 658         int                     i;
 659
 660         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 661         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 662                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 663
 664         for (i = 0; i < SK_TIMEOUT; i++) {
 665                 DELAY(1);
 666                 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
 667                         break;
 668         }
 669         if (i == SK_TIMEOUT)
 670                 if_printf(sc_if->sk_ifp, "phy write timeout\n");
 671
 672         return(0);
 673 }
 674
 675 static void
 676 sk_marv_miibus_statchg(sc_if)
 677         struct sk_if_softc      *sc_if;
 678 {
 679         return;
 680 }
 681
 682 #define HASH_BITS               6
 683
 684 static u_int32_t
 685 sk_xmchash(addr)
 686         const uint8_t *addr;
 687 {
 688         uint32_t crc;
 689
 690         /* Compute CRC for the address value. */
 691         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 692
 693         return (~crc & ((1 << HASH_BITS) - 1));
 694 }
 695
 696 static void
 697 sk_setfilt(sc_if, addr, slot)
 698         struct sk_if_softc      *sc_if;
 699         u_int16_t               *addr;
 700         int                     slot;
 701 {
 702         int                     base;
 703
 704         base = XM_RXFILT_ENTRY(slot);
 705
 706         SK_XM_WRITE_2(sc_if, base, addr[0]);
 707         SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
 708         SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
 709
 710         return;
 711 }
 712
 713 static void
 714 sk_rxfilter(sc_if)
 715         struct sk_if_softc      *sc_if;
 716 {
 717         struct sk_softc         *sc;
 718
 719         SK_IF_LOCK_ASSERT(sc_if);
 720
 721         sc = sc_if->sk_softc;
 722         if (sc->sk_type == SK_GENESIS)
 723                 sk_rxfilter_genesis(sc_if);
 724         else
 725                 sk_rxfilter_yukon(sc_if);
 726 }
 727
 728 static void
 729 sk_rxfilter_genesis(sc_if)
 730         struct sk_if_softc      *sc_if;
 731 {
 732         struct ifnet            *ifp = sc_if->sk_ifp;
 733         u_int32_t               hashes[2] = { 0, 0 }, mode;
 734         int                     h = 0, i;
 735         struct ifmultiaddr      *ifma;
 736         u_int16_t               dummy[] = { 0, 0, 0 };
 737         u_int16_t               maddr[(ETHER_ADDR_LEN+1)/2];
 738
 739         SK_IF_LOCK_ASSERT(sc_if);
 740
 741         mode = SK_XM_READ_4(sc_if, XM_MODE);
 742         mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
 743             XM_MODE_RX_USE_PERFECT);
 744         /* First, zot all the existing perfect filters. */
 745         for (i = 1; i < XM_RXFILT_MAX; i++)
 746                 sk_setfilt(sc_if, dummy, i);
 747
 748         /* Now program new ones. */
 749         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 750                 if (ifp->if_flags & IFF_ALLMULTI)
 751                         mode |= XM_MODE_RX_USE_HASH;
 752                 if (ifp->if_flags & IFF_PROMISC)
 753                         mode |= XM_MODE_RX_PROMISC;
 754                 hashes[0] = 0xFFFFFFFF;
 755                 hashes[1] = 0xFFFFFFFF;
 756         } else {
 757                 i = 1;
 758                 if_maddr_rlock(ifp);
 759                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
 760                     ifma_link) {
 761                         if (ifma->ifma_addr->sa_family != AF_LINK)
 762                                 continue;
 763                         /*
 764                          * Program the first XM_RXFILT_MAX multicast groups
 765                          * into the perfect filter.
 766                          */
 767                         bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 768                             maddr, ETHER_ADDR_LEN);
 769                         if (i < XM_RXFILT_MAX) {
 770                                 sk_setfilt(sc_if, maddr, i);
 771                                 mode |= XM_MODE_RX_USE_PERFECT;
 772                                 i++;
 773                                 continue;
 774                         }
 775                         h = sk_xmchash((const uint8_t *)maddr);
 776                         if (h < 32)
 777                                 hashes[0] |= (1 << h);
 778                         else
 779                                 hashes[1] |= (1 << (h - 32));
 780                         mode |= XM_MODE_RX_USE_HASH;
 781                 }
 782                 if_maddr_runlock(ifp);
 783         }
 784
 785         SK_XM_WRITE_4(sc_if, XM_MODE, mode);
 786         SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 787         SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 788 }
 789
 790 static void
 791 sk_rxfilter_yukon(sc_if)
 792         struct sk_if_softc      *sc_if;
 793 {
 794         struct ifnet            *ifp;
 795         u_int32_t               crc, hashes[2] = { 0, 0 }, mode;
 796         struct ifmultiaddr      *ifma;
 797
 798         SK_IF_LOCK_ASSERT(sc_if);
 799
 800         ifp = sc_if->sk_ifp;
 801         mode = SK_YU_READ_2(sc_if, YUKON_RCR);
 802         if (ifp->if_flags & IFF_PROMISC)
 803                 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
 804         else if (ifp->if_flags & IFF_ALLMULTI) {
 805                 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
 806                 hashes[0] = 0xFFFFFFFF;
 807                 hashes[1] = 0xFFFFFFFF;
 808         } else {
 809                 mode |= YU_RCR_UFLEN;
 810                 if_maddr_rlock(ifp);
 811                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 812                         if (ifma->ifma_addr->sa_family != AF_LINK)
 813                                 continue;
 814                         crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 815                             ifma->ifma_addr), ETHER_ADDR_LEN);
 816                         /* Just want the 6 least significant bits. */
 817                         crc &= 0x3f;
 818                         /* Set the corresponding bit in the hash table. */
 819                         hashes[crc >> 5] |= 1 << (crc & 0x1f);
 820                 }
 821                 if_maddr_runlock(ifp);
 822                 if (hashes[0] != 0 || hashes[1] != 0)
 823                         mode |= YU_RCR_MUFLEN;
 824         }
 825
 826         SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 827         SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 828         SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 829         SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 830         SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
 831 }
 832
 833 static int
 834 sk_init_rx_ring(sc_if)
 835         struct sk_if_softc      *sc_if;
 836 {
 837         struct sk_ring_data     *rd;
 838         bus_addr_t              addr;
 839         u_int32_t               csum_start;
 840         int                     i;
 841
 842         sc_if->sk_cdata.sk_rx_cons = 0;
 843
 844         csum_start = (ETHER_HDR_LEN + sizeof(struct ip))  << 16 |
 845             ETHER_HDR_LEN;
 846         rd = &sc_if->sk_rdata;
 847         bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 848         for (i = 0; i < SK_RX_RING_CNT; i++) {
 849                 if (sk_newbuf(sc_if, i) != 0)
 850                         return (ENOBUFS);
 851                 if (i == (SK_RX_RING_CNT - 1))
 852                         addr = SK_RX_RING_ADDR(sc_if, 0);
 853                 else
 854                         addr = SK_RX_RING_ADDR(sc_if, i + 1);
 855                 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 856                 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
 857         }
 858
 859         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
 860             sc_if->sk_cdata.sk_rx_ring_map,
 861             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 862
 863         return(0);
 864 }
 865
 866 static int
 867 sk_init_jumbo_rx_ring(sc_if)
 868         struct sk_if_softc      *sc_if;
 869 {
 870         struct sk_ring_data     *rd;
 871         bus_addr_t              addr;
 872         u_int32_t               csum_start;
 873         int                     i;
 874
 875         sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
 876
 877         csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
 878             ETHER_HDR_LEN;
 879         rd = &sc_if->sk_rdata;
 880         bzero(rd->sk_jumbo_rx_ring,
 881             sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
 882         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
 883                 if (sk_jumbo_newbuf(sc_if, i) != 0)
 884                         return (ENOBUFS);
 885                 if (i == (SK_JUMBO_RX_RING_CNT - 1))
 886                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
 887                 else
 888                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
 889                 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 890                 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
 891         }
 892
 893         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
 894             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
 895             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 896
 897         return (0);
 898 }
 899
 900 static void
 901 sk_init_tx_ring(sc_if)
 902         struct sk_if_softc      *sc_if;
 903 {
 904         struct sk_ring_data     *rd;
 905         struct sk_txdesc        *txd;
 906         bus_addr_t              addr;
 907         int                     i;
 908
 909         STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
 910         STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
 911
 912         sc_if->sk_cdata.sk_tx_prod = 0;
 913         sc_if->sk_cdata.sk_tx_cons = 0;
 914         sc_if->sk_cdata.sk_tx_cnt = 0;
 915
 916         rd = &sc_if->sk_rdata;
 917         bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 918         for (i = 0; i < SK_TX_RING_CNT; i++) {
 919                 if (i == (SK_TX_RING_CNT - 1))
 920                         addr = SK_TX_RING_ADDR(sc_if, 0);
 921                 else
 922                         addr = SK_TX_RING_ADDR(sc_if, i + 1);
 923                 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 924                 txd = &sc_if->sk_cdata.sk_txdesc[i];
 925                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
 926         }
 927
 928         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
 929             sc_if->sk_cdata.sk_tx_ring_map,
 930             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 931 }
 932
 933 static __inline void
 934 sk_discard_rxbuf(sc_if, idx)
 935         struct sk_if_softc      *sc_if;
 936         int                     idx;
 937 {
 938         struct sk_rx_desc       *r;
 939         struct sk_rxdesc        *rxd;
 940         struct mbuf             *m;
 941
 942
 943         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 944         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 945         m = rxd->rx_m;
 946         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 947 }
 948
 949 static __inline void
 950 sk_discard_jumbo_rxbuf(sc_if, idx)
 951         struct sk_if_softc      *sc_if;
 952         int                     idx;
 953 {
 954         struct sk_rx_desc       *r;
 955         struct sk_rxdesc        *rxd;
 956         struct mbuf             *m;
 957
 958         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
 959         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
 960         m = rxd->rx_m;
 961         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 962 }
 963
 964 static int
 965 sk_newbuf(sc_if, idx)
 966         struct sk_if_softc      *sc_if;
 967         int                     idx;
 968 {
 969         struct sk_rx_desc       *r;
 970         struct sk_rxdesc        *rxd;
 971         struct mbuf             *m;
 972         bus_dma_segment_t       segs[1];
 973         bus_dmamap_t            map;
 974         int                     nsegs;
 975
 976         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 977         if (m == NULL)
 978                 return (ENOBUFS);
 979         m->m_len = m->m_pkthdr.len = MCLBYTES;
 980         m_adj(m, ETHER_ALIGN);
 981
 982         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
 983             sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
 984                 m_freem(m);
 985                 return (ENOBUFS);
 986         }
 987         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 988
 989         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 990         if (rxd->rx_m != NULL) {
 991                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 992                     BUS_DMASYNC_POSTREAD);
 993                 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
 994         }
 995         map = rxd->rx_dmamap;
 996         rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
 997         sc_if->sk_cdata.sk_rx_sparemap = map;
 998         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 999             BUS_DMASYNC_PREREAD);
1000         rxd->rx_m = m;
1001         r = &sc_if->sk_rdata.sk_rx_ring[idx];
1002         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1003         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1004         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1005
1006         return (0);
1007 }
1008
1009 static int
1010 sk_jumbo_newbuf(sc_if, idx)
1011         struct sk_if_softc      *sc_if;
1012         int                     idx;
1013 {
1014         struct sk_rx_desc       *r;
1015         struct sk_rxdesc        *rxd;
1016         struct mbuf             *m;
1017         bus_dma_segment_t       segs[1];
1018         bus_dmamap_t            map;
1019         int                     nsegs;
1020
1021         m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1022         if (m == NULL)
1023                 return (ENOBUFS);
1024         if ((m->m_flags & M_EXT) == 0) {
1025                 m_freem(m);
1026                 return (ENOBUFS);
1027         }
1028         m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1029         /*
1030          * Adjust alignment so packet payload begins on a
1031          * longword boundary. Mandatory for Alpha, useful on
1032          * x86 too.
1033          */
1034         m_adj(m, ETHER_ALIGN);
1035
1036         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1037             sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1038                 m_freem(m);
1039                 return (ENOBUFS);
1040         }
1041         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1042
1043         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1044         if (rxd->rx_m != NULL) {
1045                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1046                     BUS_DMASYNC_POSTREAD);
1047                 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1048                     rxd->rx_dmamap);
1049         }
1050         map = rxd->rx_dmamap;
1051         rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1052         sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1053         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1054             BUS_DMASYNC_PREREAD);
1055         rxd->rx_m = m;
1056         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1057         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1058         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1059         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1060
1061         return (0);
1062 }
1063
1064 /*
1065  * Set media options.
1066  */
1067 static int
1068 sk_ifmedia_upd(ifp)
1069         struct ifnet            *ifp;
1070 {
1071         struct sk_if_softc      *sc_if = ifp->if_softc;
1072         struct mii_data         *mii;
1073
1074         mii = device_get_softc(sc_if->sk_miibus);
1075         sk_init(sc_if);
1076         mii_mediachg(mii);
1077
1078         return(0);
1079 }
1080
1081 /*
1082  * Report current media status.
1083  */
1084 static void
1085 sk_ifmedia_sts(ifp, ifmr)
1086         struct ifnet            *ifp;
1087         struct ifmediareq       *ifmr;
1088 {
1089         struct sk_if_softc      *sc_if;
1090         struct mii_data         *mii;
1091
1092         sc_if = ifp->if_softc;
1093         mii = device_get_softc(sc_if->sk_miibus);
1094
1095         mii_pollstat(mii);
1096         ifmr->ifm_active = mii->mii_media_active;
1097         ifmr->ifm_status = mii->mii_media_status;
1098
1099         return;
1100 }
1101
1102 static int
1103 sk_ioctl(ifp, command, data)
1104         struct ifnet            *ifp;
1105         u_long                  command;
1106         caddr_t                 data;
1107 {
1108         struct sk_if_softc      *sc_if = ifp->if_softc;
1109         struct ifreq            *ifr = (struct ifreq *) data;
1110         int                     error, mask;
1111         struct mii_data         *mii;
1112
1113         error = 0;
1114         switch(command) {
1115         case SIOCSIFMTU:
1116                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1117                         error = EINVAL;
1118                 else if (ifp->if_mtu != ifr->ifr_mtu) {
1119                         if (sc_if->sk_jumbo_disable != 0 &&
1120                             ifr->ifr_mtu > SK_MAX_FRAMELEN)
1121                                 error = EINVAL;
1122                         else {
1123                                 SK_IF_LOCK(sc_if);
1124                                 ifp->if_mtu = ifr->ifr_mtu;
1125                                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1126                                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1127                                         sk_init_locked(sc_if);
1128                                 }
1129                                 SK_IF_UNLOCK(sc_if);
1130                         }
1131                 }
1132                 break;
1133         case SIOCSIFFLAGS:
1134                 SK_IF_LOCK(sc_if);
1135                 if (ifp->if_flags & IFF_UP) {
1136                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1137                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1138                                     & (IFF_PROMISC | IFF_ALLMULTI))
1139                                         sk_rxfilter(sc_if);
1140                         } else
1141                                 sk_init_locked(sc_if);
1142                 } else {
1143                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1144                                 sk_stop(sc_if);
1145                 }
1146                 sc_if->sk_if_flags = ifp->if_flags;
1147                 SK_IF_UNLOCK(sc_if);
1148                 break;
1149         case SIOCADDMULTI:
1150         case SIOCDELMULTI:
1151                 SK_IF_LOCK(sc_if);
1152                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1153                         sk_rxfilter(sc_if);
1154                 SK_IF_UNLOCK(sc_if);
1155                 break;
1156         case SIOCGIFMEDIA:
1157         case SIOCSIFMEDIA:
1158                 mii = device_get_softc(sc_if->sk_miibus);
1159                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1160                 break;
1161         case SIOCSIFCAP:
1162                 SK_IF_LOCK(sc_if);
1163                 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1164                         SK_IF_UNLOCK(sc_if);
1165                         break;
1166                 }
1167                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1168                 if ((mask & IFCAP_TXCSUM) != 0 &&
1169                     (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1170                         ifp->if_capenable ^= IFCAP_TXCSUM;
1171                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1172                                 ifp->if_hwassist |= SK_CSUM_FEATURES;
1173                         else
1174                                 ifp->if_hwassist &= ~SK_CSUM_FEATURES;
1175                 }
1176                 if ((mask & IFCAP_RXCSUM) != 0 &&
1177                     (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
1178                         ifp->if_capenable ^= IFCAP_RXCSUM;
1179                 SK_IF_UNLOCK(sc_if);
1180                 break;
1181         default:
1182                 error = ether_ioctl(ifp, command, data);
1183                 break;
1184         }
1185
1186         return (error);
1187 }
1188
1189 /*
1190  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1191  * IDs against our list and return a device name if we find a match.
1192  */
1193 static int
1194 skc_probe(dev)
1195         device_t                dev;
1196 {
1197         struct sk_type          *t = sk_devs;
1198
1199         while(t->sk_name != NULL) {
1200                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1201                     (pci_get_device(dev) == t->sk_did)) {
1202                         /*
1203                          * Only attach to rev. 2 of the Linksys EG1032 adapter.
1204                          * Rev. 3 is supported by re(4).
1205                          */
1206                         if ((t->sk_vid == VENDORID_LINKSYS) &&
1207                                 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1208                                 (pci_get_subdevice(dev) !=
1209                                  SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1210                                 t++;
1211                                 continue;
1212                         }
1213                         device_set_desc(dev, t->sk_name);
1214                         return (BUS_PROBE_DEFAULT);
1215                 }
1216                 t++;
1217         }
1218
1219         return(ENXIO);
1220 }
1221
1222 /*
1223  * Force the GEnesis into reset, then bring it out of reset.
1224  */
1225 static void
1226 sk_reset(sc)
1227         struct sk_softc         *sc;
1228 {
1229
1230         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1231         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1232         if (SK_YUKON_FAMILY(sc->sk_type))
1233                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1234
1235         DELAY(1000);
1236         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1237         DELAY(2);
1238         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1239         if (SK_YUKON_FAMILY(sc->sk_type))
1240                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1241
1242         if (sc->sk_type == SK_GENESIS) {
1243                 /* Configure packet arbiter */
1244                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1245                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1246                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1247                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1248                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1249         }
1250
1251         /* Enable RAM interface */
1252         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1253
1254         /*
1255          * Configure interrupt moderation. The moderation timer
1256          * defers interrupts specified in the interrupt moderation
1257          * timer mask based on the timeout specified in the interrupt
1258          * moderation timer init register. Each bit in the timer
1259          * register represents one tick, so to specify a timeout in
1260          * microseconds, we have to multiply by the correct number of
1261          * ticks-per-microsecond.
1262          */
1263         switch (sc->sk_type) {
1264         case SK_GENESIS:
1265                 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1266                 break;
1267         default:
1268                 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1269                 break;
1270         }
1271         if (bootverbose)
1272                 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1273                     sc->sk_int_mod);
1274         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1275             sc->sk_int_ticks));
1276         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1277             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1278         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1279
1280         return;
1281 }
1282
1283 static int
1284 sk_probe(dev)
1285         device_t                dev;
1286 {
1287         struct sk_softc         *sc;
1288
1289         sc = device_get_softc(device_get_parent(dev));
1290
1291         /*
1292          * Not much to do here. We always know there will be
1293          * at least one XMAC present, and if there are two,
1294          * skc_attach() will create a second device instance
1295          * for us.
1296          */
1297         switch (sc->sk_type) {
1298         case SK_GENESIS:
1299                 device_set_desc(dev, "XaQti Corp. XMAC II");
1300                 break;
1301         case SK_YUKON:
1302         case SK_YUKON_LITE:
1303         case SK_YUKON_LP:
1304                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1305                 break;
1306         }
1307
1308         return (BUS_PROBE_DEFAULT);
1309 }
1310
1311 /*
1312  * Each XMAC chip is attached as a separate logical IP interface.
1313  * Single port cards will have only one logical interface of course.
1314  */
1315 static int
1316 sk_attach(dev)
1317         device_t                dev;
1318 {
1319         struct sk_softc         *sc;
1320         struct sk_if_softc      *sc_if;
1321         struct ifnet            *ifp;
1322         u_int32_t               r;
1323         int                     error, i, phy, port;
1324         u_char                  eaddr[6];
1325         u_char                  inv_mac[] = {0, 0, 0, 0, 0, 0};
1326
1327         if (dev == NULL)
1328                 return(EINVAL);
1329
1330         error = 0;
1331         sc_if = device_get_softc(dev);
1332         sc = device_get_softc(device_get_parent(dev));
1333         port = *(int *)device_get_ivars(dev);
1334
1335         sc_if->sk_if_dev = dev;
1336         sc_if->sk_port = port;
1337         sc_if->sk_softc = sc;
1338         sc->sk_if[port] = sc_if;
1339         if (port == SK_PORT_A)
1340                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1341         if (port == SK_PORT_B)
1342                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1343
1344         callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1345         callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1346
1347         if (sk_dma_alloc(sc_if) != 0) {
1348                 error = ENOMEM;
1349                 goto fail;
1350         }
1351         sk_dma_jumbo_alloc(sc_if);
1352
1353         ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1354         if (ifp == NULL) {
1355                 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1356                 error = ENOSPC;
1357                 goto fail;
1358         }
1359         ifp->if_softc = sc_if;
1360         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1361         ifp->if_mtu = ETHERMTU;
1362         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1363         /*
1364          * SK_GENESIS has a bug in checksum offload - From linux.
1365          */
1366         if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1367                 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
1368                 ifp->if_hwassist = 0;
1369         } else {
1370                 ifp->if_capabilities = 0;
1371                 ifp->if_hwassist = 0;
1372         }
1373         ifp->if_capenable = ifp->if_capabilities;
1374         /*
1375          * Some revision of Yukon controller generates corrupted
1376          * frame when TX checksum offloading is enabled.  The
1377          * frame has a valid checksum value so payload might be
1378          * modified during TX checksum calculation. Disable TX
1379          * checksum offloading but give users chance to enable it
1380          * when they know their controller works without problems
1381          * with TX checksum offloading.
1382          */
1383         ifp->if_capenable &= ~IFCAP_TXCSUM;
1384         ifp->if_ioctl = sk_ioctl;
1385         ifp->if_start = sk_start;
1386         ifp->if_init = sk_init;
1387         IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1388         ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1389         IFQ_SET_READY(&ifp->if_snd);
1390
1391         /*
1392          * Get station address for this interface. Note that
1393          * dual port cards actually come with three station
1394          * addresses: one for each port, plus an extra. The
1395          * extra one is used by the SysKonnect driver software
1396          * as a 'virtual' station address for when both ports
1397          * are operating in failover mode. Currently we don't
1398          * use this extra address.
1399          */
1400         SK_IF_LOCK(sc_if);
1401         for (i = 0; i < ETHER_ADDR_LEN; i++)
1402                 eaddr[i] =
1403                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1404
1405         /* Verify whether the station address is invalid or not. */
1406         if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1407                 device_printf(sc_if->sk_if_dev,
1408                     "Generating random ethernet address\n");
1409                 r = arc4random();
1410                 /*
1411                  * Set OUI to convenient locally assigned address.  'b'
1412                  * is 0x62, which has the locally assigned bit set, and
1413                  * the broadcast/multicast bit clear.
1414                  */
1415                 eaddr[0] = 'b';
1416                 eaddr[1] = 's';
1417                 eaddr[2] = 'd';
1418                 eaddr[3] = (r >> 16) & 0xff;
1419                 eaddr[4] = (r >>  8) & 0xff;
1420                 eaddr[5] = (r >>  0) & 0xff;
1421         }
1422         /*
1423          * Set up RAM buffer addresses. The NIC will have a certain
1424          * amount of SRAM on it, somewhere between 512K and 2MB. We
1425          * need to divide this up a) between the transmitter and
1426          * receiver and b) between the two XMACs, if this is a
1427          * dual port NIC. Our algotithm is to divide up the memory
1428          * evenly so that everyone gets a fair share.
1429          *
1430          * Just to be contrary, Yukon2 appears to have separate memory
1431          * for each MAC.
1432          */
1433         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1434                 u_int32_t               chunk, val;
1435
1436                 chunk = sc->sk_ramsize / 2;
1437                 val = sc->sk_rboff / sizeof(u_int64_t);
1438                 sc_if->sk_rx_ramstart = val;
1439                 val += (chunk / sizeof(u_int64_t));
1440                 sc_if->sk_rx_ramend = val - 1;
1441                 sc_if->sk_tx_ramstart = val;
1442                 val += (chunk / sizeof(u_int64_t));
1443                 sc_if->sk_tx_ramend = val - 1;
1444         } else {
1445                 u_int32_t               chunk, val;
1446
1447                 chunk = sc->sk_ramsize / 4;
1448                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1449                     sizeof(u_int64_t);
1450                 sc_if->sk_rx_ramstart = val;
1451                 val += (chunk / sizeof(u_int64_t));
1452                 sc_if->sk_rx_ramend = val - 1;
1453                 sc_if->sk_tx_ramstart = val;
1454                 val += (chunk / sizeof(u_int64_t));
1455                 sc_if->sk_tx_ramend = val - 1;
1456         }
1457
1458         /* Read and save PHY type and set PHY address */
1459         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1460         if (!SK_YUKON_FAMILY(sc->sk_type)) {
1461                 switch(sc_if->sk_phytype) {
1462                 case SK_PHYTYPE_XMAC:
1463                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1464                         break;
1465                 case SK_PHYTYPE_BCOM:
1466                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1467                         break;
1468                 default:
1469                         device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1470                             sc_if->sk_phytype);
1471                         error = ENODEV;
1472                         SK_IF_UNLOCK(sc_if);
1473                         goto fail;
1474                 }
1475         } else {
1476                 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1477                     sc->sk_pmd != 'S') {
1478                         /* not initialized, punt */
1479                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1480                         sc->sk_coppertype = 1;
1481                 }
1482
1483                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1484
1485                 if (!(sc->sk_coppertype))
1486                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1487         }
1488
1489         /*
1490          * Call MI attach routine.  Can't hold locks when calling into ether_*.
1491          */
1492         SK_IF_UNLOCK(sc_if);
1493         ether_ifattach(ifp, eaddr);
1494         SK_IF_LOCK(sc_if);
1495
1496         /*
1497          * The hardware should be ready for VLAN_MTU by default:
1498          * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1499          * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1500          *
1501          */
1502         ifp->if_capabilities |= IFCAP_VLAN_MTU;
1503         ifp->if_capenable |= IFCAP_VLAN_MTU;
1504         /*
1505          * Tell the upper layer(s) we support long frames.
1506          * Must appear after the call to ether_ifattach() because
1507          * ether_ifattach() sets ifi_hdrlen to the default value.
1508          */
1509         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1510
1511         /*
1512          * Do miibus setup.
1513          */
1514         phy = MII_PHY_ANY;
1515         switch (sc->sk_type) {
1516         case SK_GENESIS:
1517                 sk_init_xmac(sc_if);
1518                 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1519                         phy = 0;
1520                 break;
1521         case SK_YUKON:
1522         case SK_YUKON_LITE:
1523         case SK_YUKON_LP:
1524                 sk_init_yukon(sc_if);
1525                 phy = 0;
1526                 break;
1527         }
1528
1529         SK_IF_UNLOCK(sc_if);
1530         error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1531             sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1532         if (error != 0) {
1533                 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1534                 ether_ifdetach(ifp);
1535                 goto fail;
1536         }
1537
1538 fail:
1539         if (error) {
1540                 /* Access should be ok even though lock has been dropped */
1541                 sc->sk_if[port] = NULL;
1542                 sk_detach(dev);
1543         }
1544
1545         return(error);
1546 }
1547
1548 /*
1549  * Attach the interface. Allocate softc structures, do ifmedia
1550  * setup and ethernet/BPF attach.
1551  */
1552 static int
1553 skc_attach(dev)
1554         device_t                dev;
1555 {
1556         struct sk_softc         *sc;
1557         int                     error = 0, *port;
1558         uint8_t                 skrs;
1559         const char              *pname = NULL;
1560         char                    *revstr;
1561
1562         sc = device_get_softc(dev);
1563         sc->sk_dev = dev;
1564
1565         mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1566             MTX_DEF);
1567         mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1568         /*
1569          * Map control/status registers.
1570          */
1571         pci_enable_busmaster(dev);
1572
1573         /* Allocate resources */
1574 #ifdef SK_USEIOSPACE
1575         sc->sk_res_spec = sk_res_spec_io;
1576 #else
1577         sc->sk_res_spec = sk_res_spec_mem;
1578 #endif
1579         error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1580         if (error) {
1581                 if (sc->sk_res_spec == sk_res_spec_mem)
1582                         sc->sk_res_spec = sk_res_spec_io;
1583                 else
1584                         sc->sk_res_spec = sk_res_spec_mem;
1585                 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1586                 if (error) {
1587                         device_printf(dev, "couldn't allocate %s resources\n",
1588                             sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1589                             "I/O");
1590                         goto fail;
1591                 }
1592         }
1593
1594         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1595         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1596
1597         /* Bail out if chip is not recognized. */
1598         if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1599                 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1600                     sc->sk_type, sc->sk_rev);
1601                 error = ENXIO;
1602                 goto fail;
1603         }
1604
1605         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1606                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1607                 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1608                 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1609                 "SK interrupt moderation");
1610
1611         /* Pull in device tunables. */
1612         sc->sk_int_mod = SK_IM_DEFAULT;
1613         error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1614                 "int_mod", &sc->sk_int_mod);
1615         if (error == 0) {
1616                 if (sc->sk_int_mod < SK_IM_MIN ||
1617                     sc->sk_int_mod > SK_IM_MAX) {
1618                         device_printf(dev, "int_mod value out of range; "
1619                             "using default: %d\n", SK_IM_DEFAULT);
1620                         sc->sk_int_mod = SK_IM_DEFAULT;
1621                 }
1622         }
1623
1624         /* Reset the adapter. */
1625         sk_reset(sc);
1626
1627         skrs = sk_win_read_1(sc, SK_EPROM0);
1628         if (sc->sk_type == SK_GENESIS) {
1629                 /* Read and save RAM size and RAMbuffer offset */
1630                 switch(skrs) {
1631                 case SK_RAMSIZE_512K_64:
1632                         sc->sk_ramsize = 0x80000;
1633                         sc->sk_rboff = SK_RBOFF_0;
1634                         break;
1635                 case SK_RAMSIZE_1024K_64:
1636                         sc->sk_ramsize = 0x100000;
1637                         sc->sk_rboff = SK_RBOFF_80000;
1638                         break;
1639                 case SK_RAMSIZE_1024K_128:
1640                         sc->sk_ramsize = 0x100000;
1641                         sc->sk_rboff = SK_RBOFF_0;
1642                         break;
1643                 case SK_RAMSIZE_2048K_128:
1644                         sc->sk_ramsize = 0x200000;
1645                         sc->sk_rboff = SK_RBOFF_0;
1646                         break;
1647                 default:
1648                         device_printf(dev, "unknown ram size: %d\n", skrs);
1649                         error = ENXIO;
1650                         goto fail;
1651                 }
1652         } else { /* SK_YUKON_FAMILY */
1653                 if (skrs == 0x00)
1654                         sc->sk_ramsize = 0x20000;
1655                 else
1656                         sc->sk_ramsize = skrs * (1<<12);
1657                 sc->sk_rboff = SK_RBOFF_0;
1658         }
1659
1660         /* Read and save physical media type */
1661          sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1662
1663          if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1664                  sc->sk_coppertype = 1;
1665          else
1666                  sc->sk_coppertype = 0;
1667
1668         /* Determine whether to name it with VPD PN or just make it up.
1669          * Marvell Yukon VPD PN seems to freqently be bogus. */
1670         switch (pci_get_device(dev)) {
1671         case DEVICEID_SK_V1:
1672         case DEVICEID_BELKIN_5005:
1673         case DEVICEID_3COM_3C940:
1674         case DEVICEID_LINKSYS_EG1032:
1675         case DEVICEID_DLINK_DGE530T_A1:
1676         case DEVICEID_DLINK_DGE530T_B1:
1677                 /* Stay with VPD PN. */
1678                 (void) pci_get_vpd_ident(dev, &pname);
1679                 break;
1680         case DEVICEID_SK_V2:
1681                 /* YUKON VPD PN might bear no resemblance to reality. */
1682                 switch (sc->sk_type) {
1683                 case SK_GENESIS:
1684                         /* Stay with VPD PN. */
1685                         (void) pci_get_vpd_ident(dev, &pname);
1686                         break;
1687                 case SK_YUKON:
1688                         pname = "Marvell Yukon Gigabit Ethernet";
1689                         break;
1690                 case SK_YUKON_LITE:
1691                         pname = "Marvell Yukon Lite Gigabit Ethernet";
1692                         break;
1693                 case SK_YUKON_LP:
1694                         pname = "Marvell Yukon LP Gigabit Ethernet";
1695                         break;
1696                 default:
1697                         pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1698                         break;
1699                 }
1700
1701                 /* Yukon Lite Rev. A0 needs special test. */
1702                 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1703                         u_int32_t far;
1704                         u_int8_t testbyte;
1705
1706                         /* Save flash address register before testing. */
1707                         far = sk_win_read_4(sc, SK_EP_ADDR);
1708
1709                         sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1710                         testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1711
1712                         if (testbyte != 0x00) {
1713                                 /* Yukon Lite Rev. A0 detected. */
1714                                 sc->sk_type = SK_YUKON_LITE;
1715                                 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1716                                 /* Restore flash address register. */
1717                                 sk_win_write_4(sc, SK_EP_ADDR, far);
1718                         }
1719                 }
1720                 break;
1721         default:
1722                 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1723                         "chipver=%02x, rev=%x\n",
1724                         pci_get_vendor(dev), pci_get_device(dev),
1725                         sc->sk_type, sc->sk_rev);
1726                 error = ENXIO;
1727                 goto fail;
1728         }
1729
1730         if (sc->sk_type == SK_YUKON_LITE) {
1731                 switch (sc->sk_rev) {
1732                 case SK_YUKON_LITE_REV_A0:
1733                         revstr = "A0";
1734                         break;
1735                 case SK_YUKON_LITE_REV_A1:
1736                         revstr = "A1";
1737                         break;
1738                 case SK_YUKON_LITE_REV_A3:
1739                         revstr = "A3";
1740                         break;
1741                 default:
1742                         revstr = "";
1743                         break;
1744                 }
1745         } else {
1746                 revstr = "";
1747         }
1748
1749         /* Announce the product name and more VPD data if there. */
1750         if (pname != NULL)
1751                 device_printf(dev, "%s rev. %s(0x%x)\n",
1752                         pname, revstr, sc->sk_rev);
1753
1754         if (bootverbose) {
1755                 device_printf(dev, "chip ver  = 0x%02x\n", sc->sk_type);
1756                 device_printf(dev, "chip rev  = 0x%02x\n", sc->sk_rev);
1757                 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1758                 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1759         }
1760
1761         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1762         if (sc->sk_devs[SK_PORT_A] == NULL) {
1763                 device_printf(dev, "failed to add child for PORT_A\n");
1764                 error = ENXIO;
1765                 goto fail;
1766         }
1767         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1768         if (port == NULL) {
1769                 device_printf(dev, "failed to allocate memory for "
1770                     "ivars of PORT_A\n");
1771                 error = ENXIO;
1772                 goto fail;
1773         }
1774         *port = SK_PORT_A;
1775         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1776
1777         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1778                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1779                 if (sc->sk_devs[SK_PORT_B] == NULL) {
1780                         device_printf(dev, "failed to add child for PORT_B\n");
1781                         error = ENXIO;
1782                         goto fail;
1783                 }
1784                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1785                 if (port == NULL) {
1786                         device_printf(dev, "failed to allocate memory for "
1787                             "ivars of PORT_B\n");
1788                         error = ENXIO;
1789                         goto fail;
1790                 }
1791                 *port = SK_PORT_B;
1792                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1793         }
1794
1795         /* Turn on the 'driver is loaded' LED. */
1796         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1797
1798         error = bus_generic_attach(dev);
1799         if (error) {
1800                 device_printf(dev, "failed to attach port(s)\n");
1801                 goto fail;
1802         }
1803
1804         /* Hook interrupt last to avoid having to lock softc */
1805         error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1806             NULL, sk_intr, sc, &sc->sk_intrhand);
1807
1808         if (error) {
1809                 device_printf(dev, "couldn't set up irq\n");
1810                 goto fail;
1811         }
1812
1813 fail:
1814         if (error)
1815                 skc_detach(dev);
1816
1817         return(error);
1818 }
1819
1820 /*
1821  * Shutdown hardware and free up resources. This can be called any
1822  * time after the mutex has been initialized. It is called in both
1823  * the error case in attach and the normal detach case so it needs
1824  * to be careful about only freeing resources that have actually been
1825  * allocated.
1826  */
1827 static int
1828 sk_detach(dev)
1829         device_t                dev;
1830 {
1831         struct sk_if_softc      *sc_if;
1832         struct ifnet            *ifp;
1833
1834         sc_if = device_get_softc(dev);
1835         KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1836             ("sk mutex not initialized in sk_detach"));
1837         SK_IF_LOCK(sc_if);
1838
1839         ifp = sc_if->sk_ifp;
1840         /* These should only be active if attach_xmac succeeded */
1841         if (device_is_attached(dev)) {
1842                 sk_stop(sc_if);
1843                 /* Can't hold locks while calling detach */
1844                 SK_IF_UNLOCK(sc_if);
1845                 callout_drain(&sc_if->sk_tick_ch);
1846                 callout_drain(&sc_if->sk_watchdog_ch);
1847                 ether_ifdetach(ifp);
1848                 SK_IF_LOCK(sc_if);
1849         }
1850         if (ifp)
1851                 if_free(ifp);
1852         /*
1853          * We're generally called from skc_detach() which is using
1854          * device_delete_child() to get to here. It's already trashed
1855          * miibus for us, so don't do it here or we'll panic.
1856          */
1857         /*
1858         if (sc_if->sk_miibus != NULL)
1859                 device_delete_child(dev, sc_if->sk_miibus);
1860         */
1861         bus_generic_detach(dev);
1862         sk_dma_jumbo_free(sc_if);
1863         sk_dma_free(sc_if);
1864         SK_IF_UNLOCK(sc_if);
1865
1866         return(0);
1867 }
1868
1869 static int
1870 skc_detach(dev)
1871         device_t                dev;
1872 {
1873         struct sk_softc         *sc;
1874
1875         sc = device_get_softc(dev);
1876         KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1877
1878         if (device_is_alive(dev)) {
1879                 if (sc->sk_devs[SK_PORT_A] != NULL) {
1880                         free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1881                         device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1882                 }
1883                 if (sc->sk_devs[SK_PORT_B] != NULL) {
1884                         free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1885                         device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1886                 }
1887                 bus_generic_detach(dev);
1888         }
1889
1890         if (sc->sk_intrhand)
1891                 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1892         bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1893
1894         mtx_destroy(&sc->sk_mii_mtx);
1895         mtx_destroy(&sc->sk_mtx);
1896
1897         return(0);
1898 }
1899
1900 struct sk_dmamap_arg {
1901         bus_addr_t      sk_busaddr;
1902 };
1903
1904 static void
1905 sk_dmamap_cb(arg, segs, nseg, error)
1906         void                    *arg;
1907         bus_dma_segment_t       *segs;
1908         int                     nseg;
1909         int                     error;
1910 {
1911         struct sk_dmamap_arg    *ctx;
1912
1913         if (error != 0)
1914                 return;
1915
1916         ctx = arg;
1917         ctx->sk_busaddr = segs[0].ds_addr;
1918 }
1919
1920 /*
1921  * Allocate jumbo buffer storage. The SysKonnect adapters support
1922  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1923  * use them in their drivers. In order for us to use them, we need
1924  * large 9K receive buffers, however standard mbuf clusters are only
1925  * 2048 bytes in size. Consequently, we need to allocate and manage
1926  * our own jumbo buffer pool. Fortunately, this does not require an
1927  * excessive amount of additional code.
1928  */
1929 static int
1930 sk_dma_alloc(sc_if)
1931         struct sk_if_softc      *sc_if;
1932 {
1933         struct sk_dmamap_arg    ctx;
1934         struct sk_txdesc        *txd;
1935         struct sk_rxdesc        *rxd;
1936         int                     error, i;
1937
1938         /* create parent tag */
1939         /*
1940          * XXX
1941          * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1942          * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1943          * However bz@ reported that it does not work on amd64 with > 4GB
1944          * RAM. Until we have more clues of the breakage, disable DAC mode
1945          * by limiting DMA address to be in 32bit address space.
1946          */
1947         error = bus_dma_tag_create(
1948                     bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1949                     1, 0,                       /* algnmnt, boundary */
1950                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1951                     BUS_SPACE_MAXADDR,          /* highaddr */
1952                     NULL, NULL,                 /* filter, filterarg */
1953                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1954                     0,                          /* nsegments */
1955                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1956                     0,                          /* flags */
1957                     NULL, NULL,                 /* lockfunc, lockarg */
1958                     &sc_if->sk_cdata.sk_parent_tag);
1959         if (error != 0) {
1960                 device_printf(sc_if->sk_if_dev,
1961                     "failed to create parent DMA tag\n");
1962                 goto fail;
1963         }
1964
1965         /* create tag for Tx ring */
1966         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1967                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1968                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1969                     BUS_SPACE_MAXADDR,          /* highaddr */
1970                     NULL, NULL,                 /* filter, filterarg */
1971                     SK_TX_RING_SZ,              /* maxsize */
1972                     1,                          /* nsegments */
1973                     SK_TX_RING_SZ,              /* maxsegsize */
1974                     0,                          /* flags */
1975                     NULL, NULL,                 /* lockfunc, lockarg */
1976                     &sc_if->sk_cdata.sk_tx_ring_tag);
1977         if (error != 0) {
1978                 device_printf(sc_if->sk_if_dev,
1979                     "failed to allocate Tx ring DMA tag\n");
1980                 goto fail;
1981         }
1982
1983         /* create tag for Rx ring */
1984         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1985                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1986                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1987                     BUS_SPACE_MAXADDR,          /* highaddr */
1988                     NULL, NULL,                 /* filter, filterarg */
1989                     SK_RX_RING_SZ,              /* maxsize */
1990                     1,                          /* nsegments */
1991                     SK_RX_RING_SZ,              /* maxsegsize */
1992                     0,                          /* flags */
1993                     NULL, NULL,                 /* lockfunc, lockarg */
1994                     &sc_if->sk_cdata.sk_rx_ring_tag);
1995         if (error != 0) {
1996                 device_printf(sc_if->sk_if_dev,
1997                     "failed to allocate Rx ring DMA tag\n");
1998                 goto fail;
1999         }
2000
2001         /* create tag for Tx buffers */
2002         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2003                     1, 0,                       /* algnmnt, boundary */
2004                     BUS_SPACE_MAXADDR,          /* lowaddr */
2005                     BUS_SPACE_MAXADDR,          /* highaddr */
2006                     NULL, NULL,                 /* filter, filterarg */
2007                     MCLBYTES * SK_MAXTXSEGS,    /* maxsize */
2008                     SK_MAXTXSEGS,               /* nsegments */
2009                     MCLBYTES,                   /* maxsegsize */
2010                     0,                          /* flags */
2011                     NULL, NULL,                 /* lockfunc, lockarg */
2012                     &sc_if->sk_cdata.sk_tx_tag);
2013         if (error != 0) {
2014                 device_printf(sc_if->sk_if_dev,
2015                     "failed to allocate Tx DMA tag\n");
2016                 goto fail;
2017         }
2018
2019         /* create tag for Rx buffers */
2020         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2021                     1, 0,                       /* algnmnt, boundary */
2022                     BUS_SPACE_MAXADDR,          /* lowaddr */
2023                     BUS_SPACE_MAXADDR,          /* highaddr */
2024                     NULL, NULL,                 /* filter, filterarg */
2025                     MCLBYTES,                   /* maxsize */
2026                     1,                          /* nsegments */
2027                     MCLBYTES,                   /* maxsegsize */
2028                     0,                          /* flags */
2029                     NULL, NULL,                 /* lockfunc, lockarg */
2030                     &sc_if->sk_cdata.sk_rx_tag);
2031         if (error != 0) {
2032                 device_printf(sc_if->sk_if_dev,
2033                     "failed to allocate Rx DMA tag\n");
2034                 goto fail;
2035         }
2036
2037         /* allocate DMA'able memory and load the DMA map for Tx ring */
2038         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2039             (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
2040             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
2041         if (error != 0) {
2042                 device_printf(sc_if->sk_if_dev,
2043                     "failed to allocate DMA'able memory for Tx ring\n");
2044                 goto fail;
2045         }
2046
2047         ctx.sk_busaddr = 0;
2048         error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2049             sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2050             SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2051         if (error != 0) {
2052                 device_printf(sc_if->sk_if_dev,
2053                     "failed to load DMA'able memory for Tx ring\n");
2054                 goto fail;
2055         }
2056         sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2057
2058         /* allocate DMA'able memory and load the DMA map for Rx ring */
2059         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2060             (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2061             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2062         if (error != 0) {
2063                 device_printf(sc_if->sk_if_dev,
2064                     "failed to allocate DMA'able memory for Rx ring\n");
2065                 goto fail;
2066         }
2067
2068         ctx.sk_busaddr = 0;
2069         error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2070             sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2071             SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2072         if (error != 0) {
2073                 device_printf(sc_if->sk_if_dev,
2074                     "failed to load DMA'able memory for Rx ring\n");
2075                 goto fail;
2076         }
2077         sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2078
2079         /* create DMA maps for Tx buffers */
2080         for (i = 0; i < SK_TX_RING_CNT; i++) {
2081                 txd = &sc_if->sk_cdata.sk_txdesc[i];
2082                 txd->tx_m = NULL;
2083                 txd->tx_dmamap = NULL;
2084                 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2085                     &txd->tx_dmamap);
2086                 if (error != 0) {
2087                         device_printf(sc_if->sk_if_dev,
2088                             "failed to create Tx dmamap\n");
2089                         goto fail;
2090                 }
2091         }
2092
2093         /* create DMA maps for Rx buffers */
2094         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2095             &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2096                 device_printf(sc_if->sk_if_dev,
2097                     "failed to create spare Rx dmamap\n");
2098                 goto fail;
2099         }
2100         for (i = 0; i < SK_RX_RING_CNT; i++) {
2101                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2102                 rxd->rx_m = NULL;
2103                 rxd->rx_dmamap = NULL;
2104                 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2105                     &rxd->rx_dmamap);
2106                 if (error != 0) {
2107                         device_printf(sc_if->sk_if_dev,
2108                             "failed to create Rx dmamap\n");
2109                         goto fail;
2110                 }
2111         }
2112
2113 fail:
2114         return (error);
2115 }
2116
2117 static int
2118 sk_dma_jumbo_alloc(sc_if)
2119         struct sk_if_softc      *sc_if;
2120 {
2121         struct sk_dmamap_arg    ctx;
2122         struct sk_rxdesc        *jrxd;
2123         int                     error, i;
2124
2125         if (jumbo_disable != 0) {
2126                 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2127                 sc_if->sk_jumbo_disable = 1;
2128                 return (0);
2129         }
2130         /* create tag for jumbo Rx ring */
2131         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2132                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
2133                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2134                     BUS_SPACE_MAXADDR,          /* highaddr */
2135                     NULL, NULL,                 /* filter, filterarg */
2136                     SK_JUMBO_RX_RING_SZ,        /* maxsize */
2137                     1,                          /* nsegments */
2138                     SK_JUMBO_RX_RING_SZ,        /* maxsegsize */
2139                     0,                          /* flags */
2140                     NULL, NULL,                 /* lockfunc, lockarg */
2141                     &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2142         if (error != 0) {
2143                 device_printf(sc_if->sk_if_dev,
2144                     "failed to allocate jumbo Rx ring DMA tag\n");
2145                 goto jumbo_fail;
2146         }
2147
2148         /* create tag for jumbo Rx buffers */
2149         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2150                     1, 0,                       /* algnmnt, boundary */
2151                     BUS_SPACE_MAXADDR,          /* lowaddr */
2152                     BUS_SPACE_MAXADDR,          /* highaddr */
2153                     NULL, NULL,                 /* filter, filterarg */
2154                     MJUM9BYTES,                 /* maxsize */
2155                     1,                          /* nsegments */
2156                     MJUM9BYTES,                 /* maxsegsize */
2157                     0,                          /* flags */
2158                     NULL, NULL,                 /* lockfunc, lockarg */
2159                     &sc_if->sk_cdata.sk_jumbo_rx_tag);
2160         if (error != 0) {
2161                 device_printf(sc_if->sk_if_dev,
2162                     "failed to allocate jumbo Rx DMA tag\n");
2163                 goto jumbo_fail;
2164         }
2165
2166         /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2167         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2168             (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2169             BUS_DMA_COHERENT | BUS_DMA_ZERO,
2170             &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2171         if (error != 0) {
2172                 device_printf(sc_if->sk_if_dev,
2173                     "failed to allocate DMA'able memory for jumbo Rx ring\n");
2174                 goto jumbo_fail;
2175         }
2176
2177         ctx.sk_busaddr = 0;
2178         error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2179             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2180             sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2181             &ctx, BUS_DMA_NOWAIT);
2182         if (error != 0) {
2183                 device_printf(sc_if->sk_if_dev,
2184                     "failed to load DMA'able memory for jumbo Rx ring\n");
2185                 goto jumbo_fail;
2186         }
2187         sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2188
2189         /* create DMA maps for jumbo Rx buffers */
2190         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2191             &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2192                 device_printf(sc_if->sk_if_dev,
2193                     "failed to create spare jumbo Rx dmamap\n");
2194                 goto jumbo_fail;
2195         }
2196         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2197                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2198                 jrxd->rx_m = NULL;
2199                 jrxd->rx_dmamap = NULL;
2200                 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2201                     &jrxd->rx_dmamap);
2202                 if (error != 0) {
2203                         device_printf(sc_if->sk_if_dev,
2204                             "failed to create jumbo Rx dmamap\n");
2205                         goto jumbo_fail;
2206                 }
2207         }
2208
2209         return (0);
2210
2211 jumbo_fail:
2212         sk_dma_jumbo_free(sc_if);
2213         device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2214             "resource shortage\n");
2215         sc_if->sk_jumbo_disable = 1;
2216         return (0);
2217 }
2218
2219 static void
2220 sk_dma_free(sc_if)
2221         struct sk_if_softc      *sc_if;
2222 {
2223         struct sk_txdesc        *txd;
2224         struct sk_rxdesc        *rxd;
2225         int                     i;
2226
2227         /* Tx ring */
2228         if (sc_if->sk_cdata.sk_tx_ring_tag) {
2229                 if (sc_if->sk_cdata.sk_tx_ring_map)
2230                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2231                             sc_if->sk_cdata.sk_tx_ring_map);
2232                 if (sc_if->sk_cdata.sk_tx_ring_map &&
2233                     sc_if->sk_rdata.sk_tx_ring)
2234                         bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2235                             sc_if->sk_rdata.sk_tx_ring,
2236                             sc_if->sk_cdata.sk_tx_ring_map);
2237                 sc_if->sk_rdata.sk_tx_ring = NULL;
2238                 sc_if->sk_cdata.sk_tx_ring_map = NULL;
2239                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2240                 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2241         }
2242         /* Rx ring */
2243         if (sc_if->sk_cdata.sk_rx_ring_tag) {
2244                 if (sc_if->sk_cdata.sk_rx_ring_map)
2245                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2246                             sc_if->sk_cdata.sk_rx_ring_map);
2247                 if (sc_if->sk_cdata.sk_rx_ring_map &&
2248                     sc_if->sk_rdata.sk_rx_ring)
2249                         bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2250                             sc_if->sk_rdata.sk_rx_ring,
2251                             sc_if->sk_cdata.sk_rx_ring_map);
2252                 sc_if->sk_rdata.sk_rx_ring = NULL;
2253                 sc_if->sk_cdata.sk_rx_ring_map = NULL;
2254                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2255                 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2256         }
2257         /* Tx buffers */
2258         if (sc_if->sk_cdata.sk_tx_tag) {
2259                 for (i = 0; i < SK_TX_RING_CNT; i++) {
2260                         txd = &sc_if->sk_cdata.sk_txdesc[i];
2261                         if (txd->tx_dmamap) {
2262                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2263                                     txd->tx_dmamap);
2264                                 txd->tx_dmamap = NULL;
2265                         }
2266                 }
2267                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2268                 sc_if->sk_cdata.sk_tx_tag = NULL;
2269         }
2270         /* Rx buffers */
2271         if (sc_if->sk_cdata.sk_rx_tag) {
2272                 for (i = 0; i < SK_RX_RING_CNT; i++) {
2273                         rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2274                         if (rxd->rx_dmamap) {
2275                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2276                                     rxd->rx_dmamap);
2277                                 rxd->rx_dmamap = NULL;
2278                         }
2279                 }
2280                 if (sc_if->sk_cdata.sk_rx_sparemap) {
2281                         bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2282                             sc_if->sk_cdata.sk_rx_sparemap);
2283                         sc_if->sk_cdata.sk_rx_sparemap = NULL;
2284                 }
2285                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2286                 sc_if->sk_cdata.sk_rx_tag = NULL;
2287         }
2288
2289         if (sc_if->sk_cdata.sk_parent_tag) {
2290                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2291                 sc_if->sk_cdata.sk_parent_tag = NULL;
2292         }
2293 }
2294
2295 static void
2296 sk_dma_jumbo_free(sc_if)
2297         struct sk_if_softc      *sc_if;
2298 {
2299         struct sk_rxdesc        *jrxd;
2300         int                     i;
2301
2302         /* jumbo Rx ring */
2303         if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2304                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2305                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2306                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2307                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2308                     sc_if->sk_rdata.sk_jumbo_rx_ring)
2309                         bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2310                             sc_if->sk_rdata.sk_jumbo_rx_ring,
2311                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2312                 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2313                 sc_if->sk_cdata.sk_jumbo_rx_ring_map = NULL;
2314                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2315                 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2316         }
2317
2318         /* jumbo Rx buffers */
2319         if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2320                 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2321                         jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2322                         if (jrxd->rx_dmamap) {
2323                                 bus_dmamap_destroy(
2324                                     sc_if->sk_cdata.sk_jumbo_rx_tag,
2325                                     jrxd->rx_dmamap);
2326                                 jrxd->rx_dmamap = NULL;
2327                         }
2328                 }
2329                 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2330                         bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2331                             sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2332                         sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2333                 }
2334                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2335                 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2336         }
2337 }
2338
2339 static void
2340 sk_txcksum(ifp, m, f)
2341         struct ifnet            *ifp;
2342         struct mbuf             *m;
2343         struct sk_tx_desc       *f;
2344 {
2345         struct ip               *ip;
2346         u_int16_t               offset;
2347         u_int8_t                *p;
2348
2349         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2350         for(; m && m->m_len == 0; m = m->m_next)
2351                 ;
2352         if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2353                 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2354                 /* checksum may be corrupted */
2355                 goto sendit;
2356         }
2357         if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2358                 if (m->m_len != ETHER_HDR_LEN) {
2359                         if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2360                             __func__);
2361                         /* checksum may be corrupted */
2362                         goto sendit;
2363                 }
2364                 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2365                         ;
2366                 if (m == NULL) {
2367                         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2368                         /* checksum may be corrupted */
2369                         goto sendit;
2370                 }
2371                 ip = mtod(m, struct ip *);
2372         } else {
2373                 p = mtod(m, u_int8_t *);
2374                 p += ETHER_HDR_LEN;
2375                 ip = (struct ip *)p;
2376         }
2377         offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2378
2379 sendit:
2380         f->sk_csum_startval = 0;
2381         f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2382             (offset << 16));
2383 }
2384
2385 static int
2386 sk_encap(sc_if, m_head)
2387         struct sk_if_softc      *sc_if;
2388         struct mbuf             **m_head;
2389 {
2390         struct sk_txdesc        *txd;
2391         struct sk_tx_desc       *f = NULL;
2392         struct mbuf             *m;
2393         bus_dma_segment_t       txsegs[SK_MAXTXSEGS];
2394         u_int32_t               cflags, frag, si, sk_ctl;
2395         int                     error, i, nseg;
2396
2397         SK_IF_LOCK_ASSERT(sc_if);
2398
2399         if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2400                 return (ENOBUFS);
2401
2402         error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2403             txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2404         if (error == EFBIG) {
2405                 m = m_defrag(*m_head, M_DONTWAIT);
2406                 if (m == NULL) {
2407                         m_freem(*m_head);
2408                         *m_head = NULL;
2409                         return (ENOMEM);
2410                 }
2411                 *m_head = m;
2412                 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2413                     txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2414                 if (error != 0) {
2415                         m_freem(*m_head);
2416                         *m_head = NULL;
2417                         return (error);
2418                 }
2419         } else if (error != 0)
2420                 return (error);
2421         if (nseg == 0) {
2422                 m_freem(*m_head);
2423                 *m_head = NULL;
2424                 return (EIO);
2425         }
2426         if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2427                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2428                 return (ENOBUFS);
2429         }
2430
2431         m = *m_head;
2432         if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2433                 cflags = SK_OPCODE_CSUM;
2434         else
2435                 cflags = SK_OPCODE_DEFAULT;
2436         si = frag = sc_if->sk_cdata.sk_tx_prod;
2437         for (i = 0; i < nseg; i++) {
2438                 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2439                 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2440                 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2441                 sk_ctl = txsegs[i].ds_len | cflags;
2442                 if (i == 0) {
2443                         if (cflags == SK_OPCODE_CSUM)
2444                                 sk_txcksum(sc_if->sk_ifp, m, f);
2445                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
2446                 } else
2447                         sk_ctl |= SK_TXCTL_OWN;
2448                 f->sk_ctl = htole32(sk_ctl);
2449                 sc_if->sk_cdata.sk_tx_cnt++;
2450                 SK_INC(frag, SK_TX_RING_CNT);
2451         }
2452         sc_if->sk_cdata.sk_tx_prod = frag;
2453
2454         /* set EOF on the last desciptor */
2455         frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2456         f = &sc_if->sk_rdata.sk_tx_ring[frag];
2457         f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2458
2459         /* turn the first descriptor ownership to NIC */
2460         f = &sc_if->sk_rdata.sk_tx_ring[si];
2461         f->sk_ctl |= htole32(SK_TXCTL_OWN);
2462
2463         STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2464         STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2465         txd->tx_m = m;
2466
2467         /* sync descriptors */
2468         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2469             BUS_DMASYNC_PREWRITE);
2470         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2471             sc_if->sk_cdata.sk_tx_ring_map,
2472             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2473
2474         return (0);
2475 }
2476
2477 static void
2478 sk_start(ifp)
2479         struct ifnet            *ifp;
2480 {
2481         struct sk_if_softc *sc_if;
2482
2483         sc_if = ifp->if_softc;
2484
2485         SK_IF_LOCK(sc_if);
2486         sk_start_locked(ifp);
2487         SK_IF_UNLOCK(sc_if);
2488
2489         return;
2490 }
2491
2492 static void
2493 sk_start_locked(ifp)
2494         struct ifnet            *ifp;
2495 {
2496         struct sk_softc         *sc;
2497         struct sk_if_softc      *sc_if;
2498         struct mbuf             *m_head;
2499         int                     enq;
2500
2501         sc_if = ifp->if_softc;
2502         sc = sc_if->sk_softc;
2503
2504         SK_IF_LOCK_ASSERT(sc_if);
2505
2506         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2507             sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2508                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2509                 if (m_head == NULL)
2510                         break;
2511
2512                 /*
2513                  * Pack the data into the transmit ring. If we
2514                  * don't have room, set the OACTIVE flag and wait
2515                  * for the NIC to drain the ring.
2516                  */
2517                 if (sk_encap(sc_if, &m_head)) {
2518                         if (m_head == NULL)
2519                                 break;
2520                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2521                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2522                         break;
2523                 }
2524
2525                 enq++;
2526                 /*
2527                  * If there's a BPF listener, bounce a copy of this frame
2528                  * to him.
2529                  */
2530                 BPF_MTAP(ifp, m_head);
2531         }
2532
2533         if (enq > 0) {
2534                 /* Transmit */
2535                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2536
2537                 /* Set a timeout in case the chip goes out to lunch. */
2538                 sc_if->sk_watchdog_timer = 5;
2539         }
2540 }
2541
2542
2543 static void
2544 sk_watchdog(arg)
2545         void                    *arg;
2546 {
2547         struct sk_if_softc      *sc_if;
2548         struct ifnet            *ifp;
2549
2550         ifp = arg;
2551         sc_if = ifp->if_softc;
2552
2553         SK_IF_LOCK_ASSERT(sc_if);
2554
2555         if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2556                 goto done;
2557
2558         /*
2559          * Reclaim first as there is a possibility of losing Tx completion
2560          * interrupts.
2561          */
2562         sk_txeof(sc_if);
2563         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2564                 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2565                 ifp->if_oerrors++;
2566                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2567                 sk_init_locked(sc_if);
2568         }
2569
2570 done:
2571         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2572
2573         return;
2574 }
2575
2576 static int
2577 skc_shutdown(dev)
2578         device_t                dev;
2579 {
2580         struct sk_softc         *sc;
2581
2582         sc = device_get_softc(dev);
2583         SK_LOCK(sc);
2584
2585         /* Turn off the 'driver is loaded' LED. */
2586         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2587
2588         /*
2589          * Reset the GEnesis controller. Doing this should also
2590          * assert the resets on the attached XMAC(s).
2591          */
2592         sk_reset(sc);
2593         SK_UNLOCK(sc);
2594
2595         return (0);
2596 }
2597
2598 static int
2599 skc_suspend(dev)
2600         device_t                dev;
2601 {
2602         struct sk_softc         *sc;
2603         struct sk_if_softc      *sc_if0, *sc_if1;
2604         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2605
2606         sc = device_get_softc(dev);
2607
2608         SK_LOCK(sc);
2609
2610         sc_if0 = sc->sk_if[SK_PORT_A];
2611         sc_if1 = sc->sk_if[SK_PORT_B];
2612         if (sc_if0 != NULL)
2613                 ifp0 = sc_if0->sk_ifp;
2614         if (sc_if1 != NULL)
2615                 ifp1 = sc_if1->sk_ifp;
2616         if (ifp0 != NULL)
2617                 sk_stop(sc_if0);
2618         if (ifp1 != NULL)
2619                 sk_stop(sc_if1);
2620         sc->sk_suspended = 1;
2621
2622         SK_UNLOCK(sc);
2623
2624         return (0);
2625 }
2626
2627 static int
2628 skc_resume(dev)
2629         device_t                dev;
2630 {
2631         struct sk_softc         *sc;
2632         struct sk_if_softc      *sc_if0, *sc_if1;
2633         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2634
2635         sc = device_get_softc(dev);
2636
2637         SK_LOCK(sc);
2638
2639         sc_if0 = sc->sk_if[SK_PORT_A];
2640         sc_if1 = sc->sk_if[SK_PORT_B];
2641         if (sc_if0 != NULL)
2642                 ifp0 = sc_if0->sk_ifp;
2643         if (sc_if1 != NULL)
2644                 ifp1 = sc_if1->sk_ifp;
2645         if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2646                 sk_init_locked(sc_if0);
2647         if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2648                 sk_init_locked(sc_if1);
2649         sc->sk_suspended = 0;
2650
2651         SK_UNLOCK(sc);
2652
2653         return (0);
2654 }
2655
2656 /*
2657  * According to the data sheet from SK-NET GENESIS the hardware can compute
2658  * two Rx checksums at the same time(Each checksum start position is
2659  * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2660  * does not work at least on my Yukon hardware. I tried every possible ways
2661  * to get correct checksum value but couldn't get correct one. So TCP/UDP
2662  * checksum offload was disabled at the moment and only IP checksum offload
2663  * was enabled.
2664  * As nomral IP header size is 20 bytes I can't expect it would give an
2665  * increase in throughput. However it seems it doesn't hurt performance in
2666  * my testing. If there is a more detailed information for checksum secret
2667  * of the hardware in question please contact yongari@FreeBSD.org to add
2668  * TCP/UDP checksum offload support.
2669  */
2670 static __inline void
2671 sk_rxcksum(ifp, m, csum)
2672         struct ifnet            *ifp;
2673         struct mbuf             *m;
2674         u_int32_t               csum;
2675 {
2676         struct ether_header     *eh;
2677         struct ip               *ip;
2678         int32_t                 hlen, len, pktlen;
2679         u_int16_t               csum1, csum2, ipcsum;
2680
2681         pktlen = m->m_pkthdr.len;
2682         if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2683                 return;
2684         eh = mtod(m, struct ether_header *);
2685         if (eh->ether_type != htons(ETHERTYPE_IP))
2686                 return;
2687         ip = (struct ip *)(eh + 1);
2688         if (ip->ip_v != IPVERSION)
2689                 return;
2690         hlen = ip->ip_hl << 2;
2691         pktlen -= sizeof(struct ether_header);
2692         if (hlen < sizeof(struct ip))
2693                 return;
2694         if (ntohs(ip->ip_len) < hlen)
2695                 return;
2696         if (ntohs(ip->ip_len) != pktlen)
2697                 return;
2698
2699         csum1 = htons(csum & 0xffff);
2700         csum2 = htons((csum >> 16) & 0xffff);
2701         ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2702         /* checksum fixup for IP options */
2703         len = hlen - sizeof(struct ip);
2704         if (len > 0) {
2705                 /*
2706                  * If the second checksum value is correct we can compute IP
2707                  * checksum with simple math. Unfortunately the second checksum
2708                  * value is wrong so we can't verify the checksum from the
2709                  * value(It seems there is some magic here to get correct
2710                  * value). If the second checksum value is correct it also
2711                  * means we can get TCP/UDP checksum) here. However, it still
2712                  * needs pseudo header checksum calculation due to hardware
2713                  * limitations.
2714                  */
2715                 return;
2716         }
2717         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2718         if (ipcsum == 0xffff)
2719                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2720 }
2721
2722 static __inline int
2723 sk_rxvalid(sc, stat, len)
2724         struct sk_softc         *sc;
2725         u_int32_t               stat, len;
2726 {
2727
2728         if (sc->sk_type == SK_GENESIS) {
2729                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2730                     XM_RXSTAT_BYTES(stat) != len)
2731                         return (0);
2732         } else {
2733                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2734                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2735                     YU_RXSTAT_JABBER)) != 0 ||
2736                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2737                     YU_RXSTAT_BYTES(stat) != len)
2738                         return (0);
2739         }
2740
2741         return (1);
2742 }
2743
2744 static void
2745 sk_rxeof(sc_if)
2746         struct sk_if_softc      *sc_if;
2747 {
2748         struct sk_softc         *sc;
2749         struct mbuf             *m;
2750         struct ifnet            *ifp;
2751         struct sk_rx_desc       *cur_rx;
2752         struct sk_rxdesc        *rxd;
2753         int                     cons, prog;
2754         u_int32_t               csum, rxstat, sk_ctl;
2755
2756         sc = sc_if->sk_softc;
2757         ifp = sc_if->sk_ifp;
2758
2759         SK_IF_LOCK_ASSERT(sc_if);
2760
2761         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2762             sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2763
2764         prog = 0;
2765         for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2766             prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2767                 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2768                 sk_ctl = le32toh(cur_rx->sk_ctl);
2769                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2770                         break;
2771                 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2772                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2773
2774                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2775                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2776                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2777                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2778                     SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2779                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2780                         ifp->if_ierrors++;
2781                         sk_discard_rxbuf(sc_if, cons);
2782                         continue;
2783                 }
2784
2785                 m = rxd->rx_m;
2786                 csum = le32toh(cur_rx->sk_csum);
2787                 if (sk_newbuf(sc_if, cons) != 0) {
2788                         ifp->if_iqdrops++;
2789                         /* reuse old buffer */
2790                         sk_discard_rxbuf(sc_if, cons);
2791                         continue;
2792                 }
2793                 m->m_pkthdr.rcvif = ifp;
2794                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2795                 ifp->if_ipackets++;
2796                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2797                         sk_rxcksum(ifp, m, csum);
2798                 SK_IF_UNLOCK(sc_if);
2799                 (*ifp->if_input)(ifp, m);
2800                 SK_IF_LOCK(sc_if);
2801         }
2802
2803         if (prog > 0) {
2804                 sc_if->sk_cdata.sk_rx_cons = cons;
2805                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2806                     sc_if->sk_cdata.sk_rx_ring_map,
2807                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2808         }
2809 }
2810
2811 static void
2812 sk_jumbo_rxeof(sc_if)
2813         struct sk_if_softc      *sc_if;
2814 {
2815         struct sk_softc         *sc;
2816         struct mbuf             *m;
2817         struct ifnet            *ifp;
2818         struct sk_rx_desc       *cur_rx;
2819         struct sk_rxdesc        *jrxd;
2820         int                     cons, prog;
2821         u_int32_t               csum, rxstat, sk_ctl;
2822
2823         sc = sc_if->sk_softc;
2824         ifp = sc_if->sk_ifp;
2825
2826         SK_IF_LOCK_ASSERT(sc_if);
2827
2828         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2829             sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2830
2831         prog = 0;
2832         for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2833             prog < SK_JUMBO_RX_RING_CNT;
2834             prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2835                 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2836                 sk_ctl = le32toh(cur_rx->sk_ctl);
2837                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2838                         break;
2839                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2840                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2841
2842                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2843                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2844                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2845                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2846                     SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2847                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2848                         ifp->if_ierrors++;
2849                         sk_discard_jumbo_rxbuf(sc_if, cons);
2850                         continue;
2851                 }
2852
2853                 m = jrxd->rx_m;
2854                 csum = le32toh(cur_rx->sk_csum);
2855                 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2856                         ifp->if_iqdrops++;
2857                         /* reuse old buffer */
2858                         sk_discard_jumbo_rxbuf(sc_if, cons);
2859                         continue;
2860                 }
2861                 m->m_pkthdr.rcvif = ifp;
2862                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2863                 ifp->if_ipackets++;
2864                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2865                         sk_rxcksum(ifp, m, csum);
2866                 SK_IF_UNLOCK(sc_if);
2867                 (*ifp->if_input)(ifp, m);
2868                 SK_IF_LOCK(sc_if);
2869         }
2870
2871         if (prog > 0) {
2872                 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2873                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2874                     sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2875                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2876         }
2877 }
2878
2879 static void
2880 sk_txeof(sc_if)
2881         struct sk_if_softc      *sc_if;
2882 {
2883         struct sk_softc         *sc;
2884         struct sk_txdesc        *txd;
2885         struct sk_tx_desc       *cur_tx;
2886         struct ifnet            *ifp;
2887         u_int32_t               idx, sk_ctl;
2888
2889         sc = sc_if->sk_softc;
2890         ifp = sc_if->sk_ifp;
2891
2892         txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2893         if (txd == NULL)
2894                 return;
2895         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2896             sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2897         /*
2898          * Go through our tx ring and free mbufs for those
2899          * frames that have been sent.
2900          */
2901         for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2902                 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2903                         break;
2904                 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2905                 sk_ctl = le32toh(cur_tx->sk_ctl);
2906                 if (sk_ctl & SK_TXCTL_OWN)
2907                         break;
2908                 sc_if->sk_cdata.sk_tx_cnt--;
2909                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2910                 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2911                         continue;
2912                 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2913                     BUS_DMASYNC_POSTWRITE);
2914                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2915
2916                 ifp->if_opackets++;
2917                 m_freem(txd->tx_m);
2918                 txd->tx_m = NULL;
2919                 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2920                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2921                 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2922         }
2923         sc_if->sk_cdata.sk_tx_cons = idx;
2924         sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2925
2926         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2927             sc_if->sk_cdata.sk_tx_ring_map,
2928             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2929 }
2930
2931 static void
2932 sk_tick(xsc_if)
2933         void                    *xsc_if;
2934 {
2935         struct sk_if_softc      *sc_if;
2936         struct mii_data         *mii;
2937         struct ifnet            *ifp;
2938         int                     i;
2939
2940         sc_if = xsc_if;
2941         ifp = sc_if->sk_ifp;
2942         mii = device_get_softc(sc_if->sk_miibus);
2943
2944         if (!(ifp->if_flags & IFF_UP))
2945                 return;
2946
2947         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2948                 sk_intr_bcom(sc_if);
2949                 return;
2950         }
2951
2952         /*
2953          * According to SysKonnect, the correct way to verify that
2954          * the link has come back up is to poll bit 0 of the GPIO
2955          * register three times. This pin has the signal from the
2956          * link_sync pin connected to it; if we read the same link
2957          * state 3 times in a row, we know the link is up.
2958          */
2959         for (i = 0; i < 3; i++) {
2960                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2961                         break;
2962         }
2963
2964         if (i != 3) {
2965                 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2966                 return;
2967         }
2968
2969         /* Turn the GP0 interrupt back on. */
2970         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2971         SK_XM_READ_2(sc_if, XM_ISR);
2972         mii_tick(mii);
2973         callout_stop(&sc_if->sk_tick_ch);
2974 }
2975
2976 static void
2977 sk_yukon_tick(xsc_if)
2978         void                    *xsc_if;
2979 {
2980         struct sk_if_softc      *sc_if;
2981         struct mii_data         *mii;
2982
2983         sc_if = xsc_if;
2984         mii = device_get_softc(sc_if->sk_miibus);
2985
2986         mii_tick(mii);
2987         callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2988 }
2989
2990 static void
2991 sk_intr_bcom(sc_if)
2992         struct sk_if_softc      *sc_if;
2993 {
2994         struct mii_data         *mii;
2995         struct ifnet            *ifp;
2996         int                     status;
2997         mii = device_get_softc(sc_if->sk_miibus);
2998         ifp = sc_if->sk_ifp;
2999
3000         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3001
3002         /*
3003          * Read the PHY interrupt register to make sure
3004          * we clear any pending interrupts.
3005          */
3006         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
3007
3008         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3009                 sk_init_xmac(sc_if);
3010                 return;
3011         }
3012
3013         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3014                 int                     lstat;
3015                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3016                     BRGPHY_MII_AUXSTS);
3017
3018                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3019                         mii_mediachg(mii);
3020                         /* Turn off the link LED. */
3021                         SK_IF_WRITE_1(sc_if, 0,
3022                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
3023                         sc_if->sk_link = 0;
3024                 } else if (status & BRGPHY_ISR_LNK_CHG) {
3025                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3026                             BRGPHY_MII_IMR, 0xFF00);
3027                         mii_tick(mii);
3028                         sc_if->sk_link = 1;
3029                         /* Turn on the link LED. */
3030                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3031                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3032                             SK_LINKLED_BLINK_OFF);
3033                 } else {
3034                         mii_tick(mii);
3035                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3036                 }
3037         }
3038
3039         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3040
3041         return;
3042 }
3043
3044 static void
3045 sk_intr_xmac(sc_if)
3046         struct sk_if_softc      *sc_if;
3047 {
3048         struct sk_softc         *sc;
3049         u_int16_t               status;
3050
3051         sc = sc_if->sk_softc;
3052         status = SK_XM_READ_2(sc_if, XM_ISR);
3053
3054         /*
3055          * Link has gone down. Start MII tick timeout to
3056          * watch for link resync.
3057          */
3058         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3059                 if (status & XM_ISR_GP0_SET) {
3060                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3061                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3062                 }
3063
3064                 if (status & XM_ISR_AUTONEG_DONE) {
3065                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3066                 }
3067         }
3068
3069         if (status & XM_IMR_TX_UNDERRUN)
3070                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3071
3072         if (status & XM_IMR_RX_OVERRUN)
3073                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3074
3075         status = SK_XM_READ_2(sc_if, XM_ISR);
3076
3077         return;
3078 }
3079
3080 static void
3081 sk_intr_yukon(sc_if)
3082         struct sk_if_softc      *sc_if;
3083 {
3084         u_int8_t status;
3085
3086         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3087         /* RX overrun */
3088         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3089                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3090                     SK_RFCTL_RX_FIFO_OVER);
3091         }
3092         /* TX underrun */
3093         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3094                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3095                     SK_TFCTL_TX_FIFO_UNDER);
3096         }
3097 }
3098
3099 static void
3100 sk_intr(xsc)
3101         void                    *xsc;
3102 {
3103         struct sk_softc         *sc = xsc;
3104         struct sk_if_softc      *sc_if0, *sc_if1;
3105         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
3106         u_int32_t               status;
3107
3108         SK_LOCK(sc);
3109
3110         status = CSR_READ_4(sc, SK_ISSR);
3111         if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3112                 goto done_locked;
3113
3114         sc_if0 = sc->sk_if[SK_PORT_A];
3115         sc_if1 = sc->sk_if[SK_PORT_B];
3116
3117         if (sc_if0 != NULL)
3118                 ifp0 = sc_if0->sk_ifp;
3119         if (sc_if1 != NULL)
3120                 ifp1 = sc_if1->sk_ifp;
3121
3122         for (; (status &= sc->sk_intrmask) != 0;) {
3123                 /* Handle receive interrupts first. */
3124                 if (status & SK_ISR_RX1_EOF) {
3125                         if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3126                                 sk_jumbo_rxeof(sc_if0);
3127                         else
3128                                 sk_rxeof(sc_if0);
3129                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3130                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3131                 }
3132                 if (status & SK_ISR_RX2_EOF) {
3133                         if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3134                                 sk_jumbo_rxeof(sc_if1);
3135                         else
3136                                 sk_rxeof(sc_if1);
3137                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3138                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3139                 }
3140
3141                 /* Then transmit interrupts. */
3142                 if (status & SK_ISR_TX1_S_EOF) {
3143                         sk_txeof(sc_if0);
3144                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3145                 }
3146                 if (status & SK_ISR_TX2_S_EOF) {
3147                         sk_txeof(sc_if1);
3148                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3149                 }
3150
3151                 /* Then MAC interrupts. */
3152                 if (status & SK_ISR_MAC1 &&
3153                     ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3154                         if (sc->sk_type == SK_GENESIS)
3155                                 sk_intr_xmac(sc_if0);
3156                         else
3157                                 sk_intr_yukon(sc_if0);
3158                 }
3159
3160                 if (status & SK_ISR_MAC2 &&
3161                     ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3162                         if (sc->sk_type == SK_GENESIS)
3163                                 sk_intr_xmac(sc_if1);
3164                         else
3165                                 sk_intr_yukon(sc_if1);
3166                 }
3167
3168                 if (status & SK_ISR_EXTERNAL_REG) {
3169                         if (ifp0 != NULL &&
3170                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3171                                 sk_intr_bcom(sc_if0);
3172                         if (ifp1 != NULL &&
3173                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3174                                 sk_intr_bcom(sc_if1);
3175                 }
3176                 status = CSR_READ_4(sc, SK_ISSR);
3177         }
3178
3179         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3180
3181         if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3182                 sk_start_locked(ifp0);
3183         if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3184                 sk_start_locked(ifp1);
3185
3186 done_locked:
3187         SK_UNLOCK(sc);
3188 }
3189
3190 static void
3191 sk_init_xmac(sc_if)
3192         struct sk_if_softc      *sc_if;
3193 {
3194         struct sk_softc         *sc;
3195         struct ifnet            *ifp;
3196         u_int16_t               eaddr[(ETHER_ADDR_LEN+1)/2];
3197         struct sk_bcom_hack     bhack[] = {
3198         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3199         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3200         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3201         { 0, 0 } };
3202
3203         SK_IF_LOCK_ASSERT(sc_if);
3204
3205         sc = sc_if->sk_softc;
3206         ifp = sc_if->sk_ifp;
3207
3208         /* Unreset the XMAC. */
3209         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3210         DELAY(1000);
3211
3212         /* Reset the XMAC's internal state. */
3213         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3214
3215         /* Save the XMAC II revision */
3216         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3217
3218         /*
3219          * Perform additional initialization for external PHYs,
3220          * namely for the 1000baseTX cards that use the XMAC's
3221          * GMII mode.
3222          */
3223         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3224                 int                     i = 0;
3225                 u_int32_t               val;
3226
3227                 /* Take PHY out of reset. */
3228                 val = sk_win_read_4(sc, SK_GPIO);
3229                 if (sc_if->sk_port == SK_PORT_A)
3230                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3231                 else
3232                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3233                 sk_win_write_4(sc, SK_GPIO, val);
3234
3235                 /* Enable GMII mode on the XMAC. */
3236                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3237
3238                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3239                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3240                 DELAY(10000);
3241                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3242                     BRGPHY_MII_IMR, 0xFFF0);
3243
3244                 /*
3245                  * Early versions of the BCM5400 apparently have
3246                  * a bug that requires them to have their reserved
3247                  * registers initialized to some magic values. I don't
3248                  * know what the numbers do, I'm just the messenger.
3249                  */
3250                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3251                     == 0x6041) {
3252                         while(bhack[i].reg) {
3253                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3254                                     bhack[i].reg, bhack[i].val);
3255                                 i++;
3256                         }
3257                 }
3258         }
3259
3260         /* Set station address */
3261         bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3262         SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3263         SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3264         SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3265         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3266
3267         if (ifp->if_flags & IFF_BROADCAST) {
3268                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3269         } else {
3270                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3271         }
3272
3273         /* We don't need the FCS appended to the packet. */
3274         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3275
3276         /* We want short frames padded to 60 bytes. */
3277         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3278
3279         /*
3280          * Enable the reception of all error frames. This is is
3281          * a necessary evil due to the design of the XMAC. The
3282          * XMAC's receive FIFO is only 8K in size, however jumbo
3283          * frames can be up to 9000 bytes in length. When bad
3284          * frame filtering is enabled, the XMAC's RX FIFO operates
3285          * in 'store and forward' mode. For this to work, the
3286          * entire frame has to fit into the FIFO, but that means
3287          * that jumbo frames larger than 8192 bytes will be
3288          * truncated. Disabling all bad frame filtering causes
3289          * the RX FIFO to operate in streaming mode, in which
3290          * case the XMAC will start transfering frames out of the
3291          * RX FIFO as soon as the FIFO threshold is reached.
3292          */
3293         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3294                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3295                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3296                     XM_MODE_RX_INRANGELEN);
3297                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3298         } else
3299                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3300
3301         /*
3302          * Bump up the transmit threshold. This helps hold off transmit
3303          * underruns when we're blasting traffic from both ports at once.
3304          */
3305         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3306
3307         /* Set Rx filter */
3308         sk_rxfilter_genesis(sc_if);
3309
3310         /* Clear and enable interrupts */
3311         SK_XM_READ_2(sc_if, XM_ISR);
3312         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3313                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3314         else
3315                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3316
3317         /* Configure MAC arbiter */
3318         switch(sc_if->sk_xmac_rev) {
3319         case XM_XMAC_REV_B2:
3320                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3321                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3322                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3323                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3324                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3325                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3326                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3327                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3328                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3329                 break;
3330         case XM_XMAC_REV_C1:
3331                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3332                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3333                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3334                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3335                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3336                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3337                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3338                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3339                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3340                 break;
3341         default:
3342                 break;
3343         }
3344         sk_win_write_2(sc, SK_MACARB_CTL,
3345             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3346
3347         sc_if->sk_link = 1;
3348
3349         return;
3350 }
3351
3352 static void
3353 sk_init_yukon(sc_if)
3354         struct sk_if_softc      *sc_if;
3355 {
3356         u_int32_t               phy, v;
3357         u_int16_t               reg;
3358         struct sk_softc         *sc;
3359         struct ifnet            *ifp;
3360         u_int8_t                *eaddr;
3361         int                     i;
3362
3363         SK_IF_LOCK_ASSERT(sc_if);
3364
3365         sc = sc_if->sk_softc;
3366         ifp = sc_if->sk_ifp;
3367
3368         if (sc->sk_type == SK_YUKON_LITE &&
3369             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3370                 /*
3371                  * Workaround code for COMA mode, set PHY reset.
3372                  * Otherwise it will not correctly take chip out of
3373                  * powerdown (coma)
3374                  */
3375                 v = sk_win_read_4(sc, SK_GPIO);
3376                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3377                 sk_win_write_4(sc, SK_GPIO, v);
3378         }
3379
3380         /* GMAC and GPHY Reset */
3381         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3382         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3383         DELAY(1000);
3384
3385         if (sc->sk_type == SK_YUKON_LITE &&
3386             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3387                 /*
3388                  * Workaround code for COMA mode, clear PHY reset
3389                  */
3390                 v = sk_win_read_4(sc, SK_GPIO);
3391                 v |= SK_GPIO_DIR9;
3392                 v &= ~SK_GPIO_DAT9;
3393                 sk_win_write_4(sc, SK_GPIO, v);
3394         }
3395
3396         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3397                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3398
3399         if (sc->sk_coppertype)
3400                 phy |= SK_GPHY_COPPER;
3401         else
3402                 phy |= SK_GPHY_FIBER;
3403
3404         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3405         DELAY(1000);
3406         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3407         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3408                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3409
3410         /* unused read of the interrupt source register */
3411         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3412
3413         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3414
3415         /* MIB Counter Clear Mode set */
3416         reg |= YU_PAR_MIB_CLR;
3417         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3418
3419         /* MIB Counter Clear Mode clear */
3420         reg &= ~YU_PAR_MIB_CLR;
3421         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3422
3423         /* receive control reg */
3424         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3425
3426         /* transmit parameter register */
3427         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3428                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3429
3430         /* serial mode register */
3431         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3432         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3433                 reg |= YU_SMR_MFL_JUMBO;
3434         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3435
3436         /* Setup Yukon's station address */
3437         eaddr = IF_LLADDR(sc_if->sk_ifp);
3438         for (i = 0; i < 3; i++)
3439                 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3440                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3441         /* Set GMAC source address of flow control. */
3442         for (i = 0; i < 3; i++)
3443                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3444                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3445         /* Set GMAC virtual address. */
3446         for (i = 0; i < 3; i++)
3447                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3448                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3449
3450         /* Set Rx filter */
3451         sk_rxfilter_yukon(sc_if);
3452
3453         /* enable interrupt mask for counter overflows */
3454         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3455         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3456         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3457
3458         /* Configure RX MAC FIFO Flush Mask */
3459         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3460             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3461             YU_RXSTAT_JABBER;
3462         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3463
3464         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3465         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3466                 v = SK_TFCTL_OPERATION_ON;
3467         else
3468                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3469         /* Configure RX MAC FIFO */
3470         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3471         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3472
3473         /* Increase flush threshould to 64 bytes */
3474         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3475             SK_RFCTL_FIFO_THRESHOLD + 1);
3476
3477         /* Configure TX MAC FIFO */
3478         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3479         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3480 }
3481
3482 /*
3483  * Note that to properly initialize any part of the GEnesis chip,
3484  * you first have to take it out of reset mode.
3485  */
3486 static void
3487 sk_init(xsc)
3488         void                    *xsc;
3489 {
3490         struct sk_if_softc      *sc_if = xsc;
3491
3492         SK_IF_LOCK(sc_if);
3493         sk_init_locked(sc_if);
3494         SK_IF_UNLOCK(sc_if);
3495
3496         return;
3497 }
3498
3499 static void
3500 sk_init_locked(sc_if)
3501         struct sk_if_softc      *sc_if;
3502 {
3503         struct sk_softc         *sc;
3504         struct ifnet            *ifp;
3505         struct mii_data         *mii;
3506         u_int16_t               reg;
3507         u_int32_t               imr;
3508         int                     error;
3509
3510         SK_IF_LOCK_ASSERT(sc_if);
3511
3512         ifp = sc_if->sk_ifp;
3513         sc = sc_if->sk_softc;
3514         mii = device_get_softc(sc_if->sk_miibus);
3515
3516         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3517                 return;
3518
3519         /* Cancel pending I/O and free all RX/TX buffers. */
3520         sk_stop(sc_if);
3521
3522         if (sc->sk_type == SK_GENESIS) {
3523                 /* Configure LINK_SYNC LED */
3524                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3525                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3526                         SK_LINKLED_LINKSYNC_ON);
3527
3528                 /* Configure RX LED */
3529                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3530                         SK_RXLEDCTL_COUNTER_START);
3531
3532                 /* Configure TX LED */
3533                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3534                         SK_TXLEDCTL_COUNTER_START);
3535         }
3536
3537         /*
3538          * Configure descriptor poll timer
3539          *
3540          * SK-NET GENESIS data sheet says that possibility of losing Start
3541          * transmit command due to CPU/cache related interim storage problems
3542          * under certain conditions. The document recommends a polling
3543          * mechanism to send a Start transmit command to initiate transfer
3544          * of ready descriptors regulary. To cope with this issue sk(4) now
3545          * enables descriptor poll timer to initiate descriptor processing
3546          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3547          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3548          * command instead of waiting for next descriptor polling time.
3549          * The same rule may apply to Rx side too but it seems that is not
3550          * needed at the moment.
3551          * Since sk(4) uses descriptor polling as a last resort there is no
3552          * need to set smaller polling time than maximum allowable one.
3553          */
3554         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3555
3556         /* Configure I2C registers */
3557
3558         /* Configure XMAC(s) */
3559         switch (sc->sk_type) {
3560         case SK_GENESIS:
3561                 sk_init_xmac(sc_if);
3562                 break;
3563         case SK_YUKON:
3564         case SK_YUKON_LITE:
3565         case SK_YUKON_LP:
3566                 sk_init_yukon(sc_if);
3567                 break;
3568         }
3569         mii_mediachg(mii);
3570
3571         if (sc->sk_type == SK_GENESIS) {
3572                 /* Configure MAC FIFOs */
3573                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3574                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3575                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3576
3577                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3578                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3579                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3580         }
3581
3582         /* Configure transmit arbiter(s) */
3583         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3584             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3585
3586         /* Configure RAMbuffers */
3587         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3588         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3589         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3590         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3591         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3592         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3593
3594         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3595         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3596         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3597         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3598         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3599         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3600         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3601
3602         /* Configure BMUs */
3603         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3604         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3605                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3606                     SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3607                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3608                     SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3609         } else {
3610                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3611                     SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3612                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3613                     SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3614         }
3615
3616         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3617         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3618             SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3619         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3620             SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3621
3622         /* Init descriptors */
3623         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3624                 error = sk_init_jumbo_rx_ring(sc_if);
3625         else
3626                 error = sk_init_rx_ring(sc_if);
3627         if (error != 0) {
3628                 device_printf(sc_if->sk_if_dev,
3629                     "initialization failed: no memory for rx buffers\n");
3630                 sk_stop(sc_if);
3631                 return;
3632         }
3633         sk_init_tx_ring(sc_if);
3634
3635         /* Set interrupt moderation if changed via sysctl. */
3636         imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3637         if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3638                 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3639                     sc->sk_int_ticks));
3640                 if (bootverbose)
3641                         device_printf(sc_if->sk_if_dev,
3642                             "interrupt moderation is %d us.\n",
3643                             sc->sk_int_mod);
3644         }
3645
3646         /* Configure interrupt handling */
3647         CSR_READ_4(sc, SK_ISSR);
3648         if (sc_if->sk_port == SK_PORT_A)
3649                 sc->sk_intrmask |= SK_INTRS1;
3650         else
3651                 sc->sk_intrmask |= SK_INTRS2;
3652
3653         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3654
3655         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3656
3657         /* Start BMUs. */
3658         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3659
3660         switch(sc->sk_type) {
3661         case SK_GENESIS:
3662                 /* Enable XMACs TX and RX state machines */
3663                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3664                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3665                 break;
3666         case SK_YUKON:
3667         case SK_YUKON_LITE:
3668         case SK_YUKON_LP:
3669                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3670                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3671 #if 0
3672                 /* XXX disable 100Mbps and full duplex mode? */
3673                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3674 #endif
3675                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3676         }
3677
3678         /* Activate descriptor polling timer */
3679         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3680         /* start transfer of Tx descriptors */
3681         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3682
3683         ifp->if_drv_flags |= IFF_DRV_RUNNING;
3684         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3685
3686         switch (sc->sk_type) {
3687         case SK_YUKON:
3688         case SK_YUKON_LITE:
3689         case SK_YUKON_LP:
3690                 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3691                 break;
3692         }
3693
3694         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3695
3696         return;
3697 }
3698
3699 static void
3700 sk_stop(sc_if)
3701         struct sk_if_softc      *sc_if;
3702 {
3703         int                     i;
3704         struct sk_softc         *sc;
3705         struct sk_txdesc        *txd;
3706         struct sk_rxdesc        *rxd;
3707         struct sk_rxdesc        *jrxd;
3708         struct ifnet            *ifp;
3709         u_int32_t               val;
3710
3711         SK_IF_LOCK_ASSERT(sc_if);
3712         sc = sc_if->sk_softc;
3713         ifp = sc_if->sk_ifp;
3714
3715         callout_stop(&sc_if->sk_tick_ch);
3716         callout_stop(&sc_if->sk_watchdog_ch);
3717
3718         /* stop Tx descriptor polling timer */
3719         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3720         /* stop transfer of Tx descriptors */
3721         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3722         for (i = 0; i < SK_TIMEOUT; i++) {
3723                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3724                 if ((val & SK_TXBMU_TX_STOP) == 0)
3725                         break;
3726                 DELAY(1);
3727         }
3728         if (i == SK_TIMEOUT)
3729                 device_printf(sc_if->sk_if_dev,
3730                     "can not stop transfer of Tx descriptor\n");
3731         /* stop transfer of Rx descriptors */
3732         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3733         for (i = 0; i < SK_TIMEOUT; i++) {
3734                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3735                 if ((val & SK_RXBMU_RX_STOP) == 0)
3736                         break;
3737                 DELAY(1);
3738         }
3739         if (i == SK_TIMEOUT)
3740                 device_printf(sc_if->sk_if_dev,
3741                     "can not stop transfer of Rx descriptor\n");
3742
3743         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3744                 /* Put PHY back into reset. */
3745                 val = sk_win_read_4(sc, SK_GPIO);
3746                 if (sc_if->sk_port == SK_PORT_A) {
3747                         val |= SK_GPIO_DIR0;
3748                         val &= ~SK_GPIO_DAT0;
3749                 } else {
3750                         val |= SK_GPIO_DIR2;
3751                         val &= ~SK_GPIO_DAT2;
3752                 }
3753                 sk_win_write_4(sc, SK_GPIO, val);
3754         }
3755
3756         /* Turn off various components of this interface. */
3757         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3758         switch (sc->sk_type) {
3759         case SK_GENESIS:
3760                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3761                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3762                 break;
3763         case SK_YUKON:
3764         case SK_YUKON_LITE:
3765         case SK_YUKON_LP:
3766                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3767                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3768                 break;
3769         }
3770         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3771         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3772         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3773         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3774         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3775         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3776         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3777         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3778         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3779
3780         /* Disable interrupts */
3781         if (sc_if->sk_port == SK_PORT_A)
3782                 sc->sk_intrmask &= ~SK_INTRS1;
3783         else
3784                 sc->sk_intrmask &= ~SK_INTRS2;
3785         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3786
3787         SK_XM_READ_2(sc_if, XM_ISR);
3788         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3789
3790         /* Free RX and TX mbufs still in the queues. */
3791         for (i = 0; i < SK_RX_RING_CNT; i++) {
3792                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3793                 if (rxd->rx_m != NULL) {
3794                         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3795                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3796                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3797                             rxd->rx_dmamap);
3798                         m_freem(rxd->rx_m);
3799                         rxd->rx_m = NULL;
3800                 }
3801         }
3802         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3803                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3804                 if (jrxd->rx_m != NULL) {
3805                         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3806                             jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3807                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3808                             jrxd->rx_dmamap);
3809                         m_freem(jrxd->rx_m);
3810                         jrxd->rx_m = NULL;
3811                 }
3812         }
3813         for (i = 0; i < SK_TX_RING_CNT; i++) {
3814                 txd = &sc_if->sk_cdata.sk_txdesc[i];
3815                 if (txd->tx_m != NULL) {
3816                         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3817                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3818                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3819                             txd->tx_dmamap);
3820                         m_freem(txd->tx_m);
3821                         txd->tx_m = NULL;
3822                 }
3823         }
3824
3825         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3826
3827         return;
3828 }
3829
3830 static int
3831 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3832 {
3833         int error, value;
3834
3835         if (!arg1)
3836                 return (EINVAL);
3837         value = *(int *)arg1;
3838         error = sysctl_handle_int(oidp, &value, 0, req);
3839         if (error || !req->newptr)
3840                 return (error);
3841         if (value < low || value > high)
3842                 return (EINVAL);
3843         *(int *)arg1 = value;
3844         return (0);
3845 }
3846
3847 static int
3848 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3849 {
3850         return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3851 }