2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #ifdef HAVE_KERNEL_OPTION_HEADERS
37 #include "opt_device_polling.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/endian.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
48 #include <sys/module.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
56 #include <net/if_arp.h>
57 #include <net/ethernet.h>
58 #include <net/if_dl.h>
59 #include <net/if_media.h>
60 #include <net/if_types.h>
61 #include <net/if_vlan_var.h>
63 #include <machine/bus.h>
64 #include <machine/resource.h>
66 #include <dev/mii/mii.h>
67 #include <dev/mii/mii_bitbang.h>
68 #include <dev/mii/miivar.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
73 #include <dev/ste/if_stereg.h>
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
78 MODULE_DEPEND(ste, pci, 1, 1, 1);
79 MODULE_DEPEND(ste, ether, 1, 1, 1);
80 MODULE_DEPEND(ste, miibus, 1, 1, 1);
82 /* Define to show Tx error status. */
83 #define STE_SHOW_TXERRORS
86 * Various supported device vendors/types and their names.
88 static const struct ste_type const ste_devs[] = {
89 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
90 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
91 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
95 static int ste_attach(device_t);
96 static int ste_detach(device_t);
97 static int ste_probe(device_t);
98 static int ste_resume(device_t);
99 static int ste_shutdown(device_t);
100 static int ste_suspend(device_t);
102 static int ste_dma_alloc(struct ste_softc *);
103 static void ste_dma_free(struct ste_softc *);
104 static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int);
105 static int ste_eeprom_wait(struct ste_softc *);
106 static int ste_encap(struct ste_softc *, struct mbuf **,
108 static int ste_ifmedia_upd(struct ifnet *);
109 static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
110 static void ste_init(void *);
111 static void ste_init_locked(struct ste_softc *);
112 static int ste_init_rx_list(struct ste_softc *);
113 static void ste_init_tx_list(struct ste_softc *);
114 static void ste_intr(void *);
115 static int ste_ioctl(struct ifnet *, u_long, caddr_t);
116 static uint32_t ste_mii_bitbang_read(device_t);
117 static void ste_mii_bitbang_write(device_t, uint32_t);
118 static int ste_miibus_readreg(device_t, int, int);
119 static void ste_miibus_statchg(device_t);
120 static int ste_miibus_writereg(device_t, int, int, int);
121 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *);
122 static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int);
123 static void ste_reset(struct ste_softc *);
124 static void ste_restart_tx(struct ste_softc *);
125 static int ste_rxeof(struct ste_softc *, int);
126 static void ste_rxfilter(struct ste_softc *);
127 static void ste_setwol(struct ste_softc *);
128 static void ste_start(struct ifnet *);
129 static void ste_start_locked(struct ifnet *);
130 static void ste_stats_clear(struct ste_softc *);
131 static void ste_stats_update(struct ste_softc *);
132 static void ste_stop(struct ste_softc *);
133 static void ste_sysctl_node(struct ste_softc *);
134 static void ste_tick(void *);
135 static void ste_txeoc(struct ste_softc *);
136 static void ste_txeof(struct ste_softc *);
137 static void ste_wait(struct ste_softc *);
138 static void ste_watchdog(struct ste_softc *);
143 static const struct mii_bitbang_ops ste_mii_bitbang_ops = {
144 ste_mii_bitbang_read,
145 ste_mii_bitbang_write,
147 STE_PHYCTL_MDATA, /* MII_BIT_MDO */
148 STE_PHYCTL_MDATA, /* MII_BIT_MDI */
149 STE_PHYCTL_MCLK, /* MII_BIT_MDC */
150 STE_PHYCTL_MDIR, /* MII_BIT_DIR_HOST_PHY */
151 0, /* MII_BIT_DIR_PHY_HOST */
155 static device_method_t ste_methods[] = {
156 /* Device interface */
157 DEVMETHOD(device_probe, ste_probe),
158 DEVMETHOD(device_attach, ste_attach),
159 DEVMETHOD(device_detach, ste_detach),
160 DEVMETHOD(device_shutdown, ste_shutdown),
161 DEVMETHOD(device_suspend, ste_suspend),
162 DEVMETHOD(device_resume, ste_resume),
165 DEVMETHOD(bus_print_child, bus_generic_print_child),
166 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
169 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
170 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
171 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
176 static driver_t ste_driver = {
179 sizeof(struct ste_softc)
182 static devclass_t ste_devclass;
184 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
185 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
187 #define STE_SETBIT4(sc, reg, x) \
188 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
190 #define STE_CLRBIT4(sc, reg, x) \
191 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
193 #define STE_SETBIT2(sc, reg, x) \
194 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
196 #define STE_CLRBIT2(sc, reg, x) \
197 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
199 #define STE_SETBIT1(sc, reg, x) \
200 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
202 #define STE_CLRBIT1(sc, reg, x) \
203 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
206 * Read the MII serial port for the MII bit-bang module.
209 ste_mii_bitbang_read(device_t dev)
211 struct ste_softc *sc;
214 sc = device_get_softc(dev);
216 val = CSR_READ_1(sc, STE_PHYCTL);
217 CSR_BARRIER(sc, STE_PHYCTL, 1,
218 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
224 * Write the MII serial port for the MII bit-bang module.
227 ste_mii_bitbang_write(device_t dev, uint32_t val)
229 struct ste_softc *sc;
231 sc = device_get_softc(dev);
233 CSR_WRITE_1(sc, STE_PHYCTL, val);
234 CSR_BARRIER(sc, STE_PHYCTL, 1,
235 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
239 ste_miibus_readreg(device_t dev, int phy, int reg)
242 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg));
246 ste_miibus_writereg(device_t dev, int phy, int reg, int data)
249 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data);
255 ste_miibus_statchg(device_t dev)
257 struct ste_softc *sc;
258 struct mii_data *mii;
262 sc = device_get_softc(dev);
264 mii = device_get_softc(sc->ste_miibus);
266 if (mii == NULL || ifp == NULL ||
267 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
270 sc->ste_flags &= ~STE_FLAG_LINK;
271 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
272 (IFM_ACTIVE | IFM_AVALID)) {
273 switch (IFM_SUBTYPE(mii->mii_media_active)) {
278 sc->ste_flags |= STE_FLAG_LINK;
284 /* Program MACs with resolved speed/duplex/flow-control. */
285 if ((sc->ste_flags & STE_FLAG_LINK) != 0) {
286 cfg = CSR_READ_2(sc, STE_MACCTL0);
287 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX);
288 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
290 * ST201 data sheet says driver should enable receiving
291 * MAC control frames bit of receive mode register to
292 * receive flow-control frames but the register has no
293 * such bits. In addition the controller has no ability
294 * to send pause frames so it should be handled in
295 * driver. Implementing pause timer handling in driver
296 * layer is not trivial, so don't enable flow-control
299 cfg |= STE_MACCTL0_FULLDUPLEX;
301 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
306 ste_ifmedia_upd(struct ifnet *ifp)
308 struct ste_softc *sc;
309 struct mii_data *mii;
310 struct mii_softc *miisc;
315 mii = device_get_softc(sc->ste_miibus);
316 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
318 error = mii_mediachg(mii);
325 ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
327 struct ste_softc *sc;
328 struct mii_data *mii;
331 mii = device_get_softc(sc->ste_miibus);
334 if ((ifp->if_flags & IFF_UP) == 0) {
339 ifmr->ifm_active = mii->mii_media_active;
340 ifmr->ifm_status = mii->mii_media_status;
345 ste_wait(struct ste_softc *sc)
349 for (i = 0; i < STE_TIMEOUT; i++) {
350 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
355 if (i == STE_TIMEOUT)
356 device_printf(sc->ste_dev, "command never completed!\n");
360 * The EEPROM is slow: give it time to come ready after issuing
364 ste_eeprom_wait(struct ste_softc *sc)
370 for (i = 0; i < 100; i++) {
371 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
378 device_printf(sc->ste_dev, "eeprom failed to come ready\n");
386 * Read a sequence of words from the EEPROM. Note that ethernet address
387 * data is stored in the EEPROM in network byte order.
390 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt)
394 if (ste_eeprom_wait(sc))
397 for (i = 0; i < cnt; i++) {
398 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
399 err = ste_eeprom_wait(sc);
402 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA));
406 return (err ? 1 : 0);
410 ste_rxfilter(struct ste_softc *sc)
413 struct ifmultiaddr *ifma;
414 uint32_t hashes[2] = { 0, 0 };
421 rxcfg = CSR_READ_1(sc, STE_RX_MODE);
422 rxcfg |= STE_RXMODE_UNICAST;
423 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH |
424 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC);
425 if (ifp->if_flags & IFF_BROADCAST)
426 rxcfg |= STE_RXMODE_BROADCAST;
427 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
428 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
429 rxcfg |= STE_RXMODE_ALLMULTI;
430 if ((ifp->if_flags & IFF_PROMISC) != 0)
431 rxcfg |= STE_RXMODE_PROMISC;
435 rxcfg |= STE_RXMODE_MULTIHASH;
436 /* Now program new ones. */
438 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
439 if (ifma->ifma_addr->sa_family != AF_LINK)
441 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
442 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
444 hashes[0] |= (1 << h);
446 hashes[1] |= (1 << (h - 32));
448 if_maddr_runlock(ifp);
451 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
452 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
453 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
454 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
455 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
456 CSR_READ_1(sc, STE_RX_MODE);
459 #ifdef DEVICE_POLLING
460 static poll_handler_t ste_poll, ste_poll_locked;
463 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
465 struct ste_softc *sc = ifp->if_softc;
469 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
470 rx_npkts = ste_poll_locked(ifp, cmd, count);
476 ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
478 struct ste_softc *sc = ifp->if_softc;
483 rx_npkts = ste_rxeof(sc, count);
486 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
487 ste_start_locked(ifp);
489 if (cmd == POLL_AND_CHECK_STATUS) {
492 status = CSR_READ_2(sc, STE_ISR_ACK);
494 if (status & STE_ISR_STATS_OFLOW)
495 ste_stats_update(sc);
497 if (status & STE_ISR_HOSTERR) {
498 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
504 #endif /* DEVICE_POLLING */
509 struct ste_softc *sc;
511 uint16_t intrs, status;
517 #ifdef DEVICE_POLLING
518 if (ifp->if_capenable & IFCAP_POLLING) {
523 /* Reading STE_ISR_ACK clears STE_IMR register. */
524 status = CSR_READ_2(sc, STE_ISR_ACK);
525 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
531 if (status == 0xFFFF || (status & intrs) == 0)
534 if (sc->ste_int_rx_act > 0) {
535 status &= ~STE_ISR_RX_DMADONE;
536 intrs &= ~STE_IMR_RX_DMADONE;
539 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) {
542 * The controller has no ability to Rx interrupt
543 * moderation feature. Receiving 64 bytes frames
544 * from wire generates too many interrupts which in
545 * turn make system useless to process other useful
546 * things. Fortunately ST201 supports single shot
547 * timer so use the timer to implement Rx interrupt
548 * moderation in driver. This adds more register
549 * access but it greatly reduces number of Rx
550 * interrupts under high network load.
552 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
553 (sc->ste_int_rx_mod != 0)) {
554 if ((status & STE_ISR_RX_DMADONE) != 0) {
555 CSR_WRITE_2(sc, STE_COUNTDOWN,
556 STE_TIMER_USECS(sc->ste_int_rx_mod));
557 intrs &= ~STE_IMR_RX_DMADONE;
558 sc->ste_int_rx_act = 1;
560 intrs |= STE_IMR_RX_DMADONE;
561 sc->ste_int_rx_act = 0;
565 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
566 if ((status & STE_ISR_TX_DMADONE) != 0)
568 if ((status & STE_ISR_TX_DONE) != 0)
570 if ((status & STE_ISR_STATS_OFLOW) != 0)
571 ste_stats_update(sc);
572 if ((status & STE_ISR_HOSTERR) != 0) {
573 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
578 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
579 ste_start_locked(ifp);
581 /* Re-enable interrupts */
582 CSR_WRITE_2(sc, STE_IMR, intrs);
588 * A frame has been uploaded: pass the resulting mbuf chain up to
589 * the higher level protocols.
592 ste_rxeof(struct ste_softc *sc, int count)
596 struct ste_chain_onefrag *cur_rx;
598 int total_len, rx_npkts;
602 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
603 sc->ste_cdata.ste_rx_list_map,
604 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
606 cur_rx = sc->ste_cdata.ste_rx_head;
607 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++,
608 cur_rx = cur_rx->ste_next) {
609 rxstat = le32toh(cur_rx->ste_ptr->ste_status);
610 if ((rxstat & STE_RXSTAT_DMADONE) == 0)
612 #ifdef DEVICE_POLLING
613 if (ifp->if_capenable & IFCAP_POLLING) {
619 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
622 * If an error occurs, update stats, clear the
623 * status word and leave the mbuf cluster in place:
624 * it should simply get re-used next time this descriptor
625 * comes up in the ring.
627 if (rxstat & STE_RXSTAT_FRAME_ERR) {
629 cur_rx->ste_ptr->ste_status = 0;
633 /* No errors; receive the packet. */
634 m = cur_rx->ste_mbuf;
635 total_len = STE_RX_BYTES(rxstat);
638 * Try to conjure up a new mbuf cluster. If that
639 * fails, it means we have an out of memory condition and
640 * should leave the buffer in place and continue. This will
641 * result in a lost packet, but there's little else we
642 * can do in this situation.
644 if (ste_newbuf(sc, cur_rx) != 0) {
646 cur_rx->ste_ptr->ste_status = 0;
650 m->m_pkthdr.rcvif = ifp;
651 m->m_pkthdr.len = m->m_len = total_len;
655 (*ifp->if_input)(ifp, m);
660 sc->ste_cdata.ste_rx_head = cur_rx;
661 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
662 sc->ste_cdata.ste_rx_list_map,
663 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
670 ste_txeoc(struct ste_softc *sc)
680 * STE_TX_STATUS register implements a queue of up to 31
681 * transmit status byte. Writing an arbitrary value to the
682 * register will advance the queue to the next transmit
683 * status byte. This means if driver does not read
684 * STE_TX_STATUS register after completing sending more
685 * than 31 frames the controller would be stalled so driver
686 * should re-wake the Tx MAC. This is the most severe
687 * limitation of ST201 based controller.
690 txstat = CSR_READ_2(sc, STE_TX_STATUS);
691 if ((txstat & STE_TXSTATUS_TXDONE) == 0)
693 if ((txstat & (STE_TXSTATUS_UNDERRUN |
694 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR |
695 STE_TXSTATUS_STATSOFLOW)) != 0) {
697 #ifdef STE_SHOW_TXERRORS
698 device_printf(sc->ste_dev, "TX error : 0x%b\n",
699 txstat & 0xFF, STE_ERR_BITS);
701 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 &&
702 sc->ste_tx_thresh < STE_PACKET_SIZE) {
703 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
704 if (sc->ste_tx_thresh > STE_PACKET_SIZE)
705 sc->ste_tx_thresh = STE_PACKET_SIZE;
706 device_printf(sc->ste_dev,
707 "TX underrun, increasing TX"
708 " start threshold to %d bytes\n",
710 /* Make sure to disable active DMA cycles. */
711 STE_SETBIT4(sc, STE_DMACTL,
712 STE_DMACTL_TXDMA_STALL);
714 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
722 * Advance to next status and ACK TxComplete
723 * interrupt. ST201 data sheet was wrong here, to
724 * get next Tx status, we have to write both
725 * STE_TX_STATUS and STE_TX_FRAMEID register.
726 * Otherwise controller returns the same status
727 * as well as not acknowledge Tx completion
730 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
737 struct ste_softc *sc;
738 struct mii_data *mii;
740 sc = (struct ste_softc *)arg;
744 mii = device_get_softc(sc->ste_miibus);
747 * ukphy(4) does not seem to generate CB that reports
748 * resolved link state so if we know we lost a link,
749 * explicitly check the link state.
751 if ((sc->ste_flags & STE_FLAG_LINK) == 0)
752 ste_miibus_statchg(sc->ste_dev);
754 * Because we are not generating Tx completion
755 * interrupt for every frame, reclaim transmitted
760 ste_stats_update(sc);
762 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
766 ste_txeof(struct ste_softc *sc)
769 struct ste_chain *cur_tx;
776 idx = sc->ste_cdata.ste_tx_cons;
777 if (idx == sc->ste_cdata.ste_tx_prod)
780 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
781 sc->ste_cdata.ste_tx_list_map,
782 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
784 while (idx != sc->ste_cdata.ste_tx_prod) {
785 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
786 txstat = le32toh(cur_tx->ste_ptr->ste_ctl);
787 if ((txstat & STE_TXCTL_DMADONE) == 0)
789 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map,
790 BUS_DMASYNC_POSTWRITE);
791 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map);
792 KASSERT(cur_tx->ste_mbuf != NULL,
793 ("%s: freeing NULL mbuf!\n", __func__));
794 m_freem(cur_tx->ste_mbuf);
795 cur_tx->ste_mbuf = NULL;
796 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
798 sc->ste_cdata.ste_tx_cnt--;
799 STE_INC(idx, STE_TX_LIST_CNT);
802 sc->ste_cdata.ste_tx_cons = idx;
803 if (sc->ste_cdata.ste_tx_cnt == 0)
808 ste_stats_clear(struct ste_softc *sc)
814 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO);
815 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI);
816 CSR_READ_2(sc, STE_STAT_RX_FRAMES);
817 CSR_READ_1(sc, STE_STAT_RX_BCAST);
818 CSR_READ_1(sc, STE_STAT_RX_MCAST);
819 CSR_READ_1(sc, STE_STAT_RX_LOST);
821 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO);
822 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI);
823 CSR_READ_2(sc, STE_STAT_TX_FRAMES);
824 CSR_READ_1(sc, STE_STAT_TX_BCAST);
825 CSR_READ_1(sc, STE_STAT_TX_MCAST);
826 CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
827 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
828 CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
829 CSR_READ_1(sc, STE_STAT_LATE_COLLS);
830 CSR_READ_1(sc, STE_STAT_TX_DEFER);
831 CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
832 CSR_READ_1(sc, STE_STAT_TX_ABORT);
836 ste_stats_update(struct ste_softc *sc)
839 struct ste_hw_stats *stats;
845 stats = &sc->ste_stats;
847 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) |
848 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16;
850 stats->rx_bytes += val;
851 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES);
852 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST);
853 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST);
854 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST);
856 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) |
857 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16;
859 stats->tx_bytes += val;
860 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES);
861 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST);
862 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST);
863 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR);
864 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS);
865 stats->tx_single_colls += val;
866 ifp->if_collisions += val;
867 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS);
868 stats->tx_multi_colls += val;
869 ifp->if_collisions += val;
870 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS);
871 stats->tx_late_colls += val;
872 ifp->if_collisions += val;
873 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER);
874 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER);
875 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT);
879 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
880 * IDs against our list and return a device name if we find a match.
883 ste_probe(device_t dev)
885 const struct ste_type *t;
889 while (t->ste_name != NULL) {
890 if ((pci_get_vendor(dev) == t->ste_vid) &&
891 (pci_get_device(dev) == t->ste_did)) {
892 device_set_desc(dev, t->ste_name);
893 return (BUS_PROBE_DEFAULT);
902 * Attach the interface. Allocate softc structures, do ifmedia
903 * setup and ethernet/BPF attach.
906 ste_attach(device_t dev)
908 struct ste_softc *sc;
910 uint16_t eaddr[ETHER_ADDR_LEN / 2];
911 int error = 0, phy, pmc, prefer_iomap, rid;
913 sc = device_get_softc(dev);
917 * Only use one PHY since this chip reports multiple
918 * Note on the DFE-550 the PHY is at 1 on the DFE-580
919 * it is at 0 & 1. It is rev 0x12.
921 if (pci_get_vendor(dev) == DL_VENDORID &&
922 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
923 pci_get_revid(dev) == 0x12 )
924 sc->ste_flags |= STE_FLAG_ONE_PHY;
926 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
929 * Map control/status registers.
931 pci_enable_busmaster(dev);
934 * Prefer memory space register mapping over IO space but use
935 * IO space for a device that is known to have issues on memory
939 if (pci_get_device(dev) == ST_DEVICEID_ST201_1)
942 resource_int_value(device_get_name(sc->ste_dev),
943 device_get_unit(sc->ste_dev), "prefer_iomap",
945 if (prefer_iomap == 0) {
946 sc->ste_res_id = PCIR_BAR(1);
947 sc->ste_res_type = SYS_RES_MEMORY;
948 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
949 &sc->ste_res_id, RF_ACTIVE);
951 if (prefer_iomap || sc->ste_res == NULL) {
952 sc->ste_res_id = PCIR_BAR(0);
953 sc->ste_res_type = SYS_RES_IOPORT;
954 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type,
955 &sc->ste_res_id, RF_ACTIVE);
957 if (sc->ste_res == NULL) {
958 device_printf(dev, "couldn't map ports/memory\n");
963 /* Allocate interrupt */
965 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
966 RF_SHAREABLE | RF_ACTIVE);
968 if (sc->ste_irq == NULL) {
969 device_printf(dev, "couldn't map interrupt\n");
974 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0);
976 /* Reset the adapter. */
980 * Get station address from the EEPROM.
982 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) {
983 device_printf(dev, "failed to read station address\n");
989 if ((error = ste_dma_alloc(sc)) != 0)
992 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
994 device_printf(dev, "can not if_alloc()\n");
1001 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0)
1003 error = mii_attach(dev, &sc->ste_miibus, ifp, ste_ifmedia_upd,
1004 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1006 device_printf(dev, "attaching PHYs failed\n");
1011 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1012 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1013 ifp->if_ioctl = ste_ioctl;
1014 ifp->if_start = ste_start;
1015 ifp->if_init = ste_init;
1016 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1017 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1018 IFQ_SET_READY(&ifp->if_snd);
1020 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1023 * Call MI attach routine.
1025 ether_ifattach(ifp, (uint8_t *)eaddr);
1028 * Tell the upper layer(s) we support long frames.
1030 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1031 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1032 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
1033 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1034 ifp->if_capenable = ifp->if_capabilities;
1035 #ifdef DEVICE_POLLING
1036 ifp->if_capabilities |= IFCAP_POLLING;
1039 /* Hook interrupt last to avoid having to lock softc */
1040 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1041 NULL, ste_intr, sc, &sc->ste_intrhand);
1044 device_printf(dev, "couldn't set up irq\n");
1045 ether_ifdetach(ifp);
1057 * Shutdown hardware and free up resources. This can be called any
1058 * time after the mutex has been initialized. It is called in both
1059 * the error case in attach and the normal detach case so it needs
1060 * to be careful about only freeing resources that have actually been
1064 ste_detach(device_t dev)
1066 struct ste_softc *sc;
1069 sc = device_get_softc(dev);
1070 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1073 #ifdef DEVICE_POLLING
1074 if (ifp->if_capenable & IFCAP_POLLING)
1075 ether_poll_deregister(ifp);
1078 /* These should only be active if attach succeeded */
1079 if (device_is_attached(dev)) {
1080 ether_ifdetach(ifp);
1084 callout_drain(&sc->ste_callout);
1087 device_delete_child(dev, sc->ste_miibus);
1088 bus_generic_detach(dev);
1090 if (sc->ste_intrhand)
1091 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1093 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1095 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id,
1102 mtx_destroy(&sc->ste_mtx);
1107 struct ste_dmamap_arg {
1108 bus_addr_t ste_busaddr;
1112 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1114 struct ste_dmamap_arg *ctx;
1119 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1121 ctx = (struct ste_dmamap_arg *)arg;
1122 ctx->ste_busaddr = segs[0].ds_addr;
1126 ste_dma_alloc(struct ste_softc *sc)
1128 struct ste_chain *txc;
1129 struct ste_chain_onefrag *rxc;
1130 struct ste_dmamap_arg ctx;
1133 /* Create parent DMA tag. */
1134 error = bus_dma_tag_create(
1135 bus_get_dma_tag(sc->ste_dev), /* parent */
1136 1, 0, /* alignment, boundary */
1137 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1138 BUS_SPACE_MAXADDR, /* highaddr */
1139 NULL, NULL, /* filter, filterarg */
1140 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1142 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1144 NULL, NULL, /* lockfunc, lockarg */
1145 &sc->ste_cdata.ste_parent_tag);
1147 device_printf(sc->ste_dev,
1148 "could not create parent DMA tag.\n");
1152 /* Create DMA tag for Tx descriptor list. */
1153 error = bus_dma_tag_create(
1154 sc->ste_cdata.ste_parent_tag, /* parent */
1155 STE_DESC_ALIGN, 0, /* alignment, boundary */
1156 BUS_SPACE_MAXADDR, /* lowaddr */
1157 BUS_SPACE_MAXADDR, /* highaddr */
1158 NULL, NULL, /* filter, filterarg */
1159 STE_TX_LIST_SZ, /* maxsize */
1161 STE_TX_LIST_SZ, /* maxsegsize */
1163 NULL, NULL, /* lockfunc, lockarg */
1164 &sc->ste_cdata.ste_tx_list_tag);
1166 device_printf(sc->ste_dev,
1167 "could not create Tx list DMA tag.\n");
1171 /* Create DMA tag for Rx descriptor list. */
1172 error = bus_dma_tag_create(
1173 sc->ste_cdata.ste_parent_tag, /* parent */
1174 STE_DESC_ALIGN, 0, /* alignment, boundary */
1175 BUS_SPACE_MAXADDR, /* lowaddr */
1176 BUS_SPACE_MAXADDR, /* highaddr */
1177 NULL, NULL, /* filter, filterarg */
1178 STE_RX_LIST_SZ, /* maxsize */
1180 STE_RX_LIST_SZ, /* maxsegsize */
1182 NULL, NULL, /* lockfunc, lockarg */
1183 &sc->ste_cdata.ste_rx_list_tag);
1185 device_printf(sc->ste_dev,
1186 "could not create Rx list DMA tag.\n");
1190 /* Create DMA tag for Tx buffers. */
1191 error = bus_dma_tag_create(
1192 sc->ste_cdata.ste_parent_tag, /* parent */
1193 1, 0, /* alignment, boundary */
1194 BUS_SPACE_MAXADDR, /* lowaddr */
1195 BUS_SPACE_MAXADDR, /* highaddr */
1196 NULL, NULL, /* filter, filterarg */
1197 MCLBYTES * STE_MAXFRAGS, /* maxsize */
1198 STE_MAXFRAGS, /* nsegments */
1199 MCLBYTES, /* maxsegsize */
1201 NULL, NULL, /* lockfunc, lockarg */
1202 &sc->ste_cdata.ste_tx_tag);
1204 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n");
1208 /* Create DMA tag for Rx buffers. */
1209 error = bus_dma_tag_create(
1210 sc->ste_cdata.ste_parent_tag, /* parent */
1211 1, 0, /* alignment, boundary */
1212 BUS_SPACE_MAXADDR, /* lowaddr */
1213 BUS_SPACE_MAXADDR, /* highaddr */
1214 NULL, NULL, /* filter, filterarg */
1215 MCLBYTES, /* maxsize */
1217 MCLBYTES, /* maxsegsize */
1219 NULL, NULL, /* lockfunc, lockarg */
1220 &sc->ste_cdata.ste_rx_tag);
1222 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n");
1226 /* Allocate DMA'able memory and load the DMA map for Tx list. */
1227 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag,
1228 (void **)&sc->ste_ldata.ste_tx_list,
1229 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1230 &sc->ste_cdata.ste_tx_list_map);
1232 device_printf(sc->ste_dev,
1233 "could not allocate DMA'able memory for Tx list.\n");
1236 ctx.ste_busaddr = 0;
1237 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag,
1238 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list,
1239 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1240 if (error != 0 || ctx.ste_busaddr == 0) {
1241 device_printf(sc->ste_dev,
1242 "could not load DMA'able memory for Tx list.\n");
1245 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr;
1247 /* Allocate DMA'able memory and load the DMA map for Rx list. */
1248 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag,
1249 (void **)&sc->ste_ldata.ste_rx_list,
1250 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1251 &sc->ste_cdata.ste_rx_list_map);
1253 device_printf(sc->ste_dev,
1254 "could not allocate DMA'able memory for Rx list.\n");
1257 ctx.ste_busaddr = 0;
1258 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag,
1259 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list,
1260 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0);
1261 if (error != 0 || ctx.ste_busaddr == 0) {
1262 device_printf(sc->ste_dev,
1263 "could not load DMA'able memory for Rx list.\n");
1266 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr;
1268 /* Create DMA maps for Tx buffers. */
1269 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1270 txc = &sc->ste_cdata.ste_tx_chain[i];
1271 txc->ste_ptr = NULL;
1272 txc->ste_mbuf = NULL;
1273 txc->ste_next = NULL;
1275 txc->ste_map = NULL;
1276 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0,
1279 device_printf(sc->ste_dev,
1280 "could not create Tx dmamap.\n");
1284 /* Create DMA maps for Rx buffers. */
1285 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1286 &sc->ste_cdata.ste_rx_sparemap)) != 0) {
1287 device_printf(sc->ste_dev,
1288 "could not create spare Rx dmamap.\n");
1291 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1292 rxc = &sc->ste_cdata.ste_rx_chain[i];
1293 rxc->ste_ptr = NULL;
1294 rxc->ste_mbuf = NULL;
1295 rxc->ste_next = NULL;
1296 rxc->ste_map = NULL;
1297 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0,
1300 device_printf(sc->ste_dev,
1301 "could not create Rx dmamap.\n");
1311 ste_dma_free(struct ste_softc *sc)
1313 struct ste_chain *txc;
1314 struct ste_chain_onefrag *rxc;
1318 if (sc->ste_cdata.ste_tx_tag != NULL) {
1319 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1320 txc = &sc->ste_cdata.ste_tx_chain[i];
1321 if (txc->ste_map != NULL) {
1322 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag,
1324 txc->ste_map = NULL;
1327 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag);
1328 sc->ste_cdata.ste_tx_tag = NULL;
1331 if (sc->ste_cdata.ste_rx_tag != NULL) {
1332 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1333 rxc = &sc->ste_cdata.ste_rx_chain[i];
1334 if (rxc->ste_map != NULL) {
1335 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1337 rxc->ste_map = NULL;
1340 if (sc->ste_cdata.ste_rx_sparemap != NULL) {
1341 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag,
1342 sc->ste_cdata.ste_rx_sparemap);
1343 sc->ste_cdata.ste_rx_sparemap = NULL;
1345 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag);
1346 sc->ste_cdata.ste_rx_tag = NULL;
1348 /* Tx descriptor list. */
1349 if (sc->ste_cdata.ste_tx_list_tag != NULL) {
1350 if (sc->ste_cdata.ste_tx_list_map != NULL)
1351 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag,
1352 sc->ste_cdata.ste_tx_list_map);
1353 if (sc->ste_cdata.ste_tx_list_map != NULL &&
1354 sc->ste_ldata.ste_tx_list != NULL)
1355 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag,
1356 sc->ste_ldata.ste_tx_list,
1357 sc->ste_cdata.ste_tx_list_map);
1358 sc->ste_ldata.ste_tx_list = NULL;
1359 sc->ste_cdata.ste_tx_list_map = NULL;
1360 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag);
1361 sc->ste_cdata.ste_tx_list_tag = NULL;
1363 /* Rx descriptor list. */
1364 if (sc->ste_cdata.ste_rx_list_tag != NULL) {
1365 if (sc->ste_cdata.ste_rx_list_map != NULL)
1366 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag,
1367 sc->ste_cdata.ste_rx_list_map);
1368 if (sc->ste_cdata.ste_rx_list_map != NULL &&
1369 sc->ste_ldata.ste_rx_list != NULL)
1370 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag,
1371 sc->ste_ldata.ste_rx_list,
1372 sc->ste_cdata.ste_rx_list_map);
1373 sc->ste_ldata.ste_rx_list = NULL;
1374 sc->ste_cdata.ste_rx_list_map = NULL;
1375 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag);
1376 sc->ste_cdata.ste_rx_list_tag = NULL;
1378 if (sc->ste_cdata.ste_parent_tag != NULL) {
1379 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag);
1380 sc->ste_cdata.ste_parent_tag = NULL;
1385 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc)
1388 bus_dma_segment_t segs[1];
1392 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1395 m->m_len = m->m_pkthdr.len = MCLBYTES;
1396 m_adj(m, ETHER_ALIGN);
1398 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag,
1399 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) {
1403 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1405 if (rxc->ste_mbuf != NULL) {
1406 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1407 BUS_DMASYNC_POSTREAD);
1408 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map);
1411 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap;
1412 sc->ste_cdata.ste_rx_sparemap = map;
1413 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map,
1414 BUS_DMASYNC_PREREAD);
1416 rxc->ste_ptr->ste_status = 0;
1417 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr);
1418 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len |
1424 ste_init_rx_list(struct ste_softc *sc)
1426 struct ste_chain_data *cd;
1427 struct ste_list_data *ld;
1430 sc->ste_int_rx_act = 0;
1431 cd = &sc->ste_cdata;
1432 ld = &sc->ste_ldata;
1433 bzero(ld->ste_rx_list, STE_RX_LIST_SZ);
1434 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1435 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1436 error = ste_newbuf(sc, &cd->ste_rx_chain[i]);
1439 if (i == (STE_RX_LIST_CNT - 1)) {
1440 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0];
1441 ld->ste_rx_list[i].ste_next =
1442 htole32(ld->ste_rx_list_paddr +
1443 (sizeof(struct ste_desc_onefrag) * 0));
1445 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1];
1446 ld->ste_rx_list[i].ste_next =
1447 htole32(ld->ste_rx_list_paddr +
1448 (sizeof(struct ste_desc_onefrag) * (i + 1)));
1452 cd->ste_rx_head = &cd->ste_rx_chain[0];
1453 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag,
1454 sc->ste_cdata.ste_rx_list_map,
1455 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1461 ste_init_tx_list(struct ste_softc *sc)
1463 struct ste_chain_data *cd;
1464 struct ste_list_data *ld;
1467 cd = &sc->ste_cdata;
1468 ld = &sc->ste_ldata;
1469 bzero(ld->ste_tx_list, STE_TX_LIST_SZ);
1470 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1471 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1472 cd->ste_tx_chain[i].ste_mbuf = NULL;
1473 if (i == (STE_TX_LIST_CNT - 1)) {
1474 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0];
1475 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1476 ld->ste_tx_list_paddr +
1477 (sizeof(struct ste_desc) * 0)));
1479 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1];
1480 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO(
1481 ld->ste_tx_list_paddr +
1482 (sizeof(struct ste_desc) * (i + 1))));
1486 cd->ste_last_tx = NULL;
1487 cd->ste_tx_prod = 0;
1488 cd->ste_tx_cons = 0;
1491 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1492 sc->ste_cdata.ste_tx_list_map,
1493 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1499 struct ste_softc *sc;
1503 ste_init_locked(sc);
1508 ste_init_locked(struct ste_softc *sc)
1511 struct mii_data *mii;
1515 STE_LOCK_ASSERT(sc);
1517 mii = device_get_softc(sc->ste_miibus);
1519 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1523 /* Reset the chip to a known state. */
1526 /* Init our MAC address */
1527 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1528 CSR_WRITE_2(sc, STE_PAR0 + i,
1529 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) |
1530 IF_LLADDR(sc->ste_ifp)[i + 1] << 8));
1534 if (ste_init_rx_list(sc) != 0) {
1535 device_printf(sc->ste_dev,
1536 "initialization failed: no memory for RX buffers\n");
1541 /* Set RX polling interval */
1542 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1544 /* Init TX descriptors */
1545 ste_init_tx_list(sc);
1547 /* Clear and disable WOL. */
1548 val = CSR_READ_1(sc, STE_WAKE_EVENT);
1549 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
1550 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
1551 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
1553 /* Set the TX freethresh value */
1554 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1556 /* Set the TX start threshold for best performance. */
1557 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1559 /* Set the TX reclaim threshold. */
1560 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1562 /* Accept VLAN length packets */
1563 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1565 /* Set up the RX filter. */
1568 /* Load the address of the RX list. */
1569 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1571 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1572 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr));
1573 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1574 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1576 /* Set TX polling interval(defer until we TX first packet). */
1577 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1579 /* Load address of the TX list */
1580 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1582 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1583 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1584 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1586 /* Select 3.2us timer. */
1587 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED |
1588 STE_DMACTL_COUNTDOWN_MODE);
1590 /* Enable receiver and transmitter */
1591 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1592 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1593 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1594 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1596 /* Enable stats counters. */
1597 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1598 /* Clear stats counters. */
1599 ste_stats_clear(sc);
1601 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1602 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1603 #ifdef DEVICE_POLLING
1604 /* Disable interrupts if we are polling. */
1605 if (ifp->if_capenable & IFCAP_POLLING)
1606 CSR_WRITE_2(sc, STE_IMR, 0);
1609 /* Enable interrupts. */
1610 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1612 sc->ste_flags &= ~STE_FLAG_LINK;
1613 /* Switch to the current media. */
1616 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1617 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1619 callout_reset(&sc->ste_callout, hz, ste_tick, sc);
1623 ste_stop(struct ste_softc *sc)
1626 struct ste_chain_onefrag *cur_rx;
1627 struct ste_chain *cur_tx;
1631 STE_LOCK_ASSERT(sc);
1634 callout_stop(&sc->ste_callout);
1636 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1638 CSR_WRITE_2(sc, STE_IMR, 0);
1639 CSR_WRITE_2(sc, STE_COUNTDOWN, 0);
1640 /* Stop pending DMA. */
1641 val = CSR_READ_4(sc, STE_DMACTL);
1642 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL;
1643 CSR_WRITE_4(sc, STE_DMACTL, val);
1645 /* Disable auto-polling. */
1646 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0);
1647 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1648 /* Nullify DMA address to stop any further DMA. */
1649 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0);
1650 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1651 /* Stop TX/RX MAC. */
1652 val = CSR_READ_2(sc, STE_MACCTL1);
1653 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE |
1654 STE_MACCTL1_STATS_DISABLE;
1655 CSR_WRITE_2(sc, STE_MACCTL1, val);
1656 for (i = 0; i < STE_TIMEOUT; i++) {
1658 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE |
1659 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0)
1662 if (i == STE_TIMEOUT)
1663 device_printf(sc->ste_dev, "Stopping MAC timed out\n");
1664 /* Acknowledge any pending interrupts. */
1665 CSR_READ_2(sc, STE_ISR_ACK);
1666 ste_stats_update(sc);
1668 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1669 cur_rx = &sc->ste_cdata.ste_rx_chain[i];
1670 if (cur_rx->ste_mbuf != NULL) {
1671 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag,
1672 cur_rx->ste_map, BUS_DMASYNC_POSTREAD);
1673 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag,
1675 m_freem(cur_rx->ste_mbuf);
1676 cur_rx->ste_mbuf = NULL;
1680 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1681 cur_tx = &sc->ste_cdata.ste_tx_chain[i];
1682 if (cur_tx->ste_mbuf != NULL) {
1683 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag,
1684 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE);
1685 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag,
1687 m_freem(cur_tx->ste_mbuf);
1688 cur_tx->ste_mbuf = NULL;
1694 ste_reset(struct ste_softc *sc)
1699 ctl = CSR_READ_4(sc, STE_ASICCTL);
1700 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET |
1701 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET |
1702 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET |
1703 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET |
1704 STE_ASICCTL_EXTRESET_RESET;
1705 CSR_WRITE_4(sc, STE_ASICCTL, ctl);
1706 CSR_READ_4(sc, STE_ASICCTL);
1708 * Due to the need of accessing EEPROM controller can take
1709 * up to 1ms to complete the global reset.
1713 for (i = 0; i < STE_TIMEOUT; i++) {
1714 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1719 if (i == STE_TIMEOUT)
1720 device_printf(sc->ste_dev, "global reset never completed\n");
1724 ste_restart_tx(struct ste_softc *sc)
1729 for (i = 0; i < STE_TIMEOUT; i++) {
1730 mac = CSR_READ_2(sc, STE_MACCTL1);
1731 mac |= STE_MACCTL1_TX_ENABLE;
1732 CSR_WRITE_2(sc, STE_MACCTL1, mac);
1733 mac = CSR_READ_2(sc, STE_MACCTL1);
1734 if ((mac & STE_MACCTL1_TX_ENABLED) != 0)
1739 if (i == STE_TIMEOUT)
1740 device_printf(sc->ste_dev, "starting Tx failed");
1744 ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1746 struct ste_softc *sc;
1748 struct mii_data *mii;
1749 int error = 0, mask;
1752 ifr = (struct ifreq *)data;
1757 if ((ifp->if_flags & IFF_UP) != 0) {
1758 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1759 ((ifp->if_flags ^ sc->ste_if_flags) &
1760 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1763 ste_init_locked(sc);
1764 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1766 sc->ste_if_flags = ifp->if_flags;
1772 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1778 mii = device_get_softc(sc->ste_miibus);
1779 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1783 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1784 #ifdef DEVICE_POLLING
1785 if ((mask & IFCAP_POLLING) != 0 &&
1786 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
1787 ifp->if_capenable ^= IFCAP_POLLING;
1788 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
1789 error = ether_poll_register(ste_poll, ifp);
1794 /* Disable interrupts. */
1795 CSR_WRITE_2(sc, STE_IMR, 0);
1797 error = ether_poll_deregister(ifp);
1798 /* Enable interrupts. */
1799 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1802 #endif /* DEVICE_POLLING */
1803 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1804 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1805 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1809 error = ether_ioctl(ifp, command, data);
1817 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc)
1819 struct ste_frag *frag;
1821 struct ste_desc *desc;
1822 bus_dma_segment_t txsegs[STE_MAXFRAGS];
1823 int error, i, nsegs;
1825 STE_LOCK_ASSERT(sc);
1826 M_ASSERTPKTHDR((*m_head));
1828 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1829 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1830 if (error == EFBIG) {
1831 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS);
1838 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag,
1839 txc->ste_map, *m_head, txsegs, &nsegs, 0);
1845 } else if (error != 0)
1852 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map,
1853 BUS_DMASYNC_PREWRITE);
1855 desc = txc->ste_ptr;
1856 for (i = 0; i < nsegs; i++) {
1857 frag = &desc->ste_frags[i];
1858 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr));
1859 frag->ste_len = htole32(txsegs[i].ds_len);
1861 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST);
1863 * Because we use Tx polling we can't chain multiple
1864 * Tx descriptors here. Otherwise we race with controller.
1867 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0)
1868 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS |
1871 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS);
1872 txc->ste_mbuf = *m_head;
1873 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT);
1874 sc->ste_cdata.ste_tx_cnt++;
1880 ste_start(struct ifnet *ifp)
1882 struct ste_softc *sc;
1886 ste_start_locked(ifp);
1891 ste_start_locked(struct ifnet *ifp)
1893 struct ste_softc *sc;
1894 struct ste_chain *cur_tx;
1895 struct mbuf *m_head = NULL;
1899 STE_LOCK_ASSERT(sc);
1901 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1902 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0)
1905 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
1906 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) {
1908 * Controller may have cached copy of the last used
1909 * next ptr so we have to reserve one TFD to avoid
1912 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1915 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1918 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod];
1919 if (ste_encap(sc, &m_head, cur_tx) != 0) {
1922 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1925 if (sc->ste_cdata.ste_last_tx == NULL) {
1926 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1927 sc->ste_cdata.ste_tx_list_map,
1928 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1929 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1931 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1932 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr));
1933 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1934 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1937 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next =
1938 sc->ste_cdata.ste_last_tx->ste_phys;
1939 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag,
1940 sc->ste_cdata.ste_tx_list_map,
1941 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1943 sc->ste_cdata.ste_last_tx = cur_tx;
1947 * If there's a BPF listener, bounce a copy of this frame
1950 BPF_MTAP(ifp, m_head);
1954 sc->ste_timer = STE_TX_TIMEOUT;
1958 ste_watchdog(struct ste_softc *sc)
1963 STE_LOCK_ASSERT(sc);
1965 if (sc->ste_timer == 0 || --sc->ste_timer)
1969 if_printf(ifp, "watchdog timeout\n");
1974 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1975 ste_init_locked(sc);
1977 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1978 ste_start_locked(ifp);
1982 ste_shutdown(device_t dev)
1985 return (ste_suspend(dev));
1989 ste_suspend(device_t dev)
1991 struct ste_softc *sc;
1993 sc = device_get_softc(dev);
2004 ste_resume(device_t dev)
2006 struct ste_softc *sc;
2011 sc = device_get_softc(dev);
2013 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) {
2014 /* Disable PME and clear PME status. */
2015 pmstat = pci_read_config(sc->ste_dev,
2016 pmc + PCIR_POWER_STATUS, 2);
2017 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2018 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2019 pci_write_config(sc->ste_dev,
2020 pmc + PCIR_POWER_STATUS, pmstat, 2);
2024 if ((ifp->if_flags & IFF_UP) != 0) {
2025 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2026 ste_init_locked(sc);
2033 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2034 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2035 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
2036 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
2039 ste_sysctl_node(struct ste_softc *sc)
2041 struct sysctl_ctx_list *ctx;
2042 struct sysctl_oid_list *child, *parent;
2043 struct sysctl_oid *tree;
2044 struct ste_hw_stats *stats;
2046 stats = &sc->ste_stats;
2047 ctx = device_get_sysctl_ctx(sc->ste_dev);
2048 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev));
2050 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod",
2051 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation");
2052 /* Pull in device tunables. */
2053 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT;
2054 resource_int_value(device_get_name(sc->ste_dev),
2055 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod);
2057 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
2058 NULL, "STE statistics");
2059 parent = SYSCTL_CHILDREN(tree);
2061 /* Rx statistics. */
2062 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
2063 NULL, "Rx MAC statistics");
2064 child = SYSCTL_CHILDREN(tree);
2065 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2066 &stats->rx_bytes, "Good octets");
2067 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2068 &stats->rx_frames, "Good frames");
2069 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2070 &stats->rx_bcast_frames, "Good broadcast frames");
2071 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2072 &stats->rx_mcast_frames, "Good multicast frames");
2073 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames",
2074 &stats->rx_lost_frames, "Lost frames");
2076 /* Tx statistics. */
2077 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
2078 NULL, "Tx MAC statistics");
2079 child = SYSCTL_CHILDREN(tree);
2080 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
2081 &stats->tx_bytes, "Good octets");
2082 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
2083 &stats->tx_frames, "Good frames");
2084 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
2085 &stats->tx_bcast_frames, "Good broadcast frames");
2086 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
2087 &stats->tx_mcast_frames, "Good multicast frames");
2088 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs",
2089 &stats->tx_carrsense_errs, "Carrier sense errors");
2090 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
2091 &stats->tx_single_colls, "Single collisions");
2092 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
2093 &stats->tx_multi_colls, "Multiple collisions");
2094 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
2095 &stats->tx_late_colls, "Late collisions");
2096 STE_SYSCTL_STAT_ADD32(ctx, child, "defers",
2097 &stats->tx_frames_defered, "Frames with deferrals");
2098 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
2099 &stats->tx_excess_defers, "Frames with excessive derferrals");
2100 STE_SYSCTL_STAT_ADD32(ctx, child, "abort",
2101 &stats->tx_abort, "Aborted frames due to Excessive collisions");
2104 #undef STE_SYSCTL_STAT_ADD32
2105 #undef STE_SYSCTL_STAT_ADD64
2108 ste_setwol(struct ste_softc *sc)
2115 STE_LOCK_ASSERT(sc);
2117 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) {
2119 CSR_READ_1(sc, STE_WAKE_EVENT);
2120 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0);
2125 val = CSR_READ_1(sc, STE_WAKE_EVENT);
2126 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB |
2127 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB);
2128 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2129 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB;
2130 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
2132 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2);
2133 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2134 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2135 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2136 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);