1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 * Device driver for the Sundance Tech. TC9021 10/100/1000
34 * Ethernet controller.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #ifdef HAVE_KERNEL_OPTION_HEADERS
41 #include "opt_device_polling.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/endian.h>
48 #include <sys/malloc.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/taskqueue.h>
57 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <machine/bus.h>
65 #include <machine/resource.h>
69 #include <dev/mii/mii.h>
70 #include <dev/mii/mii_bitbang.h>
71 #include <dev/mii/miivar.h>
73 #include <dev/pci/pcireg.h>
74 #include <dev/pci/pcivar.h>
76 #include <dev/stge/if_stgereg.h>
78 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
80 MODULE_DEPEND(stge, pci, 1, 1, 1);
81 MODULE_DEPEND(stge, ether, 1, 1, 1);
82 MODULE_DEPEND(stge, miibus, 1, 1, 1);
84 /* "device miibus" required. See GENERIC if you get errors here. */
85 #include "miibus_if.h"
88 * Devices supported by this driver.
90 static const struct stge_product {
91 uint16_t stge_vendorid;
92 uint16_t stge_deviceid;
93 const char *stge_name;
94 } const stge_products[] = {
95 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
96 "Sundance ST-1023 Gigabit Ethernet" },
98 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
99 "Sundance ST-2021 Gigabit Ethernet" },
101 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
102 "Tamarack TC9021 Gigabit Ethernet" },
104 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
105 "Tamarack TC9021 Gigabit Ethernet" },
108 * The Sundance sample boards use the Sundance vendor ID,
109 * but the Tamarack product ID.
111 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
112 "Sundance TC9021 Gigabit Ethernet" },
114 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
115 "Sundance TC9021 Gigabit Ethernet" },
117 { VENDOR_DLINK, DEVICEID_DLINK_DL4000,
118 "D-Link DL-4000 Gigabit Ethernet" },
120 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
121 "Antares Gigabit Ethernet" }
124 static int stge_probe(device_t);
125 static int stge_attach(device_t);
126 static int stge_detach(device_t);
127 static int stge_shutdown(device_t);
128 static int stge_suspend(device_t);
129 static int stge_resume(device_t);
131 static int stge_encap(struct stge_softc *, struct mbuf **);
132 static void stge_start(struct ifnet *);
133 static void stge_start_locked(struct ifnet *);
134 static void stge_watchdog(struct stge_softc *);
135 static int stge_ioctl(struct ifnet *, u_long, caddr_t);
136 static void stge_init(void *);
137 static void stge_init_locked(struct stge_softc *);
138 static void stge_vlan_setup(struct stge_softc *);
139 static void stge_stop(struct stge_softc *);
140 static void stge_start_tx(struct stge_softc *);
141 static void stge_start_rx(struct stge_softc *);
142 static void stge_stop_tx(struct stge_softc *);
143 static void stge_stop_rx(struct stge_softc *);
145 static void stge_reset(struct stge_softc *, uint32_t);
146 static int stge_eeprom_wait(struct stge_softc *);
147 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
148 static void stge_tick(void *);
149 static void stge_stats_update(struct stge_softc *);
150 static void stge_set_filter(struct stge_softc *);
151 static void stge_set_multi(struct stge_softc *);
153 static void stge_link_task(void *, int);
154 static void stge_intr(void *);
155 static __inline int stge_tx_error(struct stge_softc *);
156 static void stge_txeof(struct stge_softc *);
157 static int stge_rxeof(struct stge_softc *);
158 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
159 static int stge_newbuf(struct stge_softc *, int);
160 #ifndef __NO_STRICT_ALIGNMENT
161 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
164 static int stge_miibus_readreg(device_t, int, int);
165 static int stge_miibus_writereg(device_t, int, int, int);
166 static void stge_miibus_statchg(device_t);
167 static int stge_mediachange(struct ifnet *);
168 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
170 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
171 static int stge_dma_alloc(struct stge_softc *);
172 static void stge_dma_free(struct stge_softc *);
173 static void stge_dma_wait(struct stge_softc *);
174 static void stge_init_tx_ring(struct stge_softc *);
175 static int stge_init_rx_ring(struct stge_softc *);
176 #ifdef DEVICE_POLLING
177 static int stge_poll(struct ifnet *, enum poll_cmd, int);
180 static void stge_setwol(struct stge_softc *);
181 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
182 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
183 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
188 static uint32_t stge_mii_bitbang_read(device_t);
189 static void stge_mii_bitbang_write(device_t, uint32_t);
191 static const struct mii_bitbang_ops stge_mii_bitbang_ops = {
192 stge_mii_bitbang_read,
193 stge_mii_bitbang_write,
195 PC_MgmtData, /* MII_BIT_MDO */
196 PC_MgmtData, /* MII_BIT_MDI */
197 PC_MgmtClk, /* MII_BIT_MDC */
198 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */
199 0, /* MII_BIT_DIR_PHY_HOST */
203 static device_method_t stge_methods[] = {
204 /* Device interface */
205 DEVMETHOD(device_probe, stge_probe),
206 DEVMETHOD(device_attach, stge_attach),
207 DEVMETHOD(device_detach, stge_detach),
208 DEVMETHOD(device_shutdown, stge_shutdown),
209 DEVMETHOD(device_suspend, stge_suspend),
210 DEVMETHOD(device_resume, stge_resume),
213 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
214 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
215 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
221 static driver_t stge_driver = {
224 sizeof(struct stge_softc)
227 static devclass_t stge_devclass;
229 DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0);
230 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0);
232 static struct resource_spec stge_res_spec_io[] = {
233 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE },
234 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
238 static struct resource_spec stge_res_spec_mem[] = {
239 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
240 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
245 * stge_mii_bitbang_read: [mii bit-bang interface function]
247 * Read the MII serial port for the MII bit-bang module.
250 stge_mii_bitbang_read(device_t dev)
252 struct stge_softc *sc;
255 sc = device_get_softc(dev);
257 val = CSR_READ_1(sc, STGE_PhyCtrl);
258 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
259 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
264 * stge_mii_bitbang_write: [mii big-bang interface function]
266 * Write the MII serial port for the MII bit-bang module.
269 stge_mii_bitbang_write(device_t dev, uint32_t val)
271 struct stge_softc *sc;
273 sc = device_get_softc(dev);
275 CSR_WRITE_1(sc, STGE_PhyCtrl, val);
276 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
277 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
281 * sc_miibus_readreg: [mii interface function]
283 * Read a PHY register on the MII of the TC9021.
286 stge_miibus_readreg(device_t dev, int phy, int reg)
288 struct stge_softc *sc;
291 sc = device_get_softc(dev);
293 if (reg == STGE_PhyCtrl) {
294 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
296 error = CSR_READ_1(sc, STGE_PhyCtrl);
302 val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg);
308 * stge_miibus_writereg: [mii interface function]
310 * Write a PHY register on the MII of the TC9021.
313 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
315 struct stge_softc *sc;
317 sc = device_get_softc(dev);
320 mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val);
326 * stge_miibus_statchg: [mii interface function]
328 * Callback from MII layer when media changes.
331 stge_miibus_statchg(device_t dev)
333 struct stge_softc *sc;
335 sc = device_get_softc(dev);
336 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task);
340 * stge_mediastatus: [ifmedia interface function]
342 * Get the current interface media status.
345 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
347 struct stge_softc *sc;
348 struct mii_data *mii;
351 mii = device_get_softc(sc->sc_miibus);
354 ifmr->ifm_status = mii->mii_media_status;
355 ifmr->ifm_active = mii->mii_media_active;
359 * stge_mediachange: [ifmedia interface function]
361 * Set hardware to newly-selected media.
364 stge_mediachange(struct ifnet *ifp)
366 struct stge_softc *sc;
367 struct mii_data *mii;
370 mii = device_get_softc(sc->sc_miibus);
377 stge_eeprom_wait(struct stge_softc *sc)
381 for (i = 0; i < STGE_TIMEOUT; i++) {
383 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
392 * Read data from the serial EEPROM.
395 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
398 if (stge_eeprom_wait(sc))
399 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
401 CSR_WRITE_2(sc, STGE_EepromCtrl,
402 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
403 if (stge_eeprom_wait(sc))
404 device_printf(sc->sc_dev, "EEPROM read timed out\n");
405 *data = CSR_READ_2(sc, STGE_EepromData);
410 stge_probe(device_t dev)
412 const struct stge_product *sp;
414 uint16_t vendor, devid;
416 vendor = pci_get_vendor(dev);
417 devid = pci_get_device(dev);
419 for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]);
421 if (vendor == sp->stge_vendorid &&
422 devid == sp->stge_deviceid) {
423 device_set_desc(dev, sp->stge_name);
424 return (BUS_PROBE_DEFAULT);
432 stge_attach(device_t dev)
434 struct stge_softc *sc;
436 uint8_t enaddr[ETHER_ADDR_LEN];
442 sc = device_get_softc(dev);
445 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
447 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF);
448 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
449 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc);
454 pci_enable_busmaster(dev);
455 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
456 val = pci_read_config(dev, PCIR_BAR(1), 4);
457 if ((val & 0x01) != 0)
458 sc->sc_spec = stge_res_spec_mem;
460 val = pci_read_config(dev, PCIR_BAR(0), 4);
461 if ((val & 0x01) == 0) {
462 device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
466 sc->sc_spec = stge_res_spec_io;
468 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res);
470 device_printf(dev, "couldn't allocate %s resources\n",
471 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O");
474 sc->sc_rev = pci_get_revid(dev);
476 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
477 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
478 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
479 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
481 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
482 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
483 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
484 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
486 /* Pull in device tunables. */
487 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
488 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
489 "rxint_nframe", &sc->sc_rxint_nframe);
491 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN ||
492 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) {
493 device_printf(dev, "rxint_nframe value out of range; "
494 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT);
495 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
499 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
500 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
501 "rxint_dmawait", &sc->sc_rxint_dmawait);
503 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN ||
504 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) {
505 device_printf(dev, "rxint_dmawait value out of range; "
506 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT);
507 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
511 if ((error = stge_dma_alloc(sc) != 0))
515 * Determine if we're copper or fiber. It affects how we
518 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
523 /* Load LED configuration from EEPROM. */
524 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
527 * Reset the chip to a known state.
530 stge_reset(sc, STGE_RESET_FULL);
534 * Reading the station address from the EEPROM doesn't seem
535 * to work, at least on my sample boards. Instead, since
536 * the reset sequence does AutoInit, read it from the station
537 * address registers. For Sundance 1023 you can only read it
540 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
543 v = CSR_READ_2(sc, STGE_StationAddress0);
544 enaddr[0] = v & 0xff;
546 v = CSR_READ_2(sc, STGE_StationAddress1);
547 enaddr[2] = v & 0xff;
549 v = CSR_READ_2(sc, STGE_StationAddress2);
550 enaddr[4] = v & 0xff;
554 uint16_t myaddr[ETHER_ADDR_LEN / 2];
555 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
556 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
558 myaddr[i] = le16toh(myaddr[i]);
560 bcopy(myaddr, enaddr, sizeof(enaddr));
564 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
566 device_printf(sc->sc_dev, "failed to if_alloc()\n");
572 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
573 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
574 ifp->if_ioctl = stge_ioctl;
575 ifp->if_start = stge_start;
576 ifp->if_init = stge_init;
577 ifp->if_mtu = ETHERMTU;
578 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1;
579 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
580 IFQ_SET_READY(&ifp->if_snd);
581 /* Revision B3 and earlier chips have checksum bug. */
582 if (sc->sc_rev >= 0x0c) {
583 ifp->if_hwassist = STGE_CSUM_FEATURES;
584 ifp->if_capabilities = IFCAP_HWCSUM;
586 ifp->if_hwassist = 0;
587 ifp->if_capabilities = 0;
589 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
590 ifp->if_capenable = ifp->if_capabilities;
593 * Read some important bits from the PhyCtrl register.
595 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
596 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
598 /* Set up MII bus. */
599 flags = MIIF_DOPAUSE;
600 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e)
601 flags |= MIIF_MACPRIV0;
602 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange,
603 stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
606 device_printf(sc->sc_dev, "attaching PHYs failed\n");
610 ether_ifattach(ifp, enaddr);
612 /* VLAN capability setup */
613 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
614 if (sc->sc_rev >= 0x0c)
615 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
616 ifp->if_capenable = ifp->if_capabilities;
617 #ifdef DEVICE_POLLING
618 ifp->if_capabilities |= IFCAP_POLLING;
621 * Tell the upper layer(s) we support long frames.
622 * Must appear after the call to ether_ifattach() because
623 * ether_ifattach() sets ifi_hdrlen to the default value.
625 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
628 * The manual recommends disabling early transmit, so we
629 * do. It's disabled anyway, if using IP checksumming,
630 * since the entire packet must be in the FIFO in order
631 * for the chip to perform the checksum.
633 sc->sc_txthresh = 0x0fff;
636 * Disable MWI if the PCI layer tells us to.
639 if ((cmd & PCIM_CMD_MWRICEN) == 0)
640 sc->sc_DMACtrl |= DMAC_MWIDisable;
645 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
646 NULL, stge_intr, sc, &sc->sc_ih);
649 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
662 stge_detach(device_t dev)
664 struct stge_softc *sc;
667 sc = device_get_softc(dev);
670 #ifdef DEVICE_POLLING
671 if (ifp && ifp->if_capenable & IFCAP_POLLING)
672 ether_poll_deregister(ifp);
674 if (device_is_attached(dev)) {
680 callout_drain(&sc->sc_tick_ch);
681 taskqueue_drain(taskqueue_swi, &sc->sc_link_task);
685 if (sc->sc_miibus != NULL) {
686 device_delete_child(dev, sc->sc_miibus);
687 sc->sc_miibus = NULL;
689 bus_generic_detach(dev);
698 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
701 bus_release_resources(dev, sc->sc_spec, sc->sc_res);
703 mtx_destroy(&sc->sc_mii_mtx);
704 mtx_destroy(&sc->sc_mtx);
709 struct stge_dmamap_arg {
710 bus_addr_t stge_busaddr;
714 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
716 struct stge_dmamap_arg *ctx;
721 ctx = (struct stge_dmamap_arg *)arg;
722 ctx->stge_busaddr = segs[0].ds_addr;
726 stge_dma_alloc(struct stge_softc *sc)
728 struct stge_dmamap_arg ctx;
729 struct stge_txdesc *txd;
730 struct stge_rxdesc *rxd;
733 /* create parent tag. */
734 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */
735 1, 0, /* algnmnt, boundary */
736 STGE_DMA_MAXADDR, /* lowaddr */
737 BUS_SPACE_MAXADDR, /* highaddr */
738 NULL, NULL, /* filter, filterarg */
739 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
741 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
743 NULL, NULL, /* lockfunc, lockarg */
744 &sc->sc_cdata.stge_parent_tag);
746 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
749 /* create tag for Tx ring. */
750 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
751 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
752 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
753 BUS_SPACE_MAXADDR, /* highaddr */
754 NULL, NULL, /* filter, filterarg */
755 STGE_TX_RING_SZ, /* maxsize */
757 STGE_TX_RING_SZ, /* maxsegsize */
759 NULL, NULL, /* lockfunc, lockarg */
760 &sc->sc_cdata.stge_tx_ring_tag);
762 device_printf(sc->sc_dev,
763 "failed to allocate Tx ring DMA tag\n");
767 /* create tag for Rx ring. */
768 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
769 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
770 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
771 BUS_SPACE_MAXADDR, /* highaddr */
772 NULL, NULL, /* filter, filterarg */
773 STGE_RX_RING_SZ, /* maxsize */
775 STGE_RX_RING_SZ, /* maxsegsize */
777 NULL, NULL, /* lockfunc, lockarg */
778 &sc->sc_cdata.stge_rx_ring_tag);
780 device_printf(sc->sc_dev,
781 "failed to allocate Rx ring DMA tag\n");
785 /* create tag for Tx buffers. */
786 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
787 1, 0, /* algnmnt, boundary */
788 BUS_SPACE_MAXADDR, /* lowaddr */
789 BUS_SPACE_MAXADDR, /* highaddr */
790 NULL, NULL, /* filter, filterarg */
791 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
792 STGE_MAXTXSEGS, /* nsegments */
793 MCLBYTES, /* maxsegsize */
795 NULL, NULL, /* lockfunc, lockarg */
796 &sc->sc_cdata.stge_tx_tag);
798 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
802 /* create tag for Rx buffers. */
803 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
804 1, 0, /* algnmnt, boundary */
805 BUS_SPACE_MAXADDR, /* lowaddr */
806 BUS_SPACE_MAXADDR, /* highaddr */
807 NULL, NULL, /* filter, filterarg */
808 MCLBYTES, /* maxsize */
810 MCLBYTES, /* maxsegsize */
812 NULL, NULL, /* lockfunc, lockarg */
813 &sc->sc_cdata.stge_rx_tag);
815 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
819 /* allocate DMA'able memory and load the DMA map for Tx ring. */
820 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
821 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT |
822 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map);
824 device_printf(sc->sc_dev,
825 "failed to allocate DMA'able memory for Tx ring\n");
829 ctx.stge_busaddr = 0;
830 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
831 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
832 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
833 if (error != 0 || ctx.stge_busaddr == 0) {
834 device_printf(sc->sc_dev,
835 "failed to load DMA'able memory for Tx ring\n");
838 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
840 /* allocate DMA'able memory and load the DMA map for Rx ring. */
841 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
842 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT |
843 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map);
845 device_printf(sc->sc_dev,
846 "failed to allocate DMA'able memory for Rx ring\n");
850 ctx.stge_busaddr = 0;
851 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
852 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
853 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
854 if (error != 0 || ctx.stge_busaddr == 0) {
855 device_printf(sc->sc_dev,
856 "failed to load DMA'able memory for Rx ring\n");
859 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
861 /* create DMA maps for Tx buffers. */
862 for (i = 0; i < STGE_TX_RING_CNT; i++) {
863 txd = &sc->sc_cdata.stge_txdesc[i];
866 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
869 device_printf(sc->sc_dev,
870 "failed to create Tx dmamap\n");
874 /* create DMA maps for Rx buffers. */
875 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
876 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
877 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
880 for (i = 0; i < STGE_RX_RING_CNT; i++) {
881 rxd = &sc->sc_cdata.stge_rxdesc[i];
884 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
887 device_printf(sc->sc_dev,
888 "failed to create Rx dmamap\n");
898 stge_dma_free(struct stge_softc *sc)
900 struct stge_txdesc *txd;
901 struct stge_rxdesc *rxd;
905 if (sc->sc_cdata.stge_tx_ring_tag) {
906 if (sc->sc_cdata.stge_tx_ring_map)
907 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
908 sc->sc_cdata.stge_tx_ring_map);
909 if (sc->sc_cdata.stge_tx_ring_map &&
910 sc->sc_rdata.stge_tx_ring)
911 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
912 sc->sc_rdata.stge_tx_ring,
913 sc->sc_cdata.stge_tx_ring_map);
914 sc->sc_rdata.stge_tx_ring = NULL;
915 sc->sc_cdata.stge_tx_ring_map = 0;
916 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
917 sc->sc_cdata.stge_tx_ring_tag = NULL;
920 if (sc->sc_cdata.stge_rx_ring_tag) {
921 if (sc->sc_cdata.stge_rx_ring_map)
922 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
923 sc->sc_cdata.stge_rx_ring_map);
924 if (sc->sc_cdata.stge_rx_ring_map &&
925 sc->sc_rdata.stge_rx_ring)
926 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
927 sc->sc_rdata.stge_rx_ring,
928 sc->sc_cdata.stge_rx_ring_map);
929 sc->sc_rdata.stge_rx_ring = NULL;
930 sc->sc_cdata.stge_rx_ring_map = 0;
931 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
932 sc->sc_cdata.stge_rx_ring_tag = NULL;
935 if (sc->sc_cdata.stge_tx_tag) {
936 for (i = 0; i < STGE_TX_RING_CNT; i++) {
937 txd = &sc->sc_cdata.stge_txdesc[i];
938 if (txd->tx_dmamap) {
939 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
944 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
945 sc->sc_cdata.stge_tx_tag = NULL;
948 if (sc->sc_cdata.stge_rx_tag) {
949 for (i = 0; i < STGE_RX_RING_CNT; i++) {
950 rxd = &sc->sc_cdata.stge_rxdesc[i];
951 if (rxd->rx_dmamap) {
952 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
957 if (sc->sc_cdata.stge_rx_sparemap) {
958 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
959 sc->sc_cdata.stge_rx_sparemap);
960 sc->sc_cdata.stge_rx_sparemap = 0;
962 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
963 sc->sc_cdata.stge_rx_tag = NULL;
966 if (sc->sc_cdata.stge_parent_tag) {
967 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
968 sc->sc_cdata.stge_parent_tag = NULL;
975 * Make sure the interface is stopped at reboot time.
978 stge_shutdown(device_t dev)
981 return (stge_suspend(dev));
985 stge_setwol(struct stge_softc *sc)
990 STGE_LOCK_ASSERT(sc);
993 v = CSR_READ_1(sc, STGE_WakeEvent);
994 /* Disable all WOL bits. */
995 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
997 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
998 v |= WE_MagicPktEnable | WE_WakeOnLanEnable;
999 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1000 /* Reset Tx and prevent transmission. */
1001 CSR_WRITE_4(sc, STGE_AsicCtrl,
1002 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1004 * TC9021 automatically reset link speed to 100Mbps when it's put
1005 * into sleep so there is no need to try to resetting link speed.
1010 stge_suspend(device_t dev)
1012 struct stge_softc *sc;
1014 sc = device_get_softc(dev);
1018 sc->sc_suspended = 1;
1026 stge_resume(device_t dev)
1028 struct stge_softc *sc;
1032 sc = device_get_softc(dev);
1036 * Clear WOL bits, so special frames wouldn't interfere
1037 * normal Rx operation anymore.
1039 v = CSR_READ_1(sc, STGE_WakeEvent);
1040 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1041 WE_WakeOnLanEnable);
1042 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1044 if (ifp->if_flags & IFF_UP)
1045 stge_init_locked(sc);
1047 sc->sc_suspended = 0;
1054 stge_dma_wait(struct stge_softc *sc)
1058 for (i = 0; i < STGE_TIMEOUT; i++) {
1060 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1064 if (i == STGE_TIMEOUT)
1065 device_printf(sc->sc_dev, "DMA wait timed out\n");
1069 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1071 struct stge_txdesc *txd;
1072 struct stge_tfd *tfd;
1074 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1075 int error, i, nsegs, si;
1076 uint64_t csum_flags, tfc;
1078 STGE_LOCK_ASSERT(sc);
1080 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1083 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1084 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1085 if (error == EFBIG) {
1086 m = m_collapse(*m_head, M_DONTWAIT, STGE_MAXTXSEGS);
1093 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1094 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1100 } else if (error != 0)
1110 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1111 if (m->m_pkthdr.csum_flags & CSUM_IP)
1112 csum_flags |= TFD_IPChecksumEnable;
1113 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1114 csum_flags |= TFD_TCPChecksumEnable;
1115 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1116 csum_flags |= TFD_UDPChecksumEnable;
1119 si = sc->sc_cdata.stge_tx_prod;
1120 tfd = &sc->sc_rdata.stge_tx_ring[si];
1121 for (i = 0; i < nsegs; i++)
1122 tfd->tfd_frags[i].frag_word0 =
1123 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1124 FRAG_LEN(txsegs[i].ds_len));
1125 sc->sc_cdata.stge_tx_cnt++;
1127 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1128 TFD_FragCount(nsegs) | csum_flags;
1129 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1130 tfc |= TFD_TxDMAIndicate;
1132 /* Update producer index. */
1133 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1135 /* Check if we have a VLAN tag to insert. */
1136 if (m->m_flags & M_VLANTAG)
1137 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag));
1138 tfd->tfd_control = htole64(tfc);
1140 /* Update Tx Queue. */
1141 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1142 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1145 /* Sync descriptors. */
1146 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1147 BUS_DMASYNC_PREWRITE);
1148 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1149 sc->sc_cdata.stge_tx_ring_map,
1150 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1156 * stge_start: [ifnet interface function]
1158 * Start packet transmission on the interface.
1161 stge_start(struct ifnet *ifp)
1163 struct stge_softc *sc;
1167 stge_start_locked(ifp);
1172 stge_start_locked(struct ifnet *ifp)
1174 struct stge_softc *sc;
1175 struct mbuf *m_head;
1180 STGE_LOCK_ASSERT(sc);
1182 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1183 IFF_DRV_RUNNING || sc->sc_link == 0)
1186 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1187 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1188 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1192 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1196 * Pack the data into the transmit ring. If we
1197 * don't have room, set the OACTIVE flag and wait
1198 * for the NIC to drain the ring.
1200 if (stge_encap(sc, &m_head)) {
1203 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1204 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1210 * If there's a BPF listener, bounce a copy of this frame
1213 ETHER_BPF_MTAP(ifp, m_head);
1218 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1220 /* Set a timeout in case the chip goes out to lunch. */
1221 sc->sc_watchdog_timer = 5;
1228 * Watchdog timer handler.
1231 stge_watchdog(struct stge_softc *sc)
1235 STGE_LOCK_ASSERT(sc);
1237 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer)
1241 if_printf(sc->sc_ifp, "device timeout\n");
1243 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1244 stge_init_locked(sc);
1245 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1246 stge_start_locked(ifp);
1250 * stge_ioctl: [ifnet interface function]
1252 * Handle control requests from the operator.
1255 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1257 struct stge_softc *sc;
1259 struct mii_data *mii;
1263 ifr = (struct ifreq *)data;
1267 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1269 else if (ifp->if_mtu != ifr->ifr_mtu) {
1270 ifp->if_mtu = ifr->ifr_mtu;
1272 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1273 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1274 stge_init_locked(sc);
1281 if ((ifp->if_flags & IFF_UP) != 0) {
1282 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1283 if (((ifp->if_flags ^ sc->sc_if_flags)
1284 & IFF_PROMISC) != 0)
1285 stge_set_filter(sc);
1287 if (sc->sc_detach == 0)
1288 stge_init_locked(sc);
1291 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1294 sc->sc_if_flags = ifp->if_flags;
1300 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1306 mii = device_get_softc(sc->sc_miibus);
1307 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1310 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1311 #ifdef DEVICE_POLLING
1312 if ((mask & IFCAP_POLLING) != 0) {
1313 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1314 error = ether_poll_register(stge_poll, ifp);
1318 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1319 ifp->if_capenable |= IFCAP_POLLING;
1322 error = ether_poll_deregister(ifp);
1326 CSR_WRITE_2(sc, STGE_IntEnable,
1328 ifp->if_capenable &= ~IFCAP_POLLING;
1333 if ((mask & IFCAP_HWCSUM) != 0) {
1334 ifp->if_capenable ^= IFCAP_HWCSUM;
1335 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1336 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1337 ifp->if_hwassist = STGE_CSUM_FEATURES;
1339 ifp->if_hwassist = 0;
1341 if ((mask & IFCAP_WOL) != 0 &&
1342 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1343 if ((mask & IFCAP_WOL_MAGIC) != 0)
1344 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1346 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1347 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1348 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1350 stge_vlan_setup(sc);
1354 VLAN_CAPABILITIES(ifp);
1357 error = ether_ioctl(ifp, cmd, data);
1365 stge_link_task(void *arg, int pending)
1367 struct stge_softc *sc;
1368 struct mii_data *mii;
1372 sc = (struct stge_softc *)arg;
1375 mii = device_get_softc(sc->sc_miibus);
1376 if (mii->mii_media_status & IFM_ACTIVE) {
1377 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1383 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
1384 sc->sc_MACCtrl |= MC_DuplexSelect;
1385 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0)
1386 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
1387 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0)
1388 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
1390 * Update STGE_MACCtrl register depending on link status.
1391 * (duplex, flow control etc)
1393 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1394 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1395 v |= sc->sc_MACCtrl;
1396 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1397 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1398 /* Duplex setting changed, reset Tx/Rx functions. */
1399 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1400 ac |= AC_TxReset | AC_RxReset;
1401 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1402 for (i = 0; i < STGE_TIMEOUT; i++) {
1404 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1407 if (i == STGE_TIMEOUT)
1408 device_printf(sc->sc_dev, "reset failed to complete\n");
1414 stge_tx_error(struct stge_softc *sc)
1420 txstat = CSR_READ_4(sc, STGE_TxStatus);
1421 if ((txstat & TS_TxComplete) == 0)
1424 if ((txstat & TS_TxUnderrun) != 0) {
1427 * There should be a more better way to recover
1428 * from Tx underrun instead of a full reset.
1430 if (sc->sc_nerr++ < STGE_MAXERR)
1431 device_printf(sc->sc_dev, "Tx underrun, "
1433 if (sc->sc_nerr == STGE_MAXERR)
1434 device_printf(sc->sc_dev, "too many errors; "
1435 "not reporting any more\n");
1439 /* Maximum/Late collisions, Re-enable Tx MAC. */
1440 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1441 CSR_WRITE_4(sc, STGE_MACCtrl,
1442 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1452 * Interrupt service routine.
1455 stge_intr(void *arg)
1457 struct stge_softc *sc;
1462 sc = (struct stge_softc *)arg;
1467 #ifdef DEVICE_POLLING
1468 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1471 status = CSR_READ_2(sc, STGE_IntStatus);
1472 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1475 /* Disable interrupts. */
1476 for (reinit = 0;;) {
1477 status = CSR_READ_2(sc, STGE_IntStatusAck);
1478 status &= sc->sc_IntEnable;
1481 /* Host interface errors. */
1482 if ((status & IS_HostError) != 0) {
1483 device_printf(sc->sc_dev,
1484 "Host interface error, resetting...\n");
1489 /* Receive interrupts. */
1490 if ((status & IS_RxDMAComplete) != 0) {
1492 if ((status & IS_RFDListEnd) != 0)
1493 CSR_WRITE_4(sc, STGE_DMACtrl,
1497 /* Transmit interrupts. */
1498 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1501 /* Transmission errors.*/
1502 if ((status & IS_TxComplete) != 0) {
1503 if ((reinit = stge_tx_error(sc)) != 0)
1510 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1511 stge_init_locked(sc);
1514 /* Re-enable interrupts. */
1515 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1517 /* Try to get more packets going. */
1518 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1519 stge_start_locked(ifp);
1528 * Helper; handle transmit interrupts.
1531 stge_txeof(struct stge_softc *sc)
1534 struct stge_txdesc *txd;
1538 STGE_LOCK_ASSERT(sc);
1542 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1545 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1546 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1549 * Go through our Tx list and free mbufs for those
1550 * frames which have been transmitted.
1552 for (cons = sc->sc_cdata.stge_tx_cons;;
1553 cons = (cons + 1) % STGE_TX_RING_CNT) {
1554 if (sc->sc_cdata.stge_tx_cnt <= 0)
1556 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1557 if ((control & TFD_TFDDone) == 0)
1559 sc->sc_cdata.stge_tx_cnt--;
1560 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1562 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1563 BUS_DMASYNC_POSTWRITE);
1564 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1566 /* Output counter is updated with statistics register */
1569 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1570 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1571 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1573 sc->sc_cdata.stge_tx_cons = cons;
1574 if (sc->sc_cdata.stge_tx_cnt == 0)
1575 sc->sc_watchdog_timer = 0;
1577 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1578 sc->sc_cdata.stge_tx_ring_map,
1579 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1582 static __inline void
1583 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1585 struct stge_rfd *rfd;
1587 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1588 rfd->rfd_status = 0;
1591 #ifndef __NO_STRICT_ALIGNMENT
1593 * It seems that TC9021's DMA engine has alignment restrictions in
1594 * DMA scatter operations. The first DMA segment has no address
1595 * alignment restrictins but the rest should be aligned on 4(?) bytes
1596 * boundary. Otherwise it would corrupt random memory. Since we don't
1597 * know which one is used for the first segment in advance we simply
1598 * don't align at all.
1599 * To avoid copying over an entire frame to align, we allocate a new
1600 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1601 * prepended into the existing mbuf chain.
1603 static __inline struct mbuf *
1604 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1609 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1610 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1611 m->m_data += ETHER_HDR_LEN;
1614 MGETHDR(n, M_DONTWAIT, MT_DATA);
1616 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1617 m->m_data += ETHER_HDR_LEN;
1618 m->m_len -= ETHER_HDR_LEN;
1619 n->m_len = ETHER_HDR_LEN;
1620 M_MOVE_PKTHDR(n, m);
1633 * Helper; handle receive interrupts.
1636 stge_rxeof(struct stge_softc *sc)
1639 struct stge_rxdesc *rxd;
1640 struct mbuf *mp, *m;
1643 int cons, prog, rx_npkts;
1645 STGE_LOCK_ASSERT(sc);
1650 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1651 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1654 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1655 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1656 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1657 status = RFD_RxStatus(status64);
1658 if ((status & RFD_RFDDone) == 0)
1660 #ifdef DEVICE_POLLING
1661 if (ifp->if_capenable & IFCAP_POLLING) {
1662 if (sc->sc_cdata.stge_rxcycles <= 0)
1664 sc->sc_cdata.stge_rxcycles--;
1668 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1672 * If the packet had an error, drop it. Note we count
1673 * the error later in the periodic stats update.
1675 if ((status & RFD_FrameEnd) != 0 && (status &
1676 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1677 RFD_RxAlignmentError | RFD_RxFCSError |
1678 RFD_RxLengthError)) != 0) {
1679 stge_discard_rxbuf(sc, cons);
1680 if (sc->sc_cdata.stge_rxhead != NULL) {
1681 m_freem(sc->sc_cdata.stge_rxhead);
1682 STGE_RXCHAIN_RESET(sc);
1687 * Add a new receive buffer to the ring.
1689 if (stge_newbuf(sc, cons) != 0) {
1691 stge_discard_rxbuf(sc, cons);
1692 if (sc->sc_cdata.stge_rxhead != NULL) {
1693 m_freem(sc->sc_cdata.stge_rxhead);
1694 STGE_RXCHAIN_RESET(sc);
1699 if ((status & RFD_FrameEnd) != 0)
1700 mp->m_len = RFD_RxDMAFrameLen(status) -
1701 sc->sc_cdata.stge_rxlen;
1702 sc->sc_cdata.stge_rxlen += mp->m_len;
1705 if (sc->sc_cdata.stge_rxhead == NULL) {
1706 sc->sc_cdata.stge_rxhead = mp;
1707 sc->sc_cdata.stge_rxtail = mp;
1709 mp->m_flags &= ~M_PKTHDR;
1710 sc->sc_cdata.stge_rxtail->m_next = mp;
1711 sc->sc_cdata.stge_rxtail = mp;
1714 if ((status & RFD_FrameEnd) != 0) {
1715 m = sc->sc_cdata.stge_rxhead;
1716 m->m_pkthdr.rcvif = ifp;
1717 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1719 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1721 STGE_RXCHAIN_RESET(sc);
1725 * Set the incoming checksum information for
1728 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1729 if ((status & RFD_IPDetected) != 0) {
1730 m->m_pkthdr.csum_flags |=
1732 if ((status & RFD_IPError) == 0)
1733 m->m_pkthdr.csum_flags |=
1736 if (((status & RFD_TCPDetected) != 0 &&
1737 (status & RFD_TCPError) == 0) ||
1738 ((status & RFD_UDPDetected) != 0 &&
1739 (status & RFD_UDPError) == 0)) {
1740 m->m_pkthdr.csum_flags |=
1741 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1742 m->m_pkthdr.csum_data = 0xffff;
1746 #ifndef __NO_STRICT_ALIGNMENT
1747 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1748 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1749 STGE_RXCHAIN_RESET(sc);
1754 /* Check for VLAN tagged packets. */
1755 if ((status & RFD_VLANDetected) != 0 &&
1756 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1757 m->m_pkthdr.ether_vtag = RFD_TCI(status64);
1758 m->m_flags |= M_VLANTAG;
1763 (*ifp->if_input)(ifp, m);
1767 STGE_RXCHAIN_RESET(sc);
1772 /* Update the consumer index. */
1773 sc->sc_cdata.stge_rx_cons = cons;
1774 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1775 sc->sc_cdata.stge_rx_ring_map,
1776 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1781 #ifdef DEVICE_POLLING
1783 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1785 struct stge_softc *sc;
1792 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1797 sc->sc_cdata.stge_rxcycles = count;
1798 rx_npkts = stge_rxeof(sc);
1801 if (cmd == POLL_AND_CHECK_STATUS) {
1802 status = CSR_READ_2(sc, STGE_IntStatus);
1803 status &= sc->sc_IntEnable;
1805 if ((status & IS_HostError) != 0) {
1806 device_printf(sc->sc_dev,
1807 "Host interface error, resetting...\n");
1808 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1809 stge_init_locked(sc);
1811 if ((status & IS_TxComplete) != 0) {
1812 if (stge_tx_error(sc) != 0) {
1813 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1814 stge_init_locked(sc);
1821 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1822 stge_start_locked(ifp);
1827 #endif /* DEVICE_POLLING */
1832 * One second timer, used to tick the MII.
1835 stge_tick(void *arg)
1837 struct stge_softc *sc;
1838 struct mii_data *mii;
1840 sc = (struct stge_softc *)arg;
1842 STGE_LOCK_ASSERT(sc);
1844 mii = device_get_softc(sc->sc_miibus);
1847 /* Update statistics counters. */
1848 stge_stats_update(sc);
1851 * Relcaim any pending Tx descriptors to release mbufs in a
1852 * timely manner as we don't generate Tx completion interrupts
1853 * for every frame. This limits the delay to a maximum of one
1856 if (sc->sc_cdata.stge_tx_cnt != 0)
1861 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1865 * stge_stats_update:
1867 * Read the TC9021 statistics counters.
1870 stge_stats_update(struct stge_softc *sc)
1874 STGE_LOCK_ASSERT(sc);
1878 CSR_READ_4(sc,STGE_OctetRcvOk);
1880 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk);
1882 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors);
1884 CSR_READ_4(sc, STGE_OctetXmtdOk);
1886 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk);
1888 ifp->if_collisions +=
1889 CSR_READ_4(sc, STGE_LateCollisions) +
1890 CSR_READ_4(sc, STGE_MultiColFrames) +
1891 CSR_READ_4(sc, STGE_SingleColFrames);
1894 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1895 CSR_READ_2(sc, STGE_FramesWEXDeferal);
1901 * Perform a soft reset on the TC9021.
1904 stge_reset(struct stge_softc *sc, uint32_t how)
1910 STGE_LOCK_ASSERT(sc);
1913 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1916 ac |= AC_TxReset | AC_FIFO;
1920 ac |= AC_RxReset | AC_FIFO;
1923 case STGE_RESET_FULL:
1926 * Only assert RstOut if we're fiber. We need GMII clocks
1927 * to be present in order for the reset to complete on fiber
1930 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
1931 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1932 (sc->sc_usefiber ? AC_RstOut : 0);
1936 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1938 /* Account for reset problem at 10Mbps. */
1941 for (i = 0; i < STGE_TIMEOUT; i++) {
1942 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1947 if (i == STGE_TIMEOUT)
1948 device_printf(sc->sc_dev, "reset failed to complete\n");
1950 /* Set LED, from Linux IPG driver. */
1951 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1952 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
1953 if ((sc->sc_led & 0x01) != 0)
1955 if ((sc->sc_led & 0x03) != 0)
1956 ac |= AC_LEDModeBit1;
1957 if ((sc->sc_led & 0x08) != 0)
1959 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1961 /* Set PHY, from Linux IPG driver */
1962 v = CSR_READ_1(sc, STGE_PhySet);
1963 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
1964 v |= ((sc->sc_led & 0x70) >> 4);
1965 CSR_WRITE_1(sc, STGE_PhySet, v);
1969 * stge_init: [ ifnet interface function ]
1971 * Initialize the interface.
1974 stge_init(void *xsc)
1976 struct stge_softc *sc;
1978 sc = (struct stge_softc *)xsc;
1980 stge_init_locked(sc);
1985 stge_init_locked(struct stge_softc *sc)
1988 struct mii_data *mii;
1993 STGE_LOCK_ASSERT(sc);
1996 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1998 mii = device_get_softc(sc->sc_miibus);
2001 * Cancel any pending I/O.
2006 * Reset the chip to a known state.
2008 stge_reset(sc, STGE_RESET_FULL);
2010 /* Init descriptors. */
2011 error = stge_init_rx_ring(sc);
2013 device_printf(sc->sc_dev,
2014 "initialization failed: no memory for rx buffers\n");
2018 stge_init_tx_ring(sc);
2020 /* Set the station address. */
2021 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2022 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2023 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2024 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2027 * Set the statistics masks. Disable all the RMON stats,
2028 * and disable selected stats in the non-RMON stats registers.
2030 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2031 CSR_WRITE_4(sc, STGE_StatisticsMask,
2032 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2033 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2034 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2037 /* Set up the receive filter. */
2038 stge_set_filter(sc);
2039 /* Program multicast filter. */
2043 * Give the transmit and receive ring to the chip.
2045 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2046 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2047 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2048 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2050 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2051 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2052 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2053 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2056 * Initialize the Tx auto-poll period. It's OK to make this number
2057 * large (255 is the max, but we use 127) -- we explicitly kick the
2058 * transmit engine when there's actually a packet.
2060 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2062 /* ..and the Rx auto-poll period. */
2063 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2065 /* Initialize the Tx start threshold. */
2066 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2068 /* Rx DMA thresholds, from Linux */
2069 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2070 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2072 /* Rx early threhold, from Linux */
2073 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2075 /* Tx DMA thresholds, from Linux */
2076 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2077 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2080 * Initialize the Rx DMA interrupt control register. We
2081 * request an interrupt after every incoming packet, but
2082 * defer it for sc_rxint_dmawait us. When the number of
2083 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2084 * deferring the interrupt, and signal it immediately.
2086 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2087 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2088 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2091 * Initialize the interrupt mask.
2093 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2094 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2095 #ifdef DEVICE_POLLING
2096 /* Disable interrupts if we are polling. */
2097 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2098 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2101 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2104 * Configure the DMA engine.
2105 * XXX Should auto-tune TxBurstLimit.
2107 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2110 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2111 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2114 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2115 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2118 * Set the maximum frame size.
2120 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2121 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2124 * Initialize MacCtrl -- do it before setting the media,
2125 * as setting the media will actually program the register.
2127 * Note: We have to poke the IFS value before poking
2130 /* Tx/Rx MAC should be disabled before programming IFS.*/
2131 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2133 stge_vlan_setup(sc);
2135 if (sc->sc_rev >= 6) { /* >= B.2 */
2136 /* Multi-frag frame bug work-around. */
2137 CSR_WRITE_2(sc, STGE_DebugCtrl,
2138 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2140 /* Tx Poll Now bug work-around. */
2141 CSR_WRITE_2(sc, STGE_DebugCtrl,
2142 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2143 /* Tx Poll Now bug work-around. */
2144 CSR_WRITE_2(sc, STGE_DebugCtrl,
2145 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2148 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2149 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2150 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2152 * It seems that transmitting frames without checking the state of
2153 * Rx/Tx MAC wedge the hardware.
2160 * Set the current media.
2165 * Start the one second MII clock.
2167 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2172 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2173 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2177 device_printf(sc->sc_dev, "interface not running\n");
2181 stge_vlan_setup(struct stge_softc *sc)
2188 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2189 * MC_AutoVLANuntagging bit.
2190 * MC_AutoVLANtagging bit selects which VLAN source to use
2191 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2192 * bit has priority over MC_AutoVLANtagging bit. So we always
2193 * use TFC instead of STGE_VLANTag register.
2195 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2196 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2197 v |= MC_AutoVLANuntagging;
2199 v &= ~MC_AutoVLANuntagging;
2200 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2204 * Stop transmission on the interface.
2207 stge_stop(struct stge_softc *sc)
2210 struct stge_txdesc *txd;
2211 struct stge_rxdesc *rxd;
2215 STGE_LOCK_ASSERT(sc);
2217 * Stop the one second clock.
2219 callout_stop(&sc->sc_tick_ch);
2220 sc->sc_watchdog_timer = 0;
2223 * Disable interrupts.
2225 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2228 * Stop receiver, transmitter, and stats update.
2232 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2233 v |= MC_StatisticsDisable;
2234 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2237 * Stop the transmit and receive DMA.
2240 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2241 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2242 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2243 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2246 * Free RX and TX mbufs still in the queues.
2248 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2249 rxd = &sc->sc_cdata.stge_rxdesc[i];
2250 if (rxd->rx_m != NULL) {
2251 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2252 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2253 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2259 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2260 txd = &sc->sc_cdata.stge_txdesc[i];
2261 if (txd->tx_m != NULL) {
2262 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2263 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2264 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2272 * Mark the interface down and cancel the watchdog timer.
2275 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2280 stge_start_tx(struct stge_softc *sc)
2285 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2286 if ((v & MC_TxEnabled) != 0)
2289 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2290 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2291 for (i = STGE_TIMEOUT; i > 0; i--) {
2293 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2294 if ((v & MC_TxEnabled) != 0)
2298 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2302 stge_start_rx(struct stge_softc *sc)
2307 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2308 if ((v & MC_RxEnabled) != 0)
2311 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2312 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2313 for (i = STGE_TIMEOUT; i > 0; i--) {
2315 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2316 if ((v & MC_RxEnabled) != 0)
2320 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2324 stge_stop_tx(struct stge_softc *sc)
2329 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2330 if ((v & MC_TxEnabled) == 0)
2333 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2334 for (i = STGE_TIMEOUT; i > 0; i--) {
2336 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2337 if ((v & MC_TxEnabled) == 0)
2341 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2345 stge_stop_rx(struct stge_softc *sc)
2350 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2351 if ((v & MC_RxEnabled) == 0)
2354 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2355 for (i = STGE_TIMEOUT; i > 0; i--) {
2357 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2358 if ((v & MC_RxEnabled) == 0)
2362 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2366 stge_init_tx_ring(struct stge_softc *sc)
2368 struct stge_ring_data *rd;
2369 struct stge_txdesc *txd;
2373 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2374 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2376 sc->sc_cdata.stge_tx_prod = 0;
2377 sc->sc_cdata.stge_tx_cons = 0;
2378 sc->sc_cdata.stge_tx_cnt = 0;
2381 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2382 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2383 if (i == (STGE_TX_RING_CNT - 1))
2384 addr = STGE_TX_RING_ADDR(sc, 0);
2386 addr = STGE_TX_RING_ADDR(sc, i + 1);
2387 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2388 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2389 txd = &sc->sc_cdata.stge_txdesc[i];
2390 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2393 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2394 sc->sc_cdata.stge_tx_ring_map,
2395 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2400 stge_init_rx_ring(struct stge_softc *sc)
2402 struct stge_ring_data *rd;
2406 sc->sc_cdata.stge_rx_cons = 0;
2407 STGE_RXCHAIN_RESET(sc);
2410 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2411 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2412 if (stge_newbuf(sc, i) != 0)
2414 if (i == (STGE_RX_RING_CNT - 1))
2415 addr = STGE_RX_RING_ADDR(sc, 0);
2417 addr = STGE_RX_RING_ADDR(sc, i + 1);
2418 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2419 rd->stge_rx_ring[i].rfd_status = 0;
2422 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2423 sc->sc_cdata.stge_rx_ring_map,
2424 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2432 * Add a receive buffer to the indicated descriptor.
2435 stge_newbuf(struct stge_softc *sc, int idx)
2437 struct stge_rxdesc *rxd;
2438 struct stge_rfd *rfd;
2440 bus_dma_segment_t segs[1];
2444 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2447 m->m_len = m->m_pkthdr.len = MCLBYTES;
2449 * The hardware requires 4bytes aligned DMA address when JUMBO
2452 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2453 m_adj(m, ETHER_ALIGN);
2455 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag,
2456 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2460 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2462 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2463 if (rxd->rx_m != NULL) {
2464 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2465 BUS_DMASYNC_POSTREAD);
2466 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2468 map = rxd->rx_dmamap;
2469 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2470 sc->sc_cdata.stge_rx_sparemap = map;
2471 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2472 BUS_DMASYNC_PREREAD);
2475 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2476 rfd->rfd_frag.frag_word0 =
2477 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2478 rfd->rfd_status = 0;
2486 * Set up the receive filter.
2489 stge_set_filter(struct stge_softc *sc)
2494 STGE_LOCK_ASSERT(sc);
2498 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2499 mode |= RM_ReceiveUnicast;
2500 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2501 mode |= RM_ReceiveBroadcast;
2503 mode &= ~RM_ReceiveBroadcast;
2504 if ((ifp->if_flags & IFF_PROMISC) != 0)
2505 mode |= RM_ReceiveAllFrames;
2507 mode &= ~RM_ReceiveAllFrames;
2509 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2513 stge_set_multi(struct stge_softc *sc)
2516 struct ifmultiaddr *ifma;
2522 STGE_LOCK_ASSERT(sc);
2526 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2527 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2528 if ((ifp->if_flags & IFF_PROMISC) != 0)
2529 mode |= RM_ReceiveAllFrames;
2530 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2531 mode |= RM_ReceiveMulticast;
2532 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2536 /* clear existing filters. */
2537 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2538 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2541 * Set up the multicast address filter by passing all multicast
2542 * addresses through a CRC generator, and then using the low-order
2543 * 6 bits as an index into the 64 bit multicast hash table. The
2544 * high order bits select the register, while the rest of the bits
2545 * select the bit within the register.
2548 bzero(mchash, sizeof(mchash));
2551 if_maddr_rlock(sc->sc_ifp);
2552 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) {
2553 if (ifma->ifma_addr->sa_family != AF_LINK)
2555 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2556 ifma->ifma_addr), ETHER_ADDR_LEN);
2558 /* Just want the 6 least significant bits. */
2561 /* Set the corresponding bit in the hash table. */
2562 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2565 if_maddr_runlock(ifp);
2567 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2569 mode |= RM_ReceiveMulticastHash;
2571 mode &= ~RM_ReceiveMulticastHash;
2573 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2574 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2575 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2579 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2585 value = *(int *)arg1;
2586 error = sysctl_handle_int(oidp, &value, 0, req);
2587 if (error || !req->newptr)
2589 if (value < low || value > high)
2591 *(int *)arg1 = value;
2597 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2599 return (sysctl_int_range(oidp, arg1, arg2, req,
2600 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2604 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2606 return (sysctl_int_range(oidp, arg1, arg2, req,
2607 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));