2 * Copyright (c) 2010, LSI Corp.
4 * Author : Manjunath Ranganathaiah
5 * Support: freebsdraid@lsi.com
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of the <ORGANIZATION> nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
38 #include <dev/tws/tws.h>
39 #include <dev/tws/tws_services.h>
40 #include <dev/tws/tws_hdm.h>
43 #include <cam/cam_ccb.h>
45 MALLOC_DEFINE(M_TWS, "twsbuf", "buffers used by tws driver");
46 int tws_queue_depth = TWS_MAX_REQS;
47 int tws_enable_msi = 0;
48 int tws_enable_msix = 0;
53 extern int tws_cam_attach(struct tws_softc *sc);
54 extern void tws_cam_detach(struct tws_softc *sc);
55 extern int tws_init_ctlr(struct tws_softc *sc);
56 extern boolean tws_ctlr_ready(struct tws_softc *sc);
57 extern void tws_turn_off_interrupts(struct tws_softc *sc);
58 extern void tws_q_insert_tail(struct tws_softc *sc, struct tws_request *req,
60 extern struct tws_request *tws_q_remove_request(struct tws_softc *sc,
61 struct tws_request *req, u_int8_t q_type );
62 extern struct tws_request *tws_q_remove_head(struct tws_softc *sc,
64 extern boolean tws_get_response(struct tws_softc *sc, u_int16_t *req_id);
65 extern boolean tws_ctlr_reset(struct tws_softc *sc);
66 extern void tws_intr(void *arg);
67 extern int tws_use_32bit_sgls;
70 struct tws_request *tws_get_request(struct tws_softc *sc, u_int16_t type);
71 int tws_init_connect(struct tws_softc *sc, u_int16_t mc);
72 void tws_send_event(struct tws_softc *sc, u_int8_t event);
73 uint8_t tws_get_state(struct tws_softc *sc);
74 void tws_release_request(struct tws_request *req);
78 /* Function prototypes */
79 static d_open_t tws_open;
80 static d_close_t tws_close;
81 static d_read_t tws_read;
82 static d_write_t tws_write;
83 extern d_ioctl_t tws_ioctl;
85 static int tws_init(struct tws_softc *sc);
86 static void tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs,
89 static int tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size);
90 static int tws_init_aen_q(struct tws_softc *sc);
91 static int tws_init_trace_q(struct tws_softc *sc);
92 static int tws_setup_irq(struct tws_softc *sc);
93 int tws_setup_intr(struct tws_softc *sc, int irqs);
94 int tws_teardown_intr(struct tws_softc *sc);
97 /* Character device entry points */
99 static struct cdevsw tws_cdevsw = {
100 .d_version = D_VERSION,
102 .d_close = tws_close,
104 .d_write = tws_write,
105 .d_ioctl = tws_ioctl,
110 * In the cdevsw routines, we find our softc by using the si_drv1 member
111 * of struct cdev. We set this variable to point to our softc in our
112 * attach routine when we create the /dev entry.
116 tws_open(struct cdev *dev, int oflags, int devtype, d_thread_t *td)
118 struct tws_softc *sc = dev->si_drv1;
121 TWS_TRACE_DEBUG(sc, "entry", dev, oflags);
126 tws_close(struct cdev *dev, int fflag, int devtype, d_thread_t *td)
128 struct tws_softc *sc = dev->si_drv1;
131 TWS_TRACE_DEBUG(sc, "entry", dev, fflag);
136 tws_read(struct cdev *dev, struct uio *uio, int ioflag)
138 struct tws_softc *sc = dev->si_drv1;
141 TWS_TRACE_DEBUG(sc, "entry", dev, ioflag);
146 tws_write(struct cdev *dev, struct uio *uio, int ioflag)
148 struct tws_softc *sc = dev->si_drv1;
151 TWS_TRACE_DEBUG(sc, "entry", dev, ioflag);
155 /* PCI Support Functions */
158 * Compare the device ID of this device against the IDs that this driver
159 * supports. If there is a match, set the description and return success.
162 tws_probe(device_t dev)
164 static u_int8_t first_ctlr = 1;
166 if ((pci_get_vendor(dev) == TWS_VENDOR_ID) &&
167 (pci_get_device(dev) == TWS_DEVICE_ID)) {
168 device_set_desc(dev, "LSI 3ware SAS/SATA Storage Controller");
170 printf("LSI 3ware device driver for SAS/SATA storage "
171 "controllers, version: %s\n", TWS_DRIVER_VERSION_STRING);
175 return(BUS_PROBE_DEFAULT);
180 /* Attach function is only called if the probe is successful. */
183 tws_attach(device_t dev)
185 struct tws_softc *sc = device_get_softc(dev);
190 /* Look up our softc and initialize its fields. */
192 sc->device_id = pci_get_device(dev);
193 sc->subvendor_id = pci_get_subvendor(dev);
194 sc->subdevice_id = pci_get_subdevice(dev);
196 /* Intialize mutexes */
197 mtx_init( &sc->q_lock, "tws_q_lock", NULL, MTX_DEF);
198 mtx_init( &sc->sim_lock, "tws_sim_lock", NULL, MTX_DEF);
199 mtx_init( &sc->gen_lock, "tws_gen_lock", NULL, MTX_DEF);
200 mtx_init( &sc->io_lock, "tws_io_lock", NULL, MTX_DEF);
202 if ( tws_init_trace_q(sc) == FAILURE )
203 printf("trace init failure\n");
204 /* send init event */
205 mtx_lock(&sc->gen_lock);
206 tws_send_event(sc, TWS_INIT_START);
207 mtx_unlock(&sc->gen_lock);
210 #if _BYTE_ORDER == _BIG_ENDIAN
211 TWS_TRACE(sc, "BIG endian", 0, 0);
213 /* sysctl context setup */
214 sysctl_ctx_init(&sc->tws_clist);
215 sc->tws_oidp = SYSCTL_ADD_NODE(&sc->tws_clist,
216 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
217 device_get_nameunit(dev),
219 if ( sc->tws_oidp == NULL ) {
220 tws_log(sc, SYSCTL_TREE_NODE_ADD);
223 SYSCTL_ADD_STRING(&sc->tws_clist, SYSCTL_CHILDREN(sc->tws_oidp),
224 OID_AUTO, "driver_version", CTLFLAG_RD,
225 TWS_DRIVER_VERSION_STRING, 0, "TWS driver version");
227 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
228 if ( (cmd & PCIM_CMD_PORTEN) == 0) {
229 tws_log(sc, PCI_COMMAND_READ);
232 /* Force the busmaster enable bit on. */
233 cmd |= PCIM_CMD_BUSMASTEREN;
234 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
236 bar = pci_read_config(dev, TWS_PCI_BAR0, 4);
237 TWS_TRACE_DEBUG(sc, "bar0 ", bar, 0);
238 bar = pci_read_config(dev, TWS_PCI_BAR1, 4);
239 bar = bar & ~TWS_BIT2;
240 TWS_TRACE_DEBUG(sc, "bar1 ", bar, 0);
242 /* MFA base address is BAR2 register used for
243 * push mode. Firmware will evatualy move to
244 * pull mode during witch this needs to change
246 #ifndef TWS_PULL_MODE_ENABLE
247 sc->mfa_base = (u_int64_t)pci_read_config(dev, TWS_PCI_BAR2, 4);
248 sc->mfa_base = sc->mfa_base & ~TWS_BIT2;
249 TWS_TRACE_DEBUG(sc, "bar2 ", sc->mfa_base, 0);
252 /* allocate MMIO register space */
253 sc->reg_res_id = TWS_PCI_BAR1; /* BAR1 offset */
254 if ((sc->reg_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
255 &(sc->reg_res_id), 0, ~0, 1, RF_ACTIVE))
257 tws_log(sc, ALLOC_MEMORY_RES);
260 sc->bus_tag = rman_get_bustag(sc->reg_res);
261 sc->bus_handle = rman_get_bushandle(sc->reg_res);
263 #ifndef TWS_PULL_MODE_ENABLE
264 /* Allocate bus space for inbound mfa */
265 sc->mfa_res_id = TWS_PCI_BAR2; /* BAR2 offset */
266 if ((sc->mfa_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
267 &(sc->mfa_res_id), 0, ~0, 0x100000, RF_ACTIVE))
269 tws_log(sc, ALLOC_MEMORY_RES);
272 sc->bus_mfa_tag = rman_get_bustag(sc->mfa_res);
273 sc->bus_mfa_handle = rman_get_bushandle(sc->mfa_res);
276 /* Allocate and register our interrupt. */
277 sc->intr_type = TWS_INTx; /* default */
279 if ( tws_enable_msi )
280 sc->intr_type = TWS_MSI;
281 if ( tws_setup_irq(sc) == FAILURE ) {
282 tws_log(sc, ALLOC_MEMORY_RES);
287 * Create a /dev entry for this device. The kernel will assign us
288 * a major number automatically. We use the unit number of this
289 * device as the minor number and name the character device
292 sc->tws_cdev = make_dev(&tws_cdevsw, device_get_unit(dev),
293 UID_ROOT, GID_OPERATOR, S_IRUSR | S_IWUSR, "tws%u",
294 device_get_unit(dev));
295 sc->tws_cdev->si_drv1 = sc;
297 if ( tws_init(sc) == FAILURE ) {
298 tws_log(sc, TWS_INIT_FAILURE);
301 if ( tws_init_ctlr(sc) == FAILURE ) {
302 tws_log(sc, TWS_CTLR_INIT_FAILURE);
305 if ((error = tws_cam_attach(sc))) {
306 tws_log(sc, TWS_CAM_ATTACH);
309 /* send init complete event */
310 mtx_lock(&sc->gen_lock);
311 tws_send_event(sc, TWS_INIT_COMPLETE);
312 mtx_unlock(&sc->gen_lock);
314 TWS_TRACE_DEBUG(sc, "attached successfully", 0, sc->device_id);
318 tws_teardown_intr(sc);
319 destroy_dev(sc->tws_cdev);
321 for(i=0;i<sc->irqs;i++) {
322 if ( sc->irq_res[i] ){
323 if (bus_release_resource(sc->tws_dev,
324 SYS_RES_IRQ, sc->irq_res_id[i], sc->irq_res[i]))
325 TWS_TRACE(sc, "bus irq res", 0, 0);
328 #ifndef TWS_PULL_MODE_ENABLE
332 if (bus_release_resource(sc->tws_dev,
333 SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res))
334 TWS_TRACE(sc, "bus release ", 0, sc->mfa_res_id);
337 if (bus_release_resource(sc->tws_dev,
338 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res))
339 TWS_TRACE(sc, "bus release2 ", 0, sc->reg_res_id);
342 mtx_destroy(&sc->q_lock);
343 mtx_destroy(&sc->sim_lock);
344 mtx_destroy(&sc->gen_lock);
345 mtx_destroy(&sc->io_lock);
346 sysctl_ctx_free(&sc->tws_clist);
353 tws_detach(device_t dev)
355 struct tws_softc *sc = device_get_softc(dev);
359 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
361 mtx_lock(&sc->gen_lock);
362 tws_send_event(sc, TWS_UNINIT_START);
363 mtx_unlock(&sc->gen_lock);
365 /* needs to disable interrupt before detaching from cam */
366 tws_turn_off_interrupts(sc);
367 /* clear door bell */
368 tws_write_reg(sc, TWS_I2O0_HOBDBC, ~0, 4);
369 reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);
370 TWS_TRACE_DEBUG(sc, "turn-off-intr", reg, 0);
371 sc->obfl_q_overrun = false;
372 tws_init_connect(sc, 1);
374 /* Teardown the state in our softc created in our attach routine. */
375 /* Disconnect the interrupt handler. */
376 tws_teardown_intr(sc);
378 /* Release irq resource */
379 for(i=0;i<sc->irqs;i++) {
380 if ( sc->irq_res[i] ){
381 if (bus_release_resource(sc->tws_dev,
382 SYS_RES_IRQ, sc->irq_res_id[i], sc->irq_res[i]))
383 TWS_TRACE(sc, "bus release irq resource",
384 i, sc->irq_res_id[i]);
387 if ( sc->intr_type == TWS_MSI ) {
388 pci_release_msi(sc->tws_dev);
393 /* Release memory resource */
395 if (bus_release_resource(sc->tws_dev,
396 SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res))
397 TWS_TRACE(sc, "bus release mem resource", 0, sc->mfa_res_id);
400 if (bus_release_resource(sc->tws_dev,
401 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res))
402 TWS_TRACE(sc, "bus release mem resource", 0, sc->reg_res_id);
405 free(sc->reqs, M_TWS);
406 free(sc->sense_bufs, M_TWS);
407 free(sc->scan_ccb, M_TWS);
408 free(sc->aen_q.q, M_TWS);
409 free(sc->trace_q.q, M_TWS);
410 mtx_destroy(&sc->q_lock);
411 mtx_destroy(&sc->sim_lock);
412 mtx_destroy(&sc->gen_lock);
413 mtx_destroy(&sc->io_lock);
414 destroy_dev(sc->tws_cdev);
415 sysctl_ctx_free(&sc->tws_clist);
420 tws_setup_intr(struct tws_softc *sc, int irqs)
424 for(i=0;i<irqs;i++) {
425 if (!(sc->intr_handle[i])) {
426 if ((error = bus_setup_intr(sc->tws_dev, sc->irq_res[i],
427 INTR_TYPE_CAM | INTR_MPSAFE,
428 #if (__FreeBSD_version >= 700000)
431 tws_intr, sc, &sc->intr_handle[i]))) {
432 tws_log(sc, SETUP_INTR_RES);
443 tws_teardown_intr(struct tws_softc *sc)
447 for(i=0;i<sc->irqs;i++) {
448 if (sc->intr_handle[i]) {
449 error = bus_teardown_intr(sc->tws_dev,
450 sc->irq_res[i], sc->intr_handle[i]);
451 sc->intr_handle[i] = NULL;
459 tws_setup_irq(struct tws_softc *sc)
464 cmd = pci_read_config(sc->tws_dev, PCIR_COMMAND, 2);
465 switch(sc->intr_type) {
468 pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
470 sc->irq_res_id[0] = 0;
471 sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
472 &sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
473 if ( ! sc->irq_res[0] )
475 if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
477 device_printf(sc->tws_dev, "Using legacy INTx\n");
481 pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
483 sc->irq_res_id[0] = 1;
485 if (pci_alloc_msi(sc->tws_dev, &messages) != 0 ) {
486 TWS_TRACE(sc, "pci alloc msi fail", 0, messages);
489 sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
490 &sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
492 if ( !sc->irq_res[0] )
494 if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
496 device_printf(sc->tws_dev, "Using MSI\n");
505 tws_init(struct tws_softc *sc)
508 u_int32_t max_sg_elements;
509 u_int32_t dma_mem_size;
514 if ( tws_queue_depth > TWS_MAX_REQS )
515 tws_queue_depth = TWS_MAX_REQS;
516 if (tws_queue_depth < TWS_RESERVED_REQS+1)
517 tws_queue_depth = TWS_RESERVED_REQS+1;
518 sc->is64bit = (sizeof(bus_addr_t) == 8) ? true : false;
519 max_sg_elements = (sc->is64bit && !tws_use_32bit_sgls) ?
520 TWS_MAX_64BIT_SG_ELEMENTS :
521 TWS_MAX_32BIT_SG_ELEMENTS;
522 dma_mem_size = (sizeof(struct tws_command_packet) * tws_queue_depth) +
524 if ( bus_dma_tag_create(NULL, /* parent */
525 TWS_ALIGNMENT, /* alignment */
527 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
528 BUS_SPACE_MAXADDR, /* highaddr */
529 NULL, NULL, /* filter, filterarg */
530 BUS_SPACE_MAXSIZE, /* maxsize */
531 max_sg_elements, /* numsegs */
532 BUS_SPACE_MAXSIZE, /* maxsegsize */
534 NULL, NULL, /* lockfunc, lockfuncarg */
535 &sc->parent_tag /* tag */
537 TWS_TRACE_DEBUG(sc, "DMA parent tag Create fail", max_sg_elements,
541 /* In bound message frame requires 16byte alignment.
542 * Outbound MF's can live with 4byte alignment - for now just
545 if ( bus_dma_tag_create(sc->parent_tag, /* parent */
546 TWS_IN_MF_ALIGNMENT, /* alignment */
548 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
549 BUS_SPACE_MAXADDR, /* highaddr */
550 NULL, NULL, /* filter, filterarg */
551 dma_mem_size, /* maxsize */
553 BUS_SPACE_MAXSIZE, /* maxsegsize */
555 NULL, NULL, /* lockfunc, lockfuncarg */
556 &sc->cmd_tag /* tag */
558 TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit);
562 if (bus_dmamem_alloc(sc->cmd_tag, &sc->dma_mem,
563 BUS_DMA_NOWAIT, &sc->cmd_map)) {
564 TWS_TRACE_DEBUG(sc, "DMA mem alloc fail", max_sg_elements, sc->is64bit);
568 /* if bus_dmamem_alloc succeeds then bus_dmamap_load will succeed */
570 error = bus_dmamap_load(sc->cmd_tag, sc->cmd_map, sc->dma_mem,
571 dma_mem_size, tws_dmamap_cmds_load_cbfn,
572 &sc->dma_mem_phys, 0);
575 * Create a dma tag for data buffers; size will be the maximum
576 * possible I/O size (128kB).
578 if (bus_dma_tag_create(sc->parent_tag, /* parent */
579 TWS_ALIGNMENT, /* alignment */
581 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
582 BUS_SPACE_MAXADDR, /* highaddr */
583 NULL, NULL, /* filter, filterarg */
584 TWS_MAX_IO_SIZE, /* maxsize */
585 max_sg_elements, /* nsegments */
586 TWS_MAX_IO_SIZE, /* maxsegsize */
587 BUS_DMA_ALLOCNOW, /* flags */
588 busdma_lock_mutex, /* lockfunc */
589 &sc->io_lock, /* lockfuncarg */
590 &sc->data_tag /* tag */)) {
591 TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit);
595 sc->reqs = malloc(sizeof(struct tws_request) * tws_queue_depth, M_TWS,
597 if ( sc->reqs == NULL ) {
598 TWS_TRACE_DEBUG(sc, "malloc failed", 0, sc->is64bit);
601 sc->sense_bufs = malloc(sizeof(struct tws_sense) * tws_queue_depth, M_TWS,
603 if ( sc->sense_bufs == NULL ) {
604 TWS_TRACE_DEBUG(sc, "sense malloc failed", 0, sc->is64bit);
607 sc->scan_ccb = malloc(sizeof(union ccb), M_TWS, M_WAITOK | M_ZERO);
608 if ( sc->scan_ccb == NULL ) {
609 TWS_TRACE_DEBUG(sc, "ccb malloc failed", 0, sc->is64bit);
613 if ( !tws_ctlr_ready(sc) )
614 if( !tws_ctlr_reset(sc) )
617 bzero(&sc->stats, sizeof(struct tws_stats));
619 tws_turn_off_interrupts(sc);
622 * enable pull mode by setting bit1 .
623 * setting bit0 to 1 will enable interrupt coalesing
627 #ifdef TWS_PULL_MODE_ENABLE
629 reg = tws_read_reg(sc, TWS_I2O0_CTL, 4);
630 TWS_TRACE_DEBUG(sc, "i20 ctl", reg, TWS_I2O0_CTL);
631 tws_write_reg(sc, TWS_I2O0_CTL, reg | TWS_BIT1, 4);
635 TWS_TRACE_DEBUG(sc, "dma_mem_phys", sc->dma_mem_phys, TWS_I2O0_CTL);
636 if ( tws_init_reqs(sc, dma_mem_size) == FAILURE )
638 if ( tws_init_aen_q(sc) == FAILURE )
646 tws_init_aen_q(struct tws_softc *sc)
651 sc->aen_q.overflow=0;
652 sc->aen_q.q = malloc(sizeof(struct tws_event_packet)*sc->aen_q.depth,
653 M_TWS, M_WAITOK | M_ZERO);
660 tws_init_trace_q(struct tws_softc *sc)
664 sc->trace_q.depth=256;
665 sc->trace_q.overflow=0;
666 sc->trace_q.q = malloc(sizeof(struct tws_trace_rec)*sc->trace_q.depth,
667 M_TWS, M_WAITOK | M_ZERO);
668 if ( ! sc->trace_q.q )
674 tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size)
677 struct tws_command_packet *cmd_buf;
678 cmd_buf = (struct tws_command_packet *)sc->dma_mem;
681 bzero(cmd_buf, dma_mem_size);
682 TWS_TRACE_DEBUG(sc, "phy cmd", sc->dma_mem_phys, 0);
683 mtx_lock(&sc->q_lock);
684 for ( i=0; i< tws_queue_depth; i++)
686 if (bus_dmamap_create(sc->data_tag, 0, &sc->reqs[i].dma_map)) {
687 /* log a ENOMEM failure msg here */
690 sc->reqs[i].cmd_pkt = &cmd_buf[i];
692 sc->sense_bufs[i].hdr = &cmd_buf[i].hdr ;
693 sc->sense_bufs[i].hdr_pkt_phy = sc->dma_mem_phys +
694 (i * sizeof(struct tws_command_packet));
696 sc->reqs[i].cmd_pkt_phy = sc->dma_mem_phys +
697 sizeof(struct tws_command_header) +
698 (i * sizeof(struct tws_command_packet));
699 sc->reqs[i].request_id = i;
702 sc->reqs[i].cmd_pkt->hdr.header_desc.size_header = 128;
704 sc->reqs[i].state = TWS_REQ_STATE_FREE;
705 if ( i >= TWS_RESERVED_REQS )
706 tws_q_insert_tail(sc, &sc->reqs[i], TWS_FREE_Q);
708 mtx_unlock(&sc->q_lock);
713 tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs,
717 /* printf("command load done \n"); */
719 *((bus_addr_t *)arg) = segs[0].ds_addr;
723 tws_send_event(struct tws_softc *sc, u_int8_t event)
725 mtx_assert(&sc->gen_lock, MA_OWNED);
726 TWS_TRACE_DEBUG(sc, "received event ", 0, event);
730 sc->tws_state = TWS_INIT;
733 case TWS_INIT_COMPLETE:
734 if (sc->tws_state != TWS_INIT) {
735 device_printf(sc->tws_dev, "invalid state transition %d => TWS_ONLINE\n", sc->tws_state);
737 sc->tws_state = TWS_ONLINE;
741 case TWS_RESET_START:
742 /* We can transition to reset state from any state except reset*/
743 if (sc->tws_state != TWS_RESET) {
744 sc->tws_prev_state = sc->tws_state;
745 sc->tws_state = TWS_RESET;
749 case TWS_RESET_COMPLETE:
750 if (sc->tws_state != TWS_RESET) {
751 device_printf(sc->tws_dev, "invalid state transition %d => %d (previous state)\n", sc->tws_state, sc->tws_prev_state);
753 sc->tws_state = sc->tws_prev_state;
757 case TWS_SCAN_FAILURE:
758 if (sc->tws_state != TWS_ONLINE) {
759 device_printf(sc->tws_dev, "invalid state transition %d => TWS_OFFLINE\n", sc->tws_state);
761 sc->tws_state = TWS_OFFLINE;
765 case TWS_UNINIT_START:
766 if ((sc->tws_state != TWS_ONLINE) && (sc->tws_state != TWS_OFFLINE)) {
767 device_printf(sc->tws_dev, "invalid state transition %d => TWS_UNINIT\n", sc->tws_state);
769 sc->tws_state = TWS_UNINIT;
777 tws_get_state(struct tws_softc *sc)
780 return((u_int8_t)sc->tws_state);
784 /* Called during system shutdown after sync. */
787 tws_shutdown(device_t dev)
790 struct tws_softc *sc = device_get_softc(dev);
792 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
794 tws_turn_off_interrupts(sc);
795 tws_init_connect(sc, 1);
801 * Device suspend routine.
804 tws_suspend(device_t dev)
806 struct tws_softc *sc = device_get_softc(dev);
809 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
814 * Device resume routine.
817 tws_resume(device_t dev)
820 struct tws_softc *sc = device_get_softc(dev);
823 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
829 tws_get_request(struct tws_softc *sc, u_int16_t type)
831 struct mtx *my_mutex = ((type == TWS_REQ_TYPE_SCSI_IO) ? &sc->q_lock : &sc->gen_lock);
832 struct tws_request *r = NULL;
836 if (type == TWS_REQ_TYPE_SCSI_IO) {
837 r = tws_q_remove_head(sc, TWS_FREE_Q);
839 if ( sc->reqs[type].state == TWS_REQ_STATE_FREE ) {
845 bzero(&r->cmd_pkt->cmd, sizeof(struct tws_command_apache));
849 r->flags = TWS_DIR_UNKNOWN;
850 r->error_code = TWS_REQ_RET_INVALID;
853 r->thandle.callout = NULL;
854 r->next = r->prev = NULL;
856 r->state = ((type == TWS_REQ_TYPE_SCSI_IO) ? TWS_REQ_STATE_TRAN : TWS_REQ_STATE_BUSY);
859 mtx_unlock(my_mutex);
865 tws_release_request(struct tws_request *req)
868 struct tws_softc *sc = req->sc;
870 TWS_TRACE_DEBUG(sc, "entry", sc, 0);
871 mtx_lock(&sc->q_lock);
872 tws_q_insert_tail(sc, req, TWS_FREE_Q);
873 mtx_unlock(&sc->q_lock);
876 static device_method_t tws_methods[] = {
877 /* Device interface */
878 DEVMETHOD(device_probe, tws_probe),
879 DEVMETHOD(device_attach, tws_attach),
880 DEVMETHOD(device_detach, tws_detach),
881 DEVMETHOD(device_shutdown, tws_shutdown),
882 DEVMETHOD(device_suspend, tws_suspend),
883 DEVMETHOD(device_resume, tws_resume),
885 DEVMETHOD(bus_print_child, bus_generic_print_child),
886 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
890 static driver_t tws_driver = {
893 sizeof(struct tws_softc)
897 static devclass_t tws_devclass;
899 /* DEFINE_CLASS_0(tws, tws_driver, tws_methods, sizeof(struct tws_softc)); */
900 DRIVER_MODULE(tws, pci, tws_driver, tws_devclass, 0, 0);
901 MODULE_DEPEND(tws, cam, 1, 1, 1);
902 MODULE_DEPEND(tws, pci, 1, 1, 1);
904 TUNABLE_INT("hw.tws.queue_depth", &tws_queue_depth);
905 TUNABLE_INT("hw.tws.enable_msi", &tws_enable_msi);