5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This file contains the driver for the ATMEGA series USB OTG Controller. This
31 * driver currently only supports the DCI mode of the USB hardware.
35 * NOTE: When the chip detects BUS-reset it will also reset the
36 * endpoints, Function-address and more.
39 #include <sys/stdint.h>
40 #include <sys/stddef.h>
41 #include <sys/param.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/module.h>
49 #include <sys/mutex.h>
50 #include <sys/condvar.h>
51 #include <sys/sysctl.h>
53 #include <sys/unistd.h>
54 #include <sys/callout.h>
55 #include <sys/malloc.h>
58 #include <dev/usb/usb.h>
59 #include <dev/usb/usbdi.h>
61 #define USB_DEBUG_VAR atmegadci_debug
63 #include <dev/usb/usb_core.h>
64 #include <dev/usb/usb_debug.h>
65 #include <dev/usb/usb_busdma.h>
66 #include <dev/usb/usb_process.h>
67 #include <dev/usb/usb_transfer.h>
68 #include <dev/usb/usb_device.h>
69 #include <dev/usb/usb_hub.h>
70 #include <dev/usb/usb_util.h>
72 #include <dev/usb/usb_controller.h>
73 #include <dev/usb/usb_bus.h>
74 #include <dev/usb/controller/atmegadci.h>
76 #define ATMEGA_BUS2SC(bus) \
77 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \
78 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus))))
80 #define ATMEGA_PC2SC(pc) \
81 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
84 static int atmegadci_debug = 0;
86 SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI");
87 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RW,
88 &atmegadci_debug, 0, "ATMEGA DCI debug level");
91 #define ATMEGA_INTR_ENDPT 1
95 struct usb_bus_methods atmegadci_bus_methods;
96 struct usb_pipe_methods atmegadci_device_non_isoc_methods;
97 struct usb_pipe_methods atmegadci_device_isoc_fs_methods;
99 static atmegadci_cmd_t atmegadci_setup_rx;
100 static atmegadci_cmd_t atmegadci_data_rx;
101 static atmegadci_cmd_t atmegadci_data_tx;
102 static atmegadci_cmd_t atmegadci_data_tx_sync;
103 static void atmegadci_device_done(struct usb_xfer *, usb_error_t);
104 static void atmegadci_do_poll(struct usb_bus *);
105 static void atmegadci_standard_done(struct usb_xfer *);
106 static void atmegadci_root_intr(struct atmegadci_softc *sc);
109 * Here is a list of what the chip supports:
111 static const struct usb_hw_ep_profile
112 atmegadci_ep_profile[2] = {
115 .max_in_frame_size = 64,
116 .max_out_frame_size = 64,
118 .support_control = 1,
121 .max_in_frame_size = 64,
122 .max_out_frame_size = 64,
125 .support_interrupt = 1,
126 .support_isochronous = 1,
133 atmegadci_get_hw_ep_profile(struct usb_device *udev,
134 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
137 *ppf = atmegadci_ep_profile;
138 else if (ep_addr < ATMEGA_EP_MAX)
139 *ppf = atmegadci_ep_profile + 1;
145 atmegadci_clocks_on(struct atmegadci_softc *sc)
147 if (sc->sc_flags.clocks_off &&
148 sc->sc_flags.port_powered) {
153 (sc->sc_clocks_on) (&sc->sc_bus);
155 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
157 ATMEGA_USBCON_OTGPADE |
158 ATMEGA_USBCON_VBUSTE);
160 sc->sc_flags.clocks_off = 0;
162 /* enable transceiver ? */
167 atmegadci_clocks_off(struct atmegadci_softc *sc)
169 if (!sc->sc_flags.clocks_off) {
173 /* disable Transceiver ? */
175 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
177 ATMEGA_USBCON_OTGPADE |
178 ATMEGA_USBCON_FRZCLK |
179 ATMEGA_USBCON_VBUSTE);
181 /* turn clocks off */
182 (sc->sc_clocks_off) (&sc->sc_bus);
184 sc->sc_flags.clocks_off = 1;
189 atmegadci_pull_up(struct atmegadci_softc *sc)
191 /* pullup D+, if possible */
193 if (!sc->sc_flags.d_pulled_up &&
194 sc->sc_flags.port_powered) {
195 sc->sc_flags.d_pulled_up = 1;
196 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0);
201 atmegadci_pull_down(struct atmegadci_softc *sc)
203 /* pulldown D+, if possible */
205 if (sc->sc_flags.d_pulled_up) {
206 sc->sc_flags.d_pulled_up = 0;
207 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
212 atmegadci_wakeup_peer(struct atmegadci_softc *sc)
216 if (!sc->sc_flags.status_suspend) {
220 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON);
221 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP);
223 /* wait 8 milliseconds */
224 /* Wait for reset to complete. */
225 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
227 /* hardware should have cleared RMWKUP bit */
231 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr)
233 DPRINTFN(5, "addr=%d\n", addr);
235 addr |= ATMEGA_UDADDR_ADDEN;
237 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr);
241 atmegadci_setup_rx(struct atmegadci_td *td)
243 struct atmegadci_softc *sc;
244 struct usb_device_request req;
248 /* get pointer to softc */
249 sc = ATMEGA_PC2SC(td->pc);
251 /* select endpoint number */
252 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
254 /* check endpoint status */
255 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
257 DPRINTFN(5, "UEINTX=0x%02x\n", temp);
259 if (!(temp & ATMEGA_UEINTX_RXSTPI)) {
262 /* clear did stall */
264 /* get the packet byte count */
266 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
267 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
269 /* mask away undefined bits */
272 /* verify data length */
273 if (count != td->remainder) {
274 DPRINTFN(0, "Invalid SETUP packet "
275 "length, %d bytes\n", count);
278 if (count != sizeof(req)) {
279 DPRINTFN(0, "Unsupported SETUP packet "
280 "length, %d bytes\n", count);
284 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
285 (void *)&req, sizeof(req));
287 /* copy data into real buffer */
288 usbd_copy_in(td->pc, 0, &req, sizeof(req));
290 td->offset = sizeof(req);
293 /* sneak peek the set address */
294 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
295 (req.bRequest == UR_SET_ADDRESS)) {
296 sc->sc_dv_addr = req.wValue[0] & 0x7F;
297 /* must write address before ZLP */
298 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr);
300 sc->sc_dv_addr = 0xFF;
303 /* Clear SETUP packet interrupt and all other previous interrupts */
304 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0);
305 return (0); /* complete */
308 /* abort any ongoing transfer */
309 if (!td->did_stall) {
310 DPRINTFN(5, "stalling\n");
311 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
313 ATMEGA_UECONX_STALLRQ);
316 if (temp & ATMEGA_UEINTX_RXSTPI) {
317 /* clear SETUP packet interrupt */
318 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
320 /* we only want to know if there is a SETUP packet */
321 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE);
322 return (1); /* not complete */
326 atmegadci_data_rx(struct atmegadci_td *td)
328 struct atmegadci_softc *sc;
329 struct usb_page_search buf_res;
335 to = 3; /* don't loop forever! */
338 /* get pointer to softc */
339 sc = ATMEGA_PC2SC(td->pc);
341 /* select endpoint number */
342 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
345 /* check if any of the FIFO banks have data */
346 /* check endpoint status */
347 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
349 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
351 if (temp & ATMEGA_UEINTX_RXSTPI) {
352 if (td->remainder == 0) {
354 * We are actually complete and have
355 * received the next SETUP
357 DPRINTFN(5, "faking complete\n");
358 return (0); /* complete */
361 * USB Host Aborted the transfer.
364 return (0); /* complete */
367 if (!(temp & (ATMEGA_UEINTX_FIFOCON |
368 ATMEGA_UEINTX_RXOUTI))) {
372 /* get the packet byte count */
374 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
375 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
377 /* mask away undefined bits */
380 /* verify the packet byte count */
381 if (count != td->max_packet_size) {
382 if (count < td->max_packet_size) {
383 /* we have a short packet */
387 /* invalid USB packet */
389 return (0); /* we are complete */
392 /* verify the packet byte count */
393 if (count > td->remainder) {
394 /* invalid USB packet */
396 return (0); /* we are complete */
399 usbd_get_page(td->pc, td->offset, &buf_res);
401 /* get correct length */
402 if (buf_res.length > count) {
403 buf_res.length = count;
406 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
407 buf_res.buffer, buf_res.length);
409 /* update counters */
410 count -= buf_res.length;
411 td->offset += buf_res.length;
412 td->remainder -= buf_res.length;
415 /* clear OUT packet interrupt */
416 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF);
418 /* release FIFO bank */
419 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF);
421 /* check if we are complete */
422 if ((td->remainder == 0) || got_short) {
424 /* we are complete */
427 /* else need to receive a zero length packet */
433 /* we only want to know if there is a SETUP packet or OUT packet */
434 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
435 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE);
436 return (1); /* not complete */
440 atmegadci_data_tx(struct atmegadci_td *td)
442 struct atmegadci_softc *sc;
443 struct usb_page_search buf_res;
448 to = 3; /* don't loop forever! */
450 /* get pointer to softc */
451 sc = ATMEGA_PC2SC(td->pc);
453 /* select endpoint number */
454 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
458 /* check endpoint status */
459 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
461 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
463 if (temp & ATMEGA_UEINTX_RXSTPI) {
465 * The current transfer was aborted
469 return (0); /* complete */
472 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
474 /* cannot write any data - a bank is busy */
478 count = td->max_packet_size;
479 if (td->remainder < count) {
480 /* we have a short packet */
482 count = td->remainder;
486 usbd_get_page(td->pc, td->offset, &buf_res);
488 /* get correct length */
489 if (buf_res.length > count) {
490 buf_res.length = count;
493 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX,
494 buf_res.buffer, buf_res.length);
496 /* update counters */
497 count -= buf_res.length;
498 td->offset += buf_res.length;
499 td->remainder -= buf_res.length;
502 /* clear IN packet interrupt */
503 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI);
505 /* allocate FIFO bank */
506 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON);
508 /* check remainder */
509 if (td->remainder == 0) {
511 return (0); /* complete */
513 /* else we need to transmit a short packet */
519 /* we only want to know if there is a SETUP packet or free IN packet */
520 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
521 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
522 return (1); /* not complete */
526 atmegadci_data_tx_sync(struct atmegadci_td *td)
528 struct atmegadci_softc *sc;
531 /* get pointer to softc */
532 sc = ATMEGA_PC2SC(td->pc);
534 /* select endpoint number */
535 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
537 /* check endpoint status */
538 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
540 DPRINTFN(5, "temp=0x%02x\n", temp);
542 if (temp & ATMEGA_UEINTX_RXSTPI) {
543 DPRINTFN(5, "faking complete\n");
545 return (0); /* complete */
548 * The control endpoint has only got one bank, so if that bank
549 * is free the packet has been transferred!
551 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
553 /* cannot write any data - a bank is busy */
556 if (sc->sc_dv_addr != 0xFF) {
557 /* set new address */
558 atmegadci_set_address(sc, sc->sc_dv_addr);
560 return (0); /* complete */
563 /* we only want to know if there is a SETUP packet or free IN packet */
564 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
565 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
566 return (1); /* not complete */
570 atmegadci_xfer_do_fifo(struct usb_xfer *xfer)
572 struct atmegadci_td *td;
576 td = xfer->td_transfer_cache;
578 if ((td->func) (td)) {
579 /* operation in progress */
582 if (((void *)td) == xfer->td_transfer_last) {
587 } else if (td->remainder > 0) {
589 * We had a short transfer. If there is no alternate
590 * next, stop processing !
597 * Fetch the next transfer descriptor and transfer
598 * some flags to the next transfer descriptor
601 xfer->td_transfer_cache = td;
603 return (1); /* not complete */
606 /* compute all actual lengths */
608 atmegadci_standard_done(xfer);
609 return (0); /* complete */
613 atmegadci_interrupt_poll(struct atmegadci_softc *sc)
615 struct usb_xfer *xfer;
618 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
619 if (!atmegadci_xfer_do_fifo(xfer)) {
620 /* queue has been modified */
627 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on)
629 DPRINTFN(5, "vbus = %u\n", is_on);
632 if (!sc->sc_flags.status_vbus) {
633 sc->sc_flags.status_vbus = 1;
635 /* complete root HUB interrupt endpoint */
637 atmegadci_root_intr(sc);
640 if (sc->sc_flags.status_vbus) {
641 sc->sc_flags.status_vbus = 0;
642 sc->sc_flags.status_bus_reset = 0;
643 sc->sc_flags.status_suspend = 0;
644 sc->sc_flags.change_suspend = 0;
645 sc->sc_flags.change_connect = 1;
647 /* complete root HUB interrupt endpoint */
649 atmegadci_root_intr(sc);
655 atmegadci_interrupt(struct atmegadci_softc *sc)
659 USB_BUS_LOCK(&sc->sc_bus);
661 /* read interrupt status */
662 status = ATMEGA_READ_1(sc, ATMEGA_UDINT);
664 /* clear all set interrupts */
665 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D);
667 DPRINTFN(14, "UDINT=0x%02x\n", status);
669 /* check for any bus state change interrupts */
670 if (status & ATMEGA_UDINT_EORSTI) {
672 DPRINTFN(5, "end of reset\n");
674 /* set correct state */
675 sc->sc_flags.status_bus_reset = 1;
676 sc->sc_flags.status_suspend = 0;
677 sc->sc_flags.change_suspend = 0;
678 sc->sc_flags.change_connect = 1;
680 /* disable resume interrupt */
681 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
683 ATMEGA_UDINT_EORSTE);
685 /* complete root HUB interrupt endpoint */
686 atmegadci_root_intr(sc);
689 * If resume and suspend is set at the same time we interpret
690 * that like RESUME. Resume is set when there is at least 3
691 * milliseconds of inactivity on the USB BUS.
693 if (status & ATMEGA_UDINT_WAKEUPI) {
695 DPRINTFN(5, "resume interrupt\n");
697 if (sc->sc_flags.status_suspend) {
698 /* update status bits */
699 sc->sc_flags.status_suspend = 0;
700 sc->sc_flags.change_suspend = 1;
702 /* disable resume interrupt */
703 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
705 ATMEGA_UDINT_EORSTE);
707 /* complete root HUB interrupt endpoint */
708 atmegadci_root_intr(sc);
710 } else if (status & ATMEGA_UDINT_SUSPI) {
712 DPRINTFN(5, "suspend interrupt\n");
714 if (!sc->sc_flags.status_suspend) {
715 /* update status bits */
716 sc->sc_flags.status_suspend = 1;
717 sc->sc_flags.change_suspend = 1;
719 /* disable suspend interrupt */
720 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
721 ATMEGA_UDINT_WAKEUPE |
722 ATMEGA_UDINT_EORSTE);
724 /* complete root HUB interrupt endpoint */
725 atmegadci_root_intr(sc);
729 status = ATMEGA_READ_1(sc, ATMEGA_USBINT);
731 /* clear all set interrupts */
732 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03);
734 if (status & ATMEGA_USBINT_VBUSTI) {
737 DPRINTFN(5, "USBINT=0x%02x\n", status);
739 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
740 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS);
742 /* check for any endpoint interrupts */
743 status = ATMEGA_READ_1(sc, ATMEGA_UEINT);
744 /* the hardware will clear the UEINT bits automatically */
747 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status);
749 atmegadci_interrupt_poll(sc);
751 USB_BUS_UNLOCK(&sc->sc_bus);
755 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp)
757 struct atmegadci_td *td;
759 /* get current Transfer Descriptor */
763 /* prepare for next TD */
764 temp->td_next = td->obj_next;
766 /* fill out the Transfer Descriptor */
767 td->func = temp->func;
769 td->offset = temp->offset;
770 td->remainder = temp->len;
772 td->did_stall = temp->did_stall;
773 td->short_pkt = temp->short_pkt;
774 td->alt_next = temp->setup_alt_next;
778 atmegadci_setup_standard_chain(struct usb_xfer *xfer)
780 struct atmegadci_std_temp temp;
781 struct atmegadci_softc *sc;
782 struct atmegadci_td *td;
787 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
788 xfer->address, UE_GET_ADDR(xfer->endpointno),
789 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
791 temp.max_frame_size = xfer->max_frame_size;
793 td = xfer->td_start[0];
794 xfer->td_transfer_first = td;
795 xfer->td_transfer_cache = td;
801 temp.td_next = xfer->td_start[0];
803 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
804 temp.did_stall = !xfer->flags_int.control_stall;
806 sc = ATMEGA_BUS2SC(xfer->xroot->bus);
807 ep_no = (xfer->endpointno & UE_ADDR);
809 /* check if we should prepend a setup message */
811 if (xfer->flags_int.control_xfr) {
812 if (xfer->flags_int.control_hdr) {
814 temp.func = &atmegadci_setup_rx;
815 temp.len = xfer->frlengths[0];
816 temp.pc = xfer->frbuffers + 0;
817 temp.short_pkt = temp.len ? 1 : 0;
818 /* check for last frame */
819 if (xfer->nframes == 1) {
820 /* no STATUS stage yet, SETUP is last */
821 if (xfer->flags_int.control_act)
822 temp.setup_alt_next = 0;
825 atmegadci_setup_standard_chain_sub(&temp);
832 if (x != xfer->nframes) {
833 if (xfer->endpointno & UE_DIR_IN) {
834 temp.func = &atmegadci_data_tx;
837 temp.func = &atmegadci_data_rx;
841 /* setup "pc" pointer */
842 temp.pc = xfer->frbuffers + x;
846 while (x != xfer->nframes) {
848 /* DATA0 / DATA1 message */
850 temp.len = xfer->frlengths[x];
854 if (x == xfer->nframes) {
855 if (xfer->flags_int.control_xfr) {
856 if (xfer->flags_int.control_act) {
857 temp.setup_alt_next = 0;
860 temp.setup_alt_next = 0;
865 /* make sure that we send an USB packet */
871 /* regular data transfer */
873 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
876 atmegadci_setup_standard_chain_sub(&temp);
878 if (xfer->flags_int.isochronous_xfr) {
879 temp.offset += temp.len;
881 /* get next Page Cache pointer */
882 temp.pc = xfer->frbuffers + x;
886 if (xfer->flags_int.control_xfr) {
888 /* always setup a valid "pc" pointer for status and sync */
889 temp.pc = xfer->frbuffers + 0;
892 temp.setup_alt_next = 0;
894 /* check if we need to sync */
896 /* we need a SYNC point after TX */
897 temp.func = &atmegadci_data_tx_sync;
898 atmegadci_setup_standard_chain_sub(&temp);
901 /* check if we should append a status stage */
902 if (!xfer->flags_int.control_act) {
905 * Send a DATA1 message and invert the current
906 * endpoint direction.
908 if (xfer->endpointno & UE_DIR_IN) {
909 temp.func = &atmegadci_data_rx;
912 temp.func = &atmegadci_data_tx;
916 atmegadci_setup_standard_chain_sub(&temp);
918 /* we need a SYNC point after TX */
919 temp.func = &atmegadci_data_tx_sync;
920 atmegadci_setup_standard_chain_sub(&temp);
924 /* must have at least one frame! */
926 xfer->td_transfer_last = td;
930 atmegadci_timeout(void *arg)
932 struct usb_xfer *xfer = arg;
934 DPRINTF("xfer=%p\n", xfer);
936 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
938 /* transfer is transferred */
939 atmegadci_device_done(xfer, USB_ERR_TIMEOUT);
943 atmegadci_start_standard_chain(struct usb_xfer *xfer)
947 /* poll one time - will turn on interrupts */
948 if (atmegadci_xfer_do_fifo(xfer)) {
950 /* put transfer on interrupt queue */
951 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
953 /* start timeout, if any */
954 if (xfer->timeout != 0) {
955 usbd_transfer_timeout_ms(xfer,
956 &atmegadci_timeout, xfer->timeout);
962 atmegadci_root_intr(struct atmegadci_softc *sc)
966 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
969 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
971 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
972 sizeof(sc->sc_hub_idata));
976 atmegadci_standard_done_sub(struct usb_xfer *xfer)
978 struct atmegadci_td *td;
984 td = xfer->td_transfer_cache;
989 if (xfer->aframes != xfer->nframes) {
991 * Verify the length and subtract
992 * the remainder from "frlengths[]":
994 if (len > xfer->frlengths[xfer->aframes]) {
997 xfer->frlengths[xfer->aframes] -= len;
1000 /* Check for transfer error */
1002 /* the transfer is finished */
1007 /* Check for short transfer */
1009 if (xfer->flags_int.short_frames_ok) {
1010 /* follow alt next */
1017 /* the transfer is finished */
1025 /* this USB frame is complete */
1031 /* update transfer cache */
1033 xfer->td_transfer_cache = td;
1036 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1040 atmegadci_standard_done(struct usb_xfer *xfer)
1042 usb_error_t err = 0;
1044 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1045 xfer, xfer->endpoint);
1049 xfer->td_transfer_cache = xfer->td_transfer_first;
1051 if (xfer->flags_int.control_xfr) {
1053 if (xfer->flags_int.control_hdr) {
1055 err = atmegadci_standard_done_sub(xfer);
1059 if (xfer->td_transfer_cache == NULL) {
1063 while (xfer->aframes != xfer->nframes) {
1065 err = atmegadci_standard_done_sub(xfer);
1068 if (xfer->td_transfer_cache == NULL) {
1073 if (xfer->flags_int.control_xfr &&
1074 !xfer->flags_int.control_act) {
1076 err = atmegadci_standard_done_sub(xfer);
1079 atmegadci_device_done(xfer, err);
1082 /*------------------------------------------------------------------------*
1083 * atmegadci_device_done
1085 * NOTE: this function can be called more than one time on the
1086 * same USB transfer!
1087 *------------------------------------------------------------------------*/
1089 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error)
1091 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1094 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1096 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
1097 xfer, xfer->endpoint, error);
1099 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1100 ep_no = (xfer->endpointno & UE_ADDR);
1102 /* select endpoint number */
1103 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1105 /* disable endpoint interrupt */
1106 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1108 DPRINTFN(15, "disabled interrupts!\n");
1110 /* dequeue transfer and start next transfer */
1111 usbd_transfer_done(xfer, error);
1115 atmegadci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1116 struct usb_endpoint *ep, uint8_t *did_stall)
1118 struct atmegadci_softc *sc;
1121 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1123 DPRINTFN(5, "endpoint=%p\n", ep);
1126 /* cancel any ongoing transfers */
1127 atmegadci_device_done(xfer, USB_ERR_STALLED);
1129 sc = ATMEGA_BUS2SC(udev->bus);
1130 /* get endpoint number */
1131 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1132 /* select endpoint number */
1133 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1135 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1136 ATMEGA_UECONX_EPEN |
1137 ATMEGA_UECONX_STALLRQ);
1141 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no,
1142 uint8_t ep_type, uint8_t ep_dir)
1146 if (ep_type == UE_CONTROL) {
1147 /* clearing stall is not needed */
1150 /* select endpoint number */
1151 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1153 /* set endpoint reset */
1154 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no));
1156 /* clear endpoint reset */
1157 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1160 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1161 ATMEGA_UECONX_EPEN |
1162 ATMEGA_UECONX_STALLRQ);
1164 /* reset data toggle */
1165 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1166 ATMEGA_UECONX_EPEN |
1167 ATMEGA_UECONX_RSTDT);
1170 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1171 ATMEGA_UECONX_EPEN |
1172 ATMEGA_UECONX_STALLRQC);
1175 if (ep_type == UE_BULK) {
1176 temp = ATMEGA_UECFG0X_EPTYPE2;
1177 } else if (ep_type == UE_INTERRUPT) {
1178 temp = ATMEGA_UECFG0X_EPTYPE3;
1180 temp = ATMEGA_UECFG0X_EPTYPE1;
1182 if (ep_dir & UE_DIR_IN) {
1183 temp |= ATMEGA_UECFG0X_EPDIR;
1185 /* two banks, 64-bytes wMaxPacket */
1186 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp);
1187 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1188 ATMEGA_UECFG1X_ALLOC |
1189 ATMEGA_UECFG1X_EPBK0 | /* one bank */
1190 ATMEGA_UECFG1X_EPSIZE(3));
1192 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1193 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1194 device_printf(sc->sc_bus.bdev,
1195 "Chip rejected configuration\n");
1201 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1203 struct atmegadci_softc *sc;
1204 struct usb_endpoint_descriptor *ed;
1206 DPRINTFN(5, "endpoint=%p\n", ep);
1208 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1211 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1216 sc = ATMEGA_BUS2SC(udev->bus);
1218 /* get endpoint descriptor */
1221 /* reset endpoint */
1222 atmegadci_clear_stall_sub(sc,
1223 (ed->bEndpointAddress & UE_ADDR),
1224 (ed->bmAttributes & UE_XFERTYPE),
1225 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1229 atmegadci_init(struct atmegadci_softc *sc)
1235 /* set up the bus structure */
1236 sc->sc_bus.usbrev = USB_REV_1_1;
1237 sc->sc_bus.methods = &atmegadci_bus_methods;
1239 USB_BUS_LOCK(&sc->sc_bus);
1241 /* make sure USB is enabled */
1242 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1243 ATMEGA_USBCON_USBE |
1244 ATMEGA_USBCON_FRZCLK);
1246 /* enable USB PAD regulator */
1247 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON,
1248 ATMEGA_UHWCON_UVREGE |
1249 ATMEGA_UHWCON_UIMOD);
1251 /* the following register sets up the USB PLL, assuming 16MHz X-tal */
1252 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02);
1254 /* wait for PLL to lock */
1255 for (n = 0; n != 20; n++) {
1256 if (ATMEGA_READ_1(sc, 0x49) & 0x01)
1258 /* wait a little bit for PLL to start */
1259 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1262 /* make sure USB is enabled */
1263 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1264 ATMEGA_USBCON_USBE |
1265 ATMEGA_USBCON_OTGPADE |
1266 ATMEGA_USBCON_VBUSTE);
1268 /* turn on clocks */
1269 (sc->sc_clocks_on) (&sc->sc_bus);
1271 /* make sure device is re-enumerated */
1272 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
1274 /* wait a little for things to stabilise */
1275 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1277 /* enable interrupts */
1278 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
1279 ATMEGA_UDINT_SUSPE |
1280 ATMEGA_UDINT_EORSTE);
1282 /* reset all endpoints */
1283 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1284 (1 << ATMEGA_EP_MAX) - 1);
1287 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1289 /* disable all endpoints */
1290 for (n = 0; n != ATMEGA_EP_MAX; n++) {
1292 /* select endpoint */
1293 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n);
1295 /* disable endpoint interrupt */
1296 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1298 /* disable endpoint */
1299 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0);
1302 /* turn off clocks */
1304 atmegadci_clocks_off(sc);
1306 /* read initial VBUS state */
1308 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
1309 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS);
1311 USB_BUS_UNLOCK(&sc->sc_bus);
1313 /* catch any lost interrupts */
1315 atmegadci_do_poll(&sc->sc_bus);
1317 return (0); /* success */
1321 atmegadci_uninit(struct atmegadci_softc *sc)
1323 USB_BUS_LOCK(&sc->sc_bus);
1325 /* turn on clocks */
1326 (sc->sc_clocks_on) (&sc->sc_bus);
1328 /* disable interrupts */
1329 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0);
1331 /* reset all endpoints */
1332 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1333 (1 << ATMEGA_EP_MAX) - 1);
1336 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1338 sc->sc_flags.port_powered = 0;
1339 sc->sc_flags.status_vbus = 0;
1340 sc->sc_flags.status_bus_reset = 0;
1341 sc->sc_flags.status_suspend = 0;
1342 sc->sc_flags.change_suspend = 0;
1343 sc->sc_flags.change_connect = 1;
1345 atmegadci_pull_down(sc);
1346 atmegadci_clocks_off(sc);
1348 /* disable USB PAD regulator */
1349 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0);
1351 USB_BUS_UNLOCK(&sc->sc_bus);
1355 atmegadci_suspend(struct atmegadci_softc *sc)
1361 atmegadci_resume(struct atmegadci_softc *sc)
1367 atmegadci_do_poll(struct usb_bus *bus)
1369 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
1371 USB_BUS_LOCK(&sc->sc_bus);
1372 atmegadci_interrupt_poll(sc);
1373 USB_BUS_UNLOCK(&sc->sc_bus);
1376 /*------------------------------------------------------------------------*
1377 * at91dci bulk support
1378 * at91dci control support
1379 * at91dci interrupt support
1380 *------------------------------------------------------------------------*/
1382 atmegadci_device_non_isoc_open(struct usb_xfer *xfer)
1388 atmegadci_device_non_isoc_close(struct usb_xfer *xfer)
1390 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1394 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer)
1400 atmegadci_device_non_isoc_start(struct usb_xfer *xfer)
1403 atmegadci_setup_standard_chain(xfer);
1404 atmegadci_start_standard_chain(xfer);
1407 struct usb_pipe_methods atmegadci_device_non_isoc_methods =
1409 .open = atmegadci_device_non_isoc_open,
1410 .close = atmegadci_device_non_isoc_close,
1411 .enter = atmegadci_device_non_isoc_enter,
1412 .start = atmegadci_device_non_isoc_start,
1415 /*------------------------------------------------------------------------*
1416 * at91dci full speed isochronous support
1417 *------------------------------------------------------------------------*/
1419 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer)
1425 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer)
1427 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1431 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer)
1433 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1437 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1438 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1440 /* get the current frame index */
1443 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) |
1444 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML));
1446 nframes &= ATMEGA_FRAME_MASK;
1449 * check if the frame index is within the window where the frames
1452 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK;
1454 if ((xfer->endpoint->is_synced == 0) ||
1455 (temp < xfer->nframes)) {
1457 * If there is data underflow or the pipe queue is
1458 * empty we schedule the transfer a few frames ahead
1459 * of the current frame position. Else two isochronous
1460 * transfers might overlap.
1462 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK;
1463 xfer->endpoint->is_synced = 1;
1464 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1467 * compute how many milliseconds the insertion is ahead of the
1468 * current frame position:
1470 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK;
1473 * pre-compute when the isochronous transfer will be finished:
1475 xfer->isoc_time_complete =
1476 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1479 /* compute frame number for next insertion */
1480 xfer->endpoint->isoc_next += xfer->nframes;
1483 atmegadci_setup_standard_chain(xfer);
1487 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer)
1489 /* start TD chain */
1490 atmegadci_start_standard_chain(xfer);
1493 struct usb_pipe_methods atmegadci_device_isoc_fs_methods =
1495 .open = atmegadci_device_isoc_fs_open,
1496 .close = atmegadci_device_isoc_fs_close,
1497 .enter = atmegadci_device_isoc_fs_enter,
1498 .start = atmegadci_device_isoc_fs_start,
1501 /*------------------------------------------------------------------------*
1502 * at91dci root control support
1503 *------------------------------------------------------------------------*
1504 * Simulate a hardware HUB by handling all the necessary requests.
1505 *------------------------------------------------------------------------*/
1507 static const struct usb_device_descriptor atmegadci_devd = {
1508 .bLength = sizeof(struct usb_device_descriptor),
1509 .bDescriptorType = UDESC_DEVICE,
1510 .bcdUSB = {0x00, 0x02},
1511 .bDeviceClass = UDCLASS_HUB,
1512 .bDeviceSubClass = UDSUBCLASS_HUB,
1513 .bDeviceProtocol = UDPROTO_FSHUB,
1514 .bMaxPacketSize = 64,
1515 .bcdDevice = {0x00, 0x01},
1518 .bNumConfigurations = 1,
1521 static const struct atmegadci_config_desc atmegadci_confd = {
1523 .bLength = sizeof(struct usb_config_descriptor),
1524 .bDescriptorType = UDESC_CONFIG,
1525 .wTotalLength[0] = sizeof(atmegadci_confd),
1527 .bConfigurationValue = 1,
1528 .iConfiguration = 0,
1529 .bmAttributes = UC_SELF_POWERED,
1533 .bLength = sizeof(struct usb_interface_descriptor),
1534 .bDescriptorType = UDESC_INTERFACE,
1536 .bInterfaceClass = UICLASS_HUB,
1537 .bInterfaceSubClass = UISUBCLASS_HUB,
1538 .bInterfaceProtocol = 0,
1541 .bLength = sizeof(struct usb_endpoint_descriptor),
1542 .bDescriptorType = UDESC_ENDPOINT,
1543 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT),
1544 .bmAttributes = UE_INTERRUPT,
1545 .wMaxPacketSize[0] = 8,
1550 static const struct usb_hub_descriptor_min atmegadci_hubd = {
1551 .bDescLength = sizeof(atmegadci_hubd),
1552 .bDescriptorType = UDESC_HUB,
1554 .wHubCharacteristics[0] =
1555 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
1556 .wHubCharacteristics[1] =
1557 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8,
1558 .bPwrOn2PwrGood = 50,
1559 .bHubContrCurrent = 0,
1560 .DeviceRemovable = {0}, /* port is removable */
1563 #define STRING_LANG \
1564 0x09, 0x04, /* American English */
1566 #define STRING_VENDOR \
1567 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0
1569 #define STRING_PRODUCT \
1570 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1571 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1574 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab);
1575 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor);
1576 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product);
1579 atmegadci_roothub_exec(struct usb_device *udev,
1580 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1582 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
1590 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1593 ptr = (const void *)&sc->sc_hub_temp;
1597 value = UGETW(req->wValue);
1598 index = UGETW(req->wIndex);
1600 /* demultiplex the control request */
1602 switch (req->bmRequestType) {
1603 case UT_READ_DEVICE:
1604 switch (req->bRequest) {
1605 case UR_GET_DESCRIPTOR:
1606 goto tr_handle_get_descriptor;
1608 goto tr_handle_get_config;
1610 goto tr_handle_get_status;
1616 case UT_WRITE_DEVICE:
1617 switch (req->bRequest) {
1618 case UR_SET_ADDRESS:
1619 goto tr_handle_set_address;
1621 goto tr_handle_set_config;
1622 case UR_CLEAR_FEATURE:
1623 goto tr_valid; /* nop */
1624 case UR_SET_DESCRIPTOR:
1625 goto tr_valid; /* nop */
1626 case UR_SET_FEATURE:
1632 case UT_WRITE_ENDPOINT:
1633 switch (req->bRequest) {
1634 case UR_CLEAR_FEATURE:
1635 switch (UGETW(req->wValue)) {
1636 case UF_ENDPOINT_HALT:
1637 goto tr_handle_clear_halt;
1638 case UF_DEVICE_REMOTE_WAKEUP:
1639 goto tr_handle_clear_wakeup;
1644 case UR_SET_FEATURE:
1645 switch (UGETW(req->wValue)) {
1646 case UF_ENDPOINT_HALT:
1647 goto tr_handle_set_halt;
1648 case UF_DEVICE_REMOTE_WAKEUP:
1649 goto tr_handle_set_wakeup;
1654 case UR_SYNCH_FRAME:
1655 goto tr_valid; /* nop */
1661 case UT_READ_ENDPOINT:
1662 switch (req->bRequest) {
1664 goto tr_handle_get_ep_status;
1670 case UT_WRITE_INTERFACE:
1671 switch (req->bRequest) {
1672 case UR_SET_INTERFACE:
1673 goto tr_handle_set_interface;
1674 case UR_CLEAR_FEATURE:
1675 goto tr_valid; /* nop */
1676 case UR_SET_FEATURE:
1682 case UT_READ_INTERFACE:
1683 switch (req->bRequest) {
1684 case UR_GET_INTERFACE:
1685 goto tr_handle_get_interface;
1687 goto tr_handle_get_iface_status;
1693 case UT_WRITE_CLASS_INTERFACE:
1694 case UT_WRITE_VENDOR_INTERFACE:
1698 case UT_READ_CLASS_INTERFACE:
1699 case UT_READ_VENDOR_INTERFACE:
1703 case UT_WRITE_CLASS_DEVICE:
1704 switch (req->bRequest) {
1705 case UR_CLEAR_FEATURE:
1707 case UR_SET_DESCRIPTOR:
1708 case UR_SET_FEATURE:
1715 case UT_WRITE_CLASS_OTHER:
1716 switch (req->bRequest) {
1717 case UR_CLEAR_FEATURE:
1718 goto tr_handle_clear_port_feature;
1719 case UR_SET_FEATURE:
1720 goto tr_handle_set_port_feature;
1721 case UR_CLEAR_TT_BUFFER:
1731 case UT_READ_CLASS_OTHER:
1732 switch (req->bRequest) {
1733 case UR_GET_TT_STATE:
1734 goto tr_handle_get_tt_state;
1736 goto tr_handle_get_port_status;
1742 case UT_READ_CLASS_DEVICE:
1743 switch (req->bRequest) {
1744 case UR_GET_DESCRIPTOR:
1745 goto tr_handle_get_class_descriptor;
1747 goto tr_handle_get_class_status;
1758 tr_handle_get_descriptor:
1759 switch (value >> 8) {
1764 len = sizeof(atmegadci_devd);
1765 ptr = (const void *)&atmegadci_devd;
1771 len = sizeof(atmegadci_confd);
1772 ptr = (const void *)&atmegadci_confd;
1775 switch (value & 0xff) {
1776 case 0: /* Language table */
1777 len = sizeof(atmegadci_langtab);
1778 ptr = (const void *)&atmegadci_langtab;
1781 case 1: /* Vendor */
1782 len = sizeof(atmegadci_vendor);
1783 ptr = (const void *)&atmegadci_vendor;
1786 case 2: /* Product */
1787 len = sizeof(atmegadci_product);
1788 ptr = (const void *)&atmegadci_product;
1799 tr_handle_get_config:
1801 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1804 tr_handle_get_status:
1806 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1809 tr_handle_set_address:
1810 if (value & 0xFF00) {
1813 sc->sc_rt_addr = value;
1816 tr_handle_set_config:
1820 sc->sc_conf = value;
1823 tr_handle_get_interface:
1825 sc->sc_hub_temp.wValue[0] = 0;
1828 tr_handle_get_tt_state:
1829 tr_handle_get_class_status:
1830 tr_handle_get_iface_status:
1831 tr_handle_get_ep_status:
1833 USETW(sc->sc_hub_temp.wValue, 0);
1837 tr_handle_set_interface:
1838 tr_handle_set_wakeup:
1839 tr_handle_clear_wakeup:
1840 tr_handle_clear_halt:
1843 tr_handle_clear_port_feature:
1847 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1850 case UHF_PORT_SUSPEND:
1851 atmegadci_wakeup_peer(sc);
1854 case UHF_PORT_ENABLE:
1855 sc->sc_flags.port_enabled = 0;
1859 case UHF_PORT_INDICATOR:
1860 case UHF_C_PORT_ENABLE:
1861 case UHF_C_PORT_OVER_CURRENT:
1862 case UHF_C_PORT_RESET:
1865 case UHF_PORT_POWER:
1866 sc->sc_flags.port_powered = 0;
1867 atmegadci_pull_down(sc);
1868 atmegadci_clocks_off(sc);
1870 case UHF_C_PORT_CONNECTION:
1871 /* clear connect change flag */
1872 sc->sc_flags.change_connect = 0;
1874 if (!sc->sc_flags.status_bus_reset) {
1875 /* we are not connected */
1879 /* configure the control endpoint */
1881 /* select endpoint number */
1882 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0);
1884 /* set endpoint reset */
1885 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0));
1887 /* clear endpoint reset */
1888 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1890 /* enable and stall endpoint */
1891 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1892 ATMEGA_UECONX_EPEN |
1893 ATMEGA_UECONX_STALLRQ);
1895 /* one bank, 64-bytes wMaxPacket */
1896 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X,
1897 ATMEGA_UECFG0X_EPTYPE0);
1898 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1899 ATMEGA_UECFG1X_ALLOC |
1900 ATMEGA_UECFG1X_EPBK0 |
1901 ATMEGA_UECFG1X_EPSIZE(3));
1903 /* check valid config */
1904 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1905 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1906 device_printf(sc->sc_bus.bdev,
1907 "Chip rejected EP0 configuration\n");
1910 case UHF_C_PORT_SUSPEND:
1911 sc->sc_flags.change_suspend = 0;
1914 err = USB_ERR_IOERROR;
1919 tr_handle_set_port_feature:
1923 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1926 case UHF_PORT_ENABLE:
1927 sc->sc_flags.port_enabled = 1;
1929 case UHF_PORT_SUSPEND:
1930 case UHF_PORT_RESET:
1932 case UHF_PORT_INDICATOR:
1935 case UHF_PORT_POWER:
1936 sc->sc_flags.port_powered = 1;
1939 err = USB_ERR_IOERROR;
1944 tr_handle_get_port_status:
1946 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1951 if (sc->sc_flags.status_vbus) {
1952 atmegadci_clocks_on(sc);
1953 atmegadci_pull_up(sc);
1955 atmegadci_pull_down(sc);
1956 atmegadci_clocks_off(sc);
1959 /* Select FULL-speed and Device Side Mode */
1961 value = UPS_PORT_MODE_DEVICE;
1963 if (sc->sc_flags.port_powered) {
1964 value |= UPS_PORT_POWER;
1966 if (sc->sc_flags.port_enabled) {
1967 value |= UPS_PORT_ENABLED;
1969 if (sc->sc_flags.status_vbus &&
1970 sc->sc_flags.status_bus_reset) {
1971 value |= UPS_CURRENT_CONNECT_STATUS;
1973 if (sc->sc_flags.status_suspend) {
1974 value |= UPS_SUSPEND;
1976 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1980 if (sc->sc_flags.change_connect) {
1981 value |= UPS_C_CONNECT_STATUS;
1983 if (sc->sc_flags.change_suspend) {
1984 value |= UPS_C_SUSPEND;
1986 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1987 len = sizeof(sc->sc_hub_temp.ps);
1990 tr_handle_get_class_descriptor:
1994 ptr = (const void *)&atmegadci_hubd;
1995 len = sizeof(atmegadci_hubd);
1999 err = USB_ERR_STALLED;
2008 atmegadci_xfer_setup(struct usb_setup_params *parm)
2010 const struct usb_hw_ep_profile *pf;
2011 struct atmegadci_softc *sc;
2012 struct usb_xfer *xfer;
2018 sc = ATMEGA_BUS2SC(parm->udev->bus);
2019 xfer = parm->curr_xfer;
2022 * NOTE: This driver does not use any of the parameters that
2023 * are computed from the following values. Just set some
2024 * reasonable dummies:
2026 parm->hc_max_packet_size = 0x500;
2027 parm->hc_max_packet_count = 1;
2028 parm->hc_max_frame_size = 0x500;
2030 usbd_transfer_setup_sub(parm);
2033 * compute maximum number of TDs
2035 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
2037 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2041 ntd = xfer->nframes + 1 /* SYNC */ ;
2045 * check if "usbd_transfer_setup_sub" set an error
2051 * allocate transfer descriptors
2058 ep_no = xfer->endpointno & UE_ADDR;
2059 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2062 /* should not happen */
2063 parm->err = USB_ERR_INVAL;
2068 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2070 for (n = 0; n != ntd; n++) {
2072 struct atmegadci_td *td;
2076 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2079 td->max_packet_size = xfer->max_packet_size;
2081 if (pf->support_multi_buffer) {
2082 td->support_multi_buffer = 1;
2084 td->obj_next = last_obj;
2088 parm->size[0] += sizeof(*td);
2091 xfer->td_start[0] = last_obj;
2095 atmegadci_xfer_unsetup(struct usb_xfer *xfer)
2101 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2102 struct usb_endpoint *ep)
2104 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
2106 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2108 edesc->bEndpointAddress, udev->flags.usb_mode,
2109 sc->sc_rt_addr, udev->device_index);
2111 if (udev->device_index != sc->sc_rt_addr) {
2113 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2117 if (udev->speed != USB_SPEED_FULL) {
2121 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2122 ep->methods = &atmegadci_device_isoc_fs_methods;
2124 ep->methods = &atmegadci_device_non_isoc_methods;
2128 struct usb_bus_methods atmegadci_bus_methods =
2130 .endpoint_init = &atmegadci_ep_init,
2131 .xfer_setup = &atmegadci_xfer_setup,
2132 .xfer_unsetup = &atmegadci_xfer_unsetup,
2133 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile,
2134 .set_stall = &atmegadci_set_stall,
2135 .clear_stall = &atmegadci_clear_stall,
2136 .roothub_exec = &atmegadci_roothub_exec,
2137 .xfer_poll = &atmegadci_do_poll,