2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
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6 * modification, are permitted provided that the following conditions
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15 * This product includes software developed by Bill Paul.
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36 * Definitions for the ASIX Electronics AX88172, AX88178
37 * and AX88772 to ethernet controllers.
41 * Vendor specific commands. ASIX conveniently doesn't document the 'set
42 * NODEID' command in their datasheet (thanks a lot guys).
43 * To make handling these commands easier, I added some extra data which is
44 * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with
45 * the format: LDCC. L and D are both nibbles in the high byte. L represents
46 * the data length (0 to 15) and D represents the direction (0 for vendor read,
47 * 1 for vendor write). CC is the command byte, as specified in the manual.
50 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8)
51 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
52 #define AXE_CMD_CMD(x) ((x) & 0x00FF)
54 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002
55 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002
56 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103
57 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
58 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104
59 #define AXE_CMD_MII_OPMODE_SW 0x0106
60 #define AXE_CMD_MII_READ_REG 0x2007
61 #define AXE_CMD_MII_WRITE_REG 0x2108
62 #define AXE_CMD_MII_READ_OPMODE 0x1009
63 #define AXE_CMD_MII_OPMODE_HW 0x010A
64 #define AXE_CMD_SROM_READ 0x200B
65 #define AXE_CMD_SROM_WRITE 0x010C
66 #define AXE_CMD_SROM_WR_ENABLE 0x010D
67 #define AXE_CMD_SROM_WR_DISABLE 0x010E
68 #define AXE_CMD_RXCTL_READ 0x200F
69 #define AXE_CMD_RXCTL_WRITE 0x0110
70 #define AXE_CMD_READ_IPG012 0x3011
71 #define AXE_172_CMD_WRITE_IPG0 0x0112
72 #define AXE_178_CMD_WRITE_IPG012 0x0112
73 #define AXE_172_CMD_WRITE_IPG1 0x0113
74 #define AXE_178_CMD_READ_NODEID 0x6013
75 #define AXE_172_CMD_WRITE_IPG2 0x0114
76 #define AXE_178_CMD_WRITE_NODEID 0x6114
77 #define AXE_CMD_READ_MCAST 0x8015
78 #define AXE_CMD_WRITE_MCAST 0x8116
79 #define AXE_172_CMD_READ_NODEID 0x6017
80 #define AXE_172_CMD_WRITE_NODEID 0x6118
82 #define AXE_CMD_READ_PHYID 0x2019
83 #define AXE_172_CMD_READ_MEDIA 0x101A
84 #define AXE_178_CMD_READ_MEDIA 0x201A
85 #define AXE_CMD_WRITE_MEDIA 0x011B
86 #define AXE_CMD_READ_MONITOR_MODE 0x101C
87 #define AXE_CMD_WRITE_MONITOR_MODE 0x011D
88 #define AXE_CMD_READ_GPIO 0x101E
89 #define AXE_CMD_WRITE_GPIO 0x011F
91 #define AXE_CMD_SW_RESET_REG 0x0120
92 #define AXE_CMD_SW_PHY_STATUS 0x0021
93 #define AXE_CMD_SW_PHY_SELECT 0x0122
95 /* AX88772A and AX88772B only. */
96 #define AXE_CMD_READ_VLAN_CTRL 0x4027
97 #define AXE_CMD_WRITE_VLAN_CTRL 0x4028
99 #define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A
101 #define AXE_SW_RESET_CLEAR 0x00
102 #define AXE_SW_RESET_RR 0x01
103 #define AXE_SW_RESET_RT 0x02
104 #define AXE_SW_RESET_PRTE 0x04
105 #define AXE_SW_RESET_PRL 0x08
106 #define AXE_SW_RESET_BZ 0x10
107 #define AXE_SW_RESET_IPRL 0x20
108 #define AXE_SW_RESET_IPPD 0x40
110 /* AX88178 documentation says to always write this bit... */
111 #define AXE_178_RESET_MAGIC 0x40
113 #define AXE_178_MEDIA_GMII 0x0001
114 #define AXE_MEDIA_FULL_DUPLEX 0x0002
115 #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004
117 /* AX88178/88772 documentation says to always write 1 to bit 2 */
118 #define AXE_178_MEDIA_MAGIC 0x0004
119 /* AX88772 documentation says to always write 0 to bit 3 */
120 #define AXE_178_MEDIA_ENCK 0x0008
121 #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010
122 #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010
123 #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020
124 #define AXE_178_MEDIA_JUMBO_EN 0x0040
125 #define AXE_178_MEDIA_LTPF_ONLY 0x0080
126 #define AXE_178_MEDIA_RX_EN 0x0100
127 #define AXE_178_MEDIA_100TX 0x0200
128 #define AXE_178_MEDIA_SBP 0x0800
129 #define AXE_178_MEDIA_SUPERMAC 0x1000
131 #define AXE_RXCMD_PROMISC 0x0001
132 #define AXE_RXCMD_ALLMULTI 0x0002
133 #define AXE_172_RXCMD_UNICAST 0x0004
134 #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004
135 #define AXE_RXCMD_BROADCAST 0x0008
136 #define AXE_RXCMD_MULTICAST 0x0010
137 #define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */
138 #define AXE_RXCMD_ENABLE 0x0080
139 #define AXE_178_RXCMD_MFB_MASK 0x0300
140 #define AXE_178_RXCMD_MFB_2048 0x0000
141 #define AXE_178_RXCMD_MFB_4096 0x0100
142 #define AXE_178_RXCMD_MFB_8192 0x0200
143 #define AXE_178_RXCMD_MFB_16384 0x0300
144 #define AXE_772B_RXCMD_HDR_TYPE_0 0x0000
145 #define AXE_772B_RXCMD_HDR_TYPE_1 0x0100
146 #define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200
147 #define AXE_772B_RXCMD_ADD_CHKSUM 0x0400
148 #define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */
150 #define AXE_PHY_SEL_PRI 1
151 #define AXE_PHY_SEL_SEC 0
152 #define AXE_PHY_TYPE_MASK 0xE0
153 #define AXE_PHY_TYPE_SHIFT 5
154 #define AXE_PHY_TYPE(x) \
155 (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT)
157 #define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */
158 #define PHY_TYPE_GIG 1 /* Gigabit PHY */
159 #define PHY_TYPE_SPECIAL 4 /* Special case */
160 #define PHY_TYPE_RSVD 5 /* Reserved */
161 #define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */
163 #define AXE_PHY_NO_MASK 0x1F
164 #define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK)
166 #define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */
168 #define AXE_GPIO0_EN 0x01
169 #define AXE_GPIO0 0x02
170 #define AXE_GPIO1_EN 0x04
171 #define AXE_GPIO1 0x08
172 #define AXE_GPIO2_EN 0x10
173 #define AXE_GPIO2 0x20
174 #define AXE_GPIO_RELOAD_EEPROM 0x80
176 #define AXE_PHY_MODE_MARVELL 0x00
177 #define AXE_PHY_MODE_CICADA 0x01
178 #define AXE_PHY_MODE_AGERE 0x02
179 #define AXE_PHY_MODE_CICADA_V2 0x05
180 #define AXE_PHY_MODE_AGERE_GMII 0x06
181 #define AXE_PHY_MODE_CICADA_V2_ASIX 0x09
182 #define AXE_PHY_MODE_REALTEK_8211CL 0x0C
183 #define AXE_PHY_MODE_REALTEK_8211BN 0x0D
184 #define AXE_PHY_MODE_REALTEK_8251CL 0x0E
185 #define AXE_PHY_MODE_ATTANSIC 0x40
187 /* AX88772A/AX88772B only. */
188 #define AXE_SW_PHY_SELECT_EXT 0x0000
189 #define AXE_SW_PHY_SELECT_EMBEDDED 0x0001
190 #define AXE_SW_PHY_SELECT_AUTO 0x0002
191 #define AXE_SW_PHY_SELECT_SS_MII 0x0004
192 #define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008
193 #define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C
194 #define AXE_SW_PHY_SELECT_SS_ENB 0x0010
196 /* AX88772A/AX88772B VLAN control. */
197 #define AXE_VLAN_CTRL_ENB 0x00001000
198 #define AXE_VLAN_CTRL_STRIP 0x00002000
199 #define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF
200 #define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000
202 #define AXE_BULK_BUF_SIZE 16384 /* bytes */
204 #define AXE_CTL_READ 0x01
205 #define AXE_CTL_WRITE 0x02
207 #define AXE_CONFIG_IDX 0 /* config number 1 */
208 #define AXE_IFACE_IDX 0
211 #define AXE_EEPROM_772B_NODE_ID 0x04
212 #define AXE_EEPROM_772B_PHY_PWRCFG 0x18
214 struct ax88772b_mfb {
219 #define AX88772B_MFB_2K 0
220 #define AX88772B_MFB_4K 1
221 #define AX88772B_MFB_6K 2
222 #define AX88772B_MFB_8K 3
223 #define AX88772B_MFB_16K 4
224 #define AX88772B_MFB_20K 5
225 #define AX88772B_MFB_24K 6
226 #define AX88772B_MFB_32K 7
228 struct axe_sframe_hdr {
233 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
235 /* The interrupt endpoint is currently unused by the ASIX part. */
243 struct usb_ether sc_ue;
245 struct usb_xfer *sc_xfer[AXE_N_TRANSFER];
249 #define AXE_FLAG_LINK 0x0001
250 #define AXE_FLAG_772 0x1000 /* AX88772 */
251 #define AXE_FLAG_772A 0x2000 /* AX88772A */
252 #define AXE_FLAG_772B 0x4000 /* AX88772B */
253 #define AXE_FLAG_178 0x8000 /* AX88178 */
256 uint8_t sc_phyaddrs[2];
261 #define AXE_IS_178_FAMILY(sc) \
262 ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B | \
265 #define AXE_IS_772(sc) \
266 ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B))
268 #define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
269 #define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
270 #define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)