2 * Copyright (c) 2010-2011 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/vmmeter.h>
38 #include <sys/interrupt.h>
39 #include <sys/malloc.h>
42 #include <sys/mutex.h>
43 #include <sys/sched.h>
45 #include <sys/sysctl.h>
46 #include <sys/syslog.h>
48 #include <machine/cpu.h>
49 #include <machine/fpu.h>
50 #include <machine/frame.h>
51 #include <machine/intr.h>
52 #include <machine/intrcnt.h>
53 #include <machine/md_var.h>
54 #include <machine/pcb.h>
55 #include <machine/reg.h>
56 #include <machine/smp.h>
63 struct intr_event *event; /* interrupt event */
64 volatile long *cntp; /* interrupt counter */
69 ia64_ihtype *ia64_handler[IA64_NXIVS];
71 static enum ia64_xiv_use ia64_xiv[IA64_NXIVS];
72 static struct ia64_intr *ia64_intrs[IA64_NXIVS];
74 static ia64_ihtype ia64_ih_invalid;
75 static ia64_ihtype ia64_ih_irq;
82 for (xiv = 0; xiv < IA64_NXIVS; xiv++) {
83 ia64_handler[xiv] = ia64_ih_invalid;
84 ia64_xiv[xiv] = IA64_XIV_FREE;
85 ia64_intrs[xiv] = NULL;
87 (void)ia64_xiv_reserve(15, IA64_XIV_ARCH, NULL);
91 ia64_xiv_free(u_int xiv, enum ia64_xiv_use what)
94 if (xiv >= IA64_NXIVS)
96 if (what == IA64_XIV_FREE || what == IA64_XIV_ARCH)
98 if (ia64_xiv[xiv] != what)
100 ia64_xiv[xiv] = IA64_XIV_FREE;
101 ia64_handler[xiv] = ia64_ih_invalid;
106 ia64_xiv_reserve(u_int xiv, enum ia64_xiv_use what, ia64_ihtype ih)
109 if (xiv >= IA64_NXIVS)
111 if (what == IA64_XIV_FREE)
113 if (ia64_xiv[xiv] != IA64_XIV_FREE)
115 ia64_xiv[xiv] = what;
116 ia64_handler[xiv] = (ih == NULL) ? ia64_ih_invalid: ih;
118 printf("XIV %u: use=%u, IH=%p\n", xiv, what, ih);
123 ia64_xiv_alloc(u_int prio, enum ia64_xiv_use what, ia64_ihtype ih)
129 if (hwprio > IA64_MAX_HWPRIO)
130 hwprio = IA64_MAX_HWPRIO;
132 xiv0 = IA64_NXIVS - (hwprio + 1) * 16;
134 KASSERT(xiv0 >= IA64_MIN_XIV, ("%s: min XIV", __func__));
135 KASSERT(xiv0 < IA64_NXIVS, ("%s: max XIV", __func__));
138 while (xiv < IA64_NXIVS && ia64_xiv_reserve(xiv, what, ih))
141 if (xiv < IA64_NXIVS)
145 while (xiv >= IA64_MIN_XIV && ia64_xiv_reserve(xiv, what, ih))
148 return ((xiv >= IA64_MIN_XIV) ? xiv : 0);
152 ia64_intr_eoi(void *arg)
154 u_int xiv = (uintptr_t)arg;
158 KASSERT(i != NULL, ("%s", __func__));
159 sapic_eoi(i->sapic, xiv);
163 ia64_intr_mask(void *arg)
165 u_int xiv = (uintptr_t)arg;
169 KASSERT(i != NULL, ("%s", __func__));
170 sapic_mask(i->sapic, i->irq);
171 sapic_eoi(i->sapic, xiv);
175 ia64_intr_unmask(void *arg)
177 u_int xiv = (uintptr_t)arg;
181 KASSERT(i != NULL, ("%s", __func__));
182 sapic_unmask(i->sapic, i->irq);
186 ia64_setup_intr(const char *name, int irq, driver_filter_t filter,
187 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
195 prio = intr_priority(flags);
196 if (prio > PRI_MAX_ITHD)
201 /* Get the I/O SAPIC and XIV that corresponds to the IRQ. */
202 sa = sapic_lookup(irq, &xiv);
210 i = malloc(sizeof(struct ia64_intr), M_DEVBUF,
213 sa = sapic_lookup(irq, &xiv);
214 KASSERT(sa != NULL, ("sapic_lookup"));
220 * If the IRQ has no XIV assigned to it yet, assign one based
224 xiv = ia64_xiv_alloc(prio, IA64_XIV_IRQ, ia64_ih_irq);
231 error = intr_event_create(&i->event, (void *)(uintptr_t)xiv,
232 0, irq, ia64_intr_mask, ia64_intr_unmask, ia64_intr_eoi,
233 NULL, "irq%u:", irq);
235 ia64_xiv_free(xiv, IA64_XIV_IRQ);
243 i->cntp = intrcnt + xiv;
248 sapic_enable(sa, irq, xiv);
250 if (name != NULL && *name != '\0') {
251 /* XXX needs abstraction. Too error prone. */
252 intrname = intrnames + xiv * INTRNAME_LEN;
253 memset(intrname, ' ', INTRNAME_LEN - 1);
254 bcopy(name, intrname, strlen(name));
261 KASSERT(i != NULL, ("XIV mapping bug"));
263 error = intr_event_add_handler(i->event, name, filter, handler, arg,
264 prio, flags, cookiep);
269 ia64_teardown_intr(void *cookie)
272 return (intr_event_remove_handler(cookie));
284 for (xiv = IA64_NXIVS - 1; xiv >= IA64_MIN_XIV; xiv--) {
285 if (ia64_xiv[xiv] != IA64_XIV_IRQ)
289 cpu = (cpu == 0) ? MAXCPU - 1 : cpu - 1;
290 pc = cpuid_to_pcpu[cpu];
291 } while (pc == NULL || !pc->pc_md.awake);
292 sapic_bind_intr(i->irq, pc);
297 * Interrupt handlers.
301 ia64_handle_intr(struct trapframe *tf)
304 struct trapframe *stf;
308 ia64_set_fpsr(IA64_FPSR_DEFAULT);
309 PCPU_INC(cnt.v_intr);
311 xiv = ia64_get_ivr();
314 PCPU_INC(md.stats.pcs_nstrays);
319 stf = td->td_intr_frame;
320 td->td_intr_frame = tf;
323 CTR2(KTR_INTR, "INTR: ITC=%u, XIV=%u",
324 (u_int)tf->tf_special.ifa, xiv);
325 if (!(ia64_handler[xiv])(td, xiv, tf)) {
329 xiv = ia64_get_ivr();
333 td->td_intr_frame = stf;
337 if (TRAPF_USERMODE(tf)) {
338 while (td->td_flags & (TDF_ASTPENDING|TDF_NEEDRESCHED)) {
347 ia64_ih_invalid(struct thread *td, u_int xiv, struct trapframe *tf)
350 panic("invalid XIV: %u", xiv);
355 ia64_ih_irq(struct thread *td, u_int xiv, struct trapframe *tf)
358 struct intr_event *ie; /* our interrupt event */
360 PCPU_INC(md.stats.pcs_nhwints);
362 /* Find the interrupt thread for this XIV. */
364 KASSERT(i != NULL, ("%s: unassigned XIV", __func__));
369 KASSERT(ie != NULL, ("%s: interrupt without event", __func__));
371 if (intr_event_handle(ie, tf) != 0) {
372 ia64_intr_mask((void *)(uintptr_t)xiv);
373 log(LOG_ERR, "stray irq%u\n", i->irq);
382 db_print_xiv(u_int xiv, int always)
388 db_printf("XIV %u (%p): ", xiv, i);
389 sapic_print(i->sapic, i->irq);
391 db_printf("XIV %u: unassigned\n", xiv);
394 DB_SHOW_COMMAND(xiv, db_show_xiv)
399 xiv = ((addr >> 4) % 16) * 10 + (addr % 16);
400 if (xiv >= IA64_NXIVS)
401 db_printf("error: XIV %u not in range [0..%u]\n",
402 xiv, IA64_NXIVS - 1);
404 db_print_xiv(xiv, 1);
406 for (xiv = 0; xiv < IA64_NXIVS; xiv++)
407 db_print_xiv(xiv, 0);