sys/ofed/drivers/net/mlx4/en_port.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34
  35 #include "mlx4_en.h"
  36
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/mlx4/device.h>
  40 #include <linux/mlx4/cmd.h>
  41
  42
  43 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
  44                         u64 mac, u64 clear, u8 mode)
  45 {
  46         return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
  47                         MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B);
  48 }
  49
  50 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, u32 *vlans)
  51 {
  52         struct mlx4_cmd_mailbox *mailbox;
  53         struct mlx4_set_vlan_fltr_mbox *filter;
  54         int i, j;
  55         int err = 0;
  56
  57         mailbox = mlx4_alloc_cmd_mailbox(dev);
  58         if (IS_ERR(mailbox))
  59                 return PTR_ERR(mailbox);
  60
  61         filter = mailbox->buf;
  62         memset(filter, 0, sizeof *filter);
  63         if (vlans)
  64                 for (i = 0, j = VLAN_FLTR_SIZE - 1; i < VLAN_FLTR_SIZE;
  65                     i++, j--)
  66                         filter->entry[j] = cpu_to_be32(vlans[i]);
  67         err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_VLAN_FLTR,
  68                        MLX4_CMD_TIME_CLASS_B);
  69         mlx4_free_cmd_mailbox(dev, mailbox);
  70         return err;
  71 }
  72
  73
  74 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
  75                           u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
  76 {
  77         struct mlx4_cmd_mailbox *mailbox;
  78         struct mlx4_set_port_general_context *context;
  79         int err;
  80         u32 in_mod;
  81
  82         mailbox = mlx4_alloc_cmd_mailbox(dev);
  83         if (IS_ERR(mailbox))
  84                 return PTR_ERR(mailbox);
  85         context = mailbox->buf;
  86         memset(context, 0, sizeof *context);
  87
  88         context->flags = SET_PORT_GEN_ALL_VALID;
  89         context->mtu = cpu_to_be16(mtu);
  90         context->pptx = (pptx * (!pfctx)) << 7;
  91         context->pfctx = pfctx;
  92         context->pprx = (pprx * (!pfcrx)) << 7;
  93         context->pfcrx = pfcrx;
  94
  95         in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
  96         err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
  97                        MLX4_CMD_TIME_CLASS_B);
  98
  99         mlx4_free_cmd_mailbox(dev, mailbox);
 100         return err;
 101 }
 102
 103 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
 104                            u8 promisc)
 105 {
 106         struct mlx4_cmd_mailbox *mailbox;
 107         struct mlx4_set_port_rqp_calc_context *context;
 108         int err;
 109         u32 in_mod;
 110
 111         mailbox = mlx4_alloc_cmd_mailbox(dev);
 112         if (IS_ERR(mailbox))
 113                 return PTR_ERR(mailbox);
 114         context = mailbox->buf;
 115         memset(context, 0, sizeof *context);
 116
 117         context->base_qpn = cpu_to_be32(base_qpn);
 118         context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_EN_SHIFT | base_qpn);
 119         context->mcast = cpu_to_be32((dev->caps.mc_promisc_mode <<
 120                                       SET_PORT_PROMISC_MODE_SHIFT) | base_qpn);
 121         context->intra_no_vlan = 0;
 122         context->no_vlan = MLX4_NO_VLAN_IDX;
 123         context->intra_vlan_miss = 0;
 124         context->vlan_miss = MLX4_VLAN_MISS_IDX;
 125
 126         in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
 127         err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
 128                        MLX4_CMD_TIME_CLASS_B);
 129
 130         mlx4_free_cmd_mailbox(dev, mailbox);
 131         return err;
 132 }
 133
 134 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
 135 {
 136         struct mlx4_en_query_port_context *qport_context;
 137         struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
 138         struct mlx4_en_port_state *state = &priv->port_state;
 139         struct mlx4_cmd_mailbox *mailbox;
 140         int err;
 141
 142         mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
 143         if (IS_ERR(mailbox))
 144                 return PTR_ERR(mailbox);
 145         memset(mailbox->buf, 0, sizeof(*qport_context));
 146         err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
 147                            MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B);
 148         if (err)
 149                 goto out;
 150         qport_context = mailbox->buf;
 151
 152         /* This command is always accessed from Ethtool context
 153          * already synchronized, no need in locking */
 154         state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
 155         if ((qport_context->link_speed & MLX4_EN_SPEED_MASK) ==
 156             MLX4_EN_1G_SPEED)
 157                 state->link_speed = 1000;
 158         else
 159                 state->link_speed = 10000;
 160         state->transciver = qport_context->transceiver;
 161         if (be32_to_cpu(qport_context->transceiver_code_hi) & 0x400)
 162                 state->transciver = 0x80;
 163
 164 out:
 165         mlx4_free_cmd_mailbox(mdev->dev, mailbox);
 166         return err;
 167 }
 168
 169 static int read_iboe_counters(struct mlx4_dev *dev, int index, u64 counters[])
 170 {
 171         struct mlx4_cmd_mailbox *mailbox;
 172         int err;
 173         int mode;
 174         struct mlx4_counters_ext *ext;
 175         struct mlx4_counters *reg;
 176
 177         mailbox = mlx4_alloc_cmd_mailbox(dev);
 178         if (IS_ERR(mailbox))
 179                 return -ENOMEM;
 180
 181         err = mlx4_cmd_box(dev, 0, mailbox->dma, index, 0,
 182                            MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C);
 183         if (err)
 184                 goto out;
 185
 186         mode = be32_to_cpu(((struct mlx4_counters *)mailbox->buf)->counter_mode) & 0xf;
 187         switch (mode) {
 188         case 0:
 189                 reg = mailbox->buf;
 190                 counters[0] = be64_to_cpu(reg->rx_frames);
 191                 counters[1] = be64_to_cpu(reg->tx_frames);
 192                 counters[2] = be64_to_cpu(reg->rx_bytes);
 193                 counters[3] = be64_to_cpu(reg->tx_bytes);
 194                 break;
 195         case 1:
 196                 ext = mailbox->buf;
 197                 counters[0] = be64_to_cpu(ext->rx_uni_frames);
 198                 counters[1] = be64_to_cpu(ext->tx_uni_frames);
 199                 counters[2] = be64_to_cpu(ext->rx_uni_bytes);
 200                 counters[3] = be64_to_cpu(ext->tx_uni_bytes);
 201                 break;
 202         default:
 203                 err = -EINVAL;
 204         }
 205
 206 out:
 207         mlx4_free_cmd_mailbox(dev, mailbox);
 208         return err;
 209 }
 210
 211 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
 212 {
 213         struct mlx4_en_stat_out_mbox *mlx4_en_stats;
 214         struct net_device *dev;
 215         struct mlx4_en_priv *priv;
 216         struct mlx4_cmd_mailbox *mailbox;
 217         u64 in_mod = reset << 8 | port;
 218         unsigned long oerror;
 219         unsigned long ierror;
 220         int err;
 221         int i;
 222         int counter;
 223         u64 counters[4];
 224
 225         dev = mdev->pndev[port];
 226         priv = netdev_priv(dev);
 227         memset(counters, 0, sizeof counters);
 228         counter = mlx4_get_iboe_counter(priv->mdev->dev, port);
 229         if (counter >= 0)
 230                 err = read_iboe_counters(priv->mdev->dev, counter, counters);
 231
 232         mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
 233         if (IS_ERR(mailbox))
 234                 return PTR_ERR(mailbox);
 235         memset(mailbox->buf, 0, sizeof(*mlx4_en_stats));
 236         err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
 237                            MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B);
 238         if (err)
 239                 goto out;
 240
 241         mlx4_en_stats = mailbox->buf;
 242
 243         spin_lock(&priv->stats_lock);
 244
 245         oerror = ierror = 0;
 246         dev->if_ipackets = counters[0];
 247         dev->if_ibytes = counters[2];
 248         for (i = 0; i < priv->rx_ring_num; i++) {
 249                 dev->if_ipackets += priv->rx_ring[i].packets;
 250                 dev->if_ibytes += priv->rx_ring[i].bytes;
 251                 ierror += priv->rx_ring[i].errors;
 252         }
 253         dev->if_opackets = counters[1];
 254         dev->if_obytes = counters[3];
 255         for (i = 0; i <= priv->tx_ring_num; i++) {
 256                 dev->if_opackets += priv->tx_ring[i].packets;
 257                 dev->if_obytes += priv->tx_ring[i].bytes;
 258                 oerror += priv->tx_ring[i].errors;
 259         }
 260
 261         dev->if_ierrors = be32_to_cpu(mlx4_en_stats->RDROP) + ierror;
 262         dev->if_oerrors = be32_to_cpu(mlx4_en_stats->TDROP) + oerror;
 263         dev->if_imcasts = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) +
 264                           be64_to_cpu(mlx4_en_stats->MCAST_prio_1) +
 265                           be64_to_cpu(mlx4_en_stats->MCAST_prio_2) +
 266                           be64_to_cpu(mlx4_en_stats->MCAST_prio_3) +
 267                           be64_to_cpu(mlx4_en_stats->MCAST_prio_4) +
 268                           be64_to_cpu(mlx4_en_stats->MCAST_prio_5) +
 269                           be64_to_cpu(mlx4_en_stats->MCAST_prio_6) +
 270                           be64_to_cpu(mlx4_en_stats->MCAST_prio_7) +
 271                           be64_to_cpu(mlx4_en_stats->MCAST_novlan);
 272         dev->if_omcasts = be64_to_cpu(mlx4_en_stats->TMCAST_prio_0) +
 273                           be64_to_cpu(mlx4_en_stats->TMCAST_prio_1) +
 274                           be64_to_cpu(mlx4_en_stats->TMCAST_prio_2) +
 275                           be64_to_cpu(mlx4_en_stats->TMCAST_prio_3) +
 276                           be64_to_cpu(mlx4_en_stats->TMCAST_prio_4) +
 277                           be64_to_cpu(mlx4_en_stats->TMCAST_prio_5) +
 278                           be64_to_cpu(mlx4_en_stats->TMCAST_prio_6) +
 279                           be64_to_cpu(mlx4_en_stats->TMCAST_prio_7) +
 280                           be64_to_cpu(mlx4_en_stats->TMCAST_novlan);
 281         dev->if_collisions = 0;
 282
 283         priv->pkstats.broadcast =
 284                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) +
 285                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) +
 286                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) +
 287                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) +
 288                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) +
 289                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) +
 290                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) +
 291                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) +
 292                                 be64_to_cpu(mlx4_en_stats->RBCAST_novlan);
 293         priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
 294         priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
 295         priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
 296         priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
 297         priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
 298         priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
 299         priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
 300         priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
 301         priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
 302         priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
 303         priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
 304         priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
 305         priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
 306         priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
 307         priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
 308         priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
 309         spin_unlock(&priv->stats_lock);
 310
 311 out:
 312         mlx4_free_cmd_mailbox(mdev->dev, mailbox);
 313         return err;
 314 }
 315