2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <asm/atomic.h>
42 #include <linux/mlx4/driver.h>
45 MLX4_FLAG_MSI_X = 1 << 0,
46 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
54 MLX4_BOARD_ID_LEN = 64
58 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
59 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
60 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
61 MLX4_DEV_CAP_FLAG_XRC = 1 << 3,
62 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
63 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
64 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
65 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
66 MLX4_DEV_CAP_FLAG_DPDP = 1 << 12,
67 MLX4_DEV_CAP_FLAG_RAW_ETY = 1 << 13,
68 MLX4_DEV_CAP_FLAG_BLH = 1 << 15,
69 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
70 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
71 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
72 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
73 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
74 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21,
75 MLX4_DEV_CAP_FLAG_IBOE = 1 << 30,
76 MLX4_DEV_CAP_FLAG_FC_T11 = 1 << 31
80 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
81 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
82 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
83 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
84 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
88 MLX4_EVENT_TYPE_COMP = 0x00,
89 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
90 MLX4_EVENT_TYPE_COMM_EST = 0x02,
91 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
92 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
93 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
94 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
95 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
96 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
97 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
98 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
99 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
100 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
101 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
102 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
103 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
104 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
105 MLX4_EVENT_TYPE_CMD = 0x0a
109 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
110 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
114 MLX4_PERM_LOCAL_READ = 1 << 10,
115 MLX4_PERM_LOCAL_WRITE = 1 << 11,
116 MLX4_PERM_REMOTE_READ = 1 << 12,
117 MLX4_PERM_REMOTE_WRITE = 1 << 13,
118 MLX4_PERM_ATOMIC = 1 << 14
122 MLX4_OPCODE_NOP = 0x00,
123 MLX4_OPCODE_SEND_INVAL = 0x01,
124 MLX4_OPCODE_RDMA_WRITE = 0x08,
125 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
126 MLX4_OPCODE_SEND = 0x0a,
127 MLX4_OPCODE_SEND_IMM = 0x0b,
128 MLX4_OPCODE_LSO = 0x0e,
129 MLX4_OPCODE_BIG_LSO = 0x2e,
130 MLX4_OPCODE_RDMA_READ = 0x10,
131 MLX4_OPCODE_ATOMIC_CS = 0x11,
132 MLX4_OPCODE_ATOMIC_FA = 0x12,
133 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
134 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
135 MLX4_OPCODE_BIND_MW = 0x18,
136 MLX4_OPCODE_FMR = 0x19,
137 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
138 MLX4_OPCODE_CONFIG_CMD = 0x1f,
140 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
141 MLX4_RECV_OPCODE_SEND = 0x01,
142 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
143 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
145 MLX4_CQE_OPCODE_ERROR = 0x1e,
146 MLX4_CQE_OPCODE_RESIZE = 0x16,
150 MLX4_STAT_RATE_OFFSET = 5
154 MLX4_MTT_FLAG_PRESENT = 1
157 enum mlx4_qp_region {
158 MLX4_QP_REGION_FW = 0,
159 MLX4_QP_REGION_ETH_ADDR,
160 MLX4_QP_REGION_FC_ADDR,
164 enum mlx4_port_type {
165 MLX4_PORT_TYPE_NONE = 0,
166 MLX4_PORT_TYPE_IB = 1,
167 MLX4_PORT_TYPE_ETH = 2,
168 MLX4_PORT_TYPE_AUTO = 3
171 enum mlx4_special_vlan_idx {
172 MLX4_NO_VLAN_IDX = 0,
176 #define MLX4_LEAST_ATTACHED_VECTOR 0xffffffff
179 MLX4_CUNTERS_DISABLED,
185 MAX_FAST_REG_PAGES = 511,
188 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
190 return (major << 32) | (minor << 16) | subminor;
196 int vl_cap[MLX4_MAX_PORTS + 1];
197 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
198 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
199 u64 def_mac[MLX4_MAX_PORTS + 1];
200 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
201 int gid_table_len[MLX4_MAX_PORTS + 1];
202 int pkey_table_len[MLX4_MAX_PORTS + 1];
203 int trans_type[MLX4_MAX_PORTS + 1];
204 int vendor_oui[MLX4_MAX_PORTS + 1];
205 int wavelength[MLX4_MAX_PORTS + 1];
206 u64 trans_code[MLX4_MAX_PORTS + 1];
207 int local_ca_ack_delay;
210 int bf_regs_per_page;
217 int max_qp_init_rdma;
218 int max_qp_dest_rdma;
229 int num_comp_vectors;
233 int fmr_reserved_mtts;
251 u16 stat_rate_support;
253 int loopback_support;
255 u8 port_width_cap[MLX4_MAX_PORTS + 1];
257 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
259 int reserved_qps_base[MLX4_NUM_QP_REGION];
263 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
264 u8 supported_type[MLX4_MAX_PORTS + 1];
265 enum mlx4_port_type port_mask[MLX4_MAX_PORTS + 1];
266 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
268 u32 max_basic_counters;
269 u32 max_ext_counters;
273 struct mlx4_buf_list {
279 struct mlx4_buf_list direct;
280 struct mlx4_buf_list *page_list;
293 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
296 struct mlx4_db_pgdir {
297 struct list_head list;
298 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
299 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
300 unsigned long *bits[2];
305 struct mlx4_ib_user_db_page;
310 struct mlx4_db_pgdir *pgdir;
311 struct mlx4_ib_user_db_page *user_page;
318 struct mlx4_hwq_resources {
336 struct mlx4_mpt_entry *mpt;
338 dma_addr_t dma_handle;
348 struct list_head bf_list;
349 unsigned free_bf_bmap;
351 void __iomem *bf_map;
355 unsigned long offset;
357 struct mlx4_uar *uar;
362 void (*comp) (struct mlx4_cq *);
363 void (*event) (struct mlx4_cq *, enum mlx4_event);
365 struct mlx4_uar *uar;
377 struct completion free;
381 void (*event) (struct mlx4_qp *, enum mlx4_event);
386 struct completion free;
390 void (*event) (struct mlx4_srq *, enum mlx4_event);
398 struct completion free;
410 __be32 sl_tclass_flowlabel;
423 __be32 sl_tclass_flowlabel;
432 struct mlx4_eth_av eth;
435 struct mlx4_counters {
445 struct mlx4_counters_ext {
449 __be64 rx_uni_frames;
451 __be64 rx_mcast_frames;
452 __be64 rx_mcast_bytes;
453 __be64 rx_bcast_frames;
454 __be64 rx_bcast_bytes;
455 __be64 rx_nobuf_frames;
456 __be64 rx_nobuf_bytes;
457 __be64 rx_err_frames;
459 __be64 tx_uni_frames;
461 __be64 tx_mcast_frames;
462 __be64 tx_mcast_bytes;
463 __be64 tx_bcast_frames;
464 __be64 tx_bcast_bytes;
465 __be64 tx_nobuf_frames;
466 __be64 tx_nobuf_bytes;
467 __be64 tx_err_frames;
472 struct pci_dev *pdev;
474 struct mlx4_caps caps;
475 struct radix_tree_root qp_table_tree;
476 struct radix_tree_root srq_table_tree;
478 char board_id[MLX4_BOARD_ID_LEN];
481 struct mlx4_init_port_param {
495 static inline void mlx4_query_steer_cap(struct mlx4_dev *dev, int *log_mac,
496 int *log_vlan, int *log_prio)
498 *log_mac = dev->caps.log_num_macs;
499 *log_vlan = dev->caps.log_num_vlans;
500 *log_prio = dev->caps.log_num_prios;
503 #define mlx4_foreach_port(port, dev, type) \
504 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
505 if ((type) == (dev)->caps.port_mask[(port)])
507 #define mlx4_foreach_ib_transport_port(port, dev) \
508 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
509 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
510 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
512 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
513 struct mlx4_buf *buf);
514 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
515 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
517 if (buf->direct.buf != NULL)
518 return buf->direct.buf + offset;
520 return buf->page_list[offset >> PAGE_SHIFT].buf +
521 (offset & (PAGE_SIZE - 1));
524 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
525 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
527 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
528 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
530 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
531 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
532 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
533 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
535 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
536 struct mlx4_mtt *mtt);
537 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
538 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
539 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
540 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
543 int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align, u32 *base_mridx);
544 void mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt);
545 int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
546 u64 iova, u64 size, u32 access, int npages,
547 int page_shift, struct mlx4_mr *mr);
548 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
549 int npages, int page_shift, struct mlx4_mr *mr);
550 void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr);
551 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
552 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
553 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
554 int start_index, int npages, u64 *page_list);
555 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
556 struct mlx4_buf *buf);
558 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
559 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
561 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
562 int size, int max_direct);
563 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
566 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
567 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
568 unsigned vector, int collapsed);
569 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
571 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
572 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
574 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
575 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
577 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd,
578 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
579 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
580 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
581 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
583 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
584 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
586 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
587 int block_mcast_loopback, enum mlx4_mcast_prot prot);
588 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
589 enum mlx4_mcast_prot prot);
591 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
592 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
594 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
595 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
596 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
598 int mlx4_map_phys_fmr_fbo(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
599 u64 *page_list, int npages, u64 iova, u32 fbo,
600 u32 len, u32 *lkey, u32 *rkey, int same_key);
601 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
602 int npages, u64 iova, u32 *lkey, u32 *rkey);
603 int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
604 u32 access, int max_pages, int max_maps,
605 u8 page_shift, struct mlx4_fmr *fmr);
606 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
607 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
608 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
609 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
610 u32 *lkey, u32 *rkey);
611 int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
612 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
613 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
614 int mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length,
615 u8 op_modifier, u32 in_offset[], u32 counter_out[]);
616 int mlx4_test_interrupts(struct mlx4_dev *dev);
618 void mlx4_get_fc_t11_settings(struct mlx4_dev *dev, int *enable_pre_t11, int *t11_supported);
620 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
621 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
623 #endif /* MLX4_DEVICE_H */