2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Some hw specific parts of this pmap were derived or influenced
27 * by NetBSD's ibm4xx pmap module. More generic code is shared with
28 * a few other pmap modules from the FreeBSD tree.
34 * Kernel and user threads run within one common virtual address space
37 * Virtual address space layout:
38 * -----------------------------
39 * 0x0000_0000 - 0xafff_ffff : user process
40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
43 * 0xc100_0000 - 0xfeef_ffff : KVA
44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region
51 #include <sys/cdefs.h>
52 __FBSDID("$FreeBSD$");
54 #include <sys/types.h>
55 #include <sys/param.h>
56 #include <sys/malloc.h>
60 #include <sys/queue.h>
61 #include <sys/systm.h>
62 #include <sys/kernel.h>
63 #include <sys/linker.h>
64 #include <sys/msgbuf.h>
66 #include <sys/mutex.h>
67 #include <sys/sched.h>
69 #include <sys/vmmeter.h>
72 #include <vm/vm_page.h>
73 #include <vm/vm_kern.h>
74 #include <vm/vm_pageout.h>
75 #include <vm/vm_extern.h>
76 #include <vm/vm_object.h>
77 #include <vm/vm_param.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_pager.h>
82 #include <machine/cpu.h>
83 #include <machine/pcb.h>
84 #include <machine/platform.h>
86 #include <machine/tlb.h>
87 #include <machine/spr.h>
88 #include <machine/vmparam.h>
89 #include <machine/md_var.h>
90 #include <machine/mmuvar.h>
91 #include <machine/pmap.h>
92 #include <machine/pte.h>
97 #define debugf(fmt, args...) printf(fmt, ##args)
99 #define debugf(fmt, args...)
102 #define TODO panic("%s: not implemented", __func__);
104 #include "opt_sched.h"
106 #error "e500 only works with SCHED_4BSD which uses a global scheduler lock."
108 extern struct mtx sched_lock;
110 extern int dumpsys_minidump;
112 extern unsigned char _etext[];
113 extern unsigned char _end[];
115 extern uint32_t *bootinfo;
118 extern uint32_t kernload_ap;
122 vm_offset_t kernstart;
125 /* Message buffer and tables. */
126 static vm_offset_t data_start;
127 static vm_size_t data_end;
129 /* Phys/avail memory regions. */
130 static struct mem_region *availmem_regions;
131 static int availmem_regions_sz;
132 static struct mem_region *physmem_regions;
133 static int physmem_regions_sz;
135 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
136 static vm_offset_t zero_page_va;
137 static struct mtx zero_page_mutex;
139 static struct mtx tlbivax_mutex;
142 * Reserved KVA space for mmu_booke_zero_page_idle. This is used
143 * by idle thred only, no lock required.
145 static vm_offset_t zero_page_idle_va;
147 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
148 static vm_offset_t copy_page_src_va;
149 static vm_offset_t copy_page_dst_va;
150 static struct mtx copy_page_mutex;
152 /**************************************************************************/
154 /**************************************************************************/
156 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
157 vm_prot_t, boolean_t);
159 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
160 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
163 * If user pmap is processed with mmu_booke_remove and the resident count
164 * drops to 0, there are no more pages to remove, so we need not continue.
166 #define PMAP_REMOVE_DONE(pmap) \
167 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
169 extern void tid_flush(tlbtid_t);
171 /**************************************************************************/
172 /* TLB and TID handling */
173 /**************************************************************************/
175 /* Translation ID busy table */
176 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
179 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
180 * core revisions and should be read from h/w registers during early config.
182 uint32_t tlb0_entries;
184 uint32_t tlb0_entries_per_way;
186 #define TLB0_ENTRIES (tlb0_entries)
187 #define TLB0_WAYS (tlb0_ways)
188 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
190 #define TLB1_ENTRIES 16
192 /* In-ram copy of the TLB1 */
193 static tlb_entry_t tlb1[TLB1_ENTRIES];
195 /* Next free entry in the TLB1 */
196 static unsigned int tlb1_idx;
198 static tlbtid_t tid_alloc(struct pmap *);
200 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
202 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t);
203 static void tlb1_write_entry(unsigned int);
204 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
205 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
207 static vm_size_t tsize2size(unsigned int);
208 static unsigned int size2tsize(vm_size_t);
209 static unsigned int ilog2(unsigned int);
211 static void set_mas4_defaults(void);
213 static inline void tlb0_flush_entry(vm_offset_t);
214 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
216 /**************************************************************************/
217 /* Page table management */
218 /**************************************************************************/
220 /* Data for the pv entry allocation mechanism */
221 static uma_zone_t pvzone;
222 static struct vm_object pvzone_obj;
223 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
225 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
227 #ifndef PMAP_SHPGPERPROC
228 #define PMAP_SHPGPERPROC 200
231 static void ptbl_init(void);
232 static struct ptbl_buf *ptbl_buf_alloc(void);
233 static void ptbl_buf_free(struct ptbl_buf *);
234 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
236 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int);
237 static void ptbl_free(mmu_t, pmap_t, unsigned int);
238 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
239 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
241 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
242 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
243 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t);
244 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
246 static pv_entry_t pv_alloc(void);
247 static void pv_free(pv_entry_t);
248 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
249 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
251 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
252 #define PTBL_BUFS (128 * 16)
255 TAILQ_ENTRY(ptbl_buf) link; /* list link */
256 vm_offset_t kva; /* va of mapping */
259 /* ptbl free list and a lock used for access synchronization. */
260 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
261 static struct mtx ptbl_buf_freelist_lock;
263 /* Base address of kva space allocated fot ptbl bufs. */
264 static vm_offset_t ptbl_buf_pool_vabase;
266 /* Pointer to ptbl_buf structures. */
267 static struct ptbl_buf *ptbl_bufs;
269 void pmap_bootstrap_ap(volatile uint32_t *);
272 * Kernel MMU interface
274 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
275 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
276 static void mmu_booke_clear_reference(mmu_t, vm_page_t);
277 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
278 vm_size_t, vm_offset_t);
279 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
280 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
281 vm_prot_t, boolean_t);
282 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
283 vm_page_t, vm_prot_t);
284 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
286 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
287 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
289 static void mmu_booke_init(mmu_t);
290 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
291 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
292 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
293 static boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t);
294 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t,
296 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
298 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
299 vm_object_t, vm_pindex_t, vm_size_t);
300 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
301 static void mmu_booke_page_init(mmu_t, vm_page_t);
302 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
303 static void mmu_booke_pinit(mmu_t, pmap_t);
304 static void mmu_booke_pinit0(mmu_t, pmap_t);
305 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
307 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
308 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
309 static void mmu_booke_release(mmu_t, pmap_t);
310 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
311 static void mmu_booke_remove_all(mmu_t, vm_page_t);
312 static void mmu_booke_remove_write(mmu_t, vm_page_t);
313 static void mmu_booke_zero_page(mmu_t, vm_page_t);
314 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
315 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t);
316 static void mmu_booke_activate(mmu_t, struct thread *);
317 static void mmu_booke_deactivate(mmu_t, struct thread *);
318 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
319 static void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t);
320 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
321 static vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t);
322 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t);
323 static void mmu_booke_kremove(mmu_t, vm_offset_t);
324 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
325 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
327 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *,
328 vm_size_t, vm_size_t *);
329 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *,
330 vm_size_t, vm_offset_t);
331 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *);
333 static mmu_method_t mmu_booke_methods[] = {
334 /* pmap dispatcher interface */
335 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring),
336 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
337 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference),
338 MMUMETHOD(mmu_copy, mmu_booke_copy),
339 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
340 MMUMETHOD(mmu_enter, mmu_booke_enter),
341 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
342 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
343 MMUMETHOD(mmu_extract, mmu_booke_extract),
344 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
345 MMUMETHOD(mmu_init, mmu_booke_init),
346 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
347 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
348 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
349 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
350 MMUMETHOD(mmu_map, mmu_booke_map),
351 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
352 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
353 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
354 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
355 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
356 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
357 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
358 MMUMETHOD(mmu_protect, mmu_booke_protect),
359 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
360 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
361 MMUMETHOD(mmu_release, mmu_booke_release),
362 MMUMETHOD(mmu_remove, mmu_booke_remove),
363 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
364 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
365 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
366 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
367 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
368 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
369 MMUMETHOD(mmu_activate, mmu_booke_activate),
370 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
372 /* Internal interfaces */
373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
376 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
377 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
378 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
379 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
381 /* dumpsys() support */
382 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
383 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
384 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md),
389 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
400 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
403 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
404 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
406 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
407 ("tlb_miss_lock: tried to lock self"));
409 tlb_lock(pc->pc_booke_tlb_lock);
411 CTR1(KTR_PMAP, "%s: locked", __func__);
418 tlb_miss_unlock(void)
426 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
428 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
429 __func__, pc->pc_cpuid);
431 tlb_unlock(pc->pc_booke_tlb_lock);
433 CTR1(KTR_PMAP, "%s: unlocked", __func__);
439 /* Return number of entries in TLB0. */
441 tlb0_get_tlbconf(void)
445 tlb0_cfg = mfspr(SPR_TLB0CFG);
446 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
447 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
448 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
451 /* Initialize pool of kva ptbl buffers. */
457 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
458 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
459 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
460 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
462 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
463 TAILQ_INIT(&ptbl_buf_freelist);
465 for (i = 0; i < PTBL_BUFS; i++) {
466 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
467 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
471 /* Get a ptbl_buf from the freelist. */
472 static struct ptbl_buf *
475 struct ptbl_buf *buf;
477 mtx_lock(&ptbl_buf_freelist_lock);
478 buf = TAILQ_FIRST(&ptbl_buf_freelist);
480 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
481 mtx_unlock(&ptbl_buf_freelist_lock);
483 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
488 /* Return ptbl buff to free pool. */
490 ptbl_buf_free(struct ptbl_buf *buf)
493 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
495 mtx_lock(&ptbl_buf_freelist_lock);
496 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
497 mtx_unlock(&ptbl_buf_freelist_lock);
501 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
504 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
506 struct ptbl_buf *pbuf;
508 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
510 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
512 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
513 if (pbuf->kva == (vm_offset_t)ptbl) {
514 /* Remove from pmap ptbl buf list. */
515 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
517 /* Free corresponding ptbl buf. */
523 /* Allocate page table. */
525 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
527 vm_page_t mtbl[PTBL_PAGES];
529 struct ptbl_buf *pbuf;
534 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
535 (pmap == kernel_pmap), pdir_idx);
537 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
538 ("ptbl_alloc: invalid pdir_idx"));
539 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
540 ("pte_alloc: valid ptbl entry exists!"));
542 pbuf = ptbl_buf_alloc();
544 panic("pte_alloc: couldn't alloc kernel virtual memory");
546 ptbl = (pte_t *)pbuf->kva;
548 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
550 /* Allocate ptbl pages, this will sleep! */
551 for (i = 0; i < PTBL_PAGES; i++) {
552 pidx = (PTBL_PAGES * pdir_idx) + i;
553 while ((m = vm_page_alloc(NULL, pidx,
554 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
557 vm_page_unlock_queues();
559 vm_page_lock_queues();
565 /* Map allocated pages into kernel_pmap. */
566 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
568 /* Zero whole ptbl. */
569 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
571 /* Add pbuf to the pmap ptbl bufs list. */
572 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
577 /* Free ptbl pages and invalidate pdir entry. */
579 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
587 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
588 (pmap == kernel_pmap), pdir_idx);
590 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
591 ("ptbl_free: invalid pdir_idx"));
593 ptbl = pmap->pm_pdir[pdir_idx];
595 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
597 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
600 * Invalidate the pdir entry as soon as possible, so that other CPUs
601 * don't attempt to look up the page tables we are releasing.
603 mtx_lock_spin(&tlbivax_mutex);
606 pmap->pm_pdir[pdir_idx] = NULL;
609 mtx_unlock_spin(&tlbivax_mutex);
611 for (i = 0; i < PTBL_PAGES; i++) {
612 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
613 pa = pte_vatopa(mmu, kernel_pmap, va);
614 m = PHYS_TO_VM_PAGE(pa);
615 vm_page_free_zero(m);
616 atomic_subtract_int(&cnt.v_wire_count, 1);
617 mmu_booke_kremove(mmu, va);
620 ptbl_free_pmap_ptbl(pmap, ptbl);
624 * Decrement ptbl pages hold count and attempt to free ptbl pages.
625 * Called when removing pte entry from ptbl.
627 * Return 1 if ptbl pages were freed.
630 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
637 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
638 (pmap == kernel_pmap), pdir_idx);
640 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
641 ("ptbl_unhold: invalid pdir_idx"));
642 KASSERT((pmap != kernel_pmap),
643 ("ptbl_unhold: unholding kernel ptbl!"));
645 ptbl = pmap->pm_pdir[pdir_idx];
647 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
648 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
649 ("ptbl_unhold: non kva ptbl"));
651 /* decrement hold count */
652 for (i = 0; i < PTBL_PAGES; i++) {
653 pa = pte_vatopa(mmu, kernel_pmap,
654 (vm_offset_t)ptbl + (i * PAGE_SIZE));
655 m = PHYS_TO_VM_PAGE(pa);
660 * Free ptbl pages if there are no pte etries in this ptbl.
661 * wire_count has the same value for all ptbl pages, so check the last
664 if (m->wire_count == 0) {
665 ptbl_free(mmu, pmap, pdir_idx);
667 //debugf("ptbl_unhold: e (freed ptbl)\n");
675 * Increment hold count for ptbl pages. This routine is used when a new pte
676 * entry is being inserted into the ptbl.
679 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
686 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
689 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
690 ("ptbl_hold: invalid pdir_idx"));
691 KASSERT((pmap != kernel_pmap),
692 ("ptbl_hold: holding kernel ptbl!"));
694 ptbl = pmap->pm_pdir[pdir_idx];
696 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
698 for (i = 0; i < PTBL_PAGES; i++) {
699 pa = pte_vatopa(mmu, kernel_pmap,
700 (vm_offset_t)ptbl + (i * PAGE_SIZE));
701 m = PHYS_TO_VM_PAGE(pa);
706 /* Allocate pv_entry structure. */
713 if (pv_entry_count > pv_entry_high_water)
715 pv = uma_zalloc(pvzone, M_NOWAIT);
720 /* Free pv_entry structure. */
722 pv_free(pv_entry_t pve)
726 uma_zfree(pvzone, pve);
730 /* Allocate and initialize pv_entry structure. */
732 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
736 //int su = (pmap == kernel_pmap);
737 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
738 // (u_int32_t)pmap, va, (u_int32_t)m);
742 panic("pv_insert: no pv entries!");
748 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
749 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
751 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
753 //debugf("pv_insert: e\n");
756 /* Destroy pv entry. */
758 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
762 //int su = (pmap == kernel_pmap);
763 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
765 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
766 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
769 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
770 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
771 /* remove from pv_list */
772 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
773 if (TAILQ_EMPTY(&m->md.pv_list))
774 vm_page_aflag_clear(m, PGA_WRITEABLE);
776 /* free pv entry struct */
782 //debugf("pv_remove: e\n");
786 * Clean pte entry, try to free page table page if requested.
788 * Return 1 if ptbl pages were freed, otherwise return 0.
791 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
793 unsigned int pdir_idx = PDIR_IDX(va);
794 unsigned int ptbl_idx = PTBL_IDX(va);
799 //int su = (pmap == kernel_pmap);
800 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
801 // su, (u_int32_t)pmap, va, flags);
803 ptbl = pmap->pm_pdir[pdir_idx];
804 KASSERT(ptbl, ("pte_remove: null ptbl"));
806 pte = &ptbl[ptbl_idx];
808 if (pte == NULL || !PTE_ISVALID(pte))
811 if (PTE_ISWIRED(pte))
812 pmap->pm_stats.wired_count--;
814 /* Handle managed entry. */
815 if (PTE_ISMANAGED(pte)) {
816 /* Get vm_page_t for mapped pte. */
817 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
819 if (PTE_ISMODIFIED(pte))
822 if (PTE_ISREFERENCED(pte))
823 vm_page_aflag_set(m, PGA_REFERENCED);
825 pv_remove(pmap, va, m);
828 mtx_lock_spin(&tlbivax_mutex);
831 tlb0_flush_entry(va);
836 mtx_unlock_spin(&tlbivax_mutex);
838 pmap->pm_stats.resident_count--;
840 if (flags & PTBL_UNHOLD) {
841 //debugf("pte_remove: e (unhold)\n");
842 return (ptbl_unhold(mmu, pmap, pdir_idx));
845 //debugf("pte_remove: e\n");
850 * Insert PTE for a given page and virtual address.
853 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags)
855 unsigned int pdir_idx = PDIR_IDX(va);
856 unsigned int ptbl_idx = PTBL_IDX(va);
859 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
860 pmap == kernel_pmap, pmap, va);
862 /* Get the page table pointer. */
863 ptbl = pmap->pm_pdir[pdir_idx];
866 /* Allocate page table pages. */
867 ptbl = ptbl_alloc(mmu, pmap, pdir_idx);
870 * Check if there is valid mapping for requested
871 * va, if there is, remove it.
873 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
874 if (PTE_ISVALID(pte)) {
875 pte_remove(mmu, pmap, va, PTBL_HOLD);
878 * pte is not used, increment hold count
881 if (pmap != kernel_pmap)
882 ptbl_hold(mmu, pmap, pdir_idx);
887 * Insert pv_entry into pv_list for mapped page if part of managed
890 if ((m->oflags & VPO_UNMANAGED) == 0) {
891 flags |= PTE_MANAGED;
893 /* Create and insert pv entry. */
894 pv_insert(pmap, va, m);
897 pmap->pm_stats.resident_count++;
899 mtx_lock_spin(&tlbivax_mutex);
902 tlb0_flush_entry(va);
903 if (pmap->pm_pdir[pdir_idx] == NULL) {
905 * If we just allocated a new page table, hook it in
908 pmap->pm_pdir[pdir_idx] = ptbl;
910 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
911 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
912 pte->flags |= (PTE_VALID | flags);
915 mtx_unlock_spin(&tlbivax_mutex);
918 /* Return the pa for the given pmap/va. */
920 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
925 pte = pte_find(mmu, pmap, va);
926 if ((pte != NULL) && PTE_ISVALID(pte))
927 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
931 /* Get a pointer to a PTE in a page table. */
933 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
935 unsigned int pdir_idx = PDIR_IDX(va);
936 unsigned int ptbl_idx = PTBL_IDX(va);
938 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
940 if (pmap->pm_pdir[pdir_idx])
941 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
946 /**************************************************************************/
948 /**************************************************************************/
951 * This is called during booke_init, before the system is really initialized.
954 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
956 vm_offset_t phys_kernelend;
957 struct mem_region *mp, *mp1;
960 u_int phys_avail_count;
961 vm_size_t physsz, hwphyssz, kstack0_sz;
962 vm_offset_t kernel_pdir, kstack0, va;
963 vm_paddr_t kstack0_phys;
967 debugf("mmu_booke_bootstrap: entered\n");
970 kernload_ap = kernload;
974 /* Initialize invalidation mutex */
975 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
977 /* Read TLB0 size and associativity. */
981 * Align kernel start and end address (kernel image).
982 * Note that kernel end does not necessarily relate to kernsize.
983 * kernsize is the size of the kernel that is actually mapped.
985 kernstart = trunc_page(start);
986 data_start = round_page(kernelend);
987 data_end = data_start;
990 * Addresses of preloaded modules (like file systems) use
991 * physical addresses. Make sure we relocate those into
994 preload_addr_relocate = kernstart - kernload;
996 /* Allocate the dynamic per-cpu area. */
997 dpcpu = (void *)data_end;
998 data_end += DPCPU_SIZE;
1000 /* Allocate space for the message buffer. */
1001 msgbufp = (struct msgbuf *)data_end;
1002 data_end += msgbufsize;
1003 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
1006 data_end = round_page(data_end);
1008 /* Allocate space for ptbl_bufs. */
1009 ptbl_bufs = (struct ptbl_buf *)data_end;
1010 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1011 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
1014 data_end = round_page(data_end);
1016 /* Allocate PTE tables for kernel KVA. */
1017 kernel_pdir = data_end;
1018 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1019 PDIR_SIZE - 1) / PDIR_SIZE;
1020 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1021 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1022 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1024 debugf(" data_end: 0x%08x\n", data_end);
1025 if (data_end - kernstart > kernsize) {
1026 kernsize += tlb1_mapin_region(kernstart + kernsize,
1027 kernload + kernsize, (data_end - kernstart) - kernsize);
1029 data_end = kernstart + kernsize;
1030 debugf(" updated data_end: 0x%08x\n", data_end);
1033 * Clear the structures - note we can only do it safely after the
1034 * possible additional TLB1 translations are in place (above) so that
1035 * all range up to the currently calculated 'data_end' is covered.
1037 dpcpu_init(dpcpu, 0);
1038 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1039 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1041 /*******************************************************/
1042 /* Set the start and end of kva. */
1043 /*******************************************************/
1044 virtual_avail = round_page(data_end);
1045 virtual_end = VM_MAX_KERNEL_ADDRESS;
1047 /* Allocate KVA space for page zero/copy operations. */
1048 zero_page_va = virtual_avail;
1049 virtual_avail += PAGE_SIZE;
1050 zero_page_idle_va = virtual_avail;
1051 virtual_avail += PAGE_SIZE;
1052 copy_page_src_va = virtual_avail;
1053 virtual_avail += PAGE_SIZE;
1054 copy_page_dst_va = virtual_avail;
1055 virtual_avail += PAGE_SIZE;
1056 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1057 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1058 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1059 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1061 /* Initialize page zero/copy mutexes. */
1062 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1063 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1065 /* Allocate KVA space for ptbl bufs. */
1066 ptbl_buf_pool_vabase = virtual_avail;
1067 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1068 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1069 ptbl_buf_pool_vabase, virtual_avail);
1071 /* Calculate corresponding physical addresses for the kernel region. */
1072 phys_kernelend = kernload + kernsize;
1073 debugf("kernel image and allocated data:\n");
1074 debugf(" kernload = 0x%08x\n", kernload);
1075 debugf(" kernstart = 0x%08x\n", kernstart);
1076 debugf(" kernsize = 0x%08x\n", kernsize);
1078 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1079 panic("mmu_booke_bootstrap: phys_avail too small");
1082 * Remove kernel physical address range from avail regions list. Page
1083 * align all regions. Non-page aligned memory isn't very interesting
1084 * to us. Also, sort the entries for ascending addresses.
1087 /* Retrieve phys/avail mem regions */
1088 mem_regions(&physmem_regions, &physmem_regions_sz,
1089 &availmem_regions, &availmem_regions_sz);
1091 cnt = availmem_regions_sz;
1092 debugf("processing avail regions:\n");
1093 for (mp = availmem_regions; mp->mr_size; mp++) {
1095 e = mp->mr_start + mp->mr_size;
1096 debugf(" %08x-%08x -> ", s, e);
1097 /* Check whether this region holds all of the kernel. */
1098 if (s < kernload && e > phys_kernelend) {
1099 availmem_regions[cnt].mr_start = phys_kernelend;
1100 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1103 /* Look whether this regions starts within the kernel. */
1104 if (s >= kernload && s < phys_kernelend) {
1105 if (e <= phys_kernelend)
1109 /* Now look whether this region ends within the kernel. */
1110 if (e > kernload && e <= phys_kernelend) {
1115 /* Now page align the start and size of the region. */
1121 debugf("%08x-%08x = %x\n", s, e, sz);
1123 /* Check whether some memory is left here. */
1127 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1133 /* Do an insertion sort. */
1134 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1135 if (s < mp1->mr_start)
1138 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1146 availmem_regions_sz = cnt;
1148 /*******************************************************/
1149 /* Steal physical memory for kernel stack from the end */
1150 /* of the first avail region */
1151 /*******************************************************/
1152 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1153 kstack0_phys = availmem_regions[0].mr_start +
1154 availmem_regions[0].mr_size;
1155 kstack0_phys -= kstack0_sz;
1156 availmem_regions[0].mr_size -= kstack0_sz;
1158 /*******************************************************/
1159 /* Fill in phys_avail table, based on availmem_regions */
1160 /*******************************************************/
1161 phys_avail_count = 0;
1164 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1166 debugf("fill in phys_avail:\n");
1167 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1169 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1170 availmem_regions[i].mr_start,
1171 availmem_regions[i].mr_start +
1172 availmem_regions[i].mr_size,
1173 availmem_regions[i].mr_size);
1175 if (hwphyssz != 0 &&
1176 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1177 debugf(" hw.physmem adjust\n");
1178 if (physsz < hwphyssz) {
1179 phys_avail[j] = availmem_regions[i].mr_start;
1181 availmem_regions[i].mr_start +
1189 phys_avail[j] = availmem_regions[i].mr_start;
1190 phys_avail[j + 1] = availmem_regions[i].mr_start +
1191 availmem_regions[i].mr_size;
1193 physsz += availmem_regions[i].mr_size;
1195 physmem = btoc(physsz);
1197 /* Calculate the last available physical address. */
1198 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1200 Maxmem = powerpc_btop(phys_avail[i + 1]);
1202 debugf("Maxmem = 0x%08lx\n", Maxmem);
1203 debugf("phys_avail_count = %d\n", phys_avail_count);
1204 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1207 /*******************************************************/
1208 /* Initialize (statically allocated) kernel pmap. */
1209 /*******************************************************/
1210 PMAP_LOCK_INIT(kernel_pmap);
1211 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1213 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1214 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1215 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1216 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1218 /* Initialize kernel pdir */
1219 for (i = 0; i < kernel_ptbls; i++)
1220 kernel_pmap->pm_pdir[kptbl_min + i] =
1221 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1223 for (i = 0; i < MAXCPU; i++) {
1224 kernel_pmap->pm_tid[i] = TID_KERNEL;
1226 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1227 tidbusy[i][0] = kernel_pmap;
1231 * Fill in PTEs covering kernel code and data. They are not required
1232 * for address translation, as this area is covered by static TLB1
1233 * entries, but for pte_vatopa() to work correctly with kernel area
1236 for (va = KERNBASE; va < data_end; va += PAGE_SIZE) {
1237 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1238 pte->rpn = kernload + (va - KERNBASE);
1239 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1242 /* Mark kernel_pmap active on all CPUs */
1243 CPU_FILL(&kernel_pmap->pm_active);
1245 /*******************************************************/
1247 /*******************************************************/
1249 /* Enter kstack0 into kernel map, provide guard page */
1250 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1251 thread0.td_kstack = kstack0;
1252 thread0.td_kstack_pages = KSTACK_PAGES;
1254 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1255 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1256 kstack0_phys, kstack0_phys + kstack0_sz);
1257 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1259 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1260 for (i = 0; i < KSTACK_PAGES; i++) {
1261 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1262 kstack0 += PAGE_SIZE;
1263 kstack0_phys += PAGE_SIZE;
1266 debugf("virtual_avail = %08x\n", virtual_avail);
1267 debugf("virtual_end = %08x\n", virtual_end);
1269 debugf("mmu_booke_bootstrap: exit\n");
1273 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1278 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1279 * have the snapshot of its contents in the s/w tlb1[] table, so use
1280 * these values directly to (re)program AP's TLB1 hardware.
1282 for (i = 0; i < tlb1_idx; i ++) {
1283 /* Skip invalid entries */
1284 if (!(tlb1[i].mas1 & MAS1_VALID))
1287 tlb1_write_entry(i);
1290 set_mas4_defaults();
1294 * Get the physical page address for the given pmap/virtual address.
1297 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1302 pa = pte_vatopa(mmu, pmap, va);
1309 * Extract the physical page address associated with the given
1310 * kernel virtual address.
1313 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1316 return (pte_vatopa(mmu, kernel_pmap, va));
1320 * Initialize the pmap module.
1321 * Called by vm_init, to initialize any structures that the pmap
1322 * system needs to map virtual memory.
1325 mmu_booke_init(mmu_t mmu)
1327 int shpgperproc = PMAP_SHPGPERPROC;
1330 * Initialize the address space (zone) for the pv entries. Set a
1331 * high water mark so that the system can recover from excessive
1332 * numbers of pv entries.
1334 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1335 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1337 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1338 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1340 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1341 pv_entry_high_water = 9 * (pv_entry_max / 10);
1343 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1345 /* Pre-fill pvzone with initial number of pv entries. */
1346 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1348 /* Initialize ptbl allocation. */
1353 * Map a list of wired pages into kernel virtual address space. This is
1354 * intended for temporary mappings which do not need page modification or
1355 * references recorded. Existing mappings in the region are overwritten.
1358 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1363 while (count-- > 0) {
1364 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1371 * Remove page mappings from kernel virtual address space. Intended for
1372 * temporary mappings entered by mmu_booke_qenter.
1375 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1380 while (count-- > 0) {
1381 mmu_booke_kremove(mmu, va);
1387 * Map a wired page into kernel virtual address space.
1390 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1392 unsigned int pdir_idx = PDIR_IDX(va);
1393 unsigned int ptbl_idx = PTBL_IDX(va);
1397 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1398 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1401 flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID);
1404 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1406 mtx_lock_spin(&tlbivax_mutex);
1409 if (PTE_ISVALID(pte)) {
1411 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1413 /* Flush entry from TLB0 */
1414 tlb0_flush_entry(va);
1417 pte->rpn = pa & ~PTE_PA_MASK;
1420 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1421 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1422 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1424 /* Flush the real memory from the instruction cache. */
1425 if ((flags & (PTE_I | PTE_G)) == 0) {
1426 __syncicache((void *)va, PAGE_SIZE);
1430 mtx_unlock_spin(&tlbivax_mutex);
1434 * Remove a page from kernel page table.
1437 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1439 unsigned int pdir_idx = PDIR_IDX(va);
1440 unsigned int ptbl_idx = PTBL_IDX(va);
1443 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1445 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1446 (va <= VM_MAX_KERNEL_ADDRESS)),
1447 ("mmu_booke_kremove: invalid va"));
1449 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1451 if (!PTE_ISVALID(pte)) {
1453 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1458 mtx_lock_spin(&tlbivax_mutex);
1461 /* Invalidate entry in TLB0, update PTE. */
1462 tlb0_flush_entry(va);
1467 mtx_unlock_spin(&tlbivax_mutex);
1471 * Initialize pmap associated with process 0.
1474 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1477 mmu_booke_pinit(mmu, pmap);
1478 PCPU_SET(curpmap, pmap);
1482 * Initialize a preallocated and zeroed pmap structure,
1483 * such as one in a vmspace structure.
1486 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1490 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1491 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1493 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1495 PMAP_LOCK_INIT(pmap);
1496 for (i = 0; i < MAXCPU; i++)
1497 pmap->pm_tid[i] = TID_NONE;
1498 CPU_ZERO(&kernel_pmap->pm_active);
1499 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1500 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1501 TAILQ_INIT(&pmap->pm_ptbl_list);
1505 * Release any resources held by the given physical map.
1506 * Called when a pmap initialized by mmu_booke_pinit is being released.
1507 * Should only be called if the map contains no valid mappings.
1510 mmu_booke_release(mmu_t mmu, pmap_t pmap)
1513 KASSERT(pmap->pm_stats.resident_count == 0,
1514 ("pmap_release: pmap resident count %ld != 0",
1515 pmap->pm_stats.resident_count));
1517 PMAP_LOCK_DESTROY(pmap);
1521 * Insert the given physical page at the specified virtual address in the
1522 * target physical map with the protection requested. If specified the page
1523 * will be wired down.
1526 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1527 vm_prot_t prot, boolean_t wired)
1530 vm_page_lock_queues();
1532 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired);
1533 vm_page_unlock_queues();
1538 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1539 vm_prot_t prot, boolean_t wired)
1546 pa = VM_PAGE_TO_PHYS(m);
1547 su = (pmap == kernel_pmap);
1550 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1551 // "pa=0x%08x prot=0x%08x wired=%d)\n",
1552 // (u_int32_t)pmap, su, pmap->pm_tid,
1553 // (u_int32_t)m, va, pa, prot, wired);
1556 KASSERT(((va >= virtual_avail) &&
1557 (va <= VM_MAX_KERNEL_ADDRESS)),
1558 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1560 KASSERT((va <= VM_MAXUSER_ADDRESS),
1561 ("mmu_booke_enter_locked: user pmap, non user va"));
1563 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
1564 VM_OBJECT_LOCKED(m->object),
1565 ("mmu_booke_enter_locked: page %p is not busy", m));
1567 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1570 * If there is an existing mapping, and the physical address has not
1571 * changed, must be protection or wiring change.
1573 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1574 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1577 * Before actually updating pte->flags we calculate and
1578 * prepare its new value in a helper var.
1581 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1583 /* Wiring change, just update stats. */
1585 if (!PTE_ISWIRED(pte)) {
1587 pmap->pm_stats.wired_count++;
1590 if (PTE_ISWIRED(pte)) {
1591 flags &= ~PTE_WIRED;
1592 pmap->pm_stats.wired_count--;
1596 if (prot & VM_PROT_WRITE) {
1597 /* Add write permissions. */
1602 if ((flags & PTE_MANAGED) != 0)
1603 vm_page_aflag_set(m, PGA_WRITEABLE);
1605 /* Handle modified pages, sense modify status. */
1608 * The PTE_MODIFIED flag could be set by underlying
1609 * TLB misses since we last read it (above), possibly
1610 * other CPUs could update it so we check in the PTE
1611 * directly rather than rely on that saved local flags
1614 if (PTE_ISMODIFIED(pte))
1618 if (prot & VM_PROT_EXECUTE) {
1624 * Check existing flags for execute permissions: if we
1625 * are turning execute permissions on, icache should
1628 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1632 flags &= ~PTE_REFERENCED;
1635 * The new flags value is all calculated -- only now actually
1638 mtx_lock_spin(&tlbivax_mutex);
1641 tlb0_flush_entry(va);
1645 mtx_unlock_spin(&tlbivax_mutex);
1649 * If there is an existing mapping, but it's for a different
1650 * physical address, pte_enter() will delete the old mapping.
1652 //if ((pte != NULL) && PTE_ISVALID(pte))
1653 // debugf("mmu_booke_enter_locked: replace\n");
1655 // debugf("mmu_booke_enter_locked: new\n");
1657 /* Now set up the flags and install the new mapping. */
1658 flags = (PTE_SR | PTE_VALID);
1664 if (prot & VM_PROT_WRITE) {
1669 if ((m->oflags & VPO_UNMANAGED) == 0)
1670 vm_page_aflag_set(m, PGA_WRITEABLE);
1673 if (prot & VM_PROT_EXECUTE) {
1679 /* If its wired update stats. */
1681 pmap->pm_stats.wired_count++;
1685 pte_enter(mmu, pmap, m, va, flags);
1687 /* Flush the real memory from the instruction cache. */
1688 if (prot & VM_PROT_EXECUTE)
1692 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1693 __syncicache((void *)va, PAGE_SIZE);
1699 * Maps a sequence of resident pages belonging to the same object.
1700 * The sequence begins with the given page m_start. This page is
1701 * mapped at the given virtual address start. Each subsequent page is
1702 * mapped at a virtual address that is offset from start by the same
1703 * amount as the page is offset from m_start within the object. The
1704 * last page in the sequence is the page with the largest offset from
1705 * m_start that can be mapped at a virtual address less than the given
1706 * virtual address end. Not every virtual page between start and end
1707 * is mapped; only those for which a resident page exists with the
1708 * corresponding offset from m_start are mapped.
1711 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1712 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1715 vm_pindex_t diff, psize;
1717 psize = atop(end - start);
1719 vm_page_lock_queues();
1721 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1722 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1723 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1724 m = TAILQ_NEXT(m, listq);
1726 vm_page_unlock_queues();
1731 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1735 vm_page_lock_queues();
1737 mmu_booke_enter_locked(mmu, pmap, va, m,
1738 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1739 vm_page_unlock_queues();
1744 * Remove the given range of addresses from the specified map.
1746 * It is assumed that the start and end are properly rounded to the page size.
1749 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1754 int su = (pmap == kernel_pmap);
1756 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1757 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1760 KASSERT(((va >= virtual_avail) &&
1761 (va <= VM_MAX_KERNEL_ADDRESS)),
1762 ("mmu_booke_remove: kernel pmap, non kernel va"));
1764 KASSERT((va <= VM_MAXUSER_ADDRESS),
1765 ("mmu_booke_remove: user pmap, non user va"));
1768 if (PMAP_REMOVE_DONE(pmap)) {
1769 //debugf("mmu_booke_remove: e (empty)\n");
1773 hold_flag = PTBL_HOLD_FLAG(pmap);
1774 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1776 vm_page_lock_queues();
1778 for (; va < endva; va += PAGE_SIZE) {
1779 pte = pte_find(mmu, pmap, va);
1780 if ((pte != NULL) && PTE_ISVALID(pte))
1781 pte_remove(mmu, pmap, va, hold_flag);
1784 vm_page_unlock_queues();
1786 //debugf("mmu_booke_remove: e\n");
1790 * Remove physical page from all pmaps in which it resides.
1793 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1798 vm_page_lock_queues();
1799 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1800 pvn = TAILQ_NEXT(pv, pv_link);
1802 PMAP_LOCK(pv->pv_pmap);
1803 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1804 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1805 PMAP_UNLOCK(pv->pv_pmap);
1807 vm_page_aflag_clear(m, PGA_WRITEABLE);
1808 vm_page_unlock_queues();
1812 * Map a range of physical addresses into kernel virtual address space.
1815 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1816 vm_offset_t pa_end, int prot)
1818 vm_offset_t sva = *virt;
1819 vm_offset_t va = sva;
1821 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1822 // sva, pa_start, pa_end);
1824 while (pa_start < pa_end) {
1825 mmu_booke_kenter(mmu, va, pa_start);
1827 pa_start += PAGE_SIZE;
1831 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1836 * The pmap must be activated before it's address space can be accessed in any
1840 mmu_booke_activate(mmu_t mmu, struct thread *td)
1845 pmap = &td->td_proc->p_vmspace->vm_pmap;
1847 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1848 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1850 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1852 mtx_lock_spin(&sched_lock);
1854 cpuid = PCPU_GET(cpuid);
1855 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1856 PCPU_SET(curpmap, pmap);
1858 if (pmap->pm_tid[cpuid] == TID_NONE)
1861 /* Load PID0 register with pmap tid value. */
1862 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1863 __asm __volatile("isync");
1865 mtx_unlock_spin(&sched_lock);
1867 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1868 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1872 * Deactivate the specified process's address space.
1875 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1879 pmap = &td->td_proc->p_vmspace->vm_pmap;
1881 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1882 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1884 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1885 PCPU_SET(curpmap, NULL);
1889 * Copy the range specified by src_addr/len
1890 * from the source map to the range dst_addr/len
1891 * in the destination map.
1893 * This routine is only advisory and need not do anything.
1896 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1897 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1903 * Set the physical protection on the specified range of this map as requested.
1906 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1913 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1914 mmu_booke_remove(mmu, pmap, sva, eva);
1918 if (prot & VM_PROT_WRITE)
1922 for (va = sva; va < eva; va += PAGE_SIZE) {
1923 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
1924 if (PTE_ISVALID(pte)) {
1925 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1927 mtx_lock_spin(&tlbivax_mutex);
1930 /* Handle modified pages. */
1931 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1934 tlb0_flush_entry(va);
1935 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1938 mtx_unlock_spin(&tlbivax_mutex);
1946 * Clear the write and modified bits in each of the given page's mappings.
1949 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
1954 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1955 ("mmu_booke_remove_write: page %p is not managed", m));
1958 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1959 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1960 * is clear, no page table entries need updating.
1962 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1963 if ((m->oflags & VPO_BUSY) == 0 &&
1964 (m->aflags & PGA_WRITEABLE) == 0)
1966 vm_page_lock_queues();
1967 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1968 PMAP_LOCK(pv->pv_pmap);
1969 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
1970 if (PTE_ISVALID(pte)) {
1971 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1973 mtx_lock_spin(&tlbivax_mutex);
1976 /* Handle modified pages. */
1977 if (PTE_ISMODIFIED(pte))
1980 /* Flush mapping from TLB0. */
1981 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1984 mtx_unlock_spin(&tlbivax_mutex);
1987 PMAP_UNLOCK(pv->pv_pmap);
1989 vm_page_aflag_clear(m, PGA_WRITEABLE);
1990 vm_page_unlock_queues();
1994 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2003 va = trunc_page(va);
2004 sz = round_page(sz);
2006 vm_page_lock_queues();
2007 pmap = PCPU_GET(curpmap);
2008 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2011 pte = pte_find(mmu, pm, va);
2012 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2018 /* Create a mapping in the active pmap. */
2020 m = PHYS_TO_VM_PAGE(pa);
2022 pte_enter(mmu, pmap, m, addr,
2023 PTE_SR | PTE_VALID | PTE_UR);
2024 __syncicache((void *)addr, PAGE_SIZE);
2025 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2028 __syncicache((void *)va, PAGE_SIZE);
2033 vm_page_unlock_queues();
2037 * Atomically extract and hold the physical page with the given
2038 * pmap and virtual address pair if that mapping permits the given
2042 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2054 pte = pte_find(mmu, pmap, va);
2055 if ((pte != NULL) && PTE_ISVALID(pte)) {
2056 if (pmap == kernel_pmap)
2061 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2062 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2064 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2075 * Initialize a vm_page's machine-dependent fields.
2078 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2081 TAILQ_INIT(&m->md.pv_list);
2085 * mmu_booke_zero_page_area zeros the specified hardware page by
2086 * mapping it into virtual memory and using bzero to clear
2089 * off and size must reside within a single page.
2092 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2096 /* XXX KASSERT off and size are within a single page? */
2098 mtx_lock(&zero_page_mutex);
2101 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2102 bzero((caddr_t)va + off, size);
2103 mmu_booke_kremove(mmu, va);
2105 mtx_unlock(&zero_page_mutex);
2109 * mmu_booke_zero_page zeros the specified hardware page.
2112 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2115 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2119 * mmu_booke_copy_page copies the specified (machine independent) page by
2120 * mapping the page into virtual memory and using memcopy to copy the page,
2121 * one machine dependent page at a time.
2124 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2126 vm_offset_t sva, dva;
2128 sva = copy_page_src_va;
2129 dva = copy_page_dst_va;
2131 mtx_lock(©_page_mutex);
2132 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2133 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2134 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2135 mmu_booke_kremove(mmu, dva);
2136 mmu_booke_kremove(mmu, sva);
2137 mtx_unlock(©_page_mutex);
2141 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2142 * into virtual memory and using bzero to clear its contents. This is intended
2143 * to be called from the vm_pagezero process only and outside of Giant. No
2147 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2151 va = zero_page_idle_va;
2152 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2153 bzero((caddr_t)va, PAGE_SIZE);
2154 mmu_booke_kremove(mmu, va);
2158 * Return whether or not the specified physical page was modified
2159 * in any of physical maps.
2162 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2168 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2169 ("mmu_booke_is_modified: page %p is not managed", m));
2173 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
2174 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2175 * is clear, no PTEs can be modified.
2177 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2178 if ((m->oflags & VPO_BUSY) == 0 &&
2179 (m->aflags & PGA_WRITEABLE) == 0)
2181 vm_page_lock_queues();
2182 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2183 PMAP_LOCK(pv->pv_pmap);
2184 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2186 if (PTE_ISMODIFIED(pte))
2189 PMAP_UNLOCK(pv->pv_pmap);
2193 vm_page_unlock_queues();
2198 * Return whether or not the specified virtual address is eligible
2202 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2209 * Return whether or not the specified physical page was referenced
2210 * in any physical maps.
2213 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2219 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2220 ("mmu_booke_is_referenced: page %p is not managed", m));
2222 vm_page_lock_queues();
2223 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2224 PMAP_LOCK(pv->pv_pmap);
2225 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2227 if (PTE_ISREFERENCED(pte))
2230 PMAP_UNLOCK(pv->pv_pmap);
2234 vm_page_unlock_queues();
2239 * Clear the modify bits on the specified physical page.
2242 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2247 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2248 ("mmu_booke_clear_modify: page %p is not managed", m));
2249 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2250 KASSERT((m->oflags & VPO_BUSY) == 0,
2251 ("mmu_booke_clear_modify: page %p is busy", m));
2254 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
2255 * If the object containing the page is locked and the page is not
2256 * VPO_BUSY, then PG_AWRITEABLE cannot be concurrently set.
2258 if ((m->aflags & PGA_WRITEABLE) == 0)
2260 vm_page_lock_queues();
2261 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2262 PMAP_LOCK(pv->pv_pmap);
2263 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2265 mtx_lock_spin(&tlbivax_mutex);
2268 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2269 tlb0_flush_entry(pv->pv_va);
2270 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2275 mtx_unlock_spin(&tlbivax_mutex);
2277 PMAP_UNLOCK(pv->pv_pmap);
2279 vm_page_unlock_queues();
2283 * Return a count of reference bits for a page, clearing those bits.
2284 * It is not necessary for every reference bit to be cleared, but it
2285 * is necessary that 0 only be returned when there are truly no
2286 * reference bits set.
2288 * XXX: The exact number of bits to check and clear is a matter that
2289 * should be tested and standardized at some point in the future for
2290 * optimal aging of shared pages.
2293 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2299 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2300 ("mmu_booke_ts_referenced: page %p is not managed", m));
2302 vm_page_lock_queues();
2303 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2304 PMAP_LOCK(pv->pv_pmap);
2305 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2307 if (PTE_ISREFERENCED(pte)) {
2308 mtx_lock_spin(&tlbivax_mutex);
2311 tlb0_flush_entry(pv->pv_va);
2312 pte->flags &= ~PTE_REFERENCED;
2315 mtx_unlock_spin(&tlbivax_mutex);
2318 PMAP_UNLOCK(pv->pv_pmap);
2323 PMAP_UNLOCK(pv->pv_pmap);
2325 vm_page_unlock_queues();
2330 * Clear the reference bit on the specified physical page.
2333 mmu_booke_clear_reference(mmu_t mmu, vm_page_t m)
2338 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2339 ("mmu_booke_clear_reference: page %p is not managed", m));
2340 vm_page_lock_queues();
2341 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2342 PMAP_LOCK(pv->pv_pmap);
2343 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2345 if (PTE_ISREFERENCED(pte)) {
2346 mtx_lock_spin(&tlbivax_mutex);
2349 tlb0_flush_entry(pv->pv_va);
2350 pte->flags &= ~PTE_REFERENCED;
2353 mtx_unlock_spin(&tlbivax_mutex);
2356 PMAP_UNLOCK(pv->pv_pmap);
2358 vm_page_unlock_queues();
2362 * Change wiring attribute for a map/virtual-address pair.
2365 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired)
2370 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2372 if (!PTE_ISWIRED(pte)) {
2373 pte->flags |= PTE_WIRED;
2374 pmap->pm_stats.wired_count++;
2377 if (PTE_ISWIRED(pte)) {
2378 pte->flags &= ~PTE_WIRED;
2379 pmap->pm_stats.wired_count--;
2387 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2388 * page. This count may be changed upwards or downwards in the future; it is
2389 * only necessary that true be returned for a small subset of pmaps for proper
2393 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2399 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2400 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2403 vm_page_lock_queues();
2404 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2405 if (pv->pv_pmap == pmap) {
2412 vm_page_unlock_queues();
2417 * Return the number of managed mappings to the given physical page that are
2421 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2427 if ((m->oflags & VPO_UNMANAGED) != 0)
2429 vm_page_lock_queues();
2430 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2431 PMAP_LOCK(pv->pv_pmap);
2432 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2433 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2435 PMAP_UNLOCK(pv->pv_pmap);
2437 vm_page_unlock_queues();
2442 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2448 * This currently does not work for entries that
2449 * overlap TLB1 entries.
2451 for (i = 0; i < tlb1_idx; i ++) {
2452 if (tlb1_iomapped(i, pa, size, &va) == 0)
2460 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2467 /* Raw physical memory dumps don't have a virtual address. */
2468 if (md->md_vaddr == ~0UL) {
2469 /* We always map a 256MB page at 256M. */
2470 gran = 256 * 1024 * 1024;
2471 pa = md->md_paddr + ofs;
2472 ppa = pa & ~(gran - 1);
2475 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO);
2476 if (*sz > (gran - ofs))
2481 /* Minidumps are based on virtual memory addresses. */
2482 va = md->md_vaddr + ofs;
2483 if (va >= kernstart + kernsize) {
2484 gran = PAGE_SIZE - (va & PAGE_MASK);
2492 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2496 /* Raw physical memory dumps don't have a virtual address. */
2497 if (md->md_vaddr == ~0UL) {
2499 tlb1[tlb1_idx].mas1 = 0;
2500 tlb1[tlb1_idx].mas2 = 0;
2501 tlb1[tlb1_idx].mas3 = 0;
2502 tlb1_write_entry(tlb1_idx);
2506 /* Minidumps are based on virtual memory addresses. */
2507 /* Nothing to do... */
2511 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev)
2513 static struct pmap_md md;
2517 if (dumpsys_minidump) {
2518 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2520 /* 1st: kernel .data and .bss. */
2522 md.md_vaddr = trunc_page((uintptr_t)_etext);
2523 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2526 switch (prev->md_index) {
2528 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2530 md.md_vaddr = data_start;
2531 md.md_size = data_end - data_start;
2534 /* 3rd: kernel VM. */
2535 va = prev->md_vaddr + prev->md_size;
2536 /* Find start of next chunk (from va). */
2537 while (va < virtual_end) {
2538 /* Don't dump the buffer cache. */
2539 if (va >= kmi.buffer_sva &&
2540 va < kmi.buffer_eva) {
2541 va = kmi.buffer_eva;
2544 pte = pte_find(mmu, kernel_pmap, va);
2545 if (pte != NULL && PTE_ISVALID(pte))
2549 if (va < virtual_end) {
2552 /* Find last page in chunk. */
2553 while (va < virtual_end) {
2554 /* Don't run into the buffer cache. */
2555 if (va == kmi.buffer_sva)
2557 pte = pte_find(mmu, kernel_pmap, va);
2558 if (pte == NULL || !PTE_ISVALID(pte))
2562 md.md_size = va - md.md_vaddr;
2570 } else { /* minidumps */
2571 mem_regions(&physmem_regions, &physmem_regions_sz,
2572 &availmem_regions, &availmem_regions_sz);
2575 /* first physical chunk. */
2576 md.md_paddr = physmem_regions[0].mr_start;
2577 md.md_size = physmem_regions[0].mr_size;
2580 } else if (md.md_index < physmem_regions_sz) {
2581 md.md_paddr = physmem_regions[md.md_index].mr_start;
2582 md.md_size = physmem_regions[md.md_index].mr_size;
2586 /* There's no next physical chunk. */
2595 * Map a set of physical memory pages into the kernel virtual address space.
2596 * Return a pointer to where it is mapped. This routine is intended to be used
2597 * for mapping device memory, NOT real memory.
2600 mmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2606 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa);
2610 sz = 1 << (ilog2(size) & ~1);
2612 printf("Wiring VA=%x to PA=%x (size=%x), "
2613 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2614 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO);
2624 * 'Unmap' a range mapped by mmu_booke_mapdev().
2627 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2629 vm_offset_t base, offset;
2632 * Unmap only if this is inside kernel virtual space.
2634 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2635 base = trunc_page(va);
2636 offset = va & PAGE_MASK;
2637 size = roundup(offset + size, PAGE_SIZE);
2638 kmem_free(kernel_map, base, size);
2643 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2644 * specified pmap. This eliminates the blast of soft faults on process startup
2645 * and immediately after an mmap.
2648 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2649 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2652 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
2653 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2654 ("mmu_booke_object_init_pt: non-device object"));
2658 * Perform the pmap work for mincore.
2661 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2662 vm_paddr_t *locked_pa)
2669 /**************************************************************************/
2671 /**************************************************************************/
2674 * Allocate a TID. If necessary, steal one from someone else.
2675 * The new TID is flushed from the TLB before returning.
2678 tid_alloc(pmap_t pmap)
2683 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2685 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2687 thiscpu = PCPU_GET(cpuid);
2689 tid = PCPU_GET(tid_next);
2692 PCPU_SET(tid_next, tid + 1);
2694 /* If we are stealing TID then clear the relevant pmap's field */
2695 if (tidbusy[thiscpu][tid] != NULL) {
2697 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2699 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2701 /* Flush all entries from TLB0 matching this TID. */
2705 tidbusy[thiscpu][tid] = pmap;
2706 pmap->pm_tid[thiscpu] = tid;
2707 __asm __volatile("msync; isync");
2709 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2710 PCPU_GET(tid_next));
2715 /**************************************************************************/
2717 /**************************************************************************/
2720 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2730 if (mas1 & MAS1_VALID)
2735 if (mas1 & MAS1_IPROT)
2740 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2741 tid = MAS1_GETTID(mas1);
2743 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2746 size = tsize2size(tsize);
2748 debugf("%3d: (%s) [AS=%d] "
2749 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2750 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2751 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2754 /* Convert TLB0 va and way number to tlb0[] table index. */
2755 static inline unsigned int
2756 tlb0_tableidx(vm_offset_t va, unsigned int way)
2760 idx = (way * TLB0_ENTRIES_PER_WAY);
2761 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2766 * Invalidate TLB0 entry.
2769 tlb0_flush_entry(vm_offset_t va)
2772 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2774 mtx_assert(&tlbivax_mutex, MA_OWNED);
2776 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2777 __asm __volatile("isync; msync");
2778 __asm __volatile("tlbsync; msync");
2780 CTR1(KTR_PMAP, "%s: e", __func__);
2783 /* Print out contents of the MAS registers for each TLB0 entry */
2785 tlb0_print_tlbentries(void)
2787 uint32_t mas0, mas1, mas2, mas3, mas7;
2788 int entryidx, way, idx;
2790 debugf("TLB0 entries:\n");
2791 for (way = 0; way < TLB0_WAYS; way ++)
2792 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2794 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2795 mtspr(SPR_MAS0, mas0);
2796 __asm __volatile("isync");
2798 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2799 mtspr(SPR_MAS2, mas2);
2801 __asm __volatile("isync; tlbre");
2803 mas1 = mfspr(SPR_MAS1);
2804 mas2 = mfspr(SPR_MAS2);
2805 mas3 = mfspr(SPR_MAS3);
2806 mas7 = mfspr(SPR_MAS7);
2808 idx = tlb0_tableidx(mas2, way);
2809 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2813 /**************************************************************************/
2815 /**************************************************************************/
2818 * TLB1 mapping notes:
2821 * TLB1[1] Kernel text and data.
2822 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI
2823 * windows, other devices mappings.
2827 * Write given entry to TLB1 hardware.
2828 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2831 tlb1_write_entry(unsigned int idx)
2833 uint32_t mas0, mas7;
2835 //debugf("tlb1_write_entry: s\n");
2837 /* Clear high order RPN bits */
2841 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2842 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2844 mtspr(SPR_MAS0, mas0);
2845 __asm __volatile("isync");
2846 mtspr(SPR_MAS1, tlb1[idx].mas1);
2847 __asm __volatile("isync");
2848 mtspr(SPR_MAS2, tlb1[idx].mas2);
2849 __asm __volatile("isync");
2850 mtspr(SPR_MAS3, tlb1[idx].mas3);
2851 __asm __volatile("isync");
2852 mtspr(SPR_MAS7, mas7);
2853 __asm __volatile("isync; tlbwe; isync; msync");
2855 //debugf("tlb1_write_entry: e\n");
2859 * Return the largest uint value log such that 2^log <= num.
2862 ilog2(unsigned int num)
2866 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2871 * Convert TLB TSIZE value to mapped region size.
2874 tsize2size(unsigned int tsize)
2879 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2882 return ((1 << (2 * tsize)) * 1024);
2886 * Convert region size (must be power of 4) to TLB TSIZE value.
2889 size2tsize(vm_size_t size)
2892 return (ilog2(size) / 2 - 5);
2896 * Register permanent kernel mapping in TLB1.
2898 * Entries are created starting from index 0 (current free entry is
2899 * kept in tlb1_idx) and are not supposed to be invalidated.
2902 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
2908 if (tlb1_idx >= TLB1_ENTRIES) {
2909 printf("tlb1_set_entry: TLB1 full!\n");
2913 /* Convert size to TSIZE */
2914 tsize = size2tsize(size);
2916 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2917 /* XXX TS is hard coded to 0 for now as we only use single address space */
2918 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2920 /* XXX LOCK tlb1[] */
2922 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2923 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2924 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags;
2926 /* Set supervisor RWX permission bits */
2927 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2929 tlb1_write_entry(tlb1_idx++);
2931 /* XXX UNLOCK tlb1[] */
2934 * XXX in general TLB1 updates should be propagated between CPUs,
2935 * since current design assumes to have the same TLB1 set-up on all
2942 * Map in contiguous RAM region into the TLB1 using maximum of
2943 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
2945 * If necessary round up last entry size and return total size
2946 * used by all allocated entries.
2949 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
2951 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
2952 vm_size_t mapped, pgsz, base, mask;
2955 /* Round up to the next 1M */
2956 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1);
2961 pgsz = 64*1024*1024;
2962 while (mapped < size) {
2963 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
2964 while (pgsz > (size - mapped))
2970 /* We under-map. Correct for this. */
2971 if (mapped < size) {
2972 while (pgs[idx - 1] == pgsz) {
2976 /* XXX We may increase beyond out starting point. */
2985 /* Align address to the boundary */
2987 va = (va + mask) & ~mask;
2988 pa = (pa + mask) & ~mask;
2991 for (idx = 0; idx < nents; idx++) {
2993 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz);
2994 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM);
2999 mapped = (va - base);
3000 debugf("mapped size 0x%08x (wasted space 0x%08x)\n",
3001 mapped, mapped - size);
3006 * TLB1 initialization routine, to be called after the very first
3007 * assembler level setup done in locore.S.
3010 tlb1_init(vm_offset_t ccsrbar)
3012 uint32_t mas0, mas1, mas3;
3016 if (bootinfo != NULL && bootinfo[0] != 1) {
3017 tlb1_idx = *((uint16_t *)(bootinfo + 8));
3021 /* The first entry/entries are used to map the kernel. */
3022 for (i = 0; i < tlb1_idx; i++) {
3023 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3024 mtspr(SPR_MAS0, mas0);
3025 __asm __volatile("isync; tlbre");
3027 mas1 = mfspr(SPR_MAS1);
3028 if ((mas1 & MAS1_VALID) == 0)
3031 mas3 = mfspr(SPR_MAS3);
3033 tlb1[i].mas1 = mas1;
3034 tlb1[i].mas2 = mfspr(SPR_MAS2);
3035 tlb1[i].mas3 = mas3;
3038 kernload = mas3 & MAS3_RPN;
3040 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3041 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
3044 /* Map in CCSRBAR. */
3045 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO);
3047 /* Setup TLB miss defaults */
3048 set_mas4_defaults();
3052 * Setup MAS4 defaults.
3053 * These values are loaded to MAS0-2 on a TLB miss.
3056 set_mas4_defaults(void)
3060 /* Defaults: TLB0, PID0, TSIZED=4K */
3061 mas4 = MAS4_TLBSELD0;
3062 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3066 mtspr(SPR_MAS4, mas4);
3067 __asm __volatile("isync");
3071 * Print out contents of the MAS registers for each TLB1 entry
3074 tlb1_print_tlbentries(void)
3076 uint32_t mas0, mas1, mas2, mas3, mas7;
3079 debugf("TLB1 entries:\n");
3080 for (i = 0; i < TLB1_ENTRIES; i++) {
3082 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3083 mtspr(SPR_MAS0, mas0);
3085 __asm __volatile("isync; tlbre");
3087 mas1 = mfspr(SPR_MAS1);
3088 mas2 = mfspr(SPR_MAS2);
3089 mas3 = mfspr(SPR_MAS3);
3090 mas7 = mfspr(SPR_MAS7);
3092 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3097 * Print out contents of the in-ram tlb1 table.
3100 tlb1_print_entries(void)
3104 debugf("tlb1[] table entries:\n");
3105 for (i = 0; i < TLB1_ENTRIES; i++)
3106 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3110 * Return 0 if the physical IO range is encompassed by one of the
3111 * the TLB1 entries, otherwise return related error code.
3114 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3117 vm_paddr_t pa_start;
3119 unsigned int entry_tsize;
3120 vm_size_t entry_size;
3122 *va = (vm_offset_t)NULL;
3124 /* Skip invalid entries */
3125 if (!(tlb1[i].mas1 & MAS1_VALID))
3129 * The entry must be cache-inhibited, guarded, and r/w
3130 * so it can function as an i/o page
3132 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3133 if (prot != (MAS2_I | MAS2_G))
3136 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3137 if (prot != (MAS3_SR | MAS3_SW))
3140 /* The address should be within the entry range. */
3141 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3142 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3144 entry_size = tsize2size(entry_tsize);
3145 pa_start = tlb1[i].mas3 & MAS3_RPN;
3146 pa_end = pa_start + entry_size - 1;
3148 if ((pa < pa_start) || ((pa + size) > pa_end))
3151 /* Return virtual address of this mapping. */
3152 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);