2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_auto_eoi.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/module.h>
48 #include <machine/cpufunc.h>
49 #include <machine/frame.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/md_var.h>
52 #include <machine/resource.h>
53 #include <machine/segments.h>
55 #include <dev/ic/i8259.h>
56 #include <x86/isa/icu.h>
58 #include <pc98/cbus/cbus.h>
60 #include <x86/isa/isa.h>
62 #include <isa/isavar.h>
65 #define SDT_ATPIC SDT_SYSIGT
68 #define SDT_ATPIC SDT_SYS386IGT
69 #define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL)
76 * PC-98 machines wire the slave 8259A to pin 7 on the master PIC, and
77 * PC-AT machines wire the slave PIC to pin 2 on the master PIC.
86 * Determine the base master and slave modes not including auto EOI support.
87 * All machines that FreeBSD supports use 8086 mode.
91 * PC-98 machines do not support auto EOI on the second PIC. Also, it
92 * seems that PC-98 machine PICs use buffered mode, and the master PIC
93 * uses special fully nested mode.
95 #define BASE_MASTER_MODE (ICW4_SFNM | ICW4_BUF | ICW4_MS | ICW4_8086)
96 #define BASE_SLAVE_MODE (ICW4_BUF | ICW4_8086)
98 #define BASE_MASTER_MODE ICW4_8086
99 #define BASE_SLAVE_MODE ICW4_8086
102 /* Enable automatic EOI if requested. */
104 #define MASTER_MODE (BASE_MASTER_MODE | ICW4_AEOI)
106 #define MASTER_MODE BASE_MASTER_MODE
109 #define SLAVE_MODE (BASE_SLAVE_MODE | ICW4_AEOI)
111 #define SLAVE_MODE BASE_SLAVE_MODE
114 #define IRQ_MASK(irq) (1 << (irq))
115 #define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
117 #define NUM_ISA_IRQS 16
119 static void atpic_init(void *dummy);
121 unsigned int imen; /* XXX */
124 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
125 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
126 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
127 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
128 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
129 IDTVEC(atpic_intr15);
131 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
133 #define ATPIC(io, base, eoi, imenptr) \
134 { { atpic_enable_source, atpic_disable_source, (eoi), \
135 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
136 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
137 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
140 #define INTSRC(irq) \
141 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
152 struct atpic_intsrc {
153 struct intsrc at_intsrc;
155 int at_irq; /* Relative to PIC base. */
156 enum intr_trigger at_trigger;
158 u_long at_straycount;
161 static void atpic_enable_source(struct intsrc *isrc);
162 static void atpic_disable_source(struct intsrc *isrc, int eoi);
163 static void atpic_eoi_master(struct intsrc *isrc);
164 static void atpic_eoi_slave(struct intsrc *isrc);
165 static void atpic_enable_intr(struct intsrc *isrc);
166 static void atpic_disable_intr(struct intsrc *isrc);
167 static int atpic_vector(struct intsrc *isrc);
168 static void atpic_resume(struct pic *pic);
169 static int atpic_source_pending(struct intsrc *isrc);
170 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
171 enum intr_polarity pol);
172 static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
173 static void i8259_init(struct atpic *pic, int slave);
175 static struct atpic atpics[] = {
176 ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
177 ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
180 static struct atpic_intsrc atintrs[] = {
199 CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
202 _atpic_eoi_master(struct intsrc *isrc)
205 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
206 ("%s: mismatched pic", __func__));
208 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
213 * The data sheet says no auto-EOI on slave, but it sometimes works.
214 * So, if AUTO_EOI_2 is enabled, we use it.
217 _atpic_eoi_slave(struct intsrc *isrc)
220 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
221 ("%s: mismatched pic", __func__));
223 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
225 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
231 atpic_enable_source(struct intsrc *isrc)
233 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
234 struct atpic *ap = (struct atpic *)isrc->is_pic;
237 if (*ap->at_imen & IMEN_MASK(ai)) {
238 *ap->at_imen &= ~IMEN_MASK(ai);
239 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
245 atpic_disable_source(struct intsrc *isrc, int eoi)
247 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
248 struct atpic *ap = (struct atpic *)isrc->is_pic;
251 if (ai->at_trigger != INTR_TRIGGER_EDGE) {
252 *ap->at_imen |= IMEN_MASK(ai);
253 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
257 * Take care to call these functions directly instead of through
258 * a function pointer. All of the referenced variables should
259 * still be hot in the cache.
261 if (eoi == PIC_EOI) {
262 if (isrc->is_pic == &atpics[MASTER].at_pic)
263 _atpic_eoi_master(isrc);
265 _atpic_eoi_slave(isrc);
272 atpic_eoi_master(struct intsrc *isrc)
276 _atpic_eoi_master(isrc);
282 atpic_eoi_slave(struct intsrc *isrc)
286 _atpic_eoi_slave(isrc);
292 atpic_enable_intr(struct intsrc *isrc)
297 atpic_disable_intr(struct intsrc *isrc)
303 atpic_vector(struct intsrc *isrc)
305 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
306 struct atpic *ap = (struct atpic *)isrc->is_pic;
308 return (IRQ(ap, ai));
312 atpic_source_pending(struct intsrc *isrc)
314 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
315 struct atpic *ap = (struct atpic *)isrc->is_pic;
317 return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
321 atpic_resume(struct pic *pic)
323 struct atpic *ap = (struct atpic *)pic;
325 i8259_init(ap, ap == &atpics[SLAVE]);
327 if (ap == &atpics[SLAVE] && elcr_found)
333 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
334 enum intr_polarity pol)
336 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
339 /* Map conforming values to edge/hi and sanity check the values. */
340 if (trig == INTR_TRIGGER_CONFORM)
341 trig = INTR_TRIGGER_EDGE;
342 if (pol == INTR_POLARITY_CONFORM)
343 pol = INTR_POLARITY_HIGH;
344 vector = atpic_vector(isrc);
345 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
346 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
348 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
349 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
350 pol == INTR_POLARITY_HIGH ? "high" : "low");
354 /* If there is no change, just return. */
355 if (ai->at_trigger == trig)
359 if ((vector == 0 || vector == 1 || vector == 7 || vector == 8) &&
360 trig == INTR_TRIGGER_LEVEL) {
363 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
370 * Certain IRQs can never be level/lo, so don't try to set them
371 * that way if asked. At least some ELCR registers ignore setting
372 * these bits as well.
374 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
375 trig == INTR_TRIGGER_LEVEL) {
378 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
384 printf("atpic: No ELCR to configure IRQ%u as %s\n",
385 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
390 printf("atpic: Programming IRQ%u as %s\n", vector,
391 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
393 elcr_write_trigger(atpic_vector(isrc), trig);
394 ai->at_trigger = trig;
401 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
405 * 8259A's are only used in UP in which case all interrupts always
406 * go to the sole CPU and this function shouldn't even be called.
408 panic("%s: bad cookie", __func__);
412 i8259_init(struct atpic *pic, int slave)
416 /* Reset the PIC and program with next four bytes. */
419 /* MCA uses level triggered interrupts. */
421 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM);
424 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
425 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
428 outb(imr_addr, pic->at_intbase);
431 * Setup slave links. For the master pic, indicate what line
432 * the slave is configured on. For the slave indicate
433 * which line on the master we are connected to.
436 outb(imr_addr, ICU_SLAVEID);
438 outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
442 outb(imr_addr, SLAVE_MODE);
444 outb(imr_addr, MASTER_MODE);
446 /* Set interrupt enable mask. */
447 outb(imr_addr, *pic->at_imen);
449 /* Reset is finished, default to IRR on read. */
450 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
453 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
455 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
463 struct atpic_intsrc *ai;
466 /* Start off with all interrupts disabled. */
468 i8259_init(&atpics[MASTER], 0);
469 i8259_init(&atpics[SLAVE], 1);
470 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
472 /* Install low-level interrupt handlers for all of our IRQs. */
473 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
474 if (i == ICU_SLAVEID)
476 ai->at_intsrc.is_count = &ai->at_count;
477 ai->at_intsrc.is_straycount = &ai->at_straycount;
478 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
479 ai->at_irq, ai->at_intr, SDT_ATPIC, SEL_KPL, GSEL_ATPIC);
483 /* For MCA systems, all interrupts are level triggered. */
485 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
486 ai->at_trigger = INTR_TRIGGER_LEVEL;
491 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
497 ai->at_trigger = INTR_TRIGGER_EDGE;
500 ai->at_trigger = INTR_TRIGGER_LEVEL;
505 * Look for an ELCR. If we find one, update the trigger modes.
506 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
507 * edge triggered and that everything else is level triggered.
508 * We only use the trigger information to reprogram the ELCR if
509 * we have one and as an optimization to avoid masking edge
510 * triggered interrupts. For the case that we don't have an ELCR,
511 * it doesn't hurt to mask an edge triggered interrupt, so we
512 * assume level trigger for any interrupt that we aren't sure is
516 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
517 ai->at_trigger = elcr_read_trigger(i);
519 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
526 ai->at_trigger = INTR_TRIGGER_EDGE;
529 ai->at_trigger = INTR_TRIGGER_LEVEL;
537 atpic_init(void *dummy __unused)
539 struct atpic_intsrc *ai;
543 * Register our PICs, even if we aren't going to use any of their
544 * pins so that they are suspended and resumed.
546 if (intr_register_pic(&atpics[0].at_pic) != 0 ||
547 intr_register_pic(&atpics[1].at_pic) != 0)
548 panic("Unable to register ATPICs");
551 * If any of the ISA IRQs have an interrupt source already, then
552 * assume that the APICs are being used and don't register any
553 * of our interrupt sources. This makes sure we don't accidentally
554 * use mixed mode. The "accidental" use could otherwise occur on
555 * machines that route the ACPI SCI interrupt to a different ISA
556 * IRQ (at least one machines routes it to IRQ 13) thus disabling
557 * that APIC ISA routing and allowing the ATPIC source for that IRQ
558 * to leak through. We used to depend on this feature for routing
559 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
561 for (i = 0; i < NUM_ISA_IRQS; i++)
562 if (intr_lookup_source(i) != NULL)
565 /* Loop through all interrupt sources and add them. */
566 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
567 if (i == ICU_SLAVEID)
569 intr_register_source(&ai->at_intsrc);
572 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL);
575 atpic_handle_intr(u_int vector, struct trapframe *frame)
579 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
580 isrc = &atintrs[vector].at_intsrc;
583 * If we don't have an event, see if this is a spurious
586 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
590 * Read the ISR register to see if IRQ 7/15 is really
591 * pending. Reset read register back to IRR when done.
593 port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
595 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
597 outb(port, OCW3_SEL | OCW3_RR);
599 if ((isr & IRQ_MASK(7)) == 0)
602 intr_execute_handlers(isrc, frame);
607 * Bus attachment for the ISA PIC.
609 static struct isa_pnp_id atpic_ids[] = {
610 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
615 atpic_probe(device_t dev)
619 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
626 * We might be granted IRQ 2, as this is typically consumed by chaining
627 * between the two PIC components. If we're using the APIC, however,
628 * this may not be the case, and as such we should free the resource.
631 * The generic ISA attachment code will handle allocating any other resources
632 * that we don't explicitly claim here.
635 atpic_attach(device_t dev)
637 struct resource *res;
640 /* Try to allocate our IRQ and then free it. */
642 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
644 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
648 static device_method_t atpic_methods[] = {
649 /* Device interface */
650 DEVMETHOD(device_probe, atpic_probe),
651 DEVMETHOD(device_attach, atpic_attach),
652 DEVMETHOD(device_detach, bus_generic_detach),
653 DEVMETHOD(device_shutdown, bus_generic_shutdown),
654 DEVMETHOD(device_suspend, bus_generic_suspend),
655 DEVMETHOD(device_resume, bus_generic_resume),
659 static driver_t atpic_driver = {
665 static devclass_t atpic_devclass;
667 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
669 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
673 * Return a bitmap of the current interrupt requests. This is 8259-specific
674 * and is only suitable for use at probe time.
677 isa_irq_pending(void)
684 return ((irr2 << 8) | irr1);