2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
39 #include <sys/sysctl.h>
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcib_private.h>
44 #include <isa/isavar.h>
46 #include <machine/md_var.h>
48 #include <machine/legacyvar.h>
49 #include <machine/pci_cfgreg.h>
50 #include <machine/resource.h>
55 legacy_pcib_maxslots(device_t dev)
60 /* read configuration space register */
63 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
66 return(pci_cfgregread(bus, slot, func, reg, bytes));
69 /* write configuration space register */
72 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
73 u_int reg, uint32_t data, int bytes)
75 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
81 legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
85 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
86 pci_get_function(dev), pin));
88 /* No routing possible */
89 return (PCI_INVALID_IRQ);
93 /* Pass MSI requests up to the nexus. */
96 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
101 bus = device_get_parent(pcib);
102 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
107 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
111 bus = device_get_parent(pcib);
112 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
116 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
121 bus = device_get_parent(pcib);
122 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
126 legacy_pcib_is_host_bridge(int bus, int slot, int func,
127 uint32_t id, uint8_t class, uint8_t subclass,
131 const char *s = NULL;
132 static uint8_t pxb[4]; /* hack for 450nx */
138 s = "Intel 824?? host to PCI bridge";
139 /* XXX This is a guess */
140 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
144 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
147 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
150 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
153 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
156 s = "Intel 82443LX (440 LX) host to PCI bridge";
159 s = "Intel 82443BX (440 BX) host to PCI bridge";
162 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
165 s = "Intel 82443MX host to PCI bridge";
168 s = "Intel 82443GX host to PCI bridge";
171 s = "Intel 82443GX host to AGP bridge";
174 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
177 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
178 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
182 * For the 450nx chipset, there is a whole bundle of
183 * things pretending to be host bridges. The MIOC will
184 * be seen first and isn't really a pci bridge (the
185 * actual busses are attached to the PXB's). We need to
186 * read the registers of the MIOC to figure out the
187 * bus numbers for the PXB channels.
189 * Since the MIOC doesn't have a pci bus attached, we
190 * pretend it wasn't there.
192 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
193 0xd0, 1); /* BUSNO[0] */
194 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
195 0xd1, 1) + 1; /* SUBA[0]+1 */
196 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
197 0xd3, 1); /* BUSNO[1] */
198 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
199 0xd4, 1) + 1; /* SUBA[1]+1 */
204 s = "Intel 82454NX PXB#0, Bus#A";
208 s = "Intel 82454NX PXB#0, Bus#B";
212 s = "Intel 82454NX PXB#1, Bus#A";
216 s = "Intel 82454NX PXB#1, Bus#B";
222 s = "Intel 82845 Host to PCI bridge";
225 /* AMD -- vendor 0x1022 */
227 s = "AMD Elan SC520 host to PCI bridge";
229 init_AMD_Elan_sc520();
232 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
236 s = "AMD-751 host to PCI bridge";
239 s = "AMD-761 host to PCI bridge";
242 /* SiS -- vendor 0x1039 */
253 s = "SiS 5591 host to PCI bridge";
256 s = "SiS 5591 host to AGP bridge";
259 /* VLSI -- vendor 0x1004 */
261 s = "VLSI 82C592 Host to PCI bridge";
264 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
265 /* totally. Please let me know if anything wrong. -F */
266 /* XXX need info on the MVP3 -- any takers? */
268 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
271 /* AcerLabs -- vendor 0x10b9 */
272 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
273 /* id is '10b9" but the register always shows "10b9". -Foxfair */
275 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
278 /* OPTi -- vendor 0x1045 */
280 s = "OPTi 82C700 host to PCI bridge";
283 s = "OPTi 82C822 host to PCI Bridge";
286 /* ServerWorks -- vendor 0x1166 */
288 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
289 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
298 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
299 s = "ServerWorks host to PCI bridge";
300 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
304 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
305 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
309 s = "ServerWorks CIOB30 host to PCI bridge";
310 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
315 case 0x03021014: /* IBM re-badged ServerWorks chipset */
316 s = "ServerWorks CMIC-HE host to PCI-X bridge";
317 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
320 /* XXX unknown chipset, but working */
326 s = "ServerWorks host to PCI bridge(unknown chipset)";
327 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
330 /* Compaq/HP -- vendor 0x0e11 */
332 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
333 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
336 /* Integrated Micro Solutions -- vendor 0x10e0 */
338 s = "Integrated Micro Solutions VL Bridge";
342 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
343 s = "Host to PCI bridge";
349 const char *s = NULL;
352 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
353 s = "Host to PCI bridge";
359 * Scan the first pci bus for host-pci bridges and add pcib instances
360 * to the nexus for each bridge.
363 legacy_pcib_identify(driver_t *driver, device_t parent)
372 devclass_t pci_devclass;
374 if (pci_cfgregopen() == 0)
377 * Check to see if we haven't already had a PCI bus added
378 * via some other means. If we have, bail since otherwise
379 * we're going to end up duplicating it.
381 if ((pci_devclass = devclass_find("pci")) &&
382 devclass_get_device(pci_devclass, 0))
388 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
390 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
393 * When enumerating bus devices, the standard says that
394 * one should check the header type and ignore the slots whose
395 * header types that the software doesn't know about. We use
396 * this to filter out devices.
398 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
400 if ((hdrtype & PCIM_MFDEV) &&
401 (!found_orion || hdrtype != 0xff))
402 pcifunchigh = PCI_FUNCMAX;
405 for (func = 0; func <= pcifunchigh; func++) {
407 * Read the IDs and class from the device.
410 uint8_t class, subclass, busnum;
415 id = legacy_pcib_read_config(0, bus, slot, func,
419 class = legacy_pcib_read_config(0, bus, slot, func,
421 subclass = legacy_pcib_read_config(0, bus, slot, func,
424 s = legacy_pcib_is_host_bridge(bus, slot, func,
431 * Check to see if the physical bus has already
432 * been seen. Eg: hybrid 32 and 64 bit host
433 * bridges to the same logical bus.
435 if (device_get_children(parent, &devs, &ndevs) == 0) {
436 for (i = 0; s != NULL && i < ndevs; i++) {
437 if (strcmp(device_get_name(devs[i]),
440 if (legacy_get_pcibus(devs[i]) == busnum)
449 * Add at priority 100 to make sure we
450 * go after any motherboard resources
452 child = BUS_ADD_CHILD(parent, 100,
454 device_set_desc(child, s);
455 legacy_set_pcibus(child, busnum);
458 if (id == 0x12258086)
460 if (id == 0x84c48086)
464 if (found824xx && bus == 0) {
470 * Make sure we add at least one bridge since some old
471 * hardware doesn't actually have a host-pci bridge device.
472 * Note that pci_cfgregopen() thinks we have PCI devices..
477 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
478 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
479 legacy_set_pcibus(child, 0);
484 legacy_pcib_probe(device_t dev)
487 if (pci_cfgregopen() == 0)
493 legacy_pcib_attach(device_t dev)
500 bus = pcib_get_bus(dev);
503 * Look for a PCI BIOS interrupt routing table as that will be
504 * our method of routing interrupts if we have one.
506 if (pci_pir_probe(bus, 0)) {
507 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
509 device_probe_and_attach(pir);
512 device_add_child(dev, "pci", bus);
513 return bus_generic_attach(dev);
517 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
522 case PCIB_IVAR_DOMAIN:
526 *result = legacy_get_pcibus(dev);
533 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
538 case PCIB_IVAR_DOMAIN:
541 legacy_set_pcibus(dev, value);
548 * Helper routine for x86 Host-PCI bridge driver resource allocation.
549 * This is used to adjust the start address of wildcard allocation
550 * requests to avoid low addresses that are known to be problematic.
552 * If no memory preference is given, use upper 32MB slot most BIOSes
553 * use for their memory window. This is typically only used on older
554 * laptops that don't have PCI busses behind a PCI bridge, so assuming
555 * > 32MB is likely OK.
557 * However, this can cause problems for other chipsets, so we make
558 * this tunable by hw.pci.host_mem_start.
560 SYSCTL_DECL(_hw_pci);
562 static unsigned long host_mem_start = 0x80000000;
563 TUNABLE_ULONG("hw.pci.host_mem_start", &host_mem_start);
564 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start,
565 0, "Limit the host bridge memory to being above this address.");
568 hostb_alloc_start(int type, u_long start, u_long end, u_long count)
571 if (start + count - 1 != end) {
572 if (type == SYS_RES_MEMORY && start < host_mem_start)
573 start = host_mem_start;
574 if (type == SYS_RES_IOPORT && start < 0x1000)
581 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
582 u_long start, u_long end, u_long count, u_int flags)
585 start = hostb_alloc_start(type, start, end, count);
586 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
590 static device_method_t legacy_pcib_methods[] = {
591 /* Device interface */
592 DEVMETHOD(device_identify, legacy_pcib_identify),
593 DEVMETHOD(device_probe, legacy_pcib_probe),
594 DEVMETHOD(device_attach, legacy_pcib_attach),
595 DEVMETHOD(device_shutdown, bus_generic_shutdown),
596 DEVMETHOD(device_suspend, bus_generic_suspend),
597 DEVMETHOD(device_resume, bus_generic_resume),
600 DEVMETHOD(bus_print_child, bus_generic_print_child),
601 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
602 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
603 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
604 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
605 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
606 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
607 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
608 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
609 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
612 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
613 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
614 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
615 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
616 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
617 DEVMETHOD(pcib_release_msi, pcib_release_msi),
618 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
619 DEVMETHOD(pcib_release_msix, pcib_release_msix),
620 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
625 static devclass_t hostb_devclass;
627 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
628 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
632 * Install placeholder to claim the resources owned by the
633 * PCI bus interface. This could be used to extract the
634 * config space registers in the extreme case where the PnP
635 * ID is available and the PCI BIOS isn't, but for now we just
636 * eat the PnP ID and do nothing else.
638 * XXX we should silence this probe, as it will generally confuse
641 static struct isa_pnp_id pcibus_pnp_ids[] = {
642 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
643 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
648 pcibus_pnp_probe(device_t dev)
652 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
658 pcibus_pnp_attach(device_t dev)
663 static device_method_t pcibus_pnp_methods[] = {
664 /* Device interface */
665 DEVMETHOD(device_probe, pcibus_pnp_probe),
666 DEVMETHOD(device_attach, pcibus_pnp_attach),
667 DEVMETHOD(device_detach, bus_generic_detach),
668 DEVMETHOD(device_shutdown, bus_generic_shutdown),
669 DEVMETHOD(device_suspend, bus_generic_suspend),
670 DEVMETHOD(device_resume, bus_generic_resume),
674 static devclass_t pcibus_pnp_devclass;
676 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
677 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
681 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
682 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
683 * table for interrupt routing when possible.
685 static int pcibios_pcib_probe(device_t bus);
687 static device_method_t pcibios_pcib_pci_methods[] = {
688 /* Device interface */
689 DEVMETHOD(device_probe, pcibios_pcib_probe),
692 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
697 static devclass_t pcib_devclass;
699 DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
700 sizeof(struct pcib_softc), pcib_driver);
701 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
704 pcibios_pcib_probe(device_t dev)
708 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
709 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
711 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
714 if (!pci_pir_probe(bus, 1))
716 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");