1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/raw_ostream.h"
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31 static unsigned translateShiftImm(unsigned imm) {
32 // lsr #32 and asr #32 exist, but should be encoded as a 0.
33 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
40 /// Prints the shift value with an immediate value.
41 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
42 unsigned ShImm, bool UseMarkup) {
43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
47 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
48 O << getShiftOpcStr(ShOpc);
50 if (ShOpc != ARM_AM::rrx) {
54 O << "#" << translateShiftImm(ShImm);
60 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
61 const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI,
63 const MCSubtargetInfo &STI) :
64 MCInstPrinter(MAI, MII, MRI) {
65 // Initialize the set of available features.
66 setAvailableFeatures(STI.getFeatureBits());
69 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
71 << getRegisterName(RegNo)
75 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
77 unsigned Opcode = MI->getOpcode();
79 // Check for HINT instructions w/ canonical names.
80 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
81 switch (MI->getOperand(0).getImm()) {
82 case 0: O << "\tnop"; break;
83 case 1: O << "\tyield"; break;
84 case 2: O << "\twfe"; break;
85 case 3: O << "\twfi"; break;
86 case 4: O << "\tsev"; break;
88 // Anything else should just print normally.
89 printInstruction(MI, O);
90 printAnnotation(O, Annot);
93 printPredicateOperand(MI, 1, O);
94 if (Opcode == ARM::t2HINT)
96 printAnnotation(O, Annot);
100 // Check for MOVs and print canonical forms, instead.
101 if (Opcode == ARM::MOVsr) {
102 // FIXME: Thumb variants?
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
108 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
109 printSBitModifierOperand(MI, 6, O);
110 printPredicateOperand(MI, 4, O);
113 printRegName(O, Dst.getReg());
115 printRegName(O, MO1.getReg());
118 printRegName(O, MO2.getReg());
119 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
120 printAnnotation(O, Annot);
124 if (Opcode == ARM::MOVsi) {
125 // FIXME: Thumb variants?
126 const MCOperand &Dst = MI->getOperand(0);
127 const MCOperand &MO1 = MI->getOperand(1);
128 const MCOperand &MO2 = MI->getOperand(2);
130 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
131 printSBitModifierOperand(MI, 5, O);
132 printPredicateOperand(MI, 3, O);
135 printRegName(O, Dst.getReg());
137 printRegName(O, MO1.getReg());
139 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
140 printAnnotation(O, Annot);
146 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
148 printAnnotation(O, Annot);
154 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
155 MI->getOperand(0).getReg() == ARM::SP &&
156 MI->getNumOperands() > 5) {
157 // Should only print PUSH if there are at least two registers in the list.
159 printPredicateOperand(MI, 2, O);
160 if (Opcode == ARM::t2STMDB_UPD)
163 printRegisterList(MI, 4, O);
164 printAnnotation(O, Annot);
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
168 MI->getOperand(3).getImm() == -4) {
170 printPredicateOperand(MI, 4, O);
172 printRegName(O, MI->getOperand(1).getReg());
174 printAnnotation(O, Annot);
179 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
180 MI->getOperand(0).getReg() == ARM::SP &&
181 MI->getNumOperands() > 5) {
182 // Should only print POP if there are at least two registers in the list.
184 printPredicateOperand(MI, 2, O);
185 if (Opcode == ARM::t2LDMIA_UPD)
188 printRegisterList(MI, 4, O);
189 printAnnotation(O, Annot);
192 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
193 MI->getOperand(4).getImm() == 4) {
195 printPredicateOperand(MI, 5, O);
197 printRegName(O, MI->getOperand(0).getReg());
199 printAnnotation(O, Annot);
205 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
206 MI->getOperand(0).getReg() == ARM::SP) {
207 O << '\t' << "vpush";
208 printPredicateOperand(MI, 2, O);
210 printRegisterList(MI, 4, O);
211 printAnnotation(O, Annot);
216 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
217 MI->getOperand(0).getReg() == ARM::SP) {
219 printPredicateOperand(MI, 2, O);
221 printRegisterList(MI, 4, O);
222 printAnnotation(O, Annot);
226 if (Opcode == ARM::tLDMIA) {
227 bool Writeback = true;
228 unsigned BaseReg = MI->getOperand(0).getReg();
229 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
230 if (MI->getOperand(i).getReg() == BaseReg)
236 printPredicateOperand(MI, 1, O);
238 printRegName(O, BaseReg);
239 if (Writeback) O << "!";
241 printRegisterList(MI, 3, O);
242 printAnnotation(O, Annot);
247 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
248 MI->getOperand(1).getReg() == ARM::R8) {
250 printPredicateOperand(MI, 2, O);
251 printAnnotation(O, Annot);
255 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
256 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
257 // a single GPRPair reg operand is used in the .td file to replace the two
258 // GPRs. However, when decoding them, the two GRPs cannot be automatically
259 // expressed as a GPRPair, so we have to manually merge them.
260 // FIXME: We would really like to be able to tablegen'erate this.
261 if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD) {
262 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
263 bool isStore = Opcode == ARM::STREXD;
264 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
265 if (MRC.contains(Reg)) {
268 NewMI.setOpcode(Opcode);
271 NewMI.addOperand(MI->getOperand(0));
272 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
273 &MRI.getRegClass(ARM::GPRPairRegClassID)));
274 NewMI.addOperand(NewReg);
276 // Copy the rest operands into NewMI.
277 for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
278 NewMI.addOperand(MI->getOperand(i));
279 printInstruction(&NewMI, O);
284 printInstruction(MI, O);
285 printAnnotation(O, Annot);
288 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
290 const MCOperand &Op = MI->getOperand(OpNo);
292 unsigned Reg = Op.getReg();
293 printRegName(O, Reg);
294 } else if (Op.isImm()) {
296 << '#' << formatImm(Op.getImm())
299 assert(Op.isExpr() && "unknown operand kind in printOperand");
300 // If a symbolic branch target was added as a constant expression then print
301 // that address in hex. And only print 32 unsigned bits for the address.
302 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
304 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
306 O.write_hex((uint32_t)Address);
309 // Otherwise, just print the expression.
315 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
317 const MCOperand &MO1 = MI->getOperand(OpNum);
320 else if (MO1.isImm()) {
321 O << markup("<mem:") << "[pc, "
322 << markup("<imm:") << "#" << formatImm(MO1.getImm())
323 << markup(">]>", "]");
326 llvm_unreachable("Unknown LDR label operand?");
329 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
330 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
332 // REG REG 0,SH_OPC - e.g. R5, ROR R3
333 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
334 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
336 const MCOperand &MO1 = MI->getOperand(OpNum);
337 const MCOperand &MO2 = MI->getOperand(OpNum+1);
338 const MCOperand &MO3 = MI->getOperand(OpNum+2);
340 printRegName(O, MO1.getReg());
342 // Print the shift opc.
343 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
344 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
345 if (ShOpc == ARM_AM::rrx)
349 printRegName(O, MO2.getReg());
350 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
353 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
355 const MCOperand &MO1 = MI->getOperand(OpNum);
356 const MCOperand &MO2 = MI->getOperand(OpNum+1);
358 printRegName(O, MO1.getReg());
360 // Print the shift opc.
361 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
362 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
366 //===--------------------------------------------------------------------===//
367 // Addressing Mode #2
368 //===--------------------------------------------------------------------===//
370 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
372 const MCOperand &MO1 = MI->getOperand(Op);
373 const MCOperand &MO2 = MI->getOperand(Op+1);
374 const MCOperand &MO3 = MI->getOperand(Op+2);
376 O << markup("<mem:") << "[";
377 printRegName(O, MO1.getReg());
380 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
384 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
385 << ARM_AM::getAM2Offset(MO3.getImm())
388 O << "]" << markup(">");
393 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
394 printRegName(O, MO2.getReg());
396 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
397 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
398 O << "]" << markup(">");
401 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
403 const MCOperand &MO1 = MI->getOperand(Op);
404 const MCOperand &MO2 = MI->getOperand(Op+1);
405 O << markup("<mem:") << "[";
406 printRegName(O, MO1.getReg());
408 printRegName(O, MO2.getReg());
409 O << "]" << markup(">");
412 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
414 const MCOperand &MO1 = MI->getOperand(Op);
415 const MCOperand &MO2 = MI->getOperand(Op+1);
416 O << markup("<mem:") << "[";
417 printRegName(O, MO1.getReg());
419 printRegName(O, MO2.getReg());
420 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
423 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
425 const MCOperand &MO1 = MI->getOperand(Op);
427 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
428 printOperand(MI, Op, O);
433 const MCOperand &MO3 = MI->getOperand(Op+2);
434 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
435 assert(IdxMode != ARMII::IndexModePost &&
436 "Should be pre or offset index op");
439 printAM2PreOrOffsetIndexOp(MI, Op, O);
442 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
445 const MCOperand &MO1 = MI->getOperand(OpNum);
446 const MCOperand &MO2 = MI->getOperand(OpNum+1);
449 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
451 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
457 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
458 printRegName(O, MO1.getReg());
460 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
461 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
464 //===--------------------------------------------------------------------===//
465 // Addressing Mode #3
466 //===--------------------------------------------------------------------===//
468 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
470 const MCOperand &MO1 = MI->getOperand(Op);
471 const MCOperand &MO2 = MI->getOperand(Op+1);
472 const MCOperand &MO3 = MI->getOperand(Op+2);
474 O << markup("<mem:") << "[";
475 printRegName(O, MO1.getReg());
476 O << "], " << markup(">");
479 O << (char)ARM_AM::getAM3Op(MO3.getImm());
480 printRegName(O, MO2.getReg());
484 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
487 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
492 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
494 bool AlwaysPrintImm0) {
495 const MCOperand &MO1 = MI->getOperand(Op);
496 const MCOperand &MO2 = MI->getOperand(Op+1);
497 const MCOperand &MO3 = MI->getOperand(Op+2);
499 O << markup("<mem:") << '[';
500 printRegName(O, MO1.getReg());
503 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
504 printRegName(O, MO2.getReg());
505 O << ']' << markup(">");
509 //If the op is sub we have to print the immediate even if it is 0
510 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
511 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
513 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
517 << ARM_AM::getAddrOpcStr(op)
521 O << ']' << markup(">");
524 template <bool AlwaysPrintImm0>
525 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
527 const MCOperand &MO1 = MI->getOperand(Op);
528 if (!MO1.isReg()) { // For label symbolic references.
529 printOperand(MI, Op, O);
533 const MCOperand &MO3 = MI->getOperand(Op+2);
534 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
536 if (IdxMode == ARMII::IndexModePost) {
537 printAM3PostIndexOp(MI, Op, O);
540 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
543 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
546 const MCOperand &MO1 = MI->getOperand(OpNum);
547 const MCOperand &MO2 = MI->getOperand(OpNum+1);
550 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
551 printRegName(O, MO1.getReg());
555 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
557 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
561 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
564 const MCOperand &MO = MI->getOperand(OpNum);
565 unsigned Imm = MO.getImm();
567 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
571 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
573 const MCOperand &MO1 = MI->getOperand(OpNum);
574 const MCOperand &MO2 = MI->getOperand(OpNum+1);
576 O << (MO2.getImm() ? "" : "-");
577 printRegName(O, MO1.getReg());
580 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
583 const MCOperand &MO = MI->getOperand(OpNum);
584 unsigned Imm = MO.getImm();
586 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
591 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
593 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
595 O << ARM_AM::getAMSubModeStr(Mode);
598 template <bool AlwaysPrintImm0>
599 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
601 const MCOperand &MO1 = MI->getOperand(OpNum);
602 const MCOperand &MO2 = MI->getOperand(OpNum+1);
604 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
605 printOperand(MI, OpNum, O);
609 O << markup("<mem:") << "[";
610 printRegName(O, MO1.getReg());
612 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
613 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
614 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
618 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
622 O << "]" << markup(">");
625 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
627 const MCOperand &MO1 = MI->getOperand(OpNum);
628 const MCOperand &MO2 = MI->getOperand(OpNum+1);
630 O << markup("<mem:") << "[";
631 printRegName(O, MO1.getReg());
633 O << ":" << (MO2.getImm() << 3);
635 O << "]" << markup(">");
638 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
640 const MCOperand &MO1 = MI->getOperand(OpNum);
641 O << markup("<mem:") << "[";
642 printRegName(O, MO1.getReg());
643 O << "]" << markup(">");
646 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
649 const MCOperand &MO = MI->getOperand(OpNum);
650 if (MO.getReg() == 0)
654 printRegName(O, MO.getReg());
658 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
661 const MCOperand &MO = MI->getOperand(OpNum);
662 uint32_t v = ~MO.getImm();
663 int32_t lsb = CountTrailingZeros_32(v);
664 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
665 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
666 O << markup("<imm:") << '#' << lsb << markup(">")
668 << markup("<imm:") << '#' << width << markup(">");
671 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
673 unsigned val = MI->getOperand(OpNum).getImm();
674 O << ARM_MB::MemBOptToString(val);
677 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
679 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
680 bool isASR = (ShiftOp & (1 << 5)) != 0;
681 unsigned Amt = ShiftOp & 0x1f;
685 << "#" << (Amt == 0 ? 32 : Amt)
696 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
698 unsigned Imm = MI->getOperand(OpNum).getImm();
701 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
702 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
705 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
707 unsigned Imm = MI->getOperand(OpNum).getImm();
708 // A shift amount of 32 is encoded as 0.
711 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
712 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
715 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
718 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
719 if (i != OpNum) O << ", ";
720 printRegName(O, MI->getOperand(i).getReg());
725 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
727 unsigned Reg = MI->getOperand(OpNum).getReg();
728 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
730 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
734 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
736 const MCOperand &Op = MI->getOperand(OpNum);
743 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
745 const MCOperand &Op = MI->getOperand(OpNum);
746 O << ARM_PROC::IModToString(Op.getImm());
749 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
751 const MCOperand &Op = MI->getOperand(OpNum);
752 unsigned IFlags = Op.getImm();
753 for (int i=2; i >= 0; --i)
754 if (IFlags & (1 << i))
755 O << ARM_PROC::IFlagsToString(1 << i);
761 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
763 const MCOperand &Op = MI->getOperand(OpNum);
764 unsigned SpecRegRBit = Op.getImm() >> 4;
765 unsigned Mask = Op.getImm() & 0xf;
767 if (getAvailableFeatures() & ARM::FeatureMClass) {
768 unsigned SYSm = Op.getImm();
769 unsigned Opcode = MI->getOpcode();
770 // For reads of the special registers ignore the "mask encoding" bits
771 // which are only for writes.
772 if (Opcode == ARM::t2MRS_M)
775 default: llvm_unreachable("Unexpected mask value!");
777 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
778 case 0x400: O << "apsr_g"; return;
779 case 0xc00: O << "apsr_nzcvqg"; return;
781 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
782 case 0x401: O << "iapsr_g"; return;
783 case 0xc01: O << "iapsr_nzcvqg"; return;
785 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
786 case 0x402: O << "eapsr_g"; return;
787 case 0xc02: O << "eapsr_nzcvqg"; return;
789 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
790 case 0x403: O << "xpsr_g"; return;
791 case 0xc03: O << "xpsr_nzcvqg"; return;
793 case 0x805: O << "ipsr"; return;
795 case 0x806: O << "epsr"; return;
797 case 0x807: O << "iepsr"; return;
799 case 0x808: O << "msp"; return;
801 case 0x809: O << "psp"; return;
803 case 0x810: O << "primask"; return;
805 case 0x811: O << "basepri"; return;
807 case 0x812: O << "basepri_max"; return;
809 case 0x813: O << "faultmask"; return;
811 case 0x814: O << "control"; return;
815 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
816 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
817 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
820 default: llvm_unreachable("Unexpected mask value!");
821 case 4: O << "g"; return;
822 case 8: O << "nzcvq"; return;
823 case 12: O << "nzcvqg"; return;
834 if (Mask & 8) O << 'f';
835 if (Mask & 4) O << 's';
836 if (Mask & 2) O << 'x';
837 if (Mask & 1) O << 'c';
841 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
843 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
844 // Handle the undefined 15 CC value here for printing so we don't abort().
845 if ((unsigned)CC == 15)
847 else if (CC != ARMCC::AL)
848 O << ARMCondCodeToString(CC);
851 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
854 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
855 O << ARMCondCodeToString(CC);
858 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
860 if (MI->getOperand(OpNum).getReg()) {
861 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
862 "Expect ARM CPSR register!");
867 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
869 O << MI->getOperand(OpNum).getImm();
872 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
874 O << "p" << MI->getOperand(OpNum).getImm();
877 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
879 O << "c" << MI->getOperand(OpNum).getImm();
882 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
884 O << "{" << MI->getOperand(OpNum).getImm() << "}";
887 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
889 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
892 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
894 const MCOperand &MO = MI->getOperand(OpNum);
901 int32_t OffImm = (int32_t)MO.getImm();
903 O << markup("<imm:");
904 if (OffImm == INT32_MIN)
907 O << "#-" << -OffImm;
913 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
916 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
920 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
922 unsigned Imm = MI->getOperand(OpNum).getImm();
924 << "#" << formatImm((Imm == 0 ? 32 : Imm))
928 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
930 // (3 - the number of trailing zeros) is the number of then / else.
931 unsigned Mask = MI->getOperand(OpNum).getImm();
932 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
933 unsigned CondBit0 = Firstcond & 1;
934 unsigned NumTZ = CountTrailingZeros_32(Mask);
935 assert(NumTZ <= 3 && "Invalid IT mask!");
936 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
937 bool T = ((Mask >> Pos) & 1) == CondBit0;
945 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
947 const MCOperand &MO1 = MI->getOperand(Op);
948 const MCOperand &MO2 = MI->getOperand(Op + 1);
950 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
951 printOperand(MI, Op, O);
955 O << markup("<mem:") << "[";
956 printRegName(O, MO1.getReg());
957 if (unsigned RegNum = MO2.getReg()) {
959 printRegName(O, RegNum);
961 O << "]" << markup(">");
964 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
968 const MCOperand &MO1 = MI->getOperand(Op);
969 const MCOperand &MO2 = MI->getOperand(Op + 1);
971 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
972 printOperand(MI, Op, O);
976 O << markup("<mem:") << "[";
977 printRegName(O, MO1.getReg());
978 if (unsigned ImmOffs = MO2.getImm()) {
981 << "#" << formatImm(ImmOffs * Scale)
984 O << "]" << markup(">");
987 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
990 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
993 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
996 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
999 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1002 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1005 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1007 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1010 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1011 // register with shift forms.
1012 // REG 0 0 - e.g. R5
1013 // REG IMM, SH_OPC - e.g. R5, LSL #3
1014 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1016 const MCOperand &MO1 = MI->getOperand(OpNum);
1017 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1019 unsigned Reg = MO1.getReg();
1020 printRegName(O, Reg);
1022 // Print the shift opc.
1023 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1024 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1025 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1028 template <bool AlwaysPrintImm0>
1029 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1031 const MCOperand &MO1 = MI->getOperand(OpNum);
1032 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1034 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1035 printOperand(MI, OpNum, O);
1039 O << markup("<mem:") << "[";
1040 printRegName(O, MO1.getReg());
1042 int32_t OffImm = (int32_t)MO2.getImm();
1043 bool isSub = OffImm < 0;
1044 // Special value for #-0. All others are normal.
1045 if (OffImm == INT32_MIN)
1053 else if (AlwaysPrintImm0 || OffImm > 0) {
1059 O << "]" << markup(">");
1062 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1065 const MCOperand &MO1 = MI->getOperand(OpNum);
1066 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1068 O << markup("<mem:") << "[";
1069 printRegName(O, MO1.getReg());
1071 int32_t OffImm = (int32_t)MO2.getImm();
1075 if (OffImm != 0 && UseMarkup)
1077 if (OffImm == INT32_MIN)
1079 else if (OffImm < 0)
1080 O << "#-" << -OffImm;
1081 else if (OffImm > 0)
1083 if (OffImm != 0 && UseMarkup)
1085 O << "]" << markup(">");
1088 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1091 const MCOperand &MO1 = MI->getOperand(OpNum);
1092 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1094 if (!MO1.isReg()) { // For label symbolic references.
1095 printOperand(MI, OpNum, O);
1099 O << markup("<mem:") << "[";
1100 printRegName(O, MO1.getReg());
1102 int32_t OffImm = (int32_t)MO2.getImm();
1104 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1109 if (OffImm != 0 && UseMarkup)
1111 if (OffImm == INT32_MIN)
1113 else if (OffImm < 0)
1114 O << "#-" << -OffImm;
1115 else if (OffImm > 0)
1117 if (OffImm != 0 && UseMarkup)
1119 O << "]" << markup(">");
1122 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1125 const MCOperand &MO1 = MI->getOperand(OpNum);
1126 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1128 O << markup("<mem:") << "[";
1129 printRegName(O, MO1.getReg());
1133 << "#" << formatImm(MO2.getImm() * 4)
1136 O << "]" << markup(">");
1139 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1142 const MCOperand &MO1 = MI->getOperand(OpNum);
1143 int32_t OffImm = (int32_t)MO1.getImm();
1144 O << ", " << markup("<imm:");
1146 O << "#-" << -OffImm;
1152 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1155 const MCOperand &MO1 = MI->getOperand(OpNum);
1156 int32_t OffImm = (int32_t)MO1.getImm();
1158 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1163 if (OffImm != 0 && UseMarkup)
1165 if (OffImm == INT32_MIN)
1167 else if (OffImm < 0)
1168 O << "#-" << -OffImm;
1169 else if (OffImm > 0)
1171 if (OffImm != 0 && UseMarkup)
1175 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1178 const MCOperand &MO1 = MI->getOperand(OpNum);
1179 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1180 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1182 O << markup("<mem:") << "[";
1183 printRegName(O, MO1.getReg());
1185 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1187 printRegName(O, MO2.getReg());
1189 unsigned ShAmt = MO3.getImm();
1191 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1197 O << "]" << markup(">");
1200 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1202 const MCOperand &MO = MI->getOperand(OpNum);
1203 O << markup("<imm:")
1204 << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1208 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1210 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1212 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1213 O << markup("<imm:")
1219 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1221 unsigned Imm = MI->getOperand(OpNum).getImm();
1222 O << markup("<imm:")
1223 << "#" << formatImm(Imm + 1)
1227 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1229 unsigned Imm = MI->getOperand(OpNum).getImm();
1236 default: assert (0 && "illegal ror immediate!");
1237 case 1: O << "8"; break;
1238 case 2: O << "16"; break;
1239 case 3: O << "24"; break;
1244 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1246 O << markup("<imm:")
1247 << "#" << 16 - MI->getOperand(OpNum).getImm()
1251 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1253 O << markup("<imm:")
1254 << "#" << 32 - MI->getOperand(OpNum).getImm()
1258 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1260 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1263 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1266 printRegName(O, MI->getOperand(OpNum).getReg());
1270 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1272 unsigned Reg = MI->getOperand(OpNum).getReg();
1273 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1274 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1276 printRegName(O, Reg0);
1278 printRegName(O, Reg1);
1282 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1285 unsigned Reg = MI->getOperand(OpNum).getReg();
1286 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1287 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1289 printRegName(O, Reg0);
1291 printRegName(O, Reg1);
1295 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1297 // Normally, it's not safe to use register enum values directly with
1298 // addition to get the next register, but for VFP registers, the
1299 // sort order is guaranteed because they're all of the form D<n>.
1301 printRegName(O, MI->getOperand(OpNum).getReg());
1303 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1305 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1309 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1311 // Normally, it's not safe to use register enum values directly with
1312 // addition to get the next register, but for VFP registers, the
1313 // sort order is guaranteed because they're all of the form D<n>.
1315 printRegName(O, MI->getOperand(OpNum).getReg());
1317 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1319 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1321 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1325 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1329 printRegName(O, MI->getOperand(OpNum).getReg());
1333 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1336 unsigned Reg = MI->getOperand(OpNum).getReg();
1337 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1338 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1340 printRegName(O, Reg0);
1342 printRegName(O, Reg1);
1346 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1349 // Normally, it's not safe to use register enum values directly with
1350 // addition to get the next register, but for VFP registers, the
1351 // sort order is guaranteed because they're all of the form D<n>.
1353 printRegName(O, MI->getOperand(OpNum).getReg());
1355 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1357 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1361 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1364 // Normally, it's not safe to use register enum values directly with
1365 // addition to get the next register, but for VFP registers, the
1366 // sort order is guaranteed because they're all of the form D<n>.
1368 printRegName(O, MI->getOperand(OpNum).getReg());
1370 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1372 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1374 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1378 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1381 unsigned Reg = MI->getOperand(OpNum).getReg();
1382 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1383 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1385 printRegName(O, Reg0);
1387 printRegName(O, Reg1);
1391 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1394 // Normally, it's not safe to use register enum values directly with
1395 // addition to get the next register, but for VFP registers, the
1396 // sort order is guaranteed because they're all of the form D<n>.
1398 printRegName(O, MI->getOperand(OpNum).getReg());
1400 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1402 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1406 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1409 // Normally, it's not safe to use register enum values directly with
1410 // addition to get the next register, but for VFP registers, the
1411 // sort order is guaranteed because they're all of the form D<n>.
1413 printRegName(O, MI->getOperand(OpNum).getReg());
1415 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1417 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1419 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1423 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1426 // Normally, it's not safe to use register enum values directly with
1427 // addition to get the next register, but for VFP registers, the
1428 // sort order is guaranteed because they're all of the form D<n>.
1430 printRegName(O, MI->getOperand(OpNum).getReg());
1432 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1434 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1438 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1441 // Normally, it's not safe to use register enum values directly with
1442 // addition to get the next register, but for VFP registers, the
1443 // sort order is guaranteed because they're all of the form D<n>.
1445 printRegName(O, MI->getOperand(OpNum).getReg());
1447 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1449 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1451 printRegName(O, MI->getOperand(OpNum).getReg() + 6);