1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
39 // Fields used for relation models.
42 // For cases where multiple instruction definitions really represent the
43 // same underlying instruction but with one definition for 64-bit arguments
44 // and one for 32-bit arguments, this bit breaks the degeneracy between
45 // the two forms and allows TableGen to generate mapping tables.
46 bit Interpretation64Bit = 0;
49 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
50 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
51 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
52 class PPC970_MicroCode;
54 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
55 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
56 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
57 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
58 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
59 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
60 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
61 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
63 // Two joined instructions; used to emit two adjacent instructions as one.
64 // The itinerary from the first instruction is used for scheduling and
66 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
71 bit PPC64 = 0; // Default value, override with isPPC64
73 let Namespace = "PPC";
74 let Inst{0-5} = opcode1;
75 let Inst{32-37} = opcode2;
76 let OutOperandList = OOL;
77 let InOperandList = IOL;
78 let AsmString = asmstr;
81 bits<1> PPC970_First = 0;
82 bits<1> PPC970_Single = 0;
83 bits<1> PPC970_Cracked = 0;
84 bits<3> PPC970_Unit = 0;
86 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
87 /// these must be reflected there! See comments there for what these are.
88 let TSFlags{0} = PPC970_First;
89 let TSFlags{1} = PPC970_Single;
90 let TSFlags{2} = PPC970_Cracked;
91 let TSFlags{5-3} = PPC970_Unit;
93 // Fields used for relation models.
95 bit Interpretation64Bit = 0;
99 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
100 InstrItinClass itin, list<dag> pattern>
101 : I<opcode, OOL, IOL, asmstr, itin> {
102 let Pattern = pattern;
111 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
112 : I<opcode, OOL, IOL, asmstr, BrB> {
113 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
118 let BI{0-1} = BIBO{5-6};
119 let BI{2-4} = CR{0-2};
121 let Inst{6-10} = BIBO{4-0};
122 let Inst{11-15} = BI;
123 let Inst{16-29} = BD;
128 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
130 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
136 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
137 dag OOL, dag IOL, string asmstr>
138 : I<opcode, OOL, IOL, asmstr, BrB> {
142 let Inst{11-15} = bi;
143 let Inst{16-29} = BD;
149 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
150 InstrItinClass itin, list<dag> pattern>
151 : I<opcode, OOL, IOL, asmstr, itin> {
156 let Pattern = pattern;
163 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
164 InstrItinClass itin, list<dag> pattern>
165 : I<opcode, OOL, IOL, asmstr, itin> {
169 let Pattern = pattern;
172 let Inst{11-15} = Addr{20-16}; // Base Reg
173 let Inst{16-31} = Addr{15-0}; // Displacement
176 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
177 InstrItinClass itin, list<dag> pattern>
178 : I<opcode, OOL, IOL, asmstr, itin> {
183 let Pattern = pattern;
191 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
192 InstrItinClass itin, list<dag> pattern>
193 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
195 // Even though ADDICo does not really have an RC bit, provide
196 // the declaration of one here so that isDOT has something to set.
200 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
201 InstrItinClass itin, list<dag> pattern>
202 : I<opcode, OOL, IOL, asmstr, itin> {
206 let Pattern = pattern;
213 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
214 InstrItinClass itin, list<dag> pattern>
215 : I<opcode, OOL, IOL, asmstr, itin> {
220 let Pattern = pattern;
227 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
228 InstrItinClass itin, list<dag> pattern>
229 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
234 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
235 dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
241 let Pattern = pattern;
249 let Inst{43-47} = Addr{20-16}; // Base Reg
250 let Inst{48-63} = Addr{15-0}; // Displacement
253 // This is used to emit BL8+NOP.
254 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
255 dag OOL, dag IOL, string asmstr,
256 InstrItinClass itin, list<dag> pattern>
257 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
258 OOL, IOL, asmstr, itin, pattern> {
263 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
265 : I<opcode, OOL, IOL, asmstr, itin> {
274 let Inst{11-15} = RA;
278 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
280 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
284 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
286 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
288 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
290 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
296 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
297 InstrItinClass itin, list<dag> pattern>
298 : I<opcode, OOL, IOL, asmstr, itin> {
302 let Pattern = pattern;
304 let Inst{6-10} = RST;
305 let Inst{11-15} = DS_RA{18-14}; // Register #
306 let Inst{16-29} = DS_RA{13-0}; // Displacement.
307 let Inst{30-31} = xo;
310 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
311 InstrItinClass itin, list<dag> pattern>
312 : I<opcode, OOL, IOL, asmstr, itin> {
317 let Pattern = pattern;
319 let Inst{6-10} = RST;
320 let Inst{11-15} = RA;
321 let Inst{16-29} = DS;
322 let Inst{30-31} = xo;
326 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
327 InstrItinClass itin, list<dag> pattern>
328 : I<opcode, OOL, IOL, asmstr, itin> {
333 let Pattern = pattern;
335 bit RC = 0; // set by isDOT
337 let Inst{6-10} = RST;
340 let Inst{21-30} = xo;
344 // This is the same as XForm_base_r3xo, but the first two operands are swapped
345 // when code is emitted.
346 class XForm_base_r3xo_swapped
347 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
349 : I<opcode, OOL, IOL, asmstr, itin> {
354 bit RC = 0; // set by isDOT
356 let Inst{6-10} = RST;
359 let Inst{21-30} = xo;
364 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
365 InstrItinClass itin, list<dag> pattern>
366 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
368 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
369 InstrItinClass itin, list<dag> pattern>
370 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
374 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
375 InstrItinClass itin, list<dag> pattern>
376 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
377 let Pattern = pattern;
380 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
381 InstrItinClass itin, list<dag> pattern>
382 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
384 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
385 InstrItinClass itin, list<dag> pattern>
386 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
387 let Pattern = pattern;
390 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
391 InstrItinClass itin, list<dag> pattern>
392 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
394 let Pattern = pattern;
397 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
399 : I<opcode, OOL, IOL, asmstr, itin> {
408 let Inst{11-15} = RA;
409 let Inst{16-20} = RB;
410 let Inst{21-30} = xo;
414 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
416 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
420 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
422 : I<opcode, OOL, IOL, asmstr, itin> {
429 let Inst{11-15} = FRA;
430 let Inst{16-20} = FRB;
431 let Inst{21-30} = xo;
435 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
436 InstrItinClass itin, list<dag> pattern>
437 : I<opcode, OOL, IOL, asmstr, itin> {
438 let Pattern = pattern;
442 let Inst{21-30} = xo;
446 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
447 string asmstr, InstrItinClass itin, list<dag> pattern>
448 : I<opcode, OOL, IOL, asmstr, itin> {
449 let Pattern = pattern;
453 let Inst{21-30} = xo;
457 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
458 InstrItinClass itin, list<dag> pattern>
459 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
462 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
463 InstrItinClass itin, list<dag> pattern>
464 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
468 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
469 InstrItinClass itin, list<dag> pattern>
470 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
473 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
474 // numbers presumably relates to some document, but I haven't found it.
475 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
476 InstrItinClass itin, list<dag> pattern>
477 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
478 let Pattern = pattern;
480 bit RC = 0; // set by isDOT
482 let Inst{6-10} = RST;
484 let Inst{21-30} = xo;
487 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
488 InstrItinClass itin, list<dag> pattern>
489 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
490 let Pattern = pattern;
493 bit RC = 0; // set by isDOT
497 let Inst{21-30} = xo;
501 // DCB_Form - Form X instruction, used for dcb* instructions.
502 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
503 InstrItinClass itin, list<dag> pattern>
504 : I<31, OOL, IOL, asmstr, itin> {
508 let Pattern = pattern;
510 let Inst{6-10} = immfield;
513 let Inst{21-30} = xo;
518 // DSS_Form - Form X instruction, used for altivec dss* instructions.
519 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
520 InstrItinClass itin, list<dag> pattern>
521 : I<31, OOL, IOL, asmstr, itin> {
527 let Pattern = pattern;
531 let Inst{9-10} = STRM;
534 let Inst{21-30} = xo;
539 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
540 InstrItinClass itin, list<dag> pattern>
541 : I<opcode, OOL, IOL, asmstr, itin> {
546 let Pattern = pattern;
548 let Inst{6-10} = CRD;
549 let Inst{11-15} = CRA;
550 let Inst{16-20} = CRB;
551 let Inst{21-30} = xo;
555 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
556 InstrItinClass itin, list<dag> pattern>
557 : I<opcode, OOL, IOL, asmstr, itin> {
560 let Pattern = pattern;
562 let Inst{6-10} = CRD;
563 let Inst{11-15} = CRD;
564 let Inst{16-20} = CRD;
565 let Inst{21-30} = xo;
569 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
570 InstrItinClass itin, list<dag> pattern>
571 : I<opcode, OOL, IOL, asmstr, itin> {
576 let Pattern = pattern;
579 let Inst{11-15} = BI;
581 let Inst{19-20} = BH;
582 let Inst{21-30} = xo;
586 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
587 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
588 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
589 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
593 let BI{0-1} = BIBO{5-6};
594 let BI{2-4} = CR{0-2};
599 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
600 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
601 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
607 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
609 : I<opcode, OOL, IOL, asmstr, itin> {
615 let Inst{11-13} = BFA;
618 let Inst{21-30} = xo;
623 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
625 : I<opcode, OOL, IOL, asmstr, itin> {
630 let Inst{11} = SPR{4};
631 let Inst{12} = SPR{3};
632 let Inst{13} = SPR{2};
633 let Inst{14} = SPR{1};
634 let Inst{15} = SPR{0};
635 let Inst{16} = SPR{9};
636 let Inst{17} = SPR{8};
637 let Inst{18} = SPR{7};
638 let Inst{19} = SPR{6};
639 let Inst{20} = SPR{5};
640 let Inst{21-30} = xo;
644 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
645 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
646 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
650 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
652 : I<opcode, OOL, IOL, asmstr, itin> {
657 let Inst{21-30} = xo;
661 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
663 : I<opcode, OOL, IOL, asmstr, itin> {
669 let Inst{12-19} = FXM;
671 let Inst{21-30} = xo;
675 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
677 : I<opcode, OOL, IOL, asmstr, itin> {
683 let Inst{12-19} = FXM;
685 let Inst{21-30} = xo;
689 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
691 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
693 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
694 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
695 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
700 // This is probably 1.7.9, but I don't have the reference that uses this
701 // numbering scheme...
702 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
703 InstrItinClass itin, list<dag>pattern>
704 : I<opcode, OOL, IOL, asmstr, itin> {
708 bit RC = 0; // set by isDOT
709 let Pattern = pattern;
714 let Inst{16-20} = rT;
715 let Inst{21-30} = xo;
719 // 1.7.10 XS-Form - SRADI.
720 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
721 InstrItinClass itin, list<dag> pattern>
722 : I<opcode, OOL, IOL, asmstr, itin> {
727 bit RC = 0; // set by isDOT
728 let Pattern = pattern;
732 let Inst{16-20} = SH{4,3,2,1,0};
733 let Inst{21-29} = xo;
734 let Inst{30} = SH{5};
739 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
740 InstrItinClass itin, list<dag> pattern>
741 : I<opcode, OOL, IOL, asmstr, itin> {
746 let Pattern = pattern;
748 bit RC = 0; // set by isDOT
751 let Inst{11-15} = RA;
752 let Inst{16-20} = RB;
754 let Inst{22-30} = xo;
758 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
759 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
760 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
765 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
766 InstrItinClass itin, list<dag> pattern>
767 : I<opcode, OOL, IOL, asmstr, itin> {
773 let Pattern = pattern;
775 bit RC = 0; // set by isDOT
777 let Inst{6-10} = FRT;
778 let Inst{11-15} = FRA;
779 let Inst{16-20} = FRB;
780 let Inst{21-25} = FRC;
781 let Inst{26-30} = xo;
785 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
786 InstrItinClass itin, list<dag> pattern>
787 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
791 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
792 InstrItinClass itin, list<dag> pattern>
793 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
797 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
798 InstrItinClass itin, list<dag> pattern>
799 : I<opcode, OOL, IOL, asmstr, itin> {
805 let Pattern = pattern;
808 let Inst{11-15} = RA;
809 let Inst{16-20} = RB;
810 let Inst{21-25} = COND;
811 let Inst{26-30} = xo;
816 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
817 InstrItinClass itin, list<dag> pattern>
818 : I<opcode, OOL, IOL, asmstr, itin> {
825 let Pattern = pattern;
827 bit RC = 0; // set by isDOT
830 let Inst{11-15} = RA;
831 let Inst{16-20} = RB;
832 let Inst{21-25} = MB;
833 let Inst{26-30} = ME;
837 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
838 InstrItinClass itin, list<dag> pattern>
839 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
843 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
844 InstrItinClass itin, list<dag> pattern>
845 : I<opcode, OOL, IOL, asmstr, itin> {
851 let Pattern = pattern;
853 bit RC = 0; // set by isDOT
856 let Inst{11-15} = RA;
857 let Inst{16-20} = SH{4,3,2,1,0};
858 let Inst{21-26} = MBE{4,3,2,1,0,5};
859 let Inst{27-29} = xo;
860 let Inst{30} = SH{5};
864 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
865 InstrItinClass itin, list<dag> pattern>
866 : I<opcode, OOL, IOL, asmstr, itin> {
872 let Pattern = pattern;
874 bit RC = 0; // set by isDOT
877 let Inst{11-15} = RA;
878 let Inst{16-20} = RB;
879 let Inst{21-26} = MBE{4,3,2,1,0,5};
880 let Inst{27-30} = xo;
887 // VAForm_1 - DACB ordering.
888 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
889 InstrItinClass itin, list<dag> pattern>
890 : I<4, OOL, IOL, asmstr, itin> {
896 let Pattern = pattern;
899 let Inst{11-15} = VA;
900 let Inst{16-20} = VB;
901 let Inst{21-25} = VC;
902 let Inst{26-31} = xo;
905 // VAForm_1a - DABC ordering.
906 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
907 InstrItinClass itin, list<dag> pattern>
908 : I<4, OOL, IOL, asmstr, itin> {
914 let Pattern = pattern;
917 let Inst{11-15} = VA;
918 let Inst{16-20} = VB;
919 let Inst{21-25} = VC;
920 let Inst{26-31} = xo;
923 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
924 InstrItinClass itin, list<dag> pattern>
925 : I<4, OOL, IOL, asmstr, itin> {
931 let Pattern = pattern;
934 let Inst{11-15} = VA;
935 let Inst{16-20} = VB;
937 let Inst{22-25} = SH;
938 let Inst{26-31} = xo;
942 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
943 InstrItinClass itin, list<dag> pattern>
944 : I<4, OOL, IOL, asmstr, itin> {
949 let Pattern = pattern;
952 let Inst{11-15} = VA;
953 let Inst{16-20} = VB;
954 let Inst{21-31} = xo;
957 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
958 InstrItinClass itin, list<dag> pattern>
959 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
965 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
966 InstrItinClass itin, list<dag> pattern>
967 : I<4, OOL, IOL, asmstr, itin> {
971 let Pattern = pattern;
975 let Inst{16-20} = VB;
976 let Inst{21-31} = xo;
979 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
980 InstrItinClass itin, list<dag> pattern>
981 : I<4, OOL, IOL, asmstr, itin> {
985 let Pattern = pattern;
988 let Inst{11-15} = IMM;
990 let Inst{21-31} = xo;
993 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
994 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
995 InstrItinClass itin, list<dag> pattern>
996 : I<4, OOL, IOL, asmstr, itin> {
999 let Pattern = pattern;
1001 let Inst{6-10} = VD;
1002 let Inst{11-15} = 0;
1003 let Inst{16-20} = 0;
1004 let Inst{21-31} = xo;
1007 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1008 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1009 InstrItinClass itin, list<dag> pattern>
1010 : I<4, OOL, IOL, asmstr, itin> {
1013 let Pattern = pattern;
1016 let Inst{11-15} = 0;
1017 let Inst{16-20} = VB;
1018 let Inst{21-31} = xo;
1022 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1023 InstrItinClass itin, list<dag> pattern>
1024 : I<4, OOL, IOL, asmstr, itin> {
1030 let Pattern = pattern;
1032 let Inst{6-10} = VD;
1033 let Inst{11-15} = VA;
1034 let Inst{16-20} = VB;
1036 let Inst{22-31} = xo;
1039 //===----------------------------------------------------------------------===//
1040 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1041 : I<0, OOL, IOL, asmstr, NoItinerary> {
1042 let isCodeGenOnly = 1;
1044 let Pattern = pattern;