1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/MC/MCExpr.h"
12 #include "llvm/MC/MCInst.h"
13 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
14 #include "llvm/MC/MCStreamer.h"
15 #include "llvm/MC/MCSubtargetInfo.h"
16 #include "llvm/MC/MCTargetAsmParser.h"
17 #include "llvm/Support/TargetRegistry.h"
21 // Return true if Expr is in the range [MinValue, MaxValue].
22 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
23 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
24 int64_t Value = CE->getValue();
25 return Value >= MinValue && Value <= MaxValue;
31 class SystemZOperand : public MCParsedAsmOperand {
54 SMLoc StartLoc, EndLoc;
56 // A string of length Length, starting at Data.
62 // LLVM register Num, which has kind Kind.
68 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
69 // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
86 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
87 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc)
90 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
91 // Add as immediates when possible. Null MCExpr = 0.
93 Inst.addOperand(MCOperand::CreateImm(0));
94 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
95 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
97 Inst.addOperand(MCOperand::CreateExpr(Expr));
101 // Create particular kinds of operand.
102 static SystemZOperand *createToken(StringRef Str, SMLoc Loc) {
103 SystemZOperand *Op = new SystemZOperand(KindToken, Loc, Loc);
104 Op->Token.Data = Str.data();
105 Op->Token.Length = Str.size();
108 static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
109 SMLoc StartLoc, SMLoc EndLoc) {
110 SystemZOperand *Op = new SystemZOperand(KindReg, StartLoc, EndLoc);
115 static SystemZOperand *createAccessReg(unsigned Num, SMLoc StartLoc,
117 SystemZOperand *Op = new SystemZOperand(KindAccessReg, StartLoc, EndLoc);
121 static SystemZOperand *createImm(const MCExpr *Expr, SMLoc StartLoc,
123 SystemZOperand *Op = new SystemZOperand(KindImm, StartLoc, EndLoc);
127 static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
128 const MCExpr *Disp, unsigned Index,
129 SMLoc StartLoc, SMLoc EndLoc) {
130 SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
131 Op->Mem.RegKind = RegKind;
133 Op->Mem.Index = Index;
139 virtual bool isToken() const LLVM_OVERRIDE {
140 return Kind == KindToken;
142 StringRef getToken() const {
143 assert(Kind == KindToken && "Not a token");
144 return StringRef(Token.Data, Token.Length);
147 // Register operands.
148 virtual bool isReg() const LLVM_OVERRIDE {
149 return Kind == KindReg;
151 bool isReg(RegisterKind RegKind) const {
152 return Kind == KindReg && Reg.Kind == RegKind;
154 virtual unsigned getReg() const LLVM_OVERRIDE {
155 assert(Kind == KindReg && "Not a register");
159 // Access register operands. Access registers aren't exposed to LLVM
161 bool isAccessReg() const {
162 return Kind == KindAccessReg;
165 // Immediate operands.
166 virtual bool isImm() const LLVM_OVERRIDE {
167 return Kind == KindImm;
169 bool isImm(int64_t MinValue, int64_t MaxValue) const {
170 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
172 const MCExpr *getImm() const {
173 assert(Kind == KindImm && "Not an immediate");
178 virtual bool isMem() const LLVM_OVERRIDE {
179 return Kind == KindMem;
181 bool isMem(RegisterKind RegKind, bool HasIndex) const {
182 return (Kind == KindMem &&
183 Mem.RegKind == RegKind &&
184 (HasIndex || !Mem.Index));
186 bool isMemDisp12(RegisterKind RegKind, bool HasIndex) const {
187 return isMem(RegKind, HasIndex) && inRange(Mem.Disp, 0, 0xfff);
189 bool isMemDisp20(RegisterKind RegKind, bool HasIndex) const {
190 return isMem(RegKind, HasIndex) && inRange(Mem.Disp, -524288, 524287);
193 // Override MCParsedAsmOperand.
194 virtual SMLoc getStartLoc() const LLVM_OVERRIDE { return StartLoc; }
195 virtual SMLoc getEndLoc() const LLVM_OVERRIDE { return EndLoc; }
196 virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
198 // Used by the TableGen code to add particular types of operand
199 // to an instruction.
200 void addRegOperands(MCInst &Inst, unsigned N) const {
201 assert(N == 1 && "Invalid number of operands");
202 Inst.addOperand(MCOperand::CreateReg(getReg()));
204 void addAccessRegOperands(MCInst &Inst, unsigned N) const {
205 assert(N == 1 && "Invalid number of operands");
206 assert(Kind == KindAccessReg && "Invalid operand type");
207 Inst.addOperand(MCOperand::CreateImm(AccessReg));
209 void addImmOperands(MCInst &Inst, unsigned N) const {
210 assert(N == 1 && "Invalid number of operands");
211 addExpr(Inst, getImm());
213 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
214 assert(N == 2 && "Invalid number of operands");
215 assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
216 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
217 addExpr(Inst, Mem.Disp);
219 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
220 assert(N == 3 && "Invalid number of operands");
221 assert(Kind == KindMem && "Invalid operand type");
222 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
223 addExpr(Inst, Mem.Disp);
224 Inst.addOperand(MCOperand::CreateReg(Mem.Index));
227 // Used by the TableGen code to check for particular operand types.
228 bool isGR32() const { return isReg(GR32Reg); }
229 bool isGR64() const { return isReg(GR64Reg); }
230 bool isGR128() const { return isReg(GR128Reg); }
231 bool isADDR32() const { return isReg(ADDR32Reg); }
232 bool isADDR64() const { return isReg(ADDR64Reg); }
233 bool isADDR128() const { return false; }
234 bool isFP32() const { return isReg(FP32Reg); }
235 bool isFP64() const { return isReg(FP64Reg); }
236 bool isFP128() const { return isReg(FP128Reg); }
237 bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, false); }
238 bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, false); }
239 bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, false); }
240 bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, false); }
241 bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, true); }
242 bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, true); }
243 bool isU4Imm() const { return isImm(0, 15); }
244 bool isU6Imm() const { return isImm(0, 63); }
245 bool isU8Imm() const { return isImm(0, 255); }
246 bool isS8Imm() const { return isImm(-128, 127); }
247 bool isU16Imm() const { return isImm(0, 65535); }
248 bool isS16Imm() const { return isImm(-32768, 32767); }
249 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
250 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
253 // Maps of asm register numbers to LLVM register numbers, with 0 indicating
254 // an invalid register. We don't use register class directly because that
255 // specifies the allocation order.
256 static const unsigned GR32Regs[] = {
257 SystemZ::R0W, SystemZ::R1W, SystemZ::R2W, SystemZ::R3W,
258 SystemZ::R4W, SystemZ::R5W, SystemZ::R6W, SystemZ::R7W,
259 SystemZ::R8W, SystemZ::R9W, SystemZ::R10W, SystemZ::R11W,
260 SystemZ::R12W, SystemZ::R13W, SystemZ::R14W, SystemZ::R15W
262 static const unsigned GR64Regs[] = {
263 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
264 SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
265 SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
266 SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D
268 static const unsigned GR128Regs[] = {
269 SystemZ::R0Q, 0, SystemZ::R2Q, 0,
270 SystemZ::R4Q, 0, SystemZ::R6Q, 0,
271 SystemZ::R8Q, 0, SystemZ::R10Q, 0,
272 SystemZ::R12Q, 0, SystemZ::R14Q, 0
274 static const unsigned FP32Regs[] = {
275 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
276 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
277 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
278 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S
280 static const unsigned FP64Regs[] = {
281 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
282 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
283 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
284 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D
286 static const unsigned FP128Regs[] = {
287 SystemZ::F0Q, SystemZ::F1Q, 0, 0,
288 SystemZ::F4Q, SystemZ::F5Q, 0, 0,
289 SystemZ::F8Q, SystemZ::F9Q, 0, 0,
290 SystemZ::F12Q, SystemZ::F13Q, 0, 0
293 class SystemZAsmParser : public MCTargetAsmParser {
294 #define GET_ASSEMBLER_HEADER
295 #include "SystemZGenAsmMatcher.inc"
298 MCSubtargetInfo &STI;
303 SMLoc StartLoc, EndLoc;
306 bool parseRegister(Register &Reg);
309 parseRegister(Register &Reg, char Prefix, const unsigned *Regs,
310 bool IsAddress = false);
313 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
314 char Prefix, const unsigned *Regs,
315 SystemZOperand::RegisterKind Kind,
316 bool IsAddress = false);
319 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
320 const unsigned *Regs, SystemZOperand::RegisterKind RegKind,
323 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
327 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
328 : MCTargetAsmParser(), STI(sti), Parser(parser) {
329 MCAsmParserExtension::Initialize(Parser);
331 // Initialize the set of available features.
332 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
335 // Override MCTargetAsmParser.
336 virtual bool ParseDirective(AsmToken DirectiveID) LLVM_OVERRIDE;
337 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
338 SMLoc &EndLoc) LLVM_OVERRIDE;
339 virtual bool ParseInstruction(ParseInstructionInfo &Info,
340 StringRef Name, SMLoc NameLoc,
341 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
344 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
345 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
346 MCStreamer &Out, unsigned &ErrorInfo,
347 bool MatchingInlineAsm) LLVM_OVERRIDE;
349 // Used by the TableGen code to parse particular operand types.
351 parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
352 return parseRegister(Operands, 'r', GR32Regs, SystemZOperand::GR32Reg);
355 parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
356 return parseRegister(Operands, 'r', GR64Regs, SystemZOperand::GR64Reg);
359 parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
360 return parseRegister(Operands, 'r', GR128Regs, SystemZOperand::GR128Reg);
363 parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
364 return parseRegister(Operands, 'r', GR32Regs, SystemZOperand::ADDR32Reg,
368 parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
369 return parseRegister(Operands, 'r', GR64Regs, SystemZOperand::ADDR64Reg,
373 parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
374 llvm_unreachable("Shouldn't be used as an operand");
377 parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
378 return parseRegister(Operands, 'f', FP32Regs, SystemZOperand::FP32Reg);
381 parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
382 return parseRegister(Operands, 'f', FP64Regs, SystemZOperand::FP64Reg);
385 parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
386 return parseRegister(Operands, 'f', FP128Regs, SystemZOperand::FP128Reg);
389 parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
390 return parseAddress(Operands, GR32Regs, SystemZOperand::ADDR32Reg, false);
393 parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
394 return parseAddress(Operands, GR64Regs, SystemZOperand::ADDR64Reg, false);
397 parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
398 return parseAddress(Operands, GR64Regs, SystemZOperand::ADDR64Reg, true);
401 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
405 #define GET_REGISTER_MATCHER
406 #define GET_SUBTARGET_FEATURE_NAME
407 #define GET_MATCHER_IMPLEMENTATION
408 #include "SystemZGenAsmMatcher.inc"
410 void SystemZOperand::print(raw_ostream &OS) const {
411 llvm_unreachable("Not implemented");
414 // Parse one register of the form %<prefix><number>.
415 bool SystemZAsmParser::parseRegister(Register &Reg) {
416 Reg.StartLoc = Parser.getTok().getLoc();
419 if (Parser.getTok().isNot(AsmToken::Percent))
423 // Expect a register name.
424 if (Parser.getTok().isNot(AsmToken::Identifier))
428 StringRef Name = Parser.getTok().getString();
431 Reg.Prefix = Name[0];
433 // Treat the rest of the register name as a register number.
434 if (Name.substr(1).getAsInteger(10, Reg.Number))
437 Reg.EndLoc = Parser.getTok().getLoc();
442 // Parse a register with prefix Prefix and convert it to LLVM numbering.
443 // Regs maps asm register numbers to LLVM register numbers, with zero
444 // entries indicating an invalid register. IsAddress says whether the
445 // register appears in an address context.
446 SystemZAsmParser::OperandMatchResultTy
447 SystemZAsmParser::parseRegister(Register &Reg, char Prefix,
448 const unsigned *Regs, bool IsAddress) {
449 if (parseRegister(Reg))
450 return MatchOperand_NoMatch;
451 if (Reg.Prefix != Prefix || Reg.Number > 15 || Regs[Reg.Number] == 0) {
452 Error(Reg.StartLoc, "invalid register");
453 return MatchOperand_ParseFail;
455 if (Reg.Number == 0 && IsAddress) {
456 Error(Reg.StartLoc, "%r0 used in an address");
457 return MatchOperand_ParseFail;
459 Reg.Number = Regs[Reg.Number];
460 return MatchOperand_Success;
463 // Parse a register and add it to Operands. Prefix is 'r' for GPRs,
464 // 'f' for FPRs, etc. Regs maps asm register numbers to LLVM register numbers,
465 // with zero entries indicating an invalid register. Kind is the type of
466 // register represented by Regs and IsAddress says whether the register is
467 // being parsed in an address context, meaning that %r0 evaluates as 0.
468 SystemZAsmParser::OperandMatchResultTy
469 SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
470 char Prefix, const unsigned *Regs,
471 SystemZOperand::RegisterKind Kind,
474 OperandMatchResultTy Result = parseRegister(Reg, Prefix, Regs, IsAddress);
475 if (Result == MatchOperand_Success)
476 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Number,
477 Reg.StartLoc, Reg.EndLoc));
481 // Parse a memory operand and add it to Operands. Regs maps asm register
482 // numbers to LLVM address registers and RegKind says what kind of address
483 // register we're using (ADDR32Reg or ADDR64Reg). HasIndex says whether
484 // the address allows index registers.
485 SystemZAsmParser::OperandMatchResultTy
486 SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
487 const unsigned *Regs,
488 SystemZOperand::RegisterKind RegKind,
490 SMLoc StartLoc = Parser.getTok().getLoc();
492 // Parse the displacement, which must always be present.
494 if (getParser().parseExpression(Disp))
495 return MatchOperand_NoMatch;
497 // Parse the optional base and index.
500 if (getLexer().is(AsmToken::LParen)) {
503 // Parse the first register.
505 OperandMatchResultTy Result = parseRegister(Reg, 'r', GR64Regs, true);
506 if (Result != MatchOperand_Success)
509 // Check whether there's a second register. If so, the one that we
510 // just parsed was the index.
511 if (getLexer().is(AsmToken::Comma)) {
515 Error(Reg.StartLoc, "invalid use of indexed addressing");
516 return MatchOperand_ParseFail;
520 Result = parseRegister(Reg, 'r', GR64Regs, true);
521 if (Result != MatchOperand_Success)
526 // Consume the closing bracket.
527 if (getLexer().isNot(AsmToken::RParen))
528 return MatchOperand_NoMatch;
533 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
534 Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
536 return MatchOperand_Success;
539 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
543 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
546 if (parseRegister(Reg))
547 return Error(Reg.StartLoc, "register expected");
548 if (Reg.Prefix == 'r' && Reg.Number < 16)
549 RegNo = GR64Regs[Reg.Number];
550 else if (Reg.Prefix == 'f' && Reg.Number < 16)
551 RegNo = FP64Regs[Reg.Number];
553 return Error(Reg.StartLoc, "invalid register");
554 StartLoc = Reg.StartLoc;
559 bool SystemZAsmParser::
560 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
561 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
562 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
564 // Read the remaining operands.
565 if (getLexer().isNot(AsmToken::EndOfStatement)) {
566 // Read the first operand.
567 if (parseOperand(Operands, Name)) {
568 Parser.eatToEndOfStatement();
572 // Read any subsequent operands.
573 while (getLexer().is(AsmToken::Comma)) {
575 if (parseOperand(Operands, Name)) {
576 Parser.eatToEndOfStatement();
580 if (getLexer().isNot(AsmToken::EndOfStatement)) {
581 SMLoc Loc = getLexer().getLoc();
582 Parser.eatToEndOfStatement();
583 return Error(Loc, "unexpected token in argument list");
587 // Consume the EndOfStatement.
592 bool SystemZAsmParser::
593 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
594 StringRef Mnemonic) {
595 // Check if the current operand has a custom associated parser, if so, try to
596 // custom parse the operand, or fallback to the general approach.
597 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
598 if (ResTy == MatchOperand_Success)
601 // If there wasn't a custom match, try the generic matcher below. Otherwise,
602 // there was a match, but an error occurred, in which case, just return that
603 // the operand parsing failed.
604 if (ResTy == MatchOperand_ParseFail)
607 // The only other type of operand is an immediate.
609 SMLoc StartLoc = Parser.getTok().getLoc();
610 if (getParser().parseExpression(Expr))
614 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
615 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
619 bool SystemZAsmParser::
620 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
621 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
622 MCStreamer &Out, unsigned &ErrorInfo,
623 bool MatchingInlineAsm) {
625 unsigned MatchResult;
627 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
629 switch (MatchResult) {
633 Out.EmitInstruction(Inst);
636 case Match_MissingFeature: {
637 assert(ErrorInfo && "Unknown missing feature!");
638 // Special case the error message for the very common case where only
639 // a single subtarget feature is missing
640 std::string Msg = "instruction requires:";
642 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
643 if (ErrorInfo & Mask) {
645 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
649 return Error(IDLoc, Msg);
652 case Match_InvalidOperand: {
653 SMLoc ErrorLoc = IDLoc;
654 if (ErrorInfo != ~0U) {
655 if (ErrorInfo >= Operands.size())
656 return Error(IDLoc, "too few operands for instruction");
658 ErrorLoc = ((SystemZOperand*)Operands[ErrorInfo])->getStartLoc();
659 if (ErrorLoc == SMLoc())
662 return Error(ErrorLoc, "invalid operand for instruction");
665 case Match_MnemonicFail:
666 return Error(IDLoc, "invalid instruction");
669 llvm_unreachable("Unexpected match type");
672 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
673 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
675 if (parseRegister(Reg))
676 return MatchOperand_NoMatch;
677 if (Reg.Prefix != 'a' || Reg.Number > 15) {
678 Error(Reg.StartLoc, "invalid register");
679 return MatchOperand_ParseFail;
681 Operands.push_back(SystemZOperand::createAccessReg(Reg.Number,
682 Reg.StartLoc, Reg.EndLoc));
683 return MatchOperand_Success;
686 // Force static initialization.
687 extern "C" void LLVMInitializeSystemZAsmParser() {
688 RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);