1 //===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class ImmediateAsmOperand<string name>
17 let RenderMethod = "addImmOperands";
20 // Constructs both a DAG pattern and instruction operand for an immediate
21 // of type VT. PRED returns true if a node is acceptable and XFORM returns
22 // the operand value associated with the node. ASMOP is the name of the
23 // associated asm operand, and also forms the basis of the asm print method.
24 class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop>
25 : PatLeaf<(vt imm), pred, xform>, Operand<vt> {
26 let PrintMethod = "print"##asmop##"Operand";
27 let ParserMatchClass = !cast<AsmOperandClass>(asmop);
30 // Constructs both a DAG pattern and instruction operand for a PC-relative
31 // address with address size VT. SELF is the name of the operand.
32 class PCRelAddress<ValueType vt, string self>
33 : ComplexPattern<vt, 1, "selectPCRelAddress", [z_pcrel_wrapper]>,
35 let MIOperandInfo = (ops !cast<Operand>(self));
38 // Constructs an AsmOperandClass for addressing mode FORMAT, treating the
39 // registers as having BITSIZE bits and displacements as having DISPSIZE bits.
40 class AddressAsmOperand<string format, string bitsize, string dispsize>
42 let Name = format##bitsize##"Disp"##dispsize;
43 let ParserMethod = "parse"##format##bitsize;
44 let RenderMethod = "add"##format##"Operands";
47 // Constructs both a DAG pattern and instruction operand for an addressing mode.
48 // The mode is selected by custom code in selectTYPE...SUFFIX(). The address
49 // registers have BITSIZE bits and displacements have DISPSIZE bits. NUMOPS is
50 // the number of operands that make up an address and OPERANDS lists the types
51 // of those operands using (ops ...). FORMAT is the type of addressing mode,
52 // which needs to match the names used in AddressAsmOperand.
53 class AddressingMode<string type, string bitsize, string dispsize,
54 string suffix, int numops, string format, dag operands>
55 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
56 "select"##type##dispsize##suffix,
57 [add, sub, or, frameindex, z_adjdynalloc]>,
58 Operand<!cast<ValueType>("i"##bitsize)> {
59 let PrintMethod = "print"##format##"Operand";
60 let MIOperandInfo = operands;
61 let ParserMatchClass =
62 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize);
65 // An addressing mode with a base and displacement but no index.
66 class BDMode<string type, string bitsize, string dispsize, string suffix>
67 : AddressingMode<type, bitsize, dispsize, suffix, 2, "BDAddr",
68 (ops !cast<RegisterOperand>("ADDR"##bitsize),
69 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>;
71 // An addressing mode with a base, displacement and index.
72 class BDXMode<string type, string bitsize, string dispsize, string suffix>
73 : AddressingMode<type, bitsize, dispsize, suffix, 3, "BDXAddr",
74 (ops !cast<RegisterOperand>("ADDR"##bitsize),
75 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
76 !cast<RegisterOperand>("ADDR"##bitsize))>;
78 //===----------------------------------------------------------------------===//
79 // Extracting immediate operands from nodes
80 // These all create MVT::i64 nodes to ensure the value is not sign-extended
81 // when converted from an SDNode to a MachineOperand later on.
82 //===----------------------------------------------------------------------===//
84 // Bits 0-15 (counting from the lsb).
85 def LL16 : SDNodeXForm<imm, [{
86 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
87 return CurDAG->getTargetConstant(Value, MVT::i64);
90 // Bits 16-31 (counting from the lsb).
91 def LH16 : SDNodeXForm<imm, [{
92 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
93 return CurDAG->getTargetConstant(Value, MVT::i64);
96 // Bits 32-47 (counting from the lsb).
97 def HL16 : SDNodeXForm<imm, [{
98 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
99 return CurDAG->getTargetConstant(Value, MVT::i64);
102 // Bits 48-63 (counting from the lsb).
103 def HH16 : SDNodeXForm<imm, [{
104 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
105 return CurDAG->getTargetConstant(Value, MVT::i64);
109 def LF32 : SDNodeXForm<imm, [{
110 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
111 return CurDAG->getTargetConstant(Value, MVT::i64);
115 def HF32 : SDNodeXForm<imm, [{
116 uint64_t Value = N->getZExtValue() >> 32;
117 return CurDAG->getTargetConstant(Value, MVT::i64);
120 // Truncate an immediate to a 8-bit signed quantity.
121 def SIMM8 : SDNodeXForm<imm, [{
122 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64);
125 // Truncate an immediate to a 8-bit unsigned quantity.
126 def UIMM8 : SDNodeXForm<imm, [{
127 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64);
130 // Truncate an immediate to a 16-bit signed quantity.
131 def SIMM16 : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64);
135 // Truncate an immediate to a 16-bit unsigned quantity.
136 def UIMM16 : SDNodeXForm<imm, [{
137 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64);
140 // Truncate an immediate to a 32-bit signed quantity.
141 def SIMM32 : SDNodeXForm<imm, [{
142 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64);
145 // Truncate an immediate to a 32-bit unsigned quantity.
146 def UIMM32 : SDNodeXForm<imm, [{
147 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64);
150 // Negate and then truncate an immediate to a 32-bit unsigned quantity.
151 def NEGIMM32 : SDNodeXForm<imm, [{
152 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64);
155 //===----------------------------------------------------------------------===//
156 // Immediate asm operands.
157 //===----------------------------------------------------------------------===//
159 def U4Imm : ImmediateAsmOperand<"U4Imm">;
160 def U6Imm : ImmediateAsmOperand<"U6Imm">;
161 def S8Imm : ImmediateAsmOperand<"S8Imm">;
162 def U8Imm : ImmediateAsmOperand<"U8Imm">;
163 def S16Imm : ImmediateAsmOperand<"S16Imm">;
164 def U16Imm : ImmediateAsmOperand<"U16Imm">;
165 def S32Imm : ImmediateAsmOperand<"S32Imm">;
166 def U32Imm : ImmediateAsmOperand<"U32Imm">;
168 //===----------------------------------------------------------------------===//
170 //===----------------------------------------------------------------------===//
172 def uimm8zx4 : Immediate<i8, [{
173 return isUInt<4>(N->getZExtValue());
174 }], NOOP_SDNodeXForm, "U4Imm">;
176 def uimm8zx6 : Immediate<i8, [{
177 return isUInt<6>(N->getZExtValue());
178 }], NOOP_SDNodeXForm, "U6Imm">;
180 def simm8 : Immediate<i8, [{}], SIMM8, "S8Imm">;
181 def uimm8 : Immediate<i8, [{}], UIMM8, "U8Imm">;
183 //===----------------------------------------------------------------------===//
185 //===----------------------------------------------------------------------===//
187 // Immediates for the lower and upper 16 bits of an i32, with the other
188 // bits of the i32 being zero.
189 def imm32ll16 : Immediate<i32, [{
190 return SystemZ::isImmLL(N->getZExtValue());
193 def imm32lh16 : Immediate<i32, [{
194 return SystemZ::isImmLH(N->getZExtValue());
197 // Immediates for the lower and upper 16 bits of an i32, with the other
198 // bits of the i32 being one.
199 def imm32ll16c : Immediate<i32, [{
200 return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
203 def imm32lh16c : Immediate<i32, [{
204 return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
208 def imm32sx8 : Immediate<i32, [{
209 return isInt<8>(N->getSExtValue());
212 def imm32zx8 : Immediate<i32, [{
213 return isUInt<8>(N->getZExtValue());
216 def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
218 def imm32sx16 : Immediate<i32, [{
219 return isInt<16>(N->getSExtValue());
220 }], SIMM16, "S16Imm">;
222 def imm32zx16 : Immediate<i32, [{
223 return isUInt<16>(N->getZExtValue());
224 }], UIMM16, "U16Imm">;
226 def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
228 // Full 32-bit immediates. we need both signed and unsigned versions
229 // because the assembler is picky. E.g. AFI requires signed operands
230 // while NILF requires unsigned ones.
231 def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
232 def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
234 def imm32 : ImmLeaf<i32, [{}]>;
236 //===----------------------------------------------------------------------===//
238 //===----------------------------------------------------------------------===//
240 // Immediates for 16-bit chunks of an i64, with the other bits of the
242 def imm64ll16 : Immediate<i64, [{
243 return SystemZ::isImmLL(N->getZExtValue());
246 def imm64lh16 : Immediate<i64, [{
247 return SystemZ::isImmLH(N->getZExtValue());
250 def imm64hl16 : Immediate<i64, [{
251 return SystemZ::isImmHL(N->getZExtValue());
254 def imm64hh16 : Immediate<i64, [{
255 return SystemZ::isImmHH(N->getZExtValue());
258 // Immediates for 16-bit chunks of an i64, with the other bits of the
260 def imm64ll16c : Immediate<i64, [{
261 return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
264 def imm64lh16c : Immediate<i64, [{
265 return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
268 def imm64hl16c : Immediate<i64, [{
269 return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
272 def imm64hh16c : Immediate<i64, [{
273 return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
276 // Immediates for the lower and upper 32 bits of an i64, with the other
277 // bits of the i32 being zero.
278 def imm64lf32 : Immediate<i64, [{
279 return SystemZ::isImmLF(N->getZExtValue());
282 def imm64hf32 : Immediate<i64, [{
283 return SystemZ::isImmHF(N->getZExtValue());
286 // Immediates for the lower and upper 32 bits of an i64, with the other
287 // bits of the i32 being one.
288 def imm64lf32c : Immediate<i64, [{
289 return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
292 def imm64hf32c : Immediate<i64, [{
293 return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
297 def imm64sx8 : Immediate<i64, [{
298 return isInt<8>(N->getSExtValue());
301 def imm64sx16 : Immediate<i64, [{
302 return isInt<16>(N->getSExtValue());
303 }], SIMM16, "S16Imm">;
305 def imm64zx16 : Immediate<i64, [{
306 return isUInt<16>(N->getZExtValue());
307 }], UIMM16, "U16Imm">;
309 def imm64sx32 : Immediate<i64, [{
310 return isInt<32>(N->getSExtValue());
311 }], SIMM32, "S32Imm">;
313 def imm64zx32 : Immediate<i64, [{
314 return isUInt<32>(N->getZExtValue());
315 }], UIMM32, "U32Imm">;
317 def imm64zx32n : Immediate<i64, [{
318 return isUInt<32>(-N->getSExtValue());
319 }], NEGIMM32, "U32Imm">;
321 def imm64 : ImmLeaf<i64, [{}]>;
323 //===----------------------------------------------------------------------===//
324 // Floating-point immediates
325 //===----------------------------------------------------------------------===//
327 // Floating-point zero.
328 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
330 // Floating point negative zero.
331 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
333 //===----------------------------------------------------------------------===//
334 // Symbolic address operands
335 //===----------------------------------------------------------------------===//
337 // PC-relative offsets of a basic block. The offset is sign-extended
338 // and multiplied by 2.
339 def brtarget16 : Operand<OtherVT> {
340 let EncoderMethod = "getPC16DBLEncoding";
342 def brtarget32 : Operand<OtherVT> {
343 let EncoderMethod = "getPC32DBLEncoding";
346 // A PC-relative offset of a global value. The offset is sign-extended
347 // and multiplied by 2.
348 def pcrel32 : PCRelAddress<i64, "pcrel32"> {
349 let EncoderMethod = "getPC32DBLEncoding";
352 // A PC-relative offset of a global value when the value is used as a
353 // call target. The offset is sign-extended and multiplied by 2.
354 def pcrel16call : PCRelAddress<i64, "pcrel16call"> {
355 let PrintMethod = "printCallOperand";
356 let EncoderMethod = "getPLT16DBLEncoding";
358 def pcrel32call : PCRelAddress<i64, "pcrel32call"> {
359 let PrintMethod = "printCallOperand";
360 let EncoderMethod = "getPLT32DBLEncoding";
363 //===----------------------------------------------------------------------===//
365 //===----------------------------------------------------------------------===//
367 // 12-bit displacement operands.
368 def disp12imm32 : Operand<i32>;
369 def disp12imm64 : Operand<i64>;
371 // 20-bit displacement operands.
372 def disp20imm32 : Operand<i32>;
373 def disp20imm64 : Operand<i64>;
375 def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
376 def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
377 def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
378 def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
379 def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
380 def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
382 // DAG patterns and operands for addressing modes. Each mode has
383 // the form <type><range><group> where:
386 // shift : base + displacement (32-bit)
387 // bdaddr : base + displacement
388 // bdxaddr : base + displacement + index
389 // laaddr : like bdxaddr, but used for Load Address operations
390 // dynalloc : base + displacement + index + ADJDYNALLOC
392 // <range> is one of:
393 // 12 : the displacement is an unsigned 12-bit value
394 // 20 : the displacement is a signed 20-bit value
396 // <group> is one of:
397 // pair : used when there is an equivalent instruction with the opposite
398 // range value (12 or 20)
399 // only : used when there is no equivalent instruction with the opposite
401 def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
402 def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
403 def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
404 def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
405 def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
406 def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
407 def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
408 def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
409 def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
410 def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
411 def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
412 def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
413 def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
414 def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
416 //===----------------------------------------------------------------------===//
418 //===----------------------------------------------------------------------===//
420 // Access registers. At present we just use them for accessing the thread
421 // pointer, so we don't expose them as register to LLVM.
422 def AccessReg : AsmOperandClass {
423 let Name = "AccessReg";
424 let ParserMethod = "parseAccessReg";
426 def access_reg : Immediate<i8, [{ return N->getZExtValue() < 16; }],
427 NOOP_SDNodeXForm, "AccessReg"> {
428 let ParserMatchClass = AccessReg;
431 // A 4-bit condition-code mask.
432 def cond4 : PatLeaf<(i8 imm), [{ return (N->getZExtValue() < 16); }]>,
434 let PrintMethod = "printCond4Operand";