contrib/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

   1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// \file
  11 /// \brief This file is part of the XCore Disassembler.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "XCore.h"
  16 #include "XCoreRegisterInfo.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MemoryObject.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23
  24 using namespace llvm;
  25
  26 typedef MCDisassembler::DecodeStatus DecodeStatus;
  27
  28 namespace {
  29
  30 /// \brief A disassembler class for XCore.
  31 class XCoreDisassembler : public MCDisassembler {
  32   const MCRegisterInfo *RegInfo;
  33 public:
  34   XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
  35     MCDisassembler(STI), RegInfo(Info) {}
  36
  37   /// \brief See MCDisassembler.
  38   virtual DecodeStatus getInstruction(MCInst &instr,
  39                                       uint64_t &size,
  40                                       const MemoryObject &region,
  41                                       uint64_t address,
  42                                       raw_ostream &vStream,
  43                                       raw_ostream &cStream) const;
  44
  45   const MCRegisterInfo *getRegInfo() const { return RegInfo; }
  46 };
  47 }
  48
  49 static bool readInstruction16(const MemoryObject &region,
  50                               uint64_t address,
  51                               uint64_t &size,
  52                               uint16_t &insn) {
  53   uint8_t Bytes[4];
  54
  55   // We want to read exactly 2 Bytes of data.
  56   if (region.readBytes(address, 2, Bytes, NULL) == -1) {
  57     size = 0;
  58     return false;
  59   }
  60   // Encoded as a little-endian 16-bit word in the stream.
  61   insn = (Bytes[0] <<  0) | (Bytes[1] <<  8);
  62   return true;
  63 }
  64
  65 static bool readInstruction32(const MemoryObject &region,
  66                               uint64_t address,
  67                               uint64_t &size,
  68                               uint32_t &insn) {
  69   uint8_t Bytes[4];
  70
  71   // We want to read exactly 4 Bytes of data.
  72   if (region.readBytes(address, 4, Bytes, NULL) == -1) {
  73     size = 0;
  74     return false;
  75   }
  76   // Encoded as a little-endian 32-bit word in the stream.
  77   insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
  78          (Bytes[3] << 24);
  79   return true;
  80 }
  81
  82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
  83   const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
  84   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
  85 }
  86
  87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
  88                                               unsigned RegNo,
  89                                               uint64_t Address,
  90                                               const void *Decoder);
  91
  92 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
  93                                              unsigned RegNo,
  94                                              uint64_t Address,
  95                                              const void *Decoder);
  96
  97 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
  98                                       uint64_t Address, const void *Decoder);
  99
 100 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
 101                                         uint64_t Address, const void *Decoder);
 102
 103 static DecodeStatus Decode2RInstruction(MCInst &Inst,
 104                                         unsigned Insn,
 105                                         uint64_t Address,
 106                                         const void *Decoder);
 107
 108 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
 109                                            unsigned Insn,
 110                                            uint64_t Address,
 111                                            const void *Decoder);
 112
 113 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
 114                                          unsigned Insn,
 115                                          uint64_t Address,
 116                                          const void *Decoder);
 117
 118 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
 119                                               unsigned Insn,
 120                                               uint64_t Address,
 121                                               const void *Decoder);
 122
 123 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
 124                                          unsigned Insn,
 125                                          uint64_t Address,
 126                                          const void *Decoder);
 127
 128 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
 129                                              unsigned Insn,
 130                                              uint64_t Address,
 131                                              const void *Decoder);
 132
 133 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
 134                                                    unsigned Insn,
 135                                                    uint64_t Address,
 136                                                    const void *Decoder);
 137
 138 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
 139                                          unsigned Insn,
 140                                          uint64_t Address,
 141                                          const void *Decoder);
 142
 143 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
 144                                           unsigned Insn,
 145                                           uint64_t Address,
 146                                           const void *Decoder);
 147
 148 static DecodeStatus Decode3RInstruction(MCInst &Inst,
 149                                         unsigned Insn,
 150                                         uint64_t Address,
 151                                         const void *Decoder);
 152
 153 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
 154                                            unsigned Insn,
 155                                            uint64_t Address,
 156                                            const void *Decoder);
 157
 158 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
 159                                           unsigned Insn,
 160                                           uint64_t Address,
 161                                           const void *Decoder);
 162
 163 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
 164                                               unsigned Insn,
 165                                               uint64_t Address,
 166                                               const void *Decoder);
 167
 168 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
 169                                          unsigned Insn,
 170                                          uint64_t Address,
 171                                          const void *Decoder);
 172
 173 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
 174                                                unsigned Insn,
 175                                                uint64_t Address,
 176                                                const void *Decoder);
 177
 178 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
 179                                            unsigned Insn,
 180                                            uint64_t Address,
 181                                            const void *Decoder);
 182
 183 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
 184                                                unsigned Insn,
 185                                                uint64_t Address,
 186                                                const void *Decoder);
 187
 188 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
 189                                          unsigned Insn,
 190                                          uint64_t Address,
 191                                          const void *Decoder);
 192
 193 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
 194                                          unsigned Insn,
 195                                          uint64_t Address,
 196                                          const void *Decoder);
 197
 198 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
 199                                                unsigned Insn,
 200                                                uint64_t Address,
 201                                                const void *Decoder);
 202
 203 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
 204                                                      unsigned Insn,
 205                                                      uint64_t Address,
 206                                                      const void *Decoder);
 207
 208 #include "XCoreGenDisassemblerTables.inc"
 209
 210 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
 211                                               unsigned RegNo,
 212                                               uint64_t Address,
 213                                               const void *Decoder)
 214 {
 215   if (RegNo > 11)
 216     return MCDisassembler::Fail;
 217   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
 218   Inst.addOperand(MCOperand::CreateReg(Reg));
 219   return MCDisassembler::Success;
 220 }
 221
 222 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
 223                                              unsigned RegNo,
 224                                              uint64_t Address,
 225                                              const void *Decoder)
 226 {
 227   if (RegNo > 15)
 228     return MCDisassembler::Fail;
 229   unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
 230   Inst.addOperand(MCOperand::CreateReg(Reg));
 231   return MCDisassembler::Success;
 232 }
 233
 234 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 235                                       uint64_t Address, const void *Decoder) {
 236   if (Val > 11)
 237     return MCDisassembler::Fail;
 238   static unsigned Values[] = {
 239     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
 240   };
 241   Inst.addOperand(MCOperand::CreateImm(Values[Val]));
 242   return MCDisassembler::Success;
 243 }
 244
 245 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
 246                                         uint64_t Address, const void *Decoder) {
 247   Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
 248   return MCDisassembler::Success;
 249 }
 250
 251 static DecodeStatus
 252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
 253   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 254   if (Combined < 27)
 255     return MCDisassembler::Fail;
 256   if (fieldFromInstruction(Insn, 5, 1)) {
 257     if (Combined == 31)
 258       return MCDisassembler::Fail;
 259     Combined += 5;
 260   }
 261   Combined -= 27;
 262   unsigned Op1High = Combined % 3;
 263   unsigned Op2High = Combined / 3;
 264   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
 265   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
 266   return MCDisassembler::Success;
 267 }
 268
 269 static DecodeStatus
 270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
 271                      unsigned &Op3) {
 272   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 273   if (Combined >= 27)
 274     return MCDisassembler::Fail;
 275
 276   unsigned Op1High = Combined % 3;
 277   unsigned Op2High = (Combined / 3) % 3;
 278   unsigned Op3High = Combined / 9;
 279   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
 280   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
 281   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
 282   return MCDisassembler::Success;
 283 }
 284
 285 static DecodeStatus
 286 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 287                          const void *Decoder) {
 288   // Try and decode as a 3R instruction.
 289   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
 290   switch (Opcode) {
 291   case 0x0:
 292     Inst.setOpcode(XCore::STW_2rus);
 293     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 294   case 0x1:
 295     Inst.setOpcode(XCore::LDW_2rus);
 296     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 297   case 0x2:
 298     Inst.setOpcode(XCore::ADD_3r);
 299     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 300   case 0x3:
 301     Inst.setOpcode(XCore::SUB_3r);
 302     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 303   case 0x4:
 304     Inst.setOpcode(XCore::SHL_3r);
 305     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 306   case 0x5:
 307     Inst.setOpcode(XCore::SHR_3r);
 308     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 309   case 0x6:
 310     Inst.setOpcode(XCore::EQ_3r);
 311     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 312   case 0x7:
 313     Inst.setOpcode(XCore::AND_3r);
 314     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 315   case 0x8:
 316     Inst.setOpcode(XCore::OR_3r);
 317     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 318   case 0x9:
 319     Inst.setOpcode(XCore::LDW_3r);
 320     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 321   case 0x10:
 322     Inst.setOpcode(XCore::LD16S_3r);
 323     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 324   case 0x11:
 325     Inst.setOpcode(XCore::LD8U_3r);
 326     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 327   case 0x12:
 328     Inst.setOpcode(XCore::ADD_2rus);
 329     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 330   case 0x13:
 331     Inst.setOpcode(XCore::SUB_2rus);
 332     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 333   case 0x14:
 334     Inst.setOpcode(XCore::SHL_2rus);
 335     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 336   case 0x15:
 337     Inst.setOpcode(XCore::SHR_2rus);
 338     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 339   case 0x16:
 340     Inst.setOpcode(XCore::EQ_2rus);
 341     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 342   case 0x17:
 343     Inst.setOpcode(XCore::TSETR_3r);
 344     return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
 345   case 0x18:
 346     Inst.setOpcode(XCore::LSS_3r);
 347     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 348   case 0x19:
 349     Inst.setOpcode(XCore::LSU_3r);
 350     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 351   }
 352   return MCDisassembler::Fail;
 353 }
 354
 355 static DecodeStatus
 356 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 357                     const void *Decoder) {
 358   unsigned Op1, Op2;
 359   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 360   if (S != MCDisassembler::Success)
 361     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 362
 363   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 364   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 365   return S;
 366 }
 367
 368 static DecodeStatus
 369 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 370                        const void *Decoder) {
 371   unsigned Op1, Op2;
 372   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 373   if (S != MCDisassembler::Success)
 374     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 375
 376   Inst.addOperand(MCOperand::CreateImm(Op1));
 377   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 378   return S;
 379 }
 380
 381 static DecodeStatus
 382 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 383                      const void *Decoder) {
 384   unsigned Op1, Op2;
 385   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
 386   if (S != MCDisassembler::Success)
 387     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 388
 389   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 390   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 391   return S;
 392 }
 393
 394 static DecodeStatus
 395 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 396                           const void *Decoder) {
 397   unsigned Op1, Op2;
 398   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 399   if (S != MCDisassembler::Success)
 400     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 401
 402   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 403   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 404   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 405   return S;
 406 }
 407
 408 static DecodeStatus
 409 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 410                      const void *Decoder) {
 411   unsigned Op1, Op2;
 412   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 413   if (S != MCDisassembler::Success)
 414     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 415
 416   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 417   Inst.addOperand(MCOperand::CreateImm(Op2));
 418   return S;
 419 }
 420
 421 static DecodeStatus
 422 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 423                          const void *Decoder) {
 424   unsigned Op1, Op2;
 425   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 426   if (S != MCDisassembler::Success)
 427     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 428
 429   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 430   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 431   return S;
 432 }
 433
 434 static DecodeStatus
 435 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 436                                const void *Decoder) {
 437   unsigned Op1, Op2;
 438   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 439   if (S != MCDisassembler::Success)
 440     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 441
 442   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 443   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 444   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 445   return S;
 446 }
 447
 448 static DecodeStatus
 449 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 450                           const void *Decoder) {
 451   // Try and decode as a L3R / L2RUS instruction.
 452   unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
 453                     fieldFromInstruction(Insn, 27, 5) << 4;
 454   switch (Opcode) {
 455   case 0x0c:
 456     Inst.setOpcode(XCore::STW_l3r);
 457     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 458   case 0x1c:
 459     Inst.setOpcode(XCore::XOR_l3r);
 460     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 461   case 0x2c:
 462     Inst.setOpcode(XCore::ASHR_l3r);
 463     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 464   case 0x3c:
 465     Inst.setOpcode(XCore::LDAWF_l3r);
 466     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 467   case 0x4c:
 468     Inst.setOpcode(XCore::LDAWB_l3r);
 469     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 470   case 0x5c:
 471     Inst.setOpcode(XCore::LDA16F_l3r);
 472     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 473   case 0x6c:
 474     Inst.setOpcode(XCore::LDA16B_l3r);
 475     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 476   case 0x7c:
 477     Inst.setOpcode(XCore::MUL_l3r);
 478     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 479   case 0x8c:
 480     Inst.setOpcode(XCore::DIVS_l3r);
 481     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 482   case 0x9c:
 483     Inst.setOpcode(XCore::DIVU_l3r);
 484     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 485   case 0x10c:
 486     Inst.setOpcode(XCore::ST16_l3r);
 487     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 488   case 0x11c:
 489     Inst.setOpcode(XCore::ST8_l3r);
 490     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 491   case 0x12c:
 492     Inst.setOpcode(XCore::ASHR_l2rus);
 493     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 494   case 0x12d:
 495     Inst.setOpcode(XCore::OUTPW_l2rus);
 496     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 497   case 0x12e:
 498     Inst.setOpcode(XCore::INPW_l2rus);
 499     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 500   case 0x13c:
 501     Inst.setOpcode(XCore::LDAWF_l2rus);
 502     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 503   case 0x14c:
 504     Inst.setOpcode(XCore::LDAWB_l2rus);
 505     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 506   case 0x15c:
 507     Inst.setOpcode(XCore::CRC_l3r);
 508     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
 509   case 0x18c:
 510     Inst.setOpcode(XCore::REMS_l3r);
 511     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 512   case 0x19c:
 513     Inst.setOpcode(XCore::REMU_l3r);
 514     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 515   }
 516   return MCDisassembler::Fail;
 517 }
 518
 519 static DecodeStatus
 520 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 521                                const void *Decoder) {
 522   unsigned Op1, Op2;
 523   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 524                                         Op1, Op2);
 525   if (S != MCDisassembler::Success)
 526     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 527
 528   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 529   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 530   return S;
 531 }
 532
 533 static DecodeStatus
 534 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 535                                const void *Decoder) {
 536   unsigned Op1, Op2;
 537   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 538                                         Op1, Op2);
 539   if (S != MCDisassembler::Success)
 540     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 541
 542   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 543   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 544   return S;
 545 }
 546
 547 static DecodeStatus
 548 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 549                     const void *Decoder) {
 550   unsigned Op1, Op2, Op3;
 551   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 552   if (S == MCDisassembler::Success) {
 553     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 554     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 555     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 556   }
 557   return S;
 558 }
 559
 560 static DecodeStatus
 561 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 562                        const void *Decoder) {
 563   unsigned Op1, Op2, Op3;
 564   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 565   if (S == MCDisassembler::Success) {
 566     Inst.addOperand(MCOperand::CreateImm(Op1));
 567     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 568     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 569   }
 570   return S;
 571 }
 572
 573 static DecodeStatus
 574 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 575                       const void *Decoder) {
 576   unsigned Op1, Op2, Op3;
 577   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 578   if (S == MCDisassembler::Success) {
 579     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 580     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 581     Inst.addOperand(MCOperand::CreateImm(Op3));
 582   }
 583   return S;
 584 }
 585
 586 static DecodeStatus
 587 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 588                       const void *Decoder) {
 589   unsigned Op1, Op2, Op3;
 590   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 591   if (S == MCDisassembler::Success) {
 592     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 593     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 594     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 595   }
 596   return S;
 597 }
 598
 599 static DecodeStatus
 600 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 601                      const void *Decoder) {
 602   unsigned Op1, Op2, Op3;
 603   DecodeStatus S =
 604     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 605   if (S == MCDisassembler::Success) {
 606     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 607     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 608     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 609   }
 610   return S;
 611 }
 612
 613 static DecodeStatus
 614 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 615                            const void *Decoder) {
 616   unsigned Op1, Op2, Op3;
 617   DecodeStatus S =
 618   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 619   if (S == MCDisassembler::Success) {
 620     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 621     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 622     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 623     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 624   }
 625   return S;
 626 }
 627
 628 static DecodeStatus
 629 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 630                        const void *Decoder) {
 631   unsigned Op1, Op2, Op3;
 632   DecodeStatus S =
 633   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 634   if (S == MCDisassembler::Success) {
 635     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 636     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 637     Inst.addOperand(MCOperand::CreateImm(Op3));
 638   }
 639   return S;
 640 }
 641
 642 static DecodeStatus
 643 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 644                            const void *Decoder) {
 645   unsigned Op1, Op2, Op3;
 646   DecodeStatus S =
 647   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 648   if (S == MCDisassembler::Success) {
 649     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 650     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 651     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 652   }
 653   return S;
 654 }
 655
 656 static DecodeStatus
 657 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 658                      const void *Decoder) {
 659   unsigned Op1, Op2, Op3, Op4, Op5, Op6;
 660   DecodeStatus S =
 661     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 662   if (S != MCDisassembler::Success)
 663     return S;
 664   S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
 665   if (S != MCDisassembler::Success)
 666     return S;
 667   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 668   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 669   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 670   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 671   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 672   DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
 673   return S;
 674 }
 675
 676 static DecodeStatus
 677 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 678                      const void *Decoder) {
 679   // Try and decode as a L6R instruction.
 680   Inst.clear();
 681   unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
 682   switch (Opcode) {
 683   case 0x00:
 684     Inst.setOpcode(XCore::LMUL_l6r);
 685     return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
 686   }
 687   return MCDisassembler::Fail;
 688 }
 689
 690 static DecodeStatus
 691 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 692                      const void *Decoder) {
 693   unsigned Op1, Op2, Op3, Op4, Op5;
 694   DecodeStatus S =
 695     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 696   if (S != MCDisassembler::Success)
 697     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 698   S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
 699   if (S != MCDisassembler::Success)
 700     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 701
 702   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 703   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 704   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 705   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 706   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 707   return S;
 708 }
 709
 710 static DecodeStatus
 711 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 712                            const void *Decoder) {
 713   unsigned Op1, Op2, Op3;
 714   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
 715   DecodeStatus S =
 716     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 717   if (S == MCDisassembler::Success) {
 718     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 719     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 720   }
 721   if (S == MCDisassembler::Success) {
 722     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 723     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 724     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 725   }
 726   return S;
 727 }
 728
 729 static DecodeStatus
 730 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 731                                  const void *Decoder) {
 732   unsigned Op1, Op2, Op3;
 733   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
 734   DecodeStatus S =
 735   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 736   if (S == MCDisassembler::Success) {
 737     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 738     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 739   }
 740   if (S == MCDisassembler::Success) {
 741     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 742     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 743     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 744     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 745   }
 746   return S;
 747 }
 748
 749 MCDisassembler::DecodeStatus
 750 XCoreDisassembler::getInstruction(MCInst &instr,
 751                                   uint64_t &Size,
 752                                   const MemoryObject &Region,
 753                                   uint64_t Address,
 754                                   raw_ostream &vStream,
 755                                   raw_ostream &cStream) const {
 756   uint16_t insn16;
 757
 758   if (!readInstruction16(Region, Address, Size, insn16)) {
 759     return Fail;
 760   }
 761
 762   // Calling the auto-generated decoder function.
 763   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
 764                                           Address, this, STI);
 765   if (Result != Fail) {
 766     Size = 2;
 767     return Result;
 768   }
 769
 770   uint32_t insn32;
 771
 772   if (!readInstruction32(Region, Address, Size, insn32)) {
 773     return Fail;
 774   }
 775
 776   // Calling the auto-generated decoder function.
 777   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
 778   if (Result != Fail) {
 779     Size = 4;
 780     return Result;
 781   }
 782
 783   return Fail;
 784 }
 785
 786 namespace llvm {
 787   extern Target TheXCoreTarget;
 788 }
 789
 790 static MCDisassembler *createXCoreDisassembler(const Target &T,
 791                                                const MCSubtargetInfo &STI) {
 792   return new XCoreDisassembler(STI, T.createMCRegInfo(""));
 793 }
 794
 795 extern "C" void LLVMInitializeXCoreDisassembler() {
 796   // Register the disassembler.
 797   TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
 798                                          createXCoreDisassembler);
 799 }