1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TableGen definitions from which the ARM NEON header
11 // file will be generated. See ARM document DUI0348B.
13 //===----------------------------------------------------------------------===//
18 def OP_UNAVAILABLE : Op;
41 def OP_QDMULL_LN : Op;
42 def OP_QDMLAL_LN : Op;
43 def OP_QDMLSL_LN : Op;
44 def OP_QDMULH_LN : Op;
45 def OP_QRDMULH_LN : Op;
73 class Inst <string n, string p, string t, Op o> {
81 // Certain intrinsics have different names than their representative
82 // instructions. This field allows us to handle this correctly when we
83 // are generating tests.
86 // Certain intrinsics even though they are not a WOpInst or LOpInst,
87 // generate a WOpInst/LOpInst instruction (see below for definition
88 // of a WOpInst/LOpInst). For testing purposes we need to know
89 // this. Ex: vset_lane which outputs vmov instructions.
90 bit isHiddenWInst = 0;
91 bit isHiddenLInst = 0;
94 // The following instruction classes are implemented via builtins.
95 // These declarations are used to generate Builtins.def:
97 // SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8")
98 // IInst: Instruction with generic integer suffix (e.g., "i8")
99 // WInst: Instruction with only bit size suffix (e.g., "8")
100 class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
101 class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
102 class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {}
104 // The following instruction classes are implemented via operators
105 // instead of builtins. As such these declarations are only used for
106 // the purpose of generating tests.
108 // SOpInst: Instruction with signed/unsigned suffix (e.g., "s8",
110 // IOpInst: Instruction with generic integer suffix (e.g., "i8").
111 // WOpInst: Instruction with bit size only suffix (e.g., "8").
112 // LOpInst: Logical instruction with no bit size suffix.
113 // NoTestOpInst: Intrinsic that has no corresponding instruction.
114 class SOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
115 class IOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
116 class WOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
117 class LOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
118 class NoTestOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {}
120 // prototype: return (arg, arg, ...)
122 // t: best-fit integer (int/poly args)
123 // x: signed integer (int/float args)
124 // u: unsigned integer (int/float args)
125 // f: float (int args)
127 // g: default, ignore 'Q' size modifier.
128 // w: double width elements, same num elts
129 // n: double width elements, half num elts
130 // h: half width elements, double num elts
131 // e: half width elements, double num elts, unsigned
133 // l: constant uint64
134 // s: scalar of element type
135 // a: scalar of element type (splat to vector type)
136 // k: default elt width, double num elts
137 // #: array of default vectors
139 // c: const pointer type
154 ////////////////////////////////////////////////////////////////////////////////
156 def VADD : IOpInst<"vadd", "ddd",
157 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
158 def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>;
159 def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>;
160 def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
161 def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
162 def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
163 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">;
164 def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">;
166 ////////////////////////////////////////////////////////////////////////////////
167 // E.3.2 Multiplication
168 def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>;
169 def VMULP : SInst<"vmul", "ddd", "PcQPc">;
170 def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
171 def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>;
172 def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
173 def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>;
174 def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">;
175 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
176 def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">;
177 def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">;
178 def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">;
179 def VQDMULL : SInst<"vqdmull", "wdd", "si">;
181 ////////////////////////////////////////////////////////////////////////////////
183 def VSUB : IOpInst<"vsub", "ddd",
184 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
185 def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>;
186 def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>;
187 def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
188 def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
189 def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">;
190 def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">;
192 ////////////////////////////////////////////////////////////////////////////////
194 def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
195 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
196 let InstName = "vcge" in
197 def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
198 def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
199 let InstName = "vcgt" in
200 def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
201 let InstName = "vacge" in {
202 def VCAGE : IInst<"vcage", "udd", "fQf">;
203 def VCALE : IInst<"vcale", "udd", "fQf">;
205 let InstName = "vacgt" in {
206 def VCAGT : IInst<"vcagt", "udd", "fQf">;
207 def VCALT : IInst<"vcalt", "udd", "fQf">;
209 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">;
211 ////////////////////////////////////////////////////////////////////////////////
212 // E.3.5 Absolute Difference
213 def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
214 def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>;
215 def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>;
216 def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>;
218 ////////////////////////////////////////////////////////////////////////////////
220 def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
221 def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
223 ////////////////////////////////////////////////////////////////////////////////
224 // E.3.7 Pairwise Addition
225 def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">;
226 def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
227 def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
229 ////////////////////////////////////////////////////////////////////////////////
230 // E.3.8-9 Folding Max/Min
231 def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">;
232 def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">;
234 ////////////////////////////////////////////////////////////////////////////////
235 // E.3.10 Reciprocal/Sqrt
236 def VRECPS : IInst<"vrecps", "ddd", "fQf">;
237 def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">;
239 ////////////////////////////////////////////////////////////////////////////////
240 // E.3.11 Shifts by signed variable
241 def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
242 def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
243 def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
244 def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
246 ////////////////////////////////////////////////////////////////////////////////
247 // E.3.12 Shifts by constant
249 def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
250 def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
251 def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
252 def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
253 def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
254 def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
255 def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">;
256 def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">;
257 def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">;
258 def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">;
259 def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">;
260 def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">;
261 def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">;
262 def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">;
264 ////////////////////////////////////////////////////////////////////////////////
265 // E.3.13 Shifts with insert
266 def VSRI_N : WInst<"vsri_n", "dddi",
267 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
268 def VSLI_N : WInst<"vsli_n", "dddi",
269 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
272 ////////////////////////////////////////////////////////////////////////////////
273 // E.3.14 Loads and stores of a single vector
274 def VLD1 : WInst<"vld1", "dc",
275 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
276 def VLD1_LANE : WInst<"vld1_lane", "dcdi",
277 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
278 def VLD1_DUP : WInst<"vld1_dup", "dc",
279 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
280 def VST1 : WInst<"vst1", "vpd",
281 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
282 def VST1_LANE : WInst<"vst1_lane", "vpdi",
283 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
285 ////////////////////////////////////////////////////////////////////////////////
286 // E.3.15 Loads and stores of an N-element structure
287 def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
288 def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
289 def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
290 def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">;
291 def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">;
292 def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">;
293 def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
294 def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
295 def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
296 def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
297 def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
298 def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
299 def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
300 def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
301 def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
303 ////////////////////////////////////////////////////////////////////////////////
304 // E.3.16 Extract lanes from a vector
305 let InstName = "vmov" in
306 def VGET_LANE : IInst<"vget_lane", "sdi",
307 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
309 ////////////////////////////////////////////////////////////////////////////////
310 // E.3.17 Set lanes within a vector
311 let InstName = "vmov" in
312 def VSET_LANE : IInst<"vset_lane", "dsdi",
313 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
315 ////////////////////////////////////////////////////////////////////////////////
316 // E.3.18 Initialize a vector from bit pattern
317 def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST>;
319 ////////////////////////////////////////////////////////////////////////////////
320 // E.3.19 Set all lanes to same value
321 let InstName = "vmov" in {
322 def VDUP_N : WOpInst<"vdup_n", "ds",
323 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
324 def VMOV_N : WOpInst<"vmov_n", "ds",
325 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>;
328 def VDUP_LANE: WOpInst<"vdup_lane", "dgi",
329 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl",
332 ////////////////////////////////////////////////////////////////////////////////
333 // E.3.20 Combining vectors
334 def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>;
336 ////////////////////////////////////////////////////////////////////////////////
337 // E.3.21 Splitting vectors
338 let InstName = "vmov" in {
339 def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
340 def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
343 ////////////////////////////////////////////////////////////////////////////////
344 // E.3.22 Converting vectors
345 def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">;
346 def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">;
347 def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">;
348 def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">;
349 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">;
350 let isVCVT_N = 1 in {
351 def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">;
352 def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">;
353 def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">;
355 def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">;
356 def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">;
357 def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">;
358 def VQMOVUN : SInst<"vqmovun", "ek", "sil">;
360 ////////////////////////////////////////////////////////////////////////////////
361 // E.3.23-24 Table lookup, Extended table lookup
362 let InstName = "vtbl" in {
363 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">;
364 def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">;
365 def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">;
366 def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">;
368 let InstName = "vtbx" in {
369 def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">;
370 def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">;
371 def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">;
372 def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">;
375 ////////////////////////////////////////////////////////////////////////////////
376 // E.3.25 Operations with a scalar value
377 def VMLA_LANE : IOpInst<"vmla_lane", "dddgi",
378 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
379 def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>;
380 def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>;
381 def VMLS_LANE : IOpInst<"vmls_lane", "dddgi",
382 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
383 def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>;
384 def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>;
385 def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
386 def VMUL_LANE : IOpInst<"vmul_lane", "ddgi",
387 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
388 def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">;
389 def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>;
390 def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">;
391 def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>;
392 def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">;
393 def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>;
394 def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">;
395 def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>;
396 def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
397 def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>;
398 def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">;
399 def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
400 def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>;
401 def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">;
403 ////////////////////////////////////////////////////////////////////////////////
404 // E.3.26 Vector Extract
405 def VEXT : WInst<"vext", "dddi",
406 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">;
408 ////////////////////////////////////////////////////////////////////////////////
409 // E.3.27 Reverse vector elements
410 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
412 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
413 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
415 ////////////////////////////////////////////////////////////////////////////////
416 // E.3.28 Other single operand arithmetic
417 def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">;
418 def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">;
419 def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>;
420 def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">;
421 def VCLS : SInst<"vcls", "dd", "csiQcQsQi">;
422 def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
423 def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">;
424 def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">;
425 def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">;
427 ////////////////////////////////////////////////////////////////////////////////
428 // E.3.29 Logical operations
429 def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
430 def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
431 def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
432 def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
433 def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
434 def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
435 let isHiddenLInst = 1 in
436 def VBSL : SInst<"vbsl", "dudd",
437 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">;
439 ////////////////////////////////////////////////////////////////////////////////
440 // E.3.30 Transposition operations
441 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
442 def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
443 def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
445 ////////////////////////////////////////////////////////////////////////////////
446 // E.3.31 Vector reinterpret cast operations
448 : NoTestOpInst<"vreinterpret", "dd",
449 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT>;
451 ////////////////////////////////////////////////////////////////////////////////
452 // Vector fused multiply-add operations
454 def VFMA : SInst<"vfma", "dddd", "fQf">;