lib/libpmc/libpmc.c

   1 /*-
   2  * Copyright (c) 2003-2008 Joseph Koshy
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/types.h>
  31 #include <sys/module.h>
  32 #include <sys/pmc.h>
  33 #include <sys/syscall.h>
  34
  35 #include <ctype.h>
  36 #include <errno.h>
  37 #include <fcntl.h>
  38 #include <pmc.h>
  39 #include <stdio.h>
  40 #include <stdlib.h>
  41 #include <string.h>
  42 #include <strings.h>
  43 #include <unistd.h>
  44
  45 #include "libpmcinternal.h"
  46
  47 /* Function prototypes */
  48 #if defined(__i386__)
  49 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  50     struct pmc_op_pmcallocate *_pmc_config);
  51 #endif
  52 #if defined(__amd64__) || defined(__i386__)
  53 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  54     struct pmc_op_pmcallocate *_pmc_config);
  55 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  56     struct pmc_op_pmcallocate *_pmc_config);
  57 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  58     struct pmc_op_pmcallocate *_pmc_config);
  59 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  60     struct pmc_op_pmcallocate *_pmc_config);
  61 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  62     struct pmc_op_pmcallocate *_pmc_config);
  63 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  64     struct pmc_op_pmcallocate *_pmc_config);
  65 #endif
  66 #if defined(__i386__)
  67 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  68     struct pmc_op_pmcallocate *_pmc_config);
  69 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  70     struct pmc_op_pmcallocate *_pmc_config);
  71 #endif
  72 #if defined(__amd64__) || defined(__i386__)
  73 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  74     struct pmc_op_pmcallocate *_pmc_config);
  75 #endif
  76 #if defined(__XSCALE__)
  77 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  78     struct pmc_op_pmcallocate *_pmc_config);
  79 #endif
  80 #if defined(__mips__)
  81 static int mips24k_allocate_pmc(enum pmc_event _pe, char* ctrspec,
  82                              struct pmc_op_pmcallocate *_pmc_config);
  83 #endif /* __mips__ */
  84 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  85     struct pmc_op_pmcallocate *_pmc_config);
  86
  87 #if defined(__powerpc__)
  88 static int ppc7450_allocate_pmc(enum pmc_event _pe, char* ctrspec,
  89                              struct pmc_op_pmcallocate *_pmc_config);
  90 #endif /* __powerpc__ */
  91
  92 #define PMC_CALL(cmd, params)                           \
  93         syscall(pmc_syscall, PMC_OP_##cmd, (params))
  94
  95 /*
  96  * Event aliases provide a way for the user to ask for generic events
  97  * like "cache-misses", or "instructions-retired".  These aliases are
  98  * mapped to the appropriate canonical event descriptions using a
  99  * lookup table.
 100  */
 101 struct pmc_event_alias {
 102         const char      *pm_alias;
 103         const char      *pm_spec;
 104 };
 105
 106 static const struct pmc_event_alias *pmc_mdep_event_aliases;
 107
 108 /*
 109  * The pmc_event_descr structure maps symbolic names known to the user
 110  * to integer codes used by the PMC KLD.
 111  */
 112 struct pmc_event_descr {
 113         const char      *pm_ev_name;
 114         enum pmc_event  pm_ev_code;
 115 };
 116
 117 /*
 118  * The pmc_class_descr structure maps class name prefixes for
 119  * event names to event tables and other PMC class data.
 120  */
 121 struct pmc_class_descr {
 122         const char      *pm_evc_name;
 123         size_t          pm_evc_name_size;
 124         enum pmc_class  pm_evc_class;
 125         const struct pmc_event_descr *pm_evc_event_table;
 126         size_t          pm_evc_event_table_size;
 127         int             (*pm_evc_allocate_pmc)(enum pmc_event _pe,
 128                             char *_ctrspec, struct pmc_op_pmcallocate *_pa);
 129 };
 130
 131 #define PMC_TABLE_SIZE(N)       (sizeof(N)/sizeof(N[0]))
 132 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
 133
 134 #undef  __PMC_EV
 135 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
 136
 137 /*
 138  * PMC_CLASSDEP_TABLE(NAME, CLASS)
 139  *
 140  * Define a table mapping event names and aliases to HWPMC event IDs.
 141  */
 142 #define PMC_CLASSDEP_TABLE(N, C)                                \
 143         static const struct pmc_event_descr N##_event_table[] = \
 144         {                                                       \
 145                 __PMC_EV_##C()                                  \
 146         }
 147
 148 PMC_CLASSDEP_TABLE(iaf, IAF);
 149 PMC_CLASSDEP_TABLE(k7, K7);
 150 PMC_CLASSDEP_TABLE(k8, K8);
 151 PMC_CLASSDEP_TABLE(p4, P4);
 152 PMC_CLASSDEP_TABLE(p5, P5);
 153 PMC_CLASSDEP_TABLE(p6, P6);
 154 PMC_CLASSDEP_TABLE(xscale, XSCALE);
 155 PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
 156 PMC_CLASSDEP_TABLE(ucf, UCF);
 157 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
 158
 159 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
 160
 161 #undef  __PMC_EV_ALIAS
 162 #define __PMC_EV_ALIAS(N,CODE)  { N, PMC_EV_##CODE },
 163
 164 static const struct pmc_event_descr atom_event_table[] =
 165 {
 166         __PMC_EV_ALIAS_ATOM()
 167 };
 168
 169 static const struct pmc_event_descr core_event_table[] =
 170 {
 171         __PMC_EV_ALIAS_CORE()
 172 };
 173
 174
 175 static const struct pmc_event_descr core2_event_table[] =
 176 {
 177         __PMC_EV_ALIAS_CORE2()
 178 };
 179
 180 static const struct pmc_event_descr corei7_event_table[] =
 181 {
 182         __PMC_EV_ALIAS_COREI7()
 183 };
 184
 185 static const struct pmc_event_descr haswell_event_table[] =
 186 {
 187         __PMC_EV_ALIAS_HASWELL()
 188 };
 189
 190 static const struct pmc_event_descr ivybridge_event_table[] =
 191 {
 192         __PMC_EV_ALIAS_IVYBRIDGE()
 193 };
 194
 195 static const struct pmc_event_descr ivybridge_xeon_event_table[] =
 196 {
 197         __PMC_EV_ALIAS_IVYBRIDGE_XEON()
 198 };
 199
 200 static const struct pmc_event_descr sandybridge_event_table[] =
 201 {
 202         __PMC_EV_ALIAS_SANDYBRIDGE()
 203 };
 204
 205 static const struct pmc_event_descr sandybridge_xeon_event_table[] =
 206 {
 207         __PMC_EV_ALIAS_SANDYBRIDGE_XEON()
 208 };
 209
 210 static const struct pmc_event_descr westmere_event_table[] =
 211 {
 212         __PMC_EV_ALIAS_WESTMERE()
 213 };
 214
 215 static const struct pmc_event_descr corei7uc_event_table[] =
 216 {
 217         __PMC_EV_ALIAS_COREI7UC()
 218 };
 219
 220 static const struct pmc_event_descr haswelluc_event_table[] =
 221 {
 222         __PMC_EV_ALIAS_HASWELLUC()
 223 };
 224
 225 static const struct pmc_event_descr sandybridgeuc_event_table[] =
 226 {
 227         __PMC_EV_ALIAS_SANDYBRIDGEUC()
 228 };
 229
 230 static const struct pmc_event_descr westmereuc_event_table[] =
 231 {
 232         __PMC_EV_ALIAS_WESTMEREUC()
 233 };
 234
 235 /*
 236  * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
 237  *
 238  * Map a CPU to the PMC classes it supports.
 239  */
 240 #define PMC_MDEP_TABLE(N,C,...)                         \
 241         static const enum pmc_class N##_pmc_classes[] = {       \
 242                 PMC_CLASS_##C, __VA_ARGS__                      \
 243         }
 244
 245 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 246 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 247 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 248 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 249 PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 250 PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 251 PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 252 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 253 PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 254 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 255 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 256 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 257 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 258 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 259 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 260 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
 261 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K);
 262 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450);
 263 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT);
 264
 265 static const struct pmc_event_descr tsc_event_table[] =
 266 {
 267         __PMC_EV_TSC()
 268 };
 269
 270 #undef  PMC_CLASS_TABLE_DESC
 271 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR)    \
 272 static const struct pmc_class_descr NAME##_class_table_descr =  \
 273         {                                                       \
 274                 .pm_evc_name  = #CLASS "-",                     \
 275                 .pm_evc_name_size = sizeof(#CLASS "-") - 1,     \
 276                 .pm_evc_class = PMC_CLASS_##CLASS ,             \
 277                 .pm_evc_event_table = EVENTS##_event_table ,    \
 278                 .pm_evc_event_table_size =                      \
 279                         PMC_EVENT_TABLE_SIZE(EVENTS),           \
 280                 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
 281         }
 282
 283 #if     defined(__i386__) || defined(__amd64__)
 284 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
 285 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
 286 PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
 287 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
 288 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
 289 PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
 290 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
 291 PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
 292 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
 293 PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
 294 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
 295 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
 296 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
 297 PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp);
 298 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
 299 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
 300 #endif
 301 #if     defined(__i386__)
 302 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
 303 #endif
 304 #if     defined(__i386__) || defined(__amd64__)
 305 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
 306 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
 307 #endif
 308 #if     defined(__i386__)
 309 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
 310 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
 311 #endif
 312 #if     defined(__i386__) || defined(__amd64__)
 313 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
 314 #endif
 315 #if     defined(__XSCALE__)
 316 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale);
 317 #endif
 318 #if defined(__mips__)
 319 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips24k);
 320 #endif /* __mips__ */
 321 #if defined(__powerpc__)
 322 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, ppc7450);
 323 #endif
 324
 325 static struct pmc_class_descr soft_class_table_descr =
 326 {
 327         .pm_evc_name  = "SOFT-",
 328         .pm_evc_name_size = sizeof("SOFT-") - 1,
 329         .pm_evc_class = PMC_CLASS_SOFT,
 330         .pm_evc_event_table = NULL,
 331         .pm_evc_event_table_size = 0,
 332         .pm_evc_allocate_pmc = soft_allocate_pmc
 333 };
 334
 335 #undef  PMC_CLASS_TABLE_DESC
 336
 337 static const struct pmc_class_descr **pmc_class_table;
 338 #define PMC_CLASS_TABLE_SIZE    cpu_info.pm_nclass
 339
 340 static const enum pmc_class *pmc_mdep_class_list;
 341 static size_t pmc_mdep_class_list_size;
 342
 343 /*
 344  * Mapping tables, mapping enumeration values to human readable
 345  * strings.
 346  */
 347
 348 static const char * pmc_capability_names[] = {
 349 #undef  __PMC_CAP
 350 #define __PMC_CAP(N,V,D)        #N ,
 351         __PMC_CAPS()
 352 };
 353
 354 static const char * pmc_class_names[] = {
 355 #undef  __PMC_CLASS
 356 #define __PMC_CLASS(C)  #C ,
 357         __PMC_CLASSES()
 358 };
 359
 360 struct pmc_cputype_map {
 361         enum pmc_cputype pm_cputype;
 362         const char      *pm_name;
 363 };
 364
 365 static const struct pmc_cputype_map pmc_cputype_names[] = {
 366 #undef  __PMC_CPU
 367 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
 368         __PMC_CPUS()
 369 };
 370
 371 static const char * pmc_disposition_names[] = {
 372 #undef  __PMC_DISP
 373 #define __PMC_DISP(D)   #D ,
 374         __PMC_DISPOSITIONS()
 375 };
 376
 377 static const char * pmc_mode_names[] = {
 378 #undef  __PMC_MODE
 379 #define __PMC_MODE(M,N) #M ,
 380         __PMC_MODES()
 381 };
 382
 383 static const char * pmc_state_names[] = {
 384 #undef  __PMC_STATE
 385 #define __PMC_STATE(S) #S ,
 386         __PMC_STATES()
 387 };
 388
 389 /*
 390  * Filled in by pmc_init().
 391  */
 392 static int pmc_syscall = -1;
 393 static struct pmc_cpuinfo cpu_info;
 394 static struct pmc_op_getdyneventinfo soft_event_info;
 395
 396 /* Event masks for events */
 397 struct pmc_masks {
 398         const char      *pm_name;
 399         const uint64_t  pm_value;
 400 };
 401 #define PMCMASK(N,V)    { .pm_name = #N, .pm_value = (V) }
 402 #define NULLMASK        { .pm_name = NULL }
 403
 404 #if defined(__amd64__) || defined(__i386__)
 405 static int
 406 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
 407 {
 408         const struct pmc_masks *pm;
 409         char *q, *r;
 410         int c;
 411
 412         if (pmask == NULL)      /* no mask keywords */
 413                 return (-1);
 414         q = strchr(p, '=');     /* skip '=' */
 415         if (*++q == '\0')       /* no more data */
 416                 return (-1);
 417         c = 0;                  /* count of mask keywords seen */
 418         while ((r = strsep(&q, "+")) != NULL) {
 419                 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
 420                     pm++)
 421                         ;
 422                 if (pm->pm_name == NULL) /* not found */
 423                         return (-1);
 424                 *evmask |= pm->pm_value;
 425                 c++;
 426         }
 427         return (c);
 428 }
 429 #endif
 430
 431 #define KWMATCH(p,kw)           (strcasecmp((p), (kw)) == 0)
 432 #define KWPREFIXMATCH(p,kw)     (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
 433 #define EV_ALIAS(N,S)           { .pm_alias = N, .pm_spec = S }
 434
 435 #if defined(__i386__)
 436
 437 /*
 438  * AMD K7 (Athlon) CPUs.
 439  */
 440
 441 static struct pmc_event_alias k7_aliases[] = {
 442         EV_ALIAS("branches",            "k7-retired-branches"),
 443         EV_ALIAS("branch-mispredicts",  "k7-retired-branches-mispredicted"),
 444         EV_ALIAS("cycles",              "tsc"),
 445         EV_ALIAS("dc-misses",           "k7-dc-misses"),
 446         EV_ALIAS("ic-misses",           "k7-ic-misses"),
 447         EV_ALIAS("instructions",        "k7-retired-instructions"),
 448         EV_ALIAS("interrupts",          "k7-hardware-interrupts"),
 449         EV_ALIAS(NULL, NULL)
 450 };
 451
 452 #define K7_KW_COUNT     "count"
 453 #define K7_KW_EDGE      "edge"
 454 #define K7_KW_INV       "inv"
 455 #define K7_KW_OS        "os"
 456 #define K7_KW_UNITMASK  "unitmask"
 457 #define K7_KW_USR       "usr"
 458
 459 static int
 460 k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
 461     struct pmc_op_pmcallocate *pmc_config)
 462 {
 463         char            *e, *p, *q;
 464         int             c, has_unitmask;
 465         uint32_t        count, unitmask;
 466
 467         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
 468         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 469
 470         if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
 471             pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
 472             pe == PMC_EV_K7_DC_WRITEBACKS) {
 473                 has_unitmask = 1;
 474                 unitmask = AMD_PMC_UNITMASK_MOESI;
 475         } else
 476                 unitmask = has_unitmask = 0;
 477
 478         while ((p = strsep(&ctrspec, ",")) != NULL) {
 479                 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
 480                         q = strchr(p, '=');
 481                         if (*++q == '\0') /* skip '=' */
 482                                 return (-1);
 483
 484                         count = strtol(q, &e, 0);
 485                         if (e == q || *e != '\0')
 486                                 return (-1);
 487
 488                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 489                         pmc_config->pm_md.pm_amd.pm_amd_config |=
 490                             AMD_PMC_TO_COUNTER(count);
 491
 492                 } else if (KWMATCH(p, K7_KW_EDGE)) {
 493                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 494                 } else if (KWMATCH(p, K7_KW_INV)) {
 495                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 496                 } else if (KWMATCH(p, K7_KW_OS)) {
 497                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 498                 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
 499                         if (has_unitmask == 0)
 500                                 return (-1);
 501                         unitmask = 0;
 502                         q = strchr(p, '=');
 503                         if (*++q == '\0') /* skip '=' */
 504                                 return (-1);
 505
 506                         while ((c = tolower(*q++)) != 0)
 507                                 if (c == 'm')
 508                                         unitmask |= AMD_PMC_UNITMASK_M;
 509                                 else if (c == 'o')
 510                                         unitmask |= AMD_PMC_UNITMASK_O;
 511                                 else if (c == 'e')
 512                                         unitmask |= AMD_PMC_UNITMASK_E;
 513                                 else if (c == 's')
 514                                         unitmask |= AMD_PMC_UNITMASK_S;
 515                                 else if (c == 'i')
 516                                         unitmask |= AMD_PMC_UNITMASK_I;
 517                                 else if (c == '+')
 518                                         continue;
 519                                 else
 520                                         return (-1);
 521
 522                         if (unitmask == 0)
 523                                 return (-1);
 524
 525                 } else if (KWMATCH(p, K7_KW_USR)) {
 526                         pmc_config->pm_caps |= PMC_CAP_USER;
 527                 } else
 528                         return (-1);
 529         }
 530
 531         if (has_unitmask) {
 532                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
 533                 pmc_config->pm_md.pm_amd.pm_amd_config |=
 534                     AMD_PMC_TO_UNITMASK(unitmask);
 535         }
 536
 537         return (0);
 538
 539 }
 540
 541 #endif
 542
 543 #if defined(__amd64__) || defined(__i386__)
 544
 545 /*
 546  * Intel Core (Family 6, Model E) PMCs.
 547  */
 548
 549 static struct pmc_event_alias core_aliases[] = {
 550         EV_ALIAS("branches",            "iap-br-instr-ret"),
 551         EV_ALIAS("branch-mispredicts",  "iap-br-mispred-ret"),
 552         EV_ALIAS("cycles",              "tsc-tsc"),
 553         EV_ALIAS("ic-misses",           "iap-icache-misses"),
 554         EV_ALIAS("instructions",        "iap-instr-ret"),
 555         EV_ALIAS("interrupts",          "iap-core-hw-int-rx"),
 556         EV_ALIAS("unhalted-cycles",     "iap-unhalted-core-cycles"),
 557         EV_ALIAS(NULL, NULL)
 558 };
 559
 560 /*
 561  * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
 562  * and Atom (Family 6, model 1CH) PMCs.
 563  *
 564  * We map aliases to events on the fixed-function counters if these
 565  * are present.  Note that not all CPUs in this family contain fixed-function
 566  * counters.
 567  */
 568
 569 static struct pmc_event_alias core2_aliases[] = {
 570         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 571         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 572         EV_ALIAS("cycles",              "tsc-tsc"),
 573         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 574         EV_ALIAS("instructions",        "iaf-instr-retired.any"),
 575         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 576         EV_ALIAS("unhalted-cycles",     "iaf-cpu-clk-unhalted.core"),
 577         EV_ALIAS(NULL, NULL)
 578 };
 579
 580 static struct pmc_event_alias core2_aliases_without_iaf[] = {
 581         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 582         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 583         EV_ALIAS("cycles",              "tsc-tsc"),
 584         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 585         EV_ALIAS("instructions",        "iap-inst-retired.any_p"),
 586         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 587         EV_ALIAS("unhalted-cycles",     "iap-cpu-clk-unhalted.core_p"),
 588         EV_ALIAS(NULL, NULL)
 589 };
 590
 591 #define atom_aliases                    core2_aliases
 592 #define atom_aliases_without_iaf        core2_aliases_without_iaf
 593 #define corei7_aliases                  core2_aliases
 594 #define corei7_aliases_without_iaf      core2_aliases_without_iaf
 595 #define haswell_aliases                 core2_aliases
 596 #define haswell_aliases_without_iaf     core2_aliases_without_iaf
 597 #define ivybridge_aliases               core2_aliases
 598 #define ivybridge_aliases_without_iaf   core2_aliases_without_iaf
 599 #define ivybridge_xeon_aliases          core2_aliases
 600 #define ivybridge_xeon_aliases_without_iaf      core2_aliases_without_iaf
 601 #define sandybridge_aliases             core2_aliases
 602 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf
 603 #define sandybridge_xeon_aliases        core2_aliases
 604 #define sandybridge_xeon_aliases_without_iaf    core2_aliases_without_iaf
 605 #define westmere_aliases                core2_aliases
 606 #define westmere_aliases_without_iaf    core2_aliases_without_iaf
 607
 608 #define IAF_KW_OS               "os"
 609 #define IAF_KW_USR              "usr"
 610 #define IAF_KW_ANYTHREAD        "anythread"
 611
 612 /*
 613  * Parse an event specifier for Intel fixed function counters.
 614  */
 615 static int
 616 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 617     struct pmc_op_pmcallocate *pmc_config)
 618 {
 619         char *p;
 620
 621         (void) pe;
 622
 623         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 624         pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0;
 625
 626         while ((p = strsep(&ctrspec, ",")) != NULL) {
 627                 if (KWMATCH(p, IAF_KW_OS))
 628                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 629                 else if (KWMATCH(p, IAF_KW_USR))
 630                         pmc_config->pm_caps |= PMC_CAP_USER;
 631                 else if (KWMATCH(p, IAF_KW_ANYTHREAD))
 632                         pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY;
 633                 else
 634                         return (-1);
 635         }
 636
 637         return (0);
 638 }
 639
 640 /*
 641  * Core/Core2 support.
 642  */
 643
 644 #define IAP_KW_AGENT            "agent"
 645 #define IAP_KW_ANYTHREAD        "anythread"
 646 #define IAP_KW_CACHESTATE       "cachestate"
 647 #define IAP_KW_CMASK            "cmask"
 648 #define IAP_KW_CORE             "core"
 649 #define IAP_KW_EDGE             "edge"
 650 #define IAP_KW_INV              "inv"
 651 #define IAP_KW_OS               "os"
 652 #define IAP_KW_PREFETCH         "prefetch"
 653 #define IAP_KW_SNOOPRESPONSE    "snoopresponse"
 654 #define IAP_KW_SNOOPTYPE        "snooptype"
 655 #define IAP_KW_TRANSITION       "trans"
 656 #define IAP_KW_USR              "usr"
 657 #define IAP_KW_RSP              "rsp"
 658
 659 static struct pmc_masks iap_core_mask[] = {
 660         PMCMASK(all,    (0x3 << 14)),
 661         PMCMASK(this,   (0x1 << 14)),
 662         NULLMASK
 663 };
 664
 665 static struct pmc_masks iap_agent_mask[] = {
 666         PMCMASK(this,   0),
 667         PMCMASK(any,    (0x1 << 13)),
 668         NULLMASK
 669 };
 670
 671 static struct pmc_masks iap_prefetch_mask[] = {
 672         PMCMASK(both,           (0x3 << 12)),
 673         PMCMASK(only,           (0x1 << 12)),
 674         PMCMASK(exclude,        0),
 675         NULLMASK
 676 };
 677
 678 static struct pmc_masks iap_cachestate_mask[] = {
 679         PMCMASK(i,              (1 <<  8)),
 680         PMCMASK(s,              (1 <<  9)),
 681         PMCMASK(e,              (1 << 10)),
 682         PMCMASK(m,              (1 << 11)),
 683         NULLMASK
 684 };
 685
 686 static struct pmc_masks iap_snoopresponse_mask[] = {
 687         PMCMASK(clean,          (1 << 8)),
 688         PMCMASK(hit,            (1 << 9)),
 689         PMCMASK(hitm,           (1 << 11)),
 690         NULLMASK
 691 };
 692
 693 static struct pmc_masks iap_snooptype_mask[] = {
 694         PMCMASK(cmp2s,          (1 << 8)),
 695         PMCMASK(cmp2i,          (1 << 9)),
 696         NULLMASK
 697 };
 698
 699 static struct pmc_masks iap_transition_mask[] = {
 700         PMCMASK(any,            0x00),
 701         PMCMASK(frequency,      0x10),
 702         NULLMASK
 703 };
 704
 705 static struct pmc_masks iap_rsp_mask_i7_wm[] = {
 706         PMCMASK(DMND_DATA_RD,           (1 <<  0)),
 707         PMCMASK(DMND_RFO,               (1 <<  1)),
 708         PMCMASK(DMND_IFETCH,            (1 <<  2)),
 709         PMCMASK(WB,                     (1 <<  3)),
 710         PMCMASK(PF_DATA_RD,             (1 <<  4)),
 711         PMCMASK(PF_RFO,                 (1 <<  5)),
 712         PMCMASK(PF_IFETCH,              (1 <<  6)),
 713         PMCMASK(OTHER,                  (1 <<  7)),
 714         PMCMASK(UNCORE_HIT,             (1 <<  8)),
 715         PMCMASK(OTHER_CORE_HIT_SNP,     (1 <<  9)),
 716         PMCMASK(OTHER_CORE_HITM,        (1 << 10)),
 717         PMCMASK(REMOTE_CACHE_FWD,       (1 << 12)),
 718         PMCMASK(REMOTE_DRAM,            (1 << 13)),
 719         PMCMASK(LOCAL_DRAM,             (1 << 14)),
 720         PMCMASK(NON_DRAM,               (1 << 15)),
 721         NULLMASK
 722 };
 723
 724 static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = {
 725         PMCMASK(REQ_DMND_DATA_RD,       (1ULL <<  0)),
 726         PMCMASK(REQ_DMND_RFO,           (1ULL <<  1)),
 727         PMCMASK(REQ_DMND_IFETCH,        (1ULL <<  2)),
 728         PMCMASK(REQ_WB,                 (1ULL <<  3)),
 729         PMCMASK(REQ_PF_DATA_RD,         (1ULL <<  4)),
 730         PMCMASK(REQ_PF_RFO,             (1ULL <<  5)),
 731         PMCMASK(REQ_PF_IFETCH,          (1ULL <<  6)),
 732         PMCMASK(REQ_PF_LLC_DATA_RD,     (1ULL <<  7)),
 733         PMCMASK(REQ_PF_LLC_RFO,         (1ULL <<  8)),
 734         PMCMASK(REQ_PF_LLC_IFETCH,      (1ULL <<  9)),
 735         PMCMASK(REQ_BUS_LOCKS,          (1ULL << 10)),
 736         PMCMASK(REQ_STRM_ST,            (1ULL << 11)),
 737         PMCMASK(REQ_OTHER,              (1ULL << 15)),
 738         PMCMASK(RES_ANY,                (1ULL << 16)),
 739         PMCMASK(RES_SUPPLIER_SUPP,      (1ULL << 17)),
 740         PMCMASK(RES_SUPPLIER_LLC_HITM,  (1ULL << 18)),
 741         PMCMASK(RES_SUPPLIER_LLC_HITE,  (1ULL << 19)),
 742         PMCMASK(RES_SUPPLIER_LLC_HITS,  (1ULL << 20)),
 743         PMCMASK(RES_SUPPLIER_LLC_HITF,  (1ULL << 21)),
 744         PMCMASK(RES_SUPPLIER_LOCAL,     (1ULL << 22)),
 745         PMCMASK(RES_SNOOP_SNP_NONE,     (1ULL << 31)),
 746         PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
 747         PMCMASK(RES_SNOOP_SNP_MISS,     (1ULL << 33)),
 748         PMCMASK(RES_SNOOP_HIT_NO_FWD,   (1ULL << 34)),
 749         PMCMASK(RES_SNOOP_HIT_FWD,      (1ULL << 35)),
 750         PMCMASK(RES_SNOOP_HITM,         (1ULL << 36)),
 751         PMCMASK(RES_NON_DRAM,           (1ULL << 37)),
 752         NULLMASK
 753 };
 754
 755 static struct pmc_masks iap_rsp_mask_haswell[] = {
 756         PMCMASK(REQ_DMND_DATA_RD,       (1ULL <<  0)),
 757         PMCMASK(REQ_DMND_RFO,           (1ULL <<  1)),
 758         PMCMASK(REQ_DMND_IFETCH,        (1ULL <<  2)),
 759         PMCMASK(REQ_PF_DATA_RD,         (1ULL <<  4)),
 760         PMCMASK(REQ_PF_RFO,             (1ULL <<  5)),
 761         PMCMASK(REQ_PF_IFETCH,          (1ULL <<  6)),
 762         PMCMASK(REQ_OTHER,              (1ULL << 15)),
 763         PMCMASK(RES_ANY,                (1ULL << 16)),
 764         PMCMASK(RES_SUPPLIER_SUPP,      (1ULL << 17)),
 765         PMCMASK(RES_SUPPLIER_LLC_HITM,  (1ULL << 18)),
 766         PMCMASK(RES_SUPPLIER_LLC_HITE,  (1ULL << 19)),
 767         PMCMASK(RES_SUPPLIER_LLC_HITS,  (1ULL << 20)),
 768         PMCMASK(RES_SUPPLIER_LLC_HITF,  (1ULL << 21)),
 769         PMCMASK(RES_SUPPLIER_LOCAL,     (1ULL << 22)),
 770         PMCMASK(RES_SNOOP_SNP_NONE,     (1ULL << 31)),
 771         PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
 772         PMCMASK(RES_SNOOP_SNP_MISS,     (1ULL << 33)),
 773         PMCMASK(RES_SNOOP_HIT_NO_FWD,   (1ULL << 34)),
 774         PMCMASK(RES_SNOOP_HIT_FWD,      (1ULL << 35)),
 775         PMCMASK(RES_SNOOP_HITM,         (1ULL << 36)),
 776         PMCMASK(RES_NON_DRAM,           (1ULL << 37)),
 777         NULLMASK
 778 };
 779
 780 static int
 781 iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
 782     struct pmc_op_pmcallocate *pmc_config)
 783 {
 784         char *e, *p, *q;
 785         uint64_t cachestate, evmask, rsp;
 786         int count, n;
 787
 788         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 789             PMC_CAP_QUALIFIER);
 790         pmc_config->pm_md.pm_iap.pm_iap_config = 0;
 791
 792         cachestate = evmask = rsp = 0;
 793
 794         /* Parse additional modifiers if present */
 795         while ((p = strsep(&ctrspec, ",")) != NULL) {
 796
 797                 n = 0;
 798                 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
 799                         q = strchr(p, '=');
 800                         if (*++q == '\0') /* skip '=' */
 801                                 return (-1);
 802                         count = strtol(q, &e, 0);
 803                         if (e == q || *e != '\0')
 804                                 return (-1);
 805                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 806                         pmc_config->pm_md.pm_iap.pm_iap_config |=
 807                             IAP_CMASK(count);
 808                 } else if (KWMATCH(p, IAP_KW_EDGE)) {
 809                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 810                 } else if (KWMATCH(p, IAP_KW_INV)) {
 811                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 812                 } else if (KWMATCH(p, IAP_KW_OS)) {
 813                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 814                 } else if (KWMATCH(p, IAP_KW_USR)) {
 815                         pmc_config->pm_caps |= PMC_CAP_USER;
 816                 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) {
 817                         pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY;
 818                 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) {
 819                         n = pmc_parse_mask(iap_core_mask, p, &evmask);
 820                         if (n != 1)
 821                                 return (-1);
 822                 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) {
 823                         n = pmc_parse_mask(iap_agent_mask, p, &evmask);
 824                         if (n != 1)
 825                                 return (-1);
 826                 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) {
 827                         n = pmc_parse_mask(iap_prefetch_mask, p, &evmask);
 828                         if (n != 1)
 829                                 return (-1);
 830                 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) {
 831                         n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
 832                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
 833                     KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
 834                         n = pmc_parse_mask(iap_transition_mask, p, &evmask);
 835                         if (n != 1)
 836                                 return (-1);
 837                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
 838                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
 839                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
 840                         if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
 841                                 n = pmc_parse_mask(iap_snoopresponse_mask, p,
 842                                     &evmask);
 843                         } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
 844                                 n = pmc_parse_mask(iap_snooptype_mask, p,
 845                                     &evmask);
 846                         } else
 847                                 return (-1);
 848                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
 849                     cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
 850                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 851                                 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp);
 852                         } else
 853                                 return (-1);
 854                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
 855                     cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
 856                         cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
 857                         cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) {
 858                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 859                                 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp);
 860                         } else
 861                                 return (-1);
 862                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL) {
 863                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 864                                 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
 865                         } else
 866                                 return (-1);
 867                 } else
 868                         return (-1);
 869
 870                 if (n < 0)      /* Parsing failed. */
 871                         return (-1);
 872         }
 873
 874         pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;
 875
 876         /*
 877          * If the event requires a 'cachestate' qualifier but was not
 878          * specified by the user, use a sensible default.
 879          */
 880         switch (pe) {
 881         case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
 882         case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
 883         case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
 884         case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
 885         case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
 886         case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
 887         case PMC_EV_IAP_EVENT_32H: /* Core */
 888         case PMC_EV_IAP_EVENT_40H: /* Core */
 889         case PMC_EV_IAP_EVENT_41H: /* Core */
 890         case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
 891                 if (cachestate == 0)
 892                         cachestate = (0xF << 8);
 893                 break;
 894         case PMC_EV_IAP_EVENT_77H: /* Atom */
 895                 /* IAP_EVENT_77H only accepts a cachestate qualifier on the
 896                  * Atom processor
 897                  */
 898                 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0)
 899                         cachestate = (0xF << 8);
 900             break;
 901         default:
 902                 break;
 903         }
 904
 905         pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
 906         pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
 907
 908         return (0);
 909 }
 910
 911 /*
 912  * Intel Uncore.
 913  */
 914
 915 static int
 916 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 917     struct pmc_op_pmcallocate *pmc_config)
 918 {
 919         (void) pe;
 920         (void) ctrspec;
 921
 922         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 923         pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
 924
 925         return (0);
 926 }
 927
 928 #define UCP_KW_CMASK            "cmask"
 929 #define UCP_KW_EDGE             "edge"
 930 #define UCP_KW_INV              "inv"
 931
 932 static int
 933 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
 934     struct pmc_op_pmcallocate *pmc_config)
 935 {
 936         char *e, *p, *q;
 937         int count, n;
 938
 939         (void) pe;
 940
 941         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 942             PMC_CAP_QUALIFIER);
 943         pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
 944
 945         /* Parse additional modifiers if present */
 946         while ((p = strsep(&ctrspec, ",")) != NULL) {
 947
 948                 n = 0;
 949                 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
 950                         q = strchr(p, '=');
 951                         if (*++q == '\0') /* skip '=' */
 952                                 return (-1);
 953                         count = strtol(q, &e, 0);
 954                         if (e == q || *e != '\0')
 955                                 return (-1);
 956                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 957                         pmc_config->pm_md.pm_ucp.pm_ucp_config |=
 958                             UCP_CMASK(count);
 959                 } else if (KWMATCH(p, UCP_KW_EDGE)) {
 960                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 961                 } else if (KWMATCH(p, UCP_KW_INV)) {
 962                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 963                 } else
 964                         return (-1);
 965
 966                 if (n < 0)      /* Parsing failed. */
 967                         return (-1);
 968         }
 969
 970         return (0);
 971 }
 972
 973 /*
 974  * AMD K8 PMCs.
 975  *
 976  * These are very similar to AMD K7 PMCs, but support more kinds of
 977  * events.
 978  */
 979
 980 static struct pmc_event_alias k8_aliases[] = {
 981         EV_ALIAS("branches",            "k8-fr-retired-taken-branches"),
 982         EV_ALIAS("branch-mispredicts",
 983             "k8-fr-retired-taken-branches-mispredicted"),
 984         EV_ALIAS("cycles",              "tsc"),
 985         EV_ALIAS("dc-misses",           "k8-dc-miss"),
 986         EV_ALIAS("ic-misses",           "k8-ic-miss"),
 987         EV_ALIAS("instructions",        "k8-fr-retired-x86-instructions"),
 988         EV_ALIAS("interrupts",          "k8-fr-taken-hardware-interrupts"),
 989         EV_ALIAS("unhalted-cycles",     "k8-bu-cpu-clk-unhalted"),
 990         EV_ALIAS(NULL, NULL)
 991 };
 992
 993 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
 994
 995 /*
 996  * Parsing tables
 997  */
 998
 999 /* fp dispatched fpu ops */
1000 static const struct pmc_masks k8_mask_fdfo[] = {
1001         __K8MASK(add-pipe-excluding-junk-ops,   0),
1002         __K8MASK(multiply-pipe-excluding-junk-ops,      1),
1003         __K8MASK(store-pipe-excluding-junk-ops, 2),
1004         __K8MASK(add-pipe-junk-ops,             3),
1005         __K8MASK(multiply-pipe-junk-ops,        4),
1006         __K8MASK(store-pipe-junk-ops,           5),
1007         NULLMASK
1008 };
1009
1010 /* ls segment register loads */
1011 static const struct pmc_masks k8_mask_lsrl[] = {
1012         __K8MASK(es,    0),
1013         __K8MASK(cs,    1),
1014         __K8MASK(ss,    2),
1015         __K8MASK(ds,    3),
1016         __K8MASK(fs,    4),
1017         __K8MASK(gs,    5),
1018         __K8MASK(hs,    6),
1019         NULLMASK
1020 };
1021
1022 /* ls locked operation */
1023 static const struct pmc_masks k8_mask_llo[] = {
1024         __K8MASK(locked-instructions,   0),
1025         __K8MASK(cycles-in-request,     1),
1026         __K8MASK(cycles-to-complete,    2),
1027         NULLMASK
1028 };
1029
1030 /* dc refill from {l2,system} and dc copyback */
1031 static const struct pmc_masks k8_mask_dc[] = {
1032         __K8MASK(invalid,       0),
1033         __K8MASK(shared,        1),
1034         __K8MASK(exclusive,     2),
1035         __K8MASK(owner,         3),
1036         __K8MASK(modified,      4),
1037         NULLMASK
1038 };
1039
1040 /* dc one bit ecc error */
1041 static const struct pmc_masks k8_mask_dobee[] = {
1042         __K8MASK(scrubber,      0),
1043         __K8MASK(piggyback,     1),
1044         NULLMASK
1045 };
1046
1047 /* dc dispatched prefetch instructions */
1048 static const struct pmc_masks k8_mask_ddpi[] = {
1049         __K8MASK(load,  0),
1050         __K8MASK(store, 1),
1051         __K8MASK(nta,   2),
1052         NULLMASK
1053 };
1054
1055 /* dc dcache accesses by locks */
1056 static const struct pmc_masks k8_mask_dabl[] = {
1057         __K8MASK(accesses,      0),
1058         __K8MASK(misses,        1),
1059         NULLMASK
1060 };
1061
1062 /* bu internal l2 request */
1063 static const struct pmc_masks k8_mask_bilr[] = {
1064         __K8MASK(ic-fill,       0),
1065         __K8MASK(dc-fill,       1),
1066         __K8MASK(tlb-reload,    2),
1067         __K8MASK(tag-snoop,     3),
1068         __K8MASK(cancelled,     4),
1069         NULLMASK
1070 };
1071
1072 /* bu fill request l2 miss */
1073 static const struct pmc_masks k8_mask_bfrlm[] = {
1074         __K8MASK(ic-fill,       0),
1075         __K8MASK(dc-fill,       1),
1076         __K8MASK(tlb-reload,    2),
1077         NULLMASK
1078 };
1079
1080 /* bu fill into l2 */
1081 static const struct pmc_masks k8_mask_bfil[] = {
1082         __K8MASK(dirty-l2-victim,       0),
1083         __K8MASK(victim-from-l2,        1),
1084         NULLMASK
1085 };
1086
1087 /* fr retired fpu instructions */
1088 static const struct pmc_masks k8_mask_frfi[] = {
1089         __K8MASK(x87,                   0),
1090         __K8MASK(mmx-3dnow,             1),
1091         __K8MASK(packed-sse-sse2,       2),
1092         __K8MASK(scalar-sse-sse2,       3),
1093         NULLMASK
1094 };
1095
1096 /* fr retired fastpath double op instructions */
1097 static const struct pmc_masks k8_mask_frfdoi[] = {
1098         __K8MASK(low-op-pos-0,          0),
1099         __K8MASK(low-op-pos-1,          1),
1100         __K8MASK(low-op-pos-2,          2),
1101         NULLMASK
1102 };
1103
1104 /* fr fpu exceptions */
1105 static const struct pmc_masks k8_mask_ffe[] = {
1106         __K8MASK(x87-reclass-microfaults,       0),
1107         __K8MASK(sse-retype-microfaults,        1),
1108         __K8MASK(sse-reclass-microfaults,       2),
1109         __K8MASK(sse-and-x87-microtraps,        3),
1110         NULLMASK
1111 };
1112
1113 /* nb memory controller page access event */
1114 static const struct pmc_masks k8_mask_nmcpae[] = {
1115         __K8MASK(page-hit,      0),
1116         __K8MASK(page-miss,     1),
1117         __K8MASK(page-conflict, 2),
1118         NULLMASK
1119 };
1120
1121 /* nb memory controller turnaround */
1122 static const struct pmc_masks k8_mask_nmct[] = {
1123         __K8MASK(dimm-turnaround,               0),
1124         __K8MASK(read-to-write-turnaround,      1),
1125         __K8MASK(write-to-read-turnaround,      2),
1126         NULLMASK
1127 };
1128
1129 /* nb memory controller bypass saturation */
1130 static const struct pmc_masks k8_mask_nmcbs[] = {
1131         __K8MASK(memory-controller-hi-pri-bypass,       0),
1132         __K8MASK(memory-controller-lo-pri-bypass,       1),
1133         __K8MASK(dram-controller-interface-bypass,      2),
1134         __K8MASK(dram-controller-queue-bypass,          3),
1135         NULLMASK
1136 };
1137
1138 /* nb sized commands */
1139 static const struct pmc_masks k8_mask_nsc[] = {
1140         __K8MASK(nonpostwrszbyte,       0),
1141         __K8MASK(nonpostwrszdword,      1),
1142         __K8MASK(postwrszbyte,          2),
1143         __K8MASK(postwrszdword,         3),
1144         __K8MASK(rdszbyte,              4),
1145         __K8MASK(rdszdword,             5),
1146         __K8MASK(rdmodwr,               6),
1147         NULLMASK
1148 };
1149
1150 /* nb probe result */
1151 static const struct pmc_masks k8_mask_npr[] = {
1152         __K8MASK(probe-miss,            0),
1153         __K8MASK(probe-hit,             1),
1154         __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
1155         __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
1156         NULLMASK
1157 };
1158
1159 /* nb hypertransport bus bandwidth */
1160 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
1161         __K8MASK(command,       0),
1162         __K8MASK(data,  1),
1163         __K8MASK(buffer-release, 2),
1164         __K8MASK(nop,   3),
1165         NULLMASK
1166 };
1167
1168 #undef  __K8MASK
1169
1170 #define K8_KW_COUNT     "count"
1171 #define K8_KW_EDGE      "edge"
1172 #define K8_KW_INV       "inv"
1173 #define K8_KW_MASK      "mask"
1174 #define K8_KW_OS        "os"
1175 #define K8_KW_USR       "usr"
1176
1177 static int
1178 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
1179     struct pmc_op_pmcallocate *pmc_config)
1180 {
1181         char            *e, *p, *q;
1182         int             n;
1183         uint32_t        count;
1184         uint64_t        evmask;
1185         const struct pmc_masks  *pm, *pmask;
1186
1187         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1188         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
1189
1190         pmask = NULL;
1191         evmask = 0;
1192
1193 #define __K8SETMASK(M) pmask = k8_mask_##M
1194
1195         /* setup parsing tables */
1196         switch (pe) {
1197         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1198                 __K8SETMASK(fdfo);
1199                 break;
1200         case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
1201                 __K8SETMASK(lsrl);
1202                 break;
1203         case PMC_EV_K8_LS_LOCKED_OPERATION:
1204                 __K8SETMASK(llo);
1205                 break;
1206         case PMC_EV_K8_DC_REFILL_FROM_L2:
1207         case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
1208         case PMC_EV_K8_DC_COPYBACK:
1209                 __K8SETMASK(dc);
1210                 break;
1211         case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
1212                 __K8SETMASK(dobee);
1213                 break;
1214         case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
1215                 __K8SETMASK(ddpi);
1216                 break;
1217         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1218                 __K8SETMASK(dabl);
1219                 break;
1220         case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
1221                 __K8SETMASK(bilr);
1222                 break;
1223         case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
1224                 __K8SETMASK(bfrlm);
1225                 break;
1226         case PMC_EV_K8_BU_FILL_INTO_L2:
1227                 __K8SETMASK(bfil);
1228                 break;
1229         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1230                 __K8SETMASK(frfi);
1231                 break;
1232         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1233                 __K8SETMASK(frfdoi);
1234                 break;
1235         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1236                 __K8SETMASK(ffe);
1237                 break;
1238         case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
1239                 __K8SETMASK(nmcpae);
1240                 break;
1241         case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
1242                 __K8SETMASK(nmct);
1243                 break;
1244         case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
1245                 __K8SETMASK(nmcbs);
1246                 break;
1247         case PMC_EV_K8_NB_SIZED_COMMANDS:
1248                 __K8SETMASK(nsc);
1249                 break;
1250         case PMC_EV_K8_NB_PROBE_RESULT:
1251                 __K8SETMASK(npr);
1252                 break;
1253         case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
1254         case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
1255         case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
1256                 __K8SETMASK(nhbb);
1257                 break;
1258
1259         default:
1260                 break;          /* no options defined */
1261         }
1262
1263         while ((p = strsep(&ctrspec, ",")) != NULL) {
1264                 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
1265                         q = strchr(p, '=');
1266                         if (*++q == '\0') /* skip '=' */
1267                                 return (-1);
1268
1269                         count = strtol(q, &e, 0);
1270                         if (e == q || *e != '\0')
1271                                 return (-1);
1272
1273                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1274                         pmc_config->pm_md.pm_amd.pm_amd_config |=
1275                             AMD_PMC_TO_COUNTER(count);
1276
1277                 } else if (KWMATCH(p, K8_KW_EDGE)) {
1278                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1279                 } else if (KWMATCH(p, K8_KW_INV)) {
1280                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1281                 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
1282                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1283                                 return (-1);
1284                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1285                 } else if (KWMATCH(p, K8_KW_OS)) {
1286                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1287                 } else if (KWMATCH(p, K8_KW_USR)) {
1288                         pmc_config->pm_caps |= PMC_CAP_USER;
1289                 } else
1290                         return (-1);
1291         }
1292
1293         /* other post processing */
1294         switch (pe) {
1295         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1296         case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
1297         case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
1298         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1299         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1300         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1301                 /* XXX only available in rev B and later */
1302                 break;
1303         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1304                 /* XXX only available in rev C and later */
1305                 break;
1306         case PMC_EV_K8_LS_LOCKED_OPERATION:
1307                 /* XXX CPU Rev A,B evmask is to be zero */
1308                 if (evmask & (evmask - 1)) /* > 1 bit set */
1309                         return (-1);
1310                 if (evmask == 0) {
1311                         evmask = 0x01; /* Rev C and later: #instrs */
1312                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1313                 }
1314                 break;
1315         default:
1316                 if (evmask == 0 && pmask != NULL) {
1317                         for (pm = pmask; pm->pm_name; pm++)
1318                                 evmask |= pm->pm_value;
1319                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1320                 }
1321         }
1322
1323         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1324                 pmc_config->pm_md.pm_amd.pm_amd_config =
1325                     AMD_PMC_TO_UNITMASK(evmask);
1326
1327         return (0);
1328 }
1329
1330 #endif
1331
1332 #if defined(__amd64__) || defined(__i386__)
1333
1334 /*
1335  * Intel P4 PMCs
1336  */
1337
1338 static struct pmc_event_alias p4_aliases[] = {
1339         EV_ALIAS("branches",            "p4-branch-retired,mask=mmtp+mmtm"),
1340         EV_ALIAS("branch-mispredicts",  "p4-mispred-branch-retired"),
1341         EV_ALIAS("cycles",              "tsc"),
1342         EV_ALIAS("instructions",
1343             "p4-instr-retired,mask=nbogusntag+nbogustag"),
1344         EV_ALIAS("unhalted-cycles",     "p4-global-power-events"),
1345         EV_ALIAS(NULL, NULL)
1346 };
1347
1348 #define P4_KW_ACTIVE    "active"
1349 #define P4_KW_ACTIVE_ANY "any"
1350 #define P4_KW_ACTIVE_BOTH "both"
1351 #define P4_KW_ACTIVE_NONE "none"
1352 #define P4_KW_ACTIVE_SINGLE "single"
1353 #define P4_KW_BUSREQTYPE "busreqtype"
1354 #define P4_KW_CASCADE   "cascade"
1355 #define P4_KW_EDGE      "edge"
1356 #define P4_KW_INV       "complement"
1357 #define P4_KW_OS        "os"
1358 #define P4_KW_MASK      "mask"
1359 #define P4_KW_PRECISE   "precise"
1360 #define P4_KW_TAG       "tag"
1361 #define P4_KW_THRESHOLD "threshold"
1362 #define P4_KW_USR       "usr"
1363
1364 #define __P4MASK(N,V) PMCMASK(N, (1 << (V)))
1365
1366 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */
1367         __P4MASK(dd, 0),
1368         __P4MASK(db, 1),
1369         __P4MASK(di, 2),
1370         __P4MASK(bd, 3),
1371         __P4MASK(bb, 4),
1372         __P4MASK(bi, 5),
1373         __P4MASK(id, 6),
1374         __P4MASK(ib, 7),
1375         NULLMASK
1376 };
1377
1378 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */
1379         __P4MASK(tcmiss, 0),
1380         NULLMASK,
1381 };
1382
1383 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */
1384         __P4MASK(hit, 0),
1385         __P4MASK(miss, 1),
1386         __P4MASK(hit-uc, 2),
1387         NULLMASK
1388 };
1389
1390 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */
1391         __P4MASK(st-rb-full, 2),
1392         __P4MASK(64k-conf, 3),
1393         NULLMASK
1394 };
1395
1396 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */
1397         __P4MASK(lsc, 0),
1398         __P4MASK(ssc, 1),
1399         NULLMASK
1400 };
1401
1402 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */
1403         __P4MASK(split-ld, 1),
1404         NULLMASK
1405 };
1406
1407 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */
1408         __P4MASK(split-st, 1),
1409         NULLMASK
1410 };
1411
1412 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */
1413         __P4MASK(no-sta, 1),
1414         __P4MASK(no-std, 3),
1415         __P4MASK(partial-data, 4),
1416         __P4MASK(unalgn-addr, 5),
1417         NULLMASK
1418 };
1419
1420 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */
1421         __P4MASK(dtmiss, 0),
1422         __P4MASK(itmiss, 1),
1423         NULLMASK
1424 };
1425
1426 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */
1427         __P4MASK(rd-2ndl-hits, 0),
1428         __P4MASK(rd-2ndl-hite, 1),
1429         __P4MASK(rd-2ndl-hitm, 2),
1430         __P4MASK(rd-3rdl-hits, 3),
1431         __P4MASK(rd-3rdl-hite, 4),
1432         __P4MASK(rd-3rdl-hitm, 5),
1433         __P4MASK(rd-2ndl-miss, 8),
1434         __P4MASK(rd-3rdl-miss, 9),
1435         __P4MASK(wr-2ndl-miss, 10),
1436         NULLMASK
1437 };
1438
1439 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */
1440         __P4MASK(all-read, 5),
1441         __P4MASK(all-write, 6),
1442         __P4MASK(mem-uc, 7),
1443         __P4MASK(mem-wc, 8),
1444         __P4MASK(mem-wt, 9),
1445         __P4MASK(mem-wp, 10),
1446         __P4MASK(mem-wb, 11),
1447         __P4MASK(own, 13),
1448         __P4MASK(other, 14),
1449         __P4MASK(prefetch, 15),
1450         NULLMASK
1451 };
1452
1453 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */
1454         __P4MASK(all-read, 5),
1455         __P4MASK(all-write, 6),
1456         __P4MASK(mem-uc, 7),
1457         __P4MASK(mem-wc, 8),
1458         __P4MASK(mem-wt, 9),
1459         __P4MASK(mem-wp, 10),
1460         __P4MASK(mem-wb, 11),
1461         __P4MASK(own, 13),
1462         __P4MASK(other, 14),
1463         __P4MASK(prefetch, 15),
1464         NULLMASK
1465 };
1466
1467 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */
1468         __P4MASK(drdy-drv, 0),
1469         __P4MASK(drdy-own, 1),
1470         __P4MASK(drdy-other, 2),
1471         __P4MASK(dbsy-drv, 3),
1472         __P4MASK(dbsy-own, 4),
1473         __P4MASK(dbsy-other, 5),
1474         NULLMASK
1475 };
1476
1477 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */
1478         __P4MASK(req-type0, 0),
1479         __P4MASK(req-type1, 1),
1480         __P4MASK(req-len0, 2),
1481         __P4MASK(req-len1, 3),
1482         __P4MASK(req-io-type, 5),
1483         __P4MASK(req-lock-type, 6),
1484         __P4MASK(req-cache-type, 7),
1485         __P4MASK(req-split-type, 8),
1486         __P4MASK(req-dem-type, 9),
1487         __P4MASK(req-ord-type, 10),
1488         __P4MASK(mem-type0, 11),
1489         __P4MASK(mem-type1, 12),
1490         __P4MASK(mem-type2, 13),
1491         NULLMASK
1492 };
1493
1494 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */
1495         __P4MASK(all, 15),
1496         NULLMASK
1497 };
1498
1499 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */
1500         __P4MASK(all, 15),
1501         NULLMASK
1502 };
1503
1504 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */
1505         __P4MASK(all, 15),
1506         NULLMASK
1507 };
1508
1509 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */
1510         __P4MASK(all, 15),
1511         NULLMASK
1512 };
1513
1514 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */
1515         __P4MASK(all, 15),
1516         NULLMASK
1517 };
1518
1519 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */
1520         __P4MASK(all, 15),
1521         NULLMASK
1522 };
1523
1524 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */
1525         __P4MASK(all, 15),
1526         NULLMASK
1527 };
1528
1529 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */
1530         __P4MASK(all, 15),
1531         NULLMASK
1532 };
1533
1534 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */
1535         __P4MASK(allp0, 3),
1536         __P4MASK(allp2, 4),
1537         NULLMASK
1538 };
1539
1540 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */
1541         __P4MASK(running, 0),
1542         NULLMASK
1543 };
1544
1545 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */
1546         __P4MASK(cisc, 0),
1547         NULLMASK
1548 };
1549
1550 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */
1551         __P4MASK(from-tc-build, 0),
1552         __P4MASK(from-tc-deliver, 1),
1553         __P4MASK(from-rom, 2),
1554         NULLMASK
1555 };
1556
1557 static const struct pmc_masks p4_mask_rmbt[] = {
1558         /* retired mispred branch type */
1559         __P4MASK(conditional, 1),
1560         __P4MASK(call, 2),
1561         __P4MASK(return, 3),
1562         __P4MASK(indirect, 4),
1563         NULLMASK
1564 };
1565
1566 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */
1567         __P4MASK(conditional, 1),
1568         __P4MASK(call, 2),
1569         __P4MASK(retired, 3),
1570         __P4MASK(indirect, 4),
1571         NULLMASK
1572 };
1573
1574 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */
1575         __P4MASK(sbfull, 5),
1576         NULLMASK
1577 };
1578
1579 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */
1580         __P4MASK(wcb-evicts, 0),
1581         __P4MASK(wcb-full-evict, 1),
1582         NULLMASK
1583 };
1584
1585 static const struct pmc_masks p4_mask_fee[] = { /* front end event */
1586         __P4MASK(nbogus, 0),
1587         __P4MASK(bogus, 1),
1588         NULLMASK
1589 };
1590
1591 static const struct pmc_masks p4_mask_ee[] = { /* execution event */
1592         __P4MASK(nbogus0, 0),
1593         __P4MASK(nbogus1, 1),
1594         __P4MASK(nbogus2, 2),
1595         __P4MASK(nbogus3, 3),
1596         __P4MASK(bogus0, 4),
1597         __P4MASK(bogus1, 5),
1598         __P4MASK(bogus2, 6),
1599         __P4MASK(bogus3, 7),
1600         NULLMASK
1601 };
1602
1603 static const struct pmc_masks p4_mask_re[] = { /* replay event */
1604         __P4MASK(nbogus, 0),
1605         __P4MASK(bogus, 1),
1606         NULLMASK
1607 };
1608
1609 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */
1610         __P4MASK(nbogusntag, 0),
1611         __P4MASK(nbogustag, 1),
1612         __P4MASK(bogusntag, 2),
1613         __P4MASK(bogustag, 3),
1614         NULLMASK
1615 };
1616
1617 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */
1618         __P4MASK(nbogus, 0),
1619         __P4MASK(bogus, 1),
1620         NULLMASK
1621 };
1622
1623 static const struct pmc_masks p4_mask_ut[] = { /* uop type */
1624         __P4MASK(tagloads, 1),
1625         __P4MASK(tagstores, 2),
1626         NULLMASK
1627 };
1628
1629 static const struct pmc_masks p4_mask_br[] = { /* branch retired */
1630         __P4MASK(mmnp, 0),
1631         __P4MASK(mmnm, 1),
1632         __P4MASK(mmtp, 2),
1633         __P4MASK(mmtm, 3),
1634         NULLMASK
1635 };
1636
1637 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */
1638         __P4MASK(nbogus, 0),
1639         NULLMASK
1640 };
1641
1642 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */
1643         __P4MASK(fpsu, 0),
1644         __P4MASK(fpso, 1),
1645         __P4MASK(poao, 2),
1646         __P4MASK(poau, 3),
1647         __P4MASK(prea, 4),
1648         NULLMASK
1649 };
1650
1651 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */
1652         __P4MASK(clear, 0),
1653         __P4MASK(moclear, 2),
1654         __P4MASK(smclear, 3),
1655         NULLMASK
1656 };
1657
1658 /* P4 event parser */
1659 static int
1660 p4_allocate_pmc(enum pmc_event pe, char *ctrspec,
1661     struct pmc_op_pmcallocate *pmc_config)
1662 {
1663
1664         char    *e, *p, *q;
1665         int     count, has_tag, has_busreqtype, n;
1666         uint32_t cccractivemask;
1667         uint64_t evmask;
1668         const struct pmc_masks *pm, *pmask;
1669
1670         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1671         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig =
1672             pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0;
1673
1674         pmask   = NULL;
1675         evmask  = 0;
1676         cccractivemask = 0x3;
1677         has_tag = has_busreqtype = 0;
1678
1679 #define __P4SETMASK(M) do {                             \
1680         pmask = p4_mask_##M;                            \
1681 } while (0)
1682
1683         switch (pe) {
1684         case PMC_EV_P4_TC_DELIVER_MODE:
1685                 __P4SETMASK(tcdm);
1686                 break;
1687         case PMC_EV_P4_BPU_FETCH_REQUEST:
1688                 __P4SETMASK(bfr);
1689                 break;
1690         case PMC_EV_P4_ITLB_REFERENCE:
1691                 __P4SETMASK(ir);
1692                 break;
1693         case PMC_EV_P4_MEMORY_CANCEL:
1694                 __P4SETMASK(memcan);
1695                 break;
1696         case PMC_EV_P4_MEMORY_COMPLETE:
1697                 __P4SETMASK(memcomp);
1698                 break;
1699         case PMC_EV_P4_LOAD_PORT_REPLAY:
1700                 __P4SETMASK(lpr);
1701                 break;
1702         case PMC_EV_P4_STORE_PORT_REPLAY:
1703                 __P4SETMASK(spr);
1704                 break;
1705         case PMC_EV_P4_MOB_LOAD_REPLAY:
1706                 __P4SETMASK(mlr);
1707                 break;
1708         case PMC_EV_P4_PAGE_WALK_TYPE:
1709                 __P4SETMASK(pwt);
1710                 break;
1711         case PMC_EV_P4_BSQ_CACHE_REFERENCE:
1712                 __P4SETMASK(bcr);
1713                 break;
1714         case PMC_EV_P4_IOQ_ALLOCATION:
1715                 __P4SETMASK(ia);
1716                 has_busreqtype = 1;
1717                 break;
1718         case PMC_EV_P4_IOQ_ACTIVE_ENTRIES:
1719                 __P4SETMASK(iae);
1720                 has_busreqtype = 1;
1721                 break;
1722         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1723                 __P4SETMASK(fda);
1724                 break;
1725         case PMC_EV_P4_BSQ_ALLOCATION:
1726                 __P4SETMASK(ba);
1727                 break;
1728         case PMC_EV_P4_SSE_INPUT_ASSIST:
1729                 __P4SETMASK(sia);
1730                 break;
1731         case PMC_EV_P4_PACKED_SP_UOP:
1732                 __P4SETMASK(psu);
1733                 break;
1734         case PMC_EV_P4_PACKED_DP_UOP:
1735                 __P4SETMASK(pdu);
1736                 break;
1737         case PMC_EV_P4_SCALAR_SP_UOP:
1738                 __P4SETMASK(ssu);
1739                 break;
1740         case PMC_EV_P4_SCALAR_DP_UOP:
1741                 __P4SETMASK(sdu);
1742                 break;
1743         case PMC_EV_P4_64BIT_MMX_UOP:
1744                 __P4SETMASK(64bmu);
1745                 break;
1746         case PMC_EV_P4_128BIT_MMX_UOP:
1747                 __P4SETMASK(128bmu);
1748                 break;
1749         case PMC_EV_P4_X87_FP_UOP:
1750                 __P4SETMASK(xfu);
1751                 break;
1752         case PMC_EV_P4_X87_SIMD_MOVES_UOP:
1753                 __P4SETMASK(xsmu);
1754                 break;
1755         case PMC_EV_P4_GLOBAL_POWER_EVENTS:
1756                 __P4SETMASK(gpe);
1757                 break;
1758         case PMC_EV_P4_TC_MS_XFER:
1759                 __P4SETMASK(tmx);
1760                 break;
1761         case PMC_EV_P4_UOP_QUEUE_WRITES:
1762                 __P4SETMASK(uqw);
1763                 break;
1764         case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE:
1765                 __P4SETMASK(rmbt);
1766                 break;
1767         case PMC_EV_P4_RETIRED_BRANCH_TYPE:
1768                 __P4SETMASK(rbt);
1769                 break;
1770         case PMC_EV_P4_RESOURCE_STALL:
1771                 __P4SETMASK(rs);
1772                 break;
1773         case PMC_EV_P4_WC_BUFFER:
1774                 __P4SETMASK(wb);
1775                 break;
1776         case PMC_EV_P4_BSQ_ACTIVE_ENTRIES:
1777         case PMC_EV_P4_B2B_CYCLES:
1778         case PMC_EV_P4_BNR:
1779         case PMC_EV_P4_SNOOP:
1780         case PMC_EV_P4_RESPONSE:
1781                 break;
1782         case PMC_EV_P4_FRONT_END_EVENT:
1783                 __P4SETMASK(fee);
1784                 break;
1785         case PMC_EV_P4_EXECUTION_EVENT:
1786                 __P4SETMASK(ee);
1787                 break;
1788         case PMC_EV_P4_REPLAY_EVENT:
1789                 __P4SETMASK(re);
1790                 break;
1791         case PMC_EV_P4_INSTR_RETIRED:
1792                 __P4SETMASK(insret);
1793                 break;
1794         case PMC_EV_P4_UOPS_RETIRED:
1795                 __P4SETMASK(ur);
1796                 break;
1797         case PMC_EV_P4_UOP_TYPE:
1798                 __P4SETMASK(ut);
1799                 break;
1800         case PMC_EV_P4_BRANCH_RETIRED:
1801                 __P4SETMASK(br);
1802                 break;
1803         case PMC_EV_P4_MISPRED_BRANCH_RETIRED:
1804                 __P4SETMASK(mbr);
1805                 break;
1806         case PMC_EV_P4_X87_ASSIST:
1807                 __P4SETMASK(xa);
1808                 break;
1809         case PMC_EV_P4_MACHINE_CLEAR:
1810                 __P4SETMASK(machclr);
1811                 break;
1812         default:
1813                 return (-1);
1814         }
1815
1816         /* process additional flags */
1817         while ((p = strsep(&ctrspec, ",")) != NULL) {
1818                 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) {
1819                         q = strchr(p, '=');
1820                         if (*++q == '\0') /* skip '=' */
1821                                 return (-1);
1822
1823                         if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0)
1824                                 cccractivemask = 0x0;
1825                         else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0)
1826                                 cccractivemask = 0x1;
1827                         else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0)
1828                                 cccractivemask = 0x2;
1829                         else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0)
1830                                 cccractivemask = 0x3;
1831                         else
1832                                 return (-1);
1833
1834                 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) {
1835                         if (has_busreqtype == 0)
1836                                 return (-1);
1837
1838                         q = strchr(p, '=');
1839                         if (*++q == '\0') /* skip '=' */
1840                                 return (-1);
1841
1842                         count = strtol(q, &e, 0);
1843                         if (e == q || *e != '\0')
1844                                 return (-1);
1845                         evmask = (evmask & ~0x1F) | (count & 0x1F);
1846                 } else if (KWMATCH(p, P4_KW_CASCADE))
1847                         pmc_config->pm_caps |= PMC_CAP_CASCADE;
1848                 else if (KWMATCH(p, P4_KW_EDGE))
1849                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1850                 else if (KWMATCH(p, P4_KW_INV))
1851                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1852                 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) {
1853                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1854                                 return (-1);
1855                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1856                 } else if (KWMATCH(p, P4_KW_OS))
1857                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1858                 else if (KWMATCH(p, P4_KW_PRECISE))
1859                         pmc_config->pm_caps |= PMC_CAP_PRECISE;
1860                 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) {
1861                         if (has_tag == 0)
1862                                 return (-1);
1863
1864                         q = strchr(p, '=');
1865                         if (*++q == '\0') /* skip '=' */
1866                                 return (-1);
1867
1868                         count = strtol(q, &e, 0);
1869                         if (e == q || *e != '\0')
1870                                 return (-1);
1871
1872                         pmc_config->pm_caps |= PMC_CAP_TAGGING;
1873                         pmc_config->pm_md.pm_p4.pm_p4_escrconfig |=
1874                             P4_ESCR_TO_TAG_VALUE(count);
1875                 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) {
1876                         q = strchr(p, '=');
1877                         if (*++q == '\0') /* skip '=' */
1878                                 return (-1);
1879
1880                         count = strtol(q, &e, 0);
1881                         if (e == q || *e != '\0')
1882                                 return (-1);
1883
1884                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1885                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &=
1886                             ~P4_CCCR_THRESHOLD_MASK;
1887                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1888                             P4_CCCR_TO_THRESHOLD(count);
1889                 } else if (KWMATCH(p, P4_KW_USR))
1890                         pmc_config->pm_caps |= PMC_CAP_USER;
1891                 else
1892                         return (-1);
1893         }
1894
1895         /* other post processing */
1896         if (pe == PMC_EV_P4_IOQ_ALLOCATION ||
1897             pe == PMC_EV_P4_FSB_DATA_ACTIVITY ||
1898             pe == PMC_EV_P4_BSQ_ALLOCATION)
1899                 pmc_config->pm_caps |= PMC_CAP_EDGE;
1900
1901         /* fill in thread activity mask */
1902         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1903             P4_CCCR_TO_ACTIVE_THREAD(cccractivemask);
1904
1905         if (evmask)
1906                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1907
1908         switch (pe) {
1909         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1910                 if ((evmask & 0x06) == 0x06 ||
1911                     (evmask & 0x18) == 0x18)
1912                         return (-1); /* can't have own+other bits together */
1913                 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */
1914                         evmask = 0x1D;
1915                 break;
1916         case PMC_EV_P4_MACHINE_CLEAR:
1917                 /* only one bit is allowed to be set */
1918                 if ((evmask & (evmask - 1)) != 0)
1919                         return (-1);
1920                 if (evmask == 0) {
1921                         evmask = 0x1;   /* 'CLEAR' */
1922                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1923                 }
1924                 break;
1925         default:
1926                 if (evmask == 0 && pmask) {
1927                         for (pm = pmask; pm->pm_name; pm++)
1928                                 evmask |= pm->pm_value;
1929                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1930                 }
1931         }
1932
1933         pmc_config->pm_md.pm_p4.pm_p4_escrconfig =
1934             P4_ESCR_TO_EVENT_MASK(evmask);
1935
1936         return (0);
1937 }
1938
1939 #endif
1940
1941 #if defined(__i386__)
1942
1943 /*
1944  * Pentium style PMCs
1945  */
1946
1947 static struct pmc_event_alias p5_aliases[] = {
1948         EV_ALIAS("branches",            "p5-taken-branches"),
1949         EV_ALIAS("cycles",              "tsc"),
1950         EV_ALIAS("dc-misses",           "p5-data-read-miss-or-write-miss"),
1951         EV_ALIAS("ic-misses",           "p5-code-cache-miss"),
1952         EV_ALIAS("instructions",        "p5-instructions-executed"),
1953         EV_ALIAS("interrupts",          "p5-hardware-interrupts"),
1954         EV_ALIAS("unhalted-cycles",
1955             "p5-number-of-cycles-not-in-halt-state"),
1956         EV_ALIAS(NULL, NULL)
1957 };
1958
1959 static int
1960 p5_allocate_pmc(enum pmc_event pe, char *ctrspec,
1961     struct pmc_op_pmcallocate *pmc_config)
1962 {
1963         return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */
1964 }
1965
1966 /*
1967  * Pentium Pro style PMCs.  These PMCs are found in Pentium II, Pentium III,
1968  * and Pentium M CPUs.
1969  */
1970
1971 static struct pmc_event_alias p6_aliases[] = {
1972         EV_ALIAS("branches",            "p6-br-inst-retired"),
1973         EV_ALIAS("branch-mispredicts",  "p6-br-miss-pred-retired"),
1974         EV_ALIAS("cycles",              "tsc"),
1975         EV_ALIAS("dc-misses",           "p6-dcu-lines-in"),
1976         EV_ALIAS("ic-misses",           "p6-ifu-fetch-miss"),
1977         EV_ALIAS("instructions",        "p6-inst-retired"),
1978         EV_ALIAS("interrupts",          "p6-hw-int-rx"),
1979         EV_ALIAS("unhalted-cycles",     "p6-cpu-clk-unhalted"),
1980         EV_ALIAS(NULL, NULL)
1981 };
1982
1983 #define P6_KW_CMASK     "cmask"
1984 #define P6_KW_EDGE      "edge"
1985 #define P6_KW_INV       "inv"
1986 #define P6_KW_OS        "os"
1987 #define P6_KW_UMASK     "umask"
1988 #define P6_KW_USR       "usr"
1989
1990 static struct pmc_masks p6_mask_mesi[] = {
1991         PMCMASK(m,      0x01),
1992         PMCMASK(e,      0x02),
1993         PMCMASK(s,      0x04),
1994         PMCMASK(i,      0x08),
1995         NULLMASK
1996 };
1997
1998 static struct pmc_masks p6_mask_mesihw[] = {
1999         PMCMASK(m,      0x01),
2000         PMCMASK(e,      0x02),
2001         PMCMASK(s,      0x04),
2002         PMCMASK(i,      0x08),
2003         PMCMASK(nonhw,  0x00),
2004         PMCMASK(hw,     0x10),
2005         PMCMASK(both,   0x30),
2006         NULLMASK
2007 };
2008
2009 static struct pmc_masks p6_mask_hw[] = {
2010         PMCMASK(nonhw,  0x00),
2011         PMCMASK(hw,     0x10),
2012         PMCMASK(both,   0x30),
2013         NULLMASK
2014 };
2015
2016 static struct pmc_masks p6_mask_any[] = {
2017         PMCMASK(self,   0x00),
2018         PMCMASK(any,    0x20),
2019         NULLMASK
2020 };
2021
2022 static struct pmc_masks p6_mask_ekp[] = {
2023         PMCMASK(nta,    0x00),
2024         PMCMASK(t1,     0x01),
2025         PMCMASK(t2,     0x02),
2026         PMCMASK(wos,    0x03),
2027         NULLMASK
2028 };
2029
2030 static struct pmc_masks p6_mask_pps[] = {
2031         PMCMASK(packed-and-scalar, 0x00),
2032         PMCMASK(scalar, 0x01),
2033         NULLMASK
2034 };
2035
2036 static struct pmc_masks p6_mask_mite[] = {
2037         PMCMASK(packed-multiply,         0x01),
2038         PMCMASK(packed-shift,           0x02),
2039         PMCMASK(pack,                   0x04),
2040         PMCMASK(unpack,                 0x08),
2041         PMCMASK(packed-logical,         0x10),
2042         PMCMASK(packed-arithmetic,      0x20),
2043         NULLMASK
2044 };
2045
2046 static struct pmc_masks p6_mask_fmt[] = {
2047         PMCMASK(mmxtofp,        0x00),
2048         PMCMASK(fptommx,        0x01),
2049         NULLMASK
2050 };
2051
2052 static struct pmc_masks p6_mask_sr[] = {
2053         PMCMASK(es,     0x01),
2054         PMCMASK(ds,     0x02),
2055         PMCMASK(fs,     0x04),
2056         PMCMASK(gs,     0x08),
2057         NULLMASK
2058 };
2059
2060 static struct pmc_masks p6_mask_eet[] = {
2061         PMCMASK(all,    0x00),
2062         PMCMASK(freq,   0x02),
2063         NULLMASK
2064 };
2065
2066 static struct pmc_masks p6_mask_efur[] = {
2067         PMCMASK(all,    0x00),
2068         PMCMASK(loadop, 0x01),
2069         PMCMASK(stdsta, 0x02),
2070         NULLMASK
2071 };
2072
2073 static struct pmc_masks p6_mask_essir[] = {
2074         PMCMASK(sse-packed-single,      0x00),
2075         PMCMASK(sse-packed-single-scalar-single, 0x01),
2076         PMCMASK(sse2-packed-double,     0x02),
2077         PMCMASK(sse2-scalar-double,     0x03),
2078         NULLMASK
2079 };
2080
2081 static struct pmc_masks p6_mask_esscir[] = {
2082         PMCMASK(sse-packed-single,      0x00),
2083         PMCMASK(sse-scalar-single,      0x01),
2084         PMCMASK(sse2-packed-double,     0x02),
2085         PMCMASK(sse2-scalar-double,     0x03),
2086         NULLMASK
2087 };
2088
2089 /* P6 event parser */
2090 static int
2091 p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
2092     struct pmc_op_pmcallocate *pmc_config)
2093 {
2094         char *e, *p, *q;
2095         uint64_t evmask;
2096         int count, n;
2097         const struct pmc_masks *pm, *pmask;
2098
2099         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2100         pmc_config->pm_md.pm_ppro.pm_ppro_config = 0;
2101
2102         evmask = 0;
2103
2104 #define P6MASKSET(M)    pmask = p6_mask_ ## M
2105
2106         switch(pe) {
2107         case PMC_EV_P6_L2_IFETCH:       P6MASKSET(mesi); break;
2108         case PMC_EV_P6_L2_LD:           P6MASKSET(mesi); break;
2109         case PMC_EV_P6_L2_ST:           P6MASKSET(mesi); break;
2110         case PMC_EV_P6_L2_RQSTS:        P6MASKSET(mesi); break;
2111         case PMC_EV_P6_BUS_DRDY_CLOCKS:
2112         case PMC_EV_P6_BUS_LOCK_CLOCKS:
2113         case PMC_EV_P6_BUS_TRAN_BRD:
2114         case PMC_EV_P6_BUS_TRAN_RFO:
2115         case PMC_EV_P6_BUS_TRANS_WB:
2116         case PMC_EV_P6_BUS_TRAN_IFETCH:
2117         case PMC_EV_P6_BUS_TRAN_INVAL:
2118         case PMC_EV_P6_BUS_TRAN_PWR:
2119         case PMC_EV_P6_BUS_TRANS_P:
2120         case PMC_EV_P6_BUS_TRANS_IO:
2121         case PMC_EV_P6_BUS_TRAN_DEF:
2122         case PMC_EV_P6_BUS_TRAN_BURST:
2123         case PMC_EV_P6_BUS_TRAN_ANY:
2124         case PMC_EV_P6_BUS_TRAN_MEM:
2125                 P6MASKSET(any); break;
2126         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2127         case PMC_EV_P6_EMON_KNI_PREF_MISS:
2128                 P6MASKSET(ekp); break;
2129         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2130         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2131                 P6MASKSET(pps); break;
2132         case PMC_EV_P6_MMX_INSTR_TYPE_EXEC:
2133                 P6MASKSET(mite); break;
2134         case PMC_EV_P6_FP_MMX_TRANS:
2135                 P6MASKSET(fmt); break;
2136         case PMC_EV_P6_SEG_RENAME_STALLS:
2137         case PMC_EV_P6_SEG_REG_RENAMES:
2138                 P6MASKSET(sr);  break;
2139         case PMC_EV_P6_EMON_EST_TRANS:
2140                 P6MASKSET(eet); break;
2141         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2142                 P6MASKSET(efur); break;
2143         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2144                 P6MASKSET(essir); break;
2145         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2146                 P6MASKSET(esscir); break;
2147         default:
2148                 pmask = NULL;
2149                 break;
2150         }
2151
2152         /* Pentium M PMCs have a few events with different semantics */
2153         if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) {
2154                 if (pe == PMC_EV_P6_L2_LD ||
2155                     pe == PMC_EV_P6_L2_LINES_IN ||
2156                     pe == PMC_EV_P6_L2_LINES_OUT)
2157                         P6MASKSET(mesihw);
2158                 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM)
2159                         P6MASKSET(hw);
2160         }
2161
2162         /* Parse additional modifiers if present */
2163         while ((p = strsep(&ctrspec, ",")) != NULL) {
2164                 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) {
2165                         q = strchr(p, '=');
2166                         if (*++q == '\0') /* skip '=' */
2167                                 return (-1);
2168                         count = strtol(q, &e, 0);
2169                         if (e == q || *e != '\0')
2170                                 return (-1);
2171                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
2172                         pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2173                             P6_EVSEL_TO_CMASK(count);
2174                 } else if (KWMATCH(p, P6_KW_EDGE)) {
2175                         pmc_config->pm_caps |= PMC_CAP_EDGE;
2176                 } else if (KWMATCH(p, P6_KW_INV)) {
2177                         pmc_config->pm_caps |= PMC_CAP_INVERT;
2178                 } else if (KWMATCH(p, P6_KW_OS)) {
2179                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2180                 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) {
2181                         evmask = 0;
2182                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
2183                                 return (-1);
2184                         if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS ||
2185                              pe == PMC_EV_P6_BUS_LOCK_CLOCKS ||
2186                              pe == PMC_EV_P6_BUS_TRAN_BRD ||
2187                              pe == PMC_EV_P6_BUS_TRAN_RFO ||
2188                              pe == PMC_EV_P6_BUS_TRAN_IFETCH ||
2189                              pe == PMC_EV_P6_BUS_TRAN_INVAL ||
2190                              pe == PMC_EV_P6_BUS_TRAN_PWR ||
2191                              pe == PMC_EV_P6_BUS_TRAN_DEF ||
2192                              pe == PMC_EV_P6_BUS_TRAN_BURST ||
2193                              pe == PMC_EV_P6_BUS_TRAN_ANY ||
2194                              pe == PMC_EV_P6_BUS_TRAN_MEM ||
2195                              pe == PMC_EV_P6_BUS_TRANS_IO ||
2196                              pe == PMC_EV_P6_BUS_TRANS_P ||
2197                              pe == PMC_EV_P6_BUS_TRANS_WB ||
2198                              pe == PMC_EV_P6_EMON_EST_TRANS ||
2199                              pe == PMC_EV_P6_EMON_FUSED_UOPS_RET ||
2200                              pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET ||
2201                              pe == PMC_EV_P6_EMON_KNI_INST_RETIRED ||
2202                              pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED ||
2203                              pe == PMC_EV_P6_EMON_KNI_PREF_MISS ||
2204                              pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED ||
2205                              pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED ||
2206                              pe == PMC_EV_P6_FP_MMX_TRANS)
2207                             && (n > 1)) /* Only one mask keyword is allowed. */
2208                                 return (-1);
2209                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2210                 } else if (KWMATCH(p, P6_KW_USR)) {
2211                         pmc_config->pm_caps |= PMC_CAP_USER;
2212                 } else
2213                         return (-1);
2214         }
2215
2216         /* post processing */
2217         switch (pe) {
2218
2219                 /*
2220                  * The following events default to an evmask of 0
2221                  */
2222
2223                 /* default => 'self' */
2224         case PMC_EV_P6_BUS_DRDY_CLOCKS:
2225         case PMC_EV_P6_BUS_LOCK_CLOCKS:
2226         case PMC_EV_P6_BUS_TRAN_BRD:
2227         case PMC_EV_P6_BUS_TRAN_RFO:
2228         case PMC_EV_P6_BUS_TRANS_WB:
2229         case PMC_EV_P6_BUS_TRAN_IFETCH:
2230         case PMC_EV_P6_BUS_TRAN_INVAL:
2231         case PMC_EV_P6_BUS_TRAN_PWR:
2232         case PMC_EV_P6_BUS_TRANS_P:
2233         case PMC_EV_P6_BUS_TRANS_IO:
2234         case PMC_EV_P6_BUS_TRAN_DEF:
2235         case PMC_EV_P6_BUS_TRAN_BURST:
2236         case PMC_EV_P6_BUS_TRAN_ANY:
2237         case PMC_EV_P6_BUS_TRAN_MEM:
2238
2239                 /* default => 'nta' */
2240         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2241         case PMC_EV_P6_EMON_KNI_PREF_MISS:
2242
2243                 /* default => 'packed and scalar' */
2244         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2245         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2246
2247                 /* default => 'mmx to fp transitions' */
2248         case PMC_EV_P6_FP_MMX_TRANS:
2249
2250                 /* default => 'SSE Packed Single' */
2251         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2252         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2253
2254                 /* default => 'all fused micro-ops' */
2255         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2256
2257                 /* default => 'all transitions' */
2258         case PMC_EV_P6_EMON_EST_TRANS:
2259                 break;
2260
2261         case PMC_EV_P6_MMX_UOPS_EXEC:
2262                 evmask = 0x0F;          /* only value allowed */
2263                 break;
2264
2265         default:
2266                 /*
2267                  * For all other events, set the default event mask
2268                  * to a logical OR of all the allowed event mask bits.
2269                  */
2270                 if (evmask == 0 && pmask) {
2271                         for (pm = pmask; pm->pm_name; pm++)
2272                                 evmask |= pm->pm_value;
2273                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2274                 }
2275
2276                 break;
2277         }
2278
2279         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
2280                 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2281                     P6_EVSEL_TO_UMASK(evmask);
2282
2283         return (0);
2284 }
2285
2286 #endif
2287
2288 #if     defined(__i386__) || defined(__amd64__)
2289 static int
2290 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
2291     struct pmc_op_pmcallocate *pmc_config)
2292 {
2293         if (pe != PMC_EV_TSC_TSC)
2294                 return (-1);
2295
2296         /* TSC events must be unqualified. */
2297         if (ctrspec && *ctrspec != '\0')
2298                 return (-1);
2299
2300         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
2301         pmc_config->pm_caps |= PMC_CAP_READ;
2302
2303         return (0);
2304 }
2305 #endif
2306
2307 static struct pmc_event_alias generic_aliases[] = {
2308         EV_ALIAS("instructions",                "SOFT-CLOCK.HARD"),
2309         EV_ALIAS(NULL, NULL)
2310 };
2311
2312 static int
2313 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
2314     struct pmc_op_pmcallocate *pmc_config)
2315 {
2316         (void)ctrspec;
2317         (void)pmc_config;
2318
2319         if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST)
2320                 return (-1);
2321
2322         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2323         return (0);
2324 }
2325
2326 #if     defined(__XSCALE__)
2327
2328 static struct pmc_event_alias xscale_aliases[] = {
2329         EV_ALIAS("branches",            "BRANCH_RETIRED"),
2330         EV_ALIAS("branch-mispredicts",  "BRANCH_MISPRED"),
2331         EV_ALIAS("dc-misses",           "DC_MISS"),
2332         EV_ALIAS("ic-misses",           "IC_MISS"),
2333         EV_ALIAS("instructions",        "INSTR_RETIRED"),
2334         EV_ALIAS(NULL, NULL)
2335 };
2336 static int
2337 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2338     struct pmc_op_pmcallocate *pmc_config __unused)
2339 {
2340         switch (pe) {
2341         default:
2342                 break;
2343         }
2344
2345         return (0);
2346 }
2347 #endif
2348
2349 #if defined(__mips__)
2350
2351 static struct pmc_event_alias mips24k_aliases[] = {
2352         EV_ALIAS("instructions",        "INSTR_EXECUTED"),
2353         EV_ALIAS("branches",            "BRANCH_COMPLETED"),
2354         EV_ALIAS("branch-mispredicts",  "BRANCH_MISPRED"),
2355         EV_ALIAS(NULL, NULL)
2356 };
2357
2358 #define MIPS24K_KW_OS           "os"
2359 #define MIPS24K_KW_USR          "usr"
2360 #define MIPS24K_KW_ANYTHREAD    "anythread"
2361
2362 static int
2363 mips24k_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2364                   struct pmc_op_pmcallocate *pmc_config __unused)
2365 {
2366         char *p;
2367
2368         (void) pe;
2369
2370         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2371
2372         while ((p = strsep(&ctrspec, ",")) != NULL) {
2373                 if (KWMATCH(p, MIPS24K_KW_OS))
2374                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2375                 else if (KWMATCH(p, MIPS24K_KW_USR))
2376                         pmc_config->pm_caps |= PMC_CAP_USER;
2377                 else if (KWMATCH(p, MIPS24K_KW_ANYTHREAD))
2378                         pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2379                 else
2380                         return (-1);
2381         }
2382
2383         return (0);
2384 }
2385 #endif /* __mips__ */
2386
2387 #if defined(__powerpc__)
2388
2389 static struct pmc_event_alias ppc7450_aliases[] = {
2390         EV_ALIAS("instructions",        "INSTR_COMPLETED"),
2391         EV_ALIAS("branches",            "BRANCHES_COMPLETED"),
2392         EV_ALIAS("branch-mispredicts",  "MISPREDICTED_BRANCHES"),
2393         EV_ALIAS(NULL, NULL)
2394 };
2395
2396 #define PPC7450_KW_OS           "os"
2397 #define PPC7450_KW_USR          "usr"
2398 #define PPC7450_KW_ANYTHREAD    "anythread"
2399
2400 static int
2401 ppc7450_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2402                   struct pmc_op_pmcallocate *pmc_config __unused)
2403 {
2404         char *p;
2405
2406         (void) pe;
2407
2408         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2409
2410         while ((p = strsep(&ctrspec, ",")) != NULL) {
2411                 if (KWMATCH(p, PPC7450_KW_OS))
2412                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2413                 else if (KWMATCH(p, PPC7450_KW_USR))
2414                         pmc_config->pm_caps |= PMC_CAP_USER;
2415                 else if (KWMATCH(p, PPC7450_KW_ANYTHREAD))
2416                         pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2417                 else
2418                         return (-1);
2419         }
2420
2421         return (0);
2422 }
2423 #endif /* __powerpc__ */
2424
2425
2426 /*
2427  * Match an event name `name' with its canonical form.
2428  *
2429  * Matches are case insensitive and spaces, periods, underscores and
2430  * hyphen characters are considered to match each other.
2431  *
2432  * Returns 1 for a match, 0 otherwise.
2433  */
2434
2435 static int
2436 pmc_match_event_name(const char *name, const char *canonicalname)
2437 {
2438         int cc, nc;
2439         const unsigned char *c, *n;
2440
2441         c = (const unsigned char *) canonicalname;
2442         n = (const unsigned char *) name;
2443
2444         for (; (nc = *n) && (cc = *c); n++, c++) {
2445
2446                 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
2447                     (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
2448                         continue;
2449
2450                 if (toupper(nc) == toupper(cc))
2451                         continue;
2452
2453
2454                 return (0);
2455         }
2456
2457         if (*n == '\0' && *c == '\0')
2458                 return (1);
2459
2460         return (0);
2461 }
2462
2463 /*
2464  * Match an event name against all the event named supported by a
2465  * PMC class.
2466  *
2467  * Returns an event descriptor pointer on match or NULL otherwise.
2468  */
2469 static const struct pmc_event_descr *
2470 pmc_match_event_class(const char *name,
2471     const struct pmc_class_descr *pcd)
2472 {
2473         size_t n;
2474         const struct pmc_event_descr *ev;
2475
2476         ev = pcd->pm_evc_event_table;
2477         for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
2478                 if (pmc_match_event_name(name, ev->pm_ev_name))
2479                         return (ev);
2480
2481         return (NULL);
2482 }
2483
2484 static int
2485 pmc_mdep_is_compatible_class(enum pmc_class pc)
2486 {
2487         size_t n;
2488
2489         for (n = 0; n < pmc_mdep_class_list_size; n++)
2490                 if (pmc_mdep_class_list[n] == pc)
2491                         return (1);
2492         return (0);
2493 }
2494
2495 /*
2496  * API entry points
2497  */
2498
2499 int
2500 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
2501     uint32_t flags, int cpu, pmc_id_t *pmcid)
2502 {
2503         size_t n;
2504         int retval;
2505         char *r, *spec_copy;
2506         const char *ctrname;
2507         const struct pmc_event_descr *ev;
2508         const struct pmc_event_alias *alias;
2509         struct pmc_op_pmcallocate pmc_config;
2510         const struct pmc_class_descr *pcd;
2511
2512         spec_copy = NULL;
2513         retval    = -1;
2514
2515         if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
2516             mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
2517                 errno = EINVAL;
2518                 goto out;
2519         }
2520
2521         /* replace an event alias with the canonical event specifier */
2522         if (pmc_mdep_event_aliases)
2523                 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
2524                         if (!strcasecmp(ctrspec, alias->pm_alias)) {
2525                                 spec_copy = strdup(alias->pm_spec);
2526                                 break;
2527                         }
2528
2529         if (spec_copy == NULL)
2530                 spec_copy = strdup(ctrspec);
2531
2532         r = spec_copy;
2533         ctrname = strsep(&r, ",");
2534
2535         /*
2536          * If a explicit class prefix was given by the user, restrict the
2537          * search for the event to the specified PMC class.
2538          */
2539         ev = NULL;
2540         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
2541                 pcd = pmc_class_table[n];
2542                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) &&
2543                     strncasecmp(ctrname, pcd->pm_evc_name,
2544                                 pcd->pm_evc_name_size) == 0) {
2545                         if ((ev = pmc_match_event_class(ctrname +
2546                             pcd->pm_evc_name_size, pcd)) == NULL) {
2547                                 errno = EINVAL;
2548                                 goto out;
2549                         }
2550                         break;
2551                 }
2552         }
2553
2554         /*
2555          * Otherwise, search for this event in all compatible PMC
2556          * classes.
2557          */
2558         for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
2559                 pcd = pmc_class_table[n];
2560                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class))
2561                         ev = pmc_match_event_class(ctrname, pcd);
2562         }
2563
2564         if (ev == NULL) {
2565                 errno = EINVAL;
2566                 goto out;
2567         }
2568
2569         bzero(&pmc_config, sizeof(pmc_config));
2570         pmc_config.pm_ev    = ev->pm_ev_code;
2571         pmc_config.pm_class = pcd->pm_evc_class;
2572         pmc_config.pm_cpu   = cpu;
2573         pmc_config.pm_mode  = mode;
2574         pmc_config.pm_flags = flags;
2575
2576         if (PMC_IS_SAMPLING_MODE(mode))
2577                 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
2578
2579         if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
2580                 errno = EINVAL;
2581                 goto out;
2582         }
2583
2584         if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0)
2585                 goto out;
2586
2587         *pmcid = pmc_config.pm_pmcid;
2588
2589         retval = 0;
2590
2591  out:
2592         if (spec_copy)
2593                 free(spec_copy);
2594
2595         return (retval);
2596 }
2597
2598 int
2599 pmc_attach(pmc_id_t pmc, pid_t pid)
2600 {
2601         struct pmc_op_pmcattach pmc_attach_args;
2602
2603         pmc_attach_args.pm_pmc = pmc;
2604         pmc_attach_args.pm_pid = pid;
2605
2606         return (PMC_CALL(PMCATTACH, &pmc_attach_args));
2607 }
2608
2609 int
2610 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
2611 {
2612         unsigned int i;
2613         enum pmc_class cl;
2614
2615         cl = PMC_ID_TO_CLASS(pmcid);
2616         for (i = 0; i < cpu_info.pm_nclass; i++)
2617                 if (cpu_info.pm_classes[i].pm_class == cl) {
2618                         *caps = cpu_info.pm_classes[i].pm_caps;
2619                         return (0);
2620                 }
2621         errno = EINVAL;
2622         return (-1);
2623 }
2624
2625 int
2626 pmc_configure_logfile(int fd)
2627 {
2628         struct pmc_op_configurelog cla;
2629
2630         cla.pm_logfd = fd;
2631         if (PMC_CALL(CONFIGURELOG, &cla) < 0)
2632                 return (-1);
2633         return (0);
2634 }
2635
2636 int
2637 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
2638 {
2639         if (pmc_syscall == -1) {
2640                 errno = ENXIO;
2641                 return (-1);
2642         }
2643
2644         *pci = &cpu_info;
2645         return (0);
2646 }
2647
2648 int
2649 pmc_detach(pmc_id_t pmc, pid_t pid)
2650 {
2651         struct pmc_op_pmcattach pmc_detach_args;
2652
2653         pmc_detach_args.pm_pmc = pmc;
2654         pmc_detach_args.pm_pid = pid;
2655         return (PMC_CALL(PMCDETACH, &pmc_detach_args));
2656 }
2657
2658 int
2659 pmc_disable(int cpu, int pmc)
2660 {
2661         struct pmc_op_pmcadmin ssa;
2662
2663         ssa.pm_cpu = cpu;
2664         ssa.pm_pmc = pmc;
2665         ssa.pm_state = PMC_STATE_DISABLED;
2666         return (PMC_CALL(PMCADMIN, &ssa));
2667 }
2668
2669 int
2670 pmc_enable(int cpu, int pmc)
2671 {
2672         struct pmc_op_pmcadmin ssa;
2673
2674         ssa.pm_cpu = cpu;
2675         ssa.pm_pmc = pmc;
2676         ssa.pm_state = PMC_STATE_FREE;
2677         return (PMC_CALL(PMCADMIN, &ssa));
2678 }
2679
2680 /*
2681  * Return a list of events known to a given PMC class.  'cl' is the
2682  * PMC class identifier, 'eventnames' is the returned list of 'const
2683  * char *' pointers pointing to the names of the events. 'nevents' is
2684  * the number of event name pointers returned.
2685  *
2686  * The space for 'eventnames' is allocated using malloc(3).  The caller
2687  * is responsible for freeing this space when done.
2688  */
2689 int
2690 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
2691     int *nevents)
2692 {
2693         int count;
2694         const char **names;
2695         const struct pmc_event_descr *ev;
2696
2697         switch (cl)
2698         {
2699         case PMC_CLASS_IAF:
2700                 ev = iaf_event_table;
2701                 count = PMC_EVENT_TABLE_SIZE(iaf);
2702                 break;
2703         case PMC_CLASS_IAP:
2704                 /*
2705                  * Return the most appropriate set of event name
2706                  * spellings for the current CPU.
2707                  */
2708                 switch (cpu_info.pm_cputype) {
2709                 default:
2710                 case PMC_CPU_INTEL_ATOM:
2711                         ev = atom_event_table;
2712                         count = PMC_EVENT_TABLE_SIZE(atom);
2713                         break;
2714                 case PMC_CPU_INTEL_CORE:
2715                         ev = core_event_table;
2716                         count = PMC_EVENT_TABLE_SIZE(core);
2717                         break;
2718                 case PMC_CPU_INTEL_CORE2:
2719                 case PMC_CPU_INTEL_CORE2EXTREME:
2720                         ev = core2_event_table;
2721                         count = PMC_EVENT_TABLE_SIZE(core2);
2722                         break;
2723                 case PMC_CPU_INTEL_COREI7:
2724                         ev = corei7_event_table;
2725                         count = PMC_EVENT_TABLE_SIZE(corei7);
2726                         break;
2727                 case PMC_CPU_INTEL_HASWELL:
2728                         ev = haswell_event_table;
2729                         count = PMC_EVENT_TABLE_SIZE(haswell);
2730                         break;
2731                 case PMC_CPU_INTEL_IVYBRIDGE:
2732                         ev = ivybridge_event_table;
2733                         count = PMC_EVENT_TABLE_SIZE(ivybridge);
2734                         break;
2735                 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2736                         ev = ivybridge_xeon_event_table;
2737                         count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
2738                         break;
2739                 case PMC_CPU_INTEL_SANDYBRIDGE:
2740                         ev = sandybridge_event_table;
2741                         count = PMC_EVENT_TABLE_SIZE(sandybridge);
2742                         break;
2743                 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2744                         ev = sandybridge_xeon_event_table;
2745                         count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
2746                         break;
2747                 case PMC_CPU_INTEL_WESTMERE:
2748                         ev = westmere_event_table;
2749                         count = PMC_EVENT_TABLE_SIZE(westmere);
2750                         break;
2751                 }
2752                 break;
2753         case PMC_CLASS_UCF:
2754                 ev = ucf_event_table;
2755                 count = PMC_EVENT_TABLE_SIZE(ucf);
2756                 break;
2757         case PMC_CLASS_UCP:
2758                 /*
2759                  * Return the most appropriate set of event name
2760                  * spellings for the current CPU.
2761                  */
2762                 switch (cpu_info.pm_cputype) {
2763                 default:
2764                 case PMC_CPU_INTEL_COREI7:
2765                         ev = corei7uc_event_table;
2766                         count = PMC_EVENT_TABLE_SIZE(corei7uc);
2767                         break;
2768                 case PMC_CPU_INTEL_HASWELL:
2769                         ev = haswelluc_event_table;
2770                         count = PMC_EVENT_TABLE_SIZE(haswelluc);
2771                         break;
2772                 case PMC_CPU_INTEL_SANDYBRIDGE:
2773                         ev = sandybridgeuc_event_table;
2774                         count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
2775                         break;
2776                 case PMC_CPU_INTEL_WESTMERE:
2777                         ev = westmereuc_event_table;
2778                         count = PMC_EVENT_TABLE_SIZE(westmereuc);
2779                         break;
2780                 }
2781                 break;
2782         case PMC_CLASS_TSC:
2783                 ev = tsc_event_table;
2784                 count = PMC_EVENT_TABLE_SIZE(tsc);
2785                 break;
2786         case PMC_CLASS_K7:
2787                 ev = k7_event_table;
2788                 count = PMC_EVENT_TABLE_SIZE(k7);
2789                 break;
2790         case PMC_CLASS_K8:
2791                 ev = k8_event_table;
2792                 count = PMC_EVENT_TABLE_SIZE(k8);
2793                 break;
2794         case PMC_CLASS_P4:
2795                 ev = p4_event_table;
2796                 count = PMC_EVENT_TABLE_SIZE(p4);
2797                 break;
2798         case PMC_CLASS_P5:
2799                 ev = p5_event_table;
2800                 count = PMC_EVENT_TABLE_SIZE(p5);
2801                 break;
2802         case PMC_CLASS_P6:
2803                 ev = p6_event_table;
2804                 count = PMC_EVENT_TABLE_SIZE(p6);
2805                 break;
2806         case PMC_CLASS_XSCALE:
2807                 ev = xscale_event_table;
2808                 count = PMC_EVENT_TABLE_SIZE(xscale);
2809                 break;
2810         case PMC_CLASS_MIPS24K:
2811                 ev = mips24k_event_table;
2812                 count = PMC_EVENT_TABLE_SIZE(mips24k);
2813                 break;
2814         case PMC_CLASS_PPC7450:
2815                 ev = ppc7450_event_table;
2816                 count = PMC_EVENT_TABLE_SIZE(ppc7450);
2817                 break;
2818         case PMC_CLASS_SOFT:
2819                 ev = soft_event_table;
2820                 count = soft_event_info.pm_nevent;
2821                 break;
2822         default:
2823                 errno = EINVAL;
2824                 return (-1);
2825         }
2826
2827         if ((names = malloc(count * sizeof(const char *))) == NULL)
2828                 return (-1);
2829
2830         *eventnames = names;
2831         *nevents = count;
2832
2833         for (;count--; ev++, names++)
2834                 *names = ev->pm_ev_name;
2835
2836         return (0);
2837 }
2838
2839 int
2840 pmc_flush_logfile(void)
2841 {
2842         return (PMC_CALL(FLUSHLOG,0));
2843 }
2844
2845 int
2846 pmc_close_logfile(void)
2847 {
2848         return (PMC_CALL(CLOSELOG,0));
2849 }
2850
2851 int
2852 pmc_get_driver_stats(struct pmc_driverstats *ds)
2853 {
2854         struct pmc_op_getdriverstats gms;
2855
2856         if (PMC_CALL(GETDRIVERSTATS, &gms) < 0)
2857                 return (-1);
2858
2859         /* copy out fields in the current userland<->library interface */
2860         ds->pm_intr_ignored    = gms.pm_intr_ignored;
2861         ds->pm_intr_processed  = gms.pm_intr_processed;
2862         ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
2863         ds->pm_syscalls        = gms.pm_syscalls;
2864         ds->pm_syscall_errors  = gms.pm_syscall_errors;
2865         ds->pm_buffer_requests = gms.pm_buffer_requests;
2866         ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
2867         ds->pm_log_sweeps      = gms.pm_log_sweeps;
2868         return (0);
2869 }
2870
2871 int
2872 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
2873 {
2874         struct pmc_op_getmsr gm;
2875
2876         gm.pm_pmcid = pmc;
2877         if (PMC_CALL(PMCGETMSR, &gm) < 0)
2878                 return (-1);
2879         *msr = gm.pm_msr;
2880         return (0);
2881 }
2882
2883 int
2884 pmc_init(void)
2885 {
2886         int error, pmc_mod_id;
2887         unsigned int n;
2888         uint32_t abi_version;
2889         struct module_stat pmc_modstat;
2890         struct pmc_op_getcpuinfo op_cpu_info;
2891 #if defined(__amd64__) || defined(__i386__)
2892         int cpu_has_iaf_counters;
2893         unsigned int t;
2894 #endif
2895
2896         if (pmc_syscall != -1) /* already inited */
2897                 return (0);
2898
2899         /* retrieve the system call number from the KLD */
2900         if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
2901                 return (-1);
2902
2903         pmc_modstat.version = sizeof(struct module_stat);
2904         if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
2905                 return (-1);
2906
2907         pmc_syscall = pmc_modstat.data.intval;
2908
2909         /* check the kernel module's ABI against our compiled-in version */
2910         abi_version = PMC_VERSION;
2911         if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0)
2912                 return (pmc_syscall = -1);
2913
2914         /* ignore patch & minor numbers for the comparision */
2915         if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
2916                 errno  = EPROGMISMATCH;
2917                 return (pmc_syscall = -1);
2918         }
2919
2920         if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0)
2921                 return (pmc_syscall = -1);
2922
2923         cpu_info.pm_cputype = op_cpu_info.pm_cputype;
2924         cpu_info.pm_ncpu    = op_cpu_info.pm_ncpu;
2925         cpu_info.pm_npmc    = op_cpu_info.pm_npmc;
2926         cpu_info.pm_nclass  = op_cpu_info.pm_nclass;
2927         for (n = 0; n < cpu_info.pm_nclass; n++)
2928                 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n];
2929
2930         pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE *
2931             sizeof(struct pmc_class_descr *));
2932
2933         if (pmc_class_table == NULL)
2934                 return (-1);
2935
2936         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
2937                 pmc_class_table[n] = NULL;
2938
2939         /*
2940          * Get soft events list.
2941          */
2942         soft_event_info.pm_class = PMC_CLASS_SOFT;
2943         if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0)
2944                 return (pmc_syscall = -1);
2945
2946         /* Map soft events to static list. */
2947         for (n = 0; n < soft_event_info.pm_nevent; n++) {
2948                 soft_event_table[n].pm_ev_name =
2949                     soft_event_info.pm_events[n].pm_ev_name;
2950                 soft_event_table[n].pm_ev_code =
2951                     soft_event_info.pm_events[n].pm_ev_code;
2952         }
2953         soft_class_table_descr.pm_evc_event_table_size = \
2954             soft_event_info.pm_nevent;
2955         soft_class_table_descr.pm_evc_event_table = \
2956             soft_event_table;
2957
2958         /*
2959          * Fill in the class table.
2960          */
2961         n = 0;
2962
2963         /* Fill soft events information. */
2964         pmc_class_table[n++] = &soft_class_table_descr;
2965 #if defined(__amd64__) || defined(__i386__)
2966         if (cpu_info.pm_cputype != PMC_CPU_GENERIC)
2967                 pmc_class_table[n++] = &tsc_class_table_descr;
2968
2969         /*
2970          * Check if this CPU has fixed function counters.
2971          */
2972         cpu_has_iaf_counters = 0;
2973         for (t = 0; t < cpu_info.pm_nclass; t++)
2974                 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF &&
2975                     cpu_info.pm_classes[t].pm_num > 0)
2976                         cpu_has_iaf_counters = 1;
2977 #endif
2978
2979 #define PMC_MDEP_INIT(C) do {                                   \
2980                 pmc_mdep_event_aliases    = C##_aliases;        \
2981                 pmc_mdep_class_list  = C##_pmc_classes;         \
2982                 pmc_mdep_class_list_size =                      \
2983                     PMC_TABLE_SIZE(C##_pmc_classes);            \
2984         } while (0)
2985
2986 #define PMC_MDEP_INIT_INTEL_V2(C) do {                                  \
2987                 PMC_MDEP_INIT(C);                                       \
2988                 pmc_class_table[n++] = &iaf_class_table_descr;          \
2989                 if (!cpu_has_iaf_counters)                              \
2990                         pmc_mdep_event_aliases =                        \
2991                                 C##_aliases_without_iaf;                \
2992                 pmc_class_table[n] = &C##_class_table_descr;            \
2993         } while (0)
2994
2995         /* Configure the event name parser. */
2996         switch (cpu_info.pm_cputype) {
2997 #if defined(__i386__)
2998         case PMC_CPU_AMD_K7:
2999                 PMC_MDEP_INIT(k7);
3000                 pmc_class_table[n] = &k7_class_table_descr;
3001                 break;
3002         case PMC_CPU_INTEL_P5:
3003                 PMC_MDEP_INIT(p5);
3004                 pmc_class_table[n]  = &p5_class_table_descr;
3005                 break;
3006         case PMC_CPU_INTEL_P6:          /* P6 ... Pentium M CPUs have */
3007         case PMC_CPU_INTEL_PII:         /* similar PMCs. */
3008         case PMC_CPU_INTEL_PIII:
3009         case PMC_CPU_INTEL_PM:
3010                 PMC_MDEP_INIT(p6);
3011                 pmc_class_table[n] = &p6_class_table_descr;
3012                 break;
3013 #endif
3014 #if defined(__amd64__) || defined(__i386__)
3015         case PMC_CPU_AMD_K8:
3016                 PMC_MDEP_INIT(k8);
3017                 pmc_class_table[n] = &k8_class_table_descr;
3018                 break;
3019         case PMC_CPU_INTEL_ATOM:
3020                 PMC_MDEP_INIT_INTEL_V2(atom);
3021                 break;
3022         case PMC_CPU_INTEL_CORE:
3023                 PMC_MDEP_INIT(core);
3024                 pmc_class_table[n] = &core_class_table_descr;
3025                 break;
3026         case PMC_CPU_INTEL_CORE2:
3027         case PMC_CPU_INTEL_CORE2EXTREME:
3028                 PMC_MDEP_INIT_INTEL_V2(core2);
3029                 break;
3030         case PMC_CPU_INTEL_COREI7:
3031                 pmc_class_table[n++] = &ucf_class_table_descr;
3032                 pmc_class_table[n++] = &corei7uc_class_table_descr;
3033                 PMC_MDEP_INIT_INTEL_V2(corei7);
3034                 break;
3035         case PMC_CPU_INTEL_HASWELL:
3036                 pmc_class_table[n++] = &ucf_class_table_descr;
3037                 pmc_class_table[n++] = &haswelluc_class_table_descr;
3038                 PMC_MDEP_INIT_INTEL_V2(haswell);
3039                 break;
3040         case PMC_CPU_INTEL_IVYBRIDGE:
3041                 PMC_MDEP_INIT_INTEL_V2(ivybridge);
3042                 break;
3043         case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3044                 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon);
3045                 break;
3046         case PMC_CPU_INTEL_SANDYBRIDGE:
3047                 pmc_class_table[n++] = &ucf_class_table_descr;
3048                 pmc_class_table[n++] = &sandybridgeuc_class_table_descr;
3049                 PMC_MDEP_INIT_INTEL_V2(sandybridge);
3050                 break;
3051         case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
3052                 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon);
3053                 break;
3054         case PMC_CPU_INTEL_WESTMERE:
3055                 pmc_class_table[n++] = &ucf_class_table_descr;
3056                 pmc_class_table[n++] = &westmereuc_class_table_descr;
3057                 PMC_MDEP_INIT_INTEL_V2(westmere);
3058                 break;
3059         case PMC_CPU_INTEL_PIV:
3060                 PMC_MDEP_INIT(p4);
3061                 pmc_class_table[n] = &p4_class_table_descr;
3062                 break;
3063 #endif
3064         case PMC_CPU_GENERIC:
3065                 PMC_MDEP_INIT(generic);
3066                 break;
3067 #if defined(__XSCALE__)
3068         case PMC_CPU_INTEL_XSCALE:
3069                 PMC_MDEP_INIT(xscale);
3070                 pmc_class_table[n] = &xscale_class_table_descr;
3071                 break;
3072 #endif
3073 #if defined(__mips__)
3074         case PMC_CPU_MIPS_24K:
3075                 PMC_MDEP_INIT(mips24k);
3076                 pmc_class_table[n] = &mips24k_class_table_descr;
3077                 break;
3078 #endif /* __mips__ */
3079 #if defined(__powerpc__)
3080         case PMC_CPU_PPC_7450:
3081                 PMC_MDEP_INIT(ppc7450);
3082                 pmc_class_table[n] = &ppc7450_class_table_descr;
3083                 break;
3084 #endif
3085         default:
3086                 /*
3087                  * Some kind of CPU this version of the library knows nothing
3088                  * about.  This shouldn't happen since the abi version check
3089                  * should have caught this.
3090                  */
3091                 errno = ENXIO;
3092                 return (pmc_syscall = -1);
3093         }
3094
3095         return (0);
3096 }
3097
3098 const char *
3099 pmc_name_of_capability(enum pmc_caps cap)
3100 {
3101         int i;
3102
3103         /*
3104          * 'cap' should have a single bit set and should be in
3105          * range.
3106          */
3107         if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
3108             cap > PMC_CAP_LAST) {
3109                 errno = EINVAL;
3110                 return (NULL);
3111         }
3112
3113         i = ffs(cap);
3114         return (pmc_capability_names[i - 1]);
3115 }
3116
3117 const char *
3118 pmc_name_of_class(enum pmc_class pc)
3119 {
3120         if ((int) pc >= PMC_CLASS_FIRST &&
3121             pc <= PMC_CLASS_LAST)
3122                 return (pmc_class_names[pc]);
3123
3124         errno = EINVAL;
3125         return (NULL);
3126 }
3127
3128 const char *
3129 pmc_name_of_cputype(enum pmc_cputype cp)
3130 {
3131         size_t n;
3132
3133         for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
3134                 if (cp == pmc_cputype_names[n].pm_cputype)
3135                         return (pmc_cputype_names[n].pm_name);
3136
3137         errno = EINVAL;
3138         return (NULL);
3139 }
3140
3141 const char *
3142 pmc_name_of_disposition(enum pmc_disp pd)
3143 {
3144         if ((int) pd >= PMC_DISP_FIRST &&
3145             pd <= PMC_DISP_LAST)
3146                 return (pmc_disposition_names[pd]);
3147
3148         errno = EINVAL;
3149         return (NULL);
3150 }
3151
3152 const char *
3153 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
3154 {
3155         const struct pmc_event_descr *ev, *evfence;
3156
3157         ev = evfence = NULL;
3158         if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) {
3159                 ev = iaf_event_table;
3160                 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf);
3161         } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) {
3162                 switch (cpu) {
3163                 case PMC_CPU_INTEL_ATOM:
3164                         ev = atom_event_table;
3165                         evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom);
3166                         break;
3167                 case PMC_CPU_INTEL_CORE:
3168                         ev = core_event_table;
3169                         evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core);
3170                         break;
3171                 case PMC_CPU_INTEL_CORE2:
3172                 case PMC_CPU_INTEL_CORE2EXTREME:
3173                         ev = core2_event_table;
3174                         evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
3175                         break;
3176                 case PMC_CPU_INTEL_COREI7:
3177                         ev = corei7_event_table;
3178                         evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
3179                         break;
3180                 case PMC_CPU_INTEL_HASWELL:
3181                         ev = haswell_event_table;
3182                         evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell);
3183                         break;
3184                 case PMC_CPU_INTEL_IVYBRIDGE:
3185                         ev = ivybridge_event_table;
3186                         evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
3187                         break;
3188                 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3189                         ev = ivybridge_xeon_event_table;
3190                         evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
3191                         break;
3192                 case PMC_CPU_INTEL_SANDYBRIDGE:
3193                         ev = sandybridge_event_table;
3194                         evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge);
3195                         break;
3196                 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
3197                         ev = sandybridge_xeon_event_table;
3198                         evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
3199                         break;
3200                 case PMC_CPU_INTEL_WESTMERE:
3201                         ev = westmere_event_table;
3202                         evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
3203                         break;
3204                 default:        /* Unknown CPU type. */
3205                         break;
3206                 }
3207         } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) {
3208                 ev = ucf_event_table;
3209                 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf);
3210         } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) {
3211                 switch (cpu) {
3212                 case PMC_CPU_INTEL_COREI7:
3213                         ev = corei7uc_event_table;
3214                         evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
3215                         break;
3216                 case PMC_CPU_INTEL_SANDYBRIDGE:
3217                         ev = sandybridgeuc_event_table;
3218                         evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc);
3219                         break;
3220                 case PMC_CPU_INTEL_WESTMERE:
3221                         ev = westmereuc_event_table;
3222                         evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
3223                         break;
3224                 default:        /* Unknown CPU type. */
3225                         break;
3226                 }
3227         } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
3228                 ev = k7_event_table;
3229                 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
3230         } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
3231                 ev = k8_event_table;
3232                 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
3233         } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
3234                 ev = p4_event_table;
3235                 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
3236         } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
3237                 ev = p5_event_table;
3238                 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
3239         } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
3240                 ev = p6_event_table;
3241                 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6);
3242         } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) {
3243                 ev = xscale_event_table;
3244                 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale);
3245         } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
3246                 ev = mips24k_event_table;
3247                 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k);
3248         } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
3249                 ev = ppc7450_event_table;
3250                 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
3251         } else if (pe == PMC_EV_TSC_TSC) {
3252                 ev = tsc_event_table;
3253                 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
3254         } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) {
3255                 ev = soft_event_table;
3256                 evfence = soft_event_table + soft_event_info.pm_nevent;
3257         }
3258
3259         for (; ev != evfence; ev++)
3260                 if (pe == ev->pm_ev_code)
3261                         return (ev->pm_ev_name);
3262
3263         return (NULL);
3264 }
3265
3266 const char *
3267 pmc_name_of_event(enum pmc_event pe)
3268 {
3269         const char *n;
3270
3271         if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
3272                 return (n);
3273
3274         errno = EINVAL;
3275         return (NULL);
3276 }
3277
3278 const char *
3279 pmc_name_of_mode(enum pmc_mode pm)
3280 {
3281         if ((int) pm >= PMC_MODE_FIRST &&
3282             pm <= PMC_MODE_LAST)
3283                 return (pmc_mode_names[pm]);
3284
3285         errno = EINVAL;
3286         return (NULL);
3287 }
3288
3289 const char *
3290 pmc_name_of_state(enum pmc_state ps)
3291 {
3292         if ((int) ps >= PMC_STATE_FIRST &&
3293             ps <= PMC_STATE_LAST)
3294                 return (pmc_state_names[ps]);
3295
3296         errno = EINVAL;
3297         return (NULL);
3298 }
3299
3300 int
3301 pmc_ncpu(void)
3302 {
3303         if (pmc_syscall == -1) {
3304                 errno = ENXIO;
3305                 return (-1);
3306         }
3307
3308         return (cpu_info.pm_ncpu);
3309 }
3310
3311 int
3312 pmc_npmc(int cpu)
3313 {
3314         if (pmc_syscall == -1) {
3315                 errno = ENXIO;
3316                 return (-1);
3317         }
3318
3319         if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
3320                 errno = EINVAL;
3321                 return (-1);
3322         }
3323
3324         return (cpu_info.pm_npmc);
3325 }
3326
3327 int
3328 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
3329 {
3330         int nbytes, npmc;
3331         struct pmc_op_getpmcinfo *pmci;
3332
3333         if ((npmc = pmc_npmc(cpu)) < 0)
3334                 return (-1);
3335
3336         nbytes = sizeof(struct pmc_op_getpmcinfo) +
3337             npmc * sizeof(struct pmc_info);
3338
3339         if ((pmci = calloc(1, nbytes)) == NULL)
3340                 return (-1);
3341
3342         pmci->pm_cpu  = cpu;
3343
3344         if (PMC_CALL(GETPMCINFO, pmci) < 0) {
3345                 free(pmci);
3346                 return (-1);
3347         }
3348
3349         /* kernel<->library, library<->userland interfaces are identical */
3350         *ppmci = (struct pmc_pmcinfo *) pmci;
3351         return (0);
3352 }
3353
3354 int
3355 pmc_read(pmc_id_t pmc, pmc_value_t *value)
3356 {
3357         struct pmc_op_pmcrw pmc_read_op;
3358
3359         pmc_read_op.pm_pmcid = pmc;
3360         pmc_read_op.pm_flags = PMC_F_OLDVALUE;
3361         pmc_read_op.pm_value = -1;
3362
3363         if (PMC_CALL(PMCRW, &pmc_read_op) < 0)
3364                 return (-1);
3365
3366         *value = pmc_read_op.pm_value;
3367         return (0);
3368 }
3369
3370 int
3371 pmc_release(pmc_id_t pmc)
3372 {
3373         struct pmc_op_simple    pmc_release_args;
3374
3375         pmc_release_args.pm_pmcid = pmc;
3376         return (PMC_CALL(PMCRELEASE, &pmc_release_args));
3377 }
3378
3379 int
3380 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
3381 {
3382         struct pmc_op_pmcrw pmc_rw_op;
3383
3384         pmc_rw_op.pm_pmcid = pmc;
3385         pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
3386         pmc_rw_op.pm_value = newvalue;
3387
3388         if (PMC_CALL(PMCRW, &pmc_rw_op) < 0)
3389                 return (-1);
3390
3391         *oldvaluep = pmc_rw_op.pm_value;
3392         return (0);
3393 }
3394
3395 int
3396 pmc_set(pmc_id_t pmc, pmc_value_t value)
3397 {
3398         struct pmc_op_pmcsetcount sc;
3399
3400         sc.pm_pmcid = pmc;
3401         sc.pm_count = value;
3402
3403         if (PMC_CALL(PMCSETCOUNT, &sc) < 0)
3404                 return (-1);
3405         return (0);
3406 }
3407
3408 int
3409 pmc_start(pmc_id_t pmc)
3410 {
3411         struct pmc_op_simple    pmc_start_args;
3412
3413         pmc_start_args.pm_pmcid = pmc;
3414         return (PMC_CALL(PMCSTART, &pmc_start_args));
3415 }
3416
3417 int
3418 pmc_stop(pmc_id_t pmc)
3419 {
3420         struct pmc_op_simple    pmc_stop_args;
3421
3422         pmc_stop_args.pm_pmcid = pmc;
3423         return (PMC_CALL(PMCSTOP, &pmc_stop_args));
3424 }
3425
3426 int
3427 pmc_width(pmc_id_t pmcid, uint32_t *width)
3428 {
3429         unsigned int i;
3430         enum pmc_class cl;
3431
3432         cl = PMC_ID_TO_CLASS(pmcid);
3433         for (i = 0; i < cpu_info.pm_nclass; i++)
3434                 if (cpu_info.pm_classes[i].pm_class == cl) {
3435                         *width = cpu_info.pm_classes[i].pm_width;
3436                         return (0);
3437                 }
3438         errno = EINVAL;
3439         return (-1);
3440 }
3441
3442 int
3443 pmc_write(pmc_id_t pmc, pmc_value_t value)
3444 {
3445         struct pmc_op_pmcrw pmc_write_op;
3446
3447         pmc_write_op.pm_pmcid = pmc;
3448         pmc_write_op.pm_flags = PMC_F_NEWVALUE;
3449         pmc_write_op.pm_value = value;
3450         return (PMC_CALL(PMCRW, &pmc_write_op));
3451 }
3452
3453 int
3454 pmc_writelog(uint32_t userdata)
3455 {
3456         struct pmc_op_writelog wl;
3457
3458         wl.pm_userdata = userdata;
3459         return (PMC_CALL(WRITELOG, &wl));
3460 }