sys/amd64/amd64/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/systm.h>
  51 #include <sys/kernel.h>
  52 #include <sys/sysctl.h>
  53 #include <sys/power.h>
  54
  55 #include <machine/asmacros.h>
  56 #include <machine/clock.h>
  57 #include <machine/cputypes.h>
  58 #include <machine/frame.h>
  59 #include <machine/intr_machdep.h>
  60 #include <machine/segments.h>
  61 #include <machine/specialreg.h>
  62 #include <machine/md_var.h>
  63
  64 #include <x86/isa/icu.h>
  65
  66 /* XXX - should be in header file: */
  67 void printcpuinfo(void);
  68 void identify_cpu(void);
  69 void earlysetcpuclass(void);
  70 void panicifcpuunsupported(void);
  71
  72 static u_int find_cpu_vendor_id(void);
  73 static void print_AMD_info(void);
  74 static void print_AMD_assoc(int i);
  75 static void print_via_padlock_info(void);
  76
  77 int     cpu_class;
  78 char machine[] = "amd64";
  79
  80 #ifdef SCTL_MASK32
  81 extern int adaptive_machine_arch;
  82 #endif
  83
  84 static int
  85 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
  86 {
  87 #ifdef SCTL_MASK32
  88         static const char machine32[] = "i386";
  89 #endif
  90         int error;
  91
  92 #ifdef SCTL_MASK32
  93         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
  94                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
  95         else
  96 #endif
  97                 error = SYSCTL_OUT(req, machine, sizeof(machine));
  98         return (error);
  99
 100 }
 101 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
 102     NULL, 0, sysctl_hw_machine, "A", "Machine class");
 103
 104 static char cpu_model[128];
 105 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
 106     cpu_model, 0, "Machine model");
 107
 108 static int hw_clockrate;
 109 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 110     &hw_clockrate, 0, "CPU instruction clock rate");
 111
 112 static eventhandler_tag tsc_post_tag;
 113
 114 static char cpu_brand[48];
 115
 116 static struct {
 117         char    *cpu_name;
 118         int     cpu_class;
 119 } amd64_cpus[] = {
 120         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
 121         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
 122 };
 123
 124 static struct {
 125         char    *vendor;
 126         u_int   vendor_id;
 127 } cpu_vendors[] = {
 128         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 129         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 130         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 131 };
 132
 133
 134 void
 135 printcpuinfo(void)
 136 {
 137         u_int regs[4], i;
 138         char *brand;
 139
 140         cpu_class = amd64_cpus[cpu].cpu_class;
 141         printf("CPU: ");
 142         strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
 143
 144         /* Check for extended CPUID information and a processor name. */
 145         if (cpu_exthigh >= 0x80000004) {
 146                 brand = cpu_brand;
 147                 for (i = 0x80000002; i < 0x80000005; i++) {
 148                         do_cpuid(i, regs);
 149                         memcpy(brand, regs, sizeof(regs));
 150                         brand += sizeof(regs);
 151                 }
 152         }
 153
 154         switch (cpu_vendor_id) {
 155         case CPU_VENDOR_INTEL:
 156                 /* Please make up your mind folks! */
 157                 strcat(cpu_model, "EM64T");
 158                 break;
 159         case CPU_VENDOR_AMD:
 160                 /*
 161                  * Values taken from AMD Processor Recognition
 162                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 163                  * (also describes ``Features'' encodings.
 164                  */
 165                 strcpy(cpu_model, "AMD ");
 166                 if ((cpu_id & 0xf00) == 0xf00)
 167                         strcat(cpu_model, "AMD64 Processor");
 168                 else
 169                         strcat(cpu_model, "Unknown");
 170                 break;
 171         case CPU_VENDOR_CENTAUR:
 172                 strcpy(cpu_model, "VIA ");
 173                 if ((cpu_id & 0xff0) == 0x6f0)
 174                         strcat(cpu_model, "Nano Processor");
 175                 else
 176                         strcat(cpu_model, "Unknown");
 177                 break;
 178         default:
 179                 strcat(cpu_model, "Unknown");
 180                 break;
 181         }
 182
 183         /*
 184          * Replace cpu_model with cpu_brand minus leading spaces if
 185          * we have one.
 186          */
 187         brand = cpu_brand;
 188         while (*brand == ' ')
 189                 ++brand;
 190         if (*brand != '\0')
 191                 strcpy(cpu_model, brand);
 192
 193         printf("%s (", cpu_model);
 194         switch(cpu_class) {
 195         case CPUCLASS_K8:
 196                 if (tsc_freq != 0) {
 197                         hw_clockrate = (tsc_freq + 5000) / 1000000;
 198                         printf("%jd.%02d-MHz ",
 199                                (intmax_t)(tsc_freq + 4999) / 1000000,
 200                                (u_int)((tsc_freq + 4999) / 10000) % 100);
 201                 }
 202                 printf("K8");
 203                 break;
 204         default:
 205                 printf("Unknown");      /* will panic below... */
 206         }
 207         printf("-class CPU)\n");
 208         if (*cpu_vendor)
 209                 printf("  Origin = \"%s\"", cpu_vendor);
 210         if (cpu_id)
 211                 printf("  Id = 0x%x", cpu_id);
 212
 213         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 214             cpu_vendor_id == CPU_VENDOR_AMD ||
 215             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 216                 printf("  Family = 0x%x", CPUID_TO_FAMILY(cpu_id));
 217                 printf("  Model = 0x%x", CPUID_TO_MODEL(cpu_id));
 218                 printf("  Stepping = %u", cpu_id & CPUID_STEPPING);
 219
 220                 /*
 221                  * AMD CPUID Specification
 222                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 223                  *
 224                  * Intel Processor Identification and CPUID Instruction
 225                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 226                  */
 227                 if (cpu_high > 0) {
 228
 229                         /*
 230                          * Here we should probably set up flags indicating
 231                          * whether or not various features are available.
 232                          * The interesting ones are probably VME, PSE, PAE,
 233                          * and PGE.  The code already assumes without bothering
 234                          * to check that all CPUs >= Pentium have a TSC and
 235                          * MSRs.
 236                          */
 237                         printf("\n  Features=0x%b", cpu_feature,
 238                         "\020"
 239                         "\001FPU"       /* Integral FPU */
 240                         "\002VME"       /* Extended VM86 mode support */
 241                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 242                         "\004PSE"       /* 4MByte page tables */
 243                         "\005TSC"       /* Timestamp counter */
 244                         "\006MSR"       /* Machine specific registers */
 245                         "\007PAE"       /* Physical address extension */
 246                         "\010MCE"       /* Machine Check support */
 247                         "\011CX8"       /* CMPEXCH8 instruction */
 248                         "\012APIC"      /* SMP local APIC */
 249                         "\013oldMTRR"   /* Previous implementation of MTRR */
 250                         "\014SEP"       /* Fast System Call */
 251                         "\015MTRR"      /* Memory Type Range Registers */
 252                         "\016PGE"       /* PG_G (global bit) support */
 253                         "\017MCA"       /* Machine Check Architecture */
 254                         "\020CMOV"      /* CMOV instruction */
 255                         "\021PAT"       /* Page attributes table */
 256                         "\022PSE36"     /* 36 bit address space support */
 257                         "\023PN"        /* Processor Serial number */
 258                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 259                         "\025<b20>"
 260                         "\026DTS"       /* Debug Trace Store */
 261                         "\027ACPI"      /* ACPI support */
 262                         "\030MMX"       /* MMX instructions */
 263                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 264                         "\032SSE"       /* Streaming SIMD Extensions */
 265                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 266                         "\034SS"        /* Self snoop */
 267                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 268                         "\036TM"        /* Thermal Monitor clock slowdown */
 269                         "\037IA64"      /* CPU can execute IA64 instructions */
 270                         "\040PBE"       /* Pending Break Enable */
 271                         );
 272
 273                         if (cpu_feature2 != 0) {
 274                                 printf("\n  Features2=0x%b", cpu_feature2,
 275                                 "\020"
 276                                 "\001SSE3"      /* SSE3 */
 277                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 278                                 "\003DTES64"    /* 64-bit Debug Trace */
 279                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 280                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 281                                 "\006VMX"       /* Virtual Machine Extensions */
 282                                 "\007SMX"       /* Safer Mode Extensions */
 283                                 "\010EST"       /* Enhanced SpeedStep */
 284                                 "\011TM2"       /* Thermal Monitor 2 */
 285                                 "\012SSSE3"     /* SSSE3 */
 286                                 "\013CNXT-ID"   /* L1 context ID available */
 287                                 "\014<b11>"
 288                                 "\015FMA"       /* Fused Multiply Add */
 289                                 "\016CX16"      /* CMPXCHG16B Instruction */
 290                                 "\017xTPR"      /* Send Task Priority Messages*/
 291                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 292                                 "\021<b16>"
 293                                 "\022PCID"      /* Process-context Identifiers*/
 294                                 "\023DCA"       /* Direct Cache Access */
 295                                 "\024SSE4.1"    /* SSE 4.1 */
 296                                 "\025SSE4.2"    /* SSE 4.2 */
 297                                 "\026x2APIC"    /* xAPIC Extensions */
 298                                 "\027MOVBE"     /* MOVBE Instruction */
 299                                 "\030POPCNT"    /* POPCNT Instruction */
 300                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 301                                 "\032AESNI"     /* AES Crypto */
 302                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 303                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 304                                 "\035AVX"       /* Advanced Vector Extensions */
 305                                 "\036F16C"      /* Half-precision conversions */
 306                                 "\037RDRAND"    /* RDRAND Instruction */
 307                                 "\040HV"        /* Hypervisor */
 308                                 );
 309                         }
 310
 311                         if (amd_feature != 0) {
 312                                 printf("\n  AMD Features=0x%b", amd_feature,
 313                                 "\020"          /* in hex */
 314                                 "\001<s0>"      /* Same */
 315                                 "\002<s1>"      /* Same */
 316                                 "\003<s2>"      /* Same */
 317                                 "\004<s3>"      /* Same */
 318                                 "\005<s4>"      /* Same */
 319                                 "\006<s5>"      /* Same */
 320                                 "\007<s6>"      /* Same */
 321                                 "\010<s7>"      /* Same */
 322                                 "\011<s8>"      /* Same */
 323                                 "\012<s9>"      /* Same */
 324                                 "\013<b10>"     /* Undefined */
 325                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 326                                 "\015<s12>"     /* Same */
 327                                 "\016<s13>"     /* Same */
 328                                 "\017<s14>"     /* Same */
 329                                 "\020<s15>"     /* Same */
 330                                 "\021<s16>"     /* Same */
 331                                 "\022<s17>"     /* Same */
 332                                 "\023<b18>"     /* Reserved, unknown */
 333                                 "\024MP"        /* Multiprocessor Capable */
 334                                 "\025NX"        /* Has EFER.NXE, NX */
 335                                 "\026<b21>"     /* Undefined */
 336                                 "\027MMX+"      /* AMD MMX Extensions */
 337                                 "\030<s23>"     /* Same */
 338                                 "\031<s24>"     /* Same */
 339                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 340                                 "\033Page1GB"   /* 1-GB large page support */
 341                                 "\034RDTSCP"    /* RDTSCP */
 342                                 "\035<b28>"     /* Undefined */
 343                                 "\036LM"        /* 64 bit long mode */
 344                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 345                                 "\0403DNow!"    /* AMD 3DNow! */
 346                                 );
 347                         }
 348
 349                         if (amd_feature2 != 0) {
 350                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 351                                 "\020"
 352                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 353                                 "\002CMP"       /* CMP legacy */
 354                                 "\003SVM"       /* Secure Virtual Mode */
 355                                 "\004ExtAPIC"   /* Extended APIC register */
 356                                 "\005CR8"       /* CR8 in legacy mode */
 357                                 "\006ABM"       /* LZCNT instruction */
 358                                 "\007SSE4A"     /* SSE4A */
 359                                 "\010MAS"       /* Misaligned SSE mode */
 360                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 361                                 "\012OSVW"      /* OS visible workaround */
 362                                 "\013IBS"       /* Instruction based sampling */
 363                                 "\014XOP"       /* XOP extended instructions */
 364                                 "\015SKINIT"    /* SKINIT/STGI */
 365                                 "\016WDT"       /* Watchdog timer */
 366                                 "\017<b14>"
 367                                 "\020LWP"       /* Lightweight Profiling */
 368                                 "\021FMA4"      /* 4-operand FMA instructions */
 369                                 "\022<b17>"
 370                                 "\023<b18>"
 371                                 "\024NodeId"    /* NodeId MSR support */
 372                                 "\025<b20>"
 373                                 "\026TBM"       /* Trailing Bit Manipulation */
 374                                 "\027Topology"  /* Topology Extensions */
 375                                 "\030<b23>"
 376                                 "\031<b24>"
 377                                 "\032<b25>"
 378                                 "\033<b26>"
 379                                 "\034<b27>"
 380                                 "\035<b28>"
 381                                 "\036<b29>"
 382                                 "\037<b30>"
 383                                 "\040<b31>"
 384                                 );
 385                         }
 386
 387                         if (cpu_stdext_feature != 0) {
 388                                 printf("\n  Standard Extended Features=0x%b",
 389                                     cpu_stdext_feature,
 390                                        "\020"
 391                                        "\001GSFSBASE"
 392                                        "\002TSCADJ"
 393                                        "\010SMEP"
 394                                        "\012ENHMOVSB"
 395                                        "\013INVPCID"
 396                                        );
 397                         }
 398
 399                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
 400                                 print_via_padlock_info();
 401
 402                         if ((cpu_feature & CPUID_HTT) &&
 403                             cpu_vendor_id == CPU_VENDOR_AMD)
 404                                 cpu_feature &= ~CPUID_HTT;
 405
 406                         /*
 407                          * If this CPU supports P-state invariant TSC then
 408                          * mention the capability.
 409                          */
 410                         if (tsc_is_invariant) {
 411                                 printf("\n  TSC: P-state invariant");
 412                                 if (tsc_perf_stat)
 413                                         printf(", performance statistics");
 414                         }
 415
 416                 }
 417         }
 418         /* Avoid ugly blank lines: only print newline when we have to. */
 419         if (*cpu_vendor || cpu_id)
 420                 printf("\n");
 421
 422         if (!bootverbose)
 423                 return;
 424
 425         if (cpu_vendor_id == CPU_VENDOR_AMD)
 426                 print_AMD_info();
 427 }
 428
 429 void
 430 panicifcpuunsupported(void)
 431 {
 432
 433 #ifndef HAMMER
 434 #error "You need to specify a cpu type"
 435 #endif
 436         /*
 437          * Now that we have told the user what they have,
 438          * let them know if that machine type isn't configured.
 439          */
 440         switch (cpu_class) {
 441         case CPUCLASS_X86:
 442 #ifndef HAMMER
 443         case CPUCLASS_K8:
 444 #endif
 445                 panic("CPU class not configured");
 446         default:
 447                 break;
 448         }
 449 }
 450
 451
 452 /* Update TSC freq with the value indicated by the caller. */
 453 static void
 454 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
 455 {
 456
 457         /* If there was an error during the transition, don't do anything. */
 458         if (status != 0)
 459                 return;
 460
 461         /* Total setting for this level gives the new frequency in MHz. */
 462         hw_clockrate = level->total_set.freq;
 463 }
 464
 465 static void
 466 hook_tsc_freq(void *arg __unused)
 467 {
 468
 469         if (tsc_is_invariant)
 470                 return;
 471
 472         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
 473             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
 474 }
 475
 476 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
 477
 478 /*
 479  * Final stage of CPU identification.
 480  */
 481 void
 482 identify_cpu(void)
 483 {
 484         u_int regs[4], cpu_stdext_disable;
 485
 486         do_cpuid(0, regs);
 487         cpu_high = regs[0];
 488         ((u_int *)&cpu_vendor)[0] = regs[1];
 489         ((u_int *)&cpu_vendor)[1] = regs[3];
 490         ((u_int *)&cpu_vendor)[2] = regs[2];
 491         cpu_vendor[12] = '\0';
 492         cpu_vendor_id = find_cpu_vendor_id();
 493
 494         do_cpuid(1, regs);
 495         cpu_id = regs[0];
 496         cpu_procinfo = regs[1];
 497         cpu_feature = regs[3];
 498         cpu_feature2 = regs[2];
 499
 500         /*
 501          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
 502          * function number again if it is set from BIOS.  It is necessary
 503          * for probing correct CPU topology later.
 504          * XXX This is only done on the BSP package.
 505          */
 506         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) {
 507                 uint64_t msr;
 508                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
 509                 if ((msr & 0x400000ULL) != 0) {
 510                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
 511                         do_cpuid(0, regs);
 512                         cpu_high = regs[0];
 513                 }
 514         }
 515
 516         if (cpu_high >= 7) {
 517                 cpuid_count(7, 0, regs);
 518                 cpu_stdext_feature = regs[1];
 519
 520                 /*
 521                  * Some hypervisors fail to filter out unsupported
 522                  * extended features.  For now, disable the
 523                  * extensions, activation of which requires setting a
 524                  * bit in CR4, and which VM monitors do not support.
 525                  */
 526                 if (cpu_feature2 & CPUID2_HV) {
 527                         cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
 528                             CPUID_STDEXT_SMEP;
 529                 } else
 530                         cpu_stdext_disable = 0;
 531                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
 532                 cpu_stdext_feature &= ~cpu_stdext_disable;
 533         }
 534
 535         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 536             cpu_vendor_id == CPU_VENDOR_AMD ||
 537             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 538                 do_cpuid(0x80000000, regs);
 539                 cpu_exthigh = regs[0];
 540         }
 541         if (cpu_exthigh >= 0x80000001) {
 542                 do_cpuid(0x80000001, regs);
 543                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
 544                 amd_feature2 = regs[2];
 545         }
 546         if (cpu_exthigh >= 0x80000007) {
 547                 do_cpuid(0x80000007, regs);
 548                 amd_pminfo = regs[3];
 549         }
 550         if (cpu_exthigh >= 0x80000008) {
 551                 do_cpuid(0x80000008, regs);
 552                 cpu_procinfo2 = regs[2];
 553         }
 554
 555         /* XXX */
 556         cpu = CPU_CLAWHAMMER;
 557 }
 558
 559 static u_int
 560 find_cpu_vendor_id(void)
 561 {
 562         int     i;
 563
 564         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
 565                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
 566                         return (cpu_vendors[i].vendor_id);
 567         return (0);
 568 }
 569
 570 static void
 571 print_AMD_assoc(int i)
 572 {
 573         if (i == 255)
 574                 printf(", fully associative\n");
 575         else
 576                 printf(", %d-way associative\n", i);
 577 }
 578
 579 static void
 580 print_AMD_l2_assoc(int i)
 581 {
 582         switch (i & 0x0f) {
 583         case 0: printf(", disabled/not present\n"); break;
 584         case 1: printf(", direct mapped\n"); break;
 585         case 2: printf(", 2-way associative\n"); break;
 586         case 4: printf(", 4-way associative\n"); break;
 587         case 6: printf(", 8-way associative\n"); break;
 588         case 8: printf(", 16-way associative\n"); break;
 589         case 15: printf(", fully associative\n"); break;
 590         default: printf(", reserved configuration\n"); break;
 591         }
 592 }
 593
 594 static void
 595 print_AMD_info(void)
 596 {
 597         u_int regs[4];
 598
 599         if (cpu_exthigh < 0x80000005)
 600                 return;
 601
 602         do_cpuid(0x80000005, regs);
 603         printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
 604         print_AMD_assoc(regs[0] >> 24);
 605
 606         printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
 607         print_AMD_assoc((regs[0] >> 8) & 0xff);
 608
 609         printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
 610         print_AMD_assoc(regs[1] >> 24);
 611
 612         printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
 613         print_AMD_assoc((regs[1] >> 8) & 0xff);
 614
 615         printf("L1 data cache: %d kbytes", regs[2] >> 24);
 616         printf(", %d bytes/line", regs[2] & 0xff);
 617         printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
 618         print_AMD_assoc((regs[2] >> 16) & 0xff);
 619
 620         printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
 621         printf(", %d bytes/line", regs[3] & 0xff);
 622         printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
 623         print_AMD_assoc((regs[3] >> 16) & 0xff);
 624
 625         if (cpu_exthigh >= 0x80000006) {
 626                 do_cpuid(0x80000006, regs);
 627                 if ((regs[0] >> 16) != 0) {
 628                         printf("L2 2MB data TLB: %d entries",
 629                             (regs[0] >> 16) & 0xfff);
 630                         print_AMD_l2_assoc(regs[0] >> 28);
 631                         printf("L2 2MB instruction TLB: %d entries",
 632                             regs[0] & 0xfff);
 633                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
 634                 } else {
 635                         printf("L2 2MB unified TLB: %d entries",
 636                             regs[0] & 0xfff);
 637                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
 638                 }
 639                 if ((regs[1] >> 16) != 0) {
 640                         printf("L2 4KB data TLB: %d entries",
 641                             (regs[1] >> 16) & 0xfff);
 642                         print_AMD_l2_assoc(regs[1] >> 28);
 643
 644                         printf("L2 4KB instruction TLB: %d entries",
 645                             (regs[1] >> 16) & 0xfff);
 646                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
 647                 } else {
 648                         printf("L2 4KB unified TLB: %d entries",
 649                             (regs[1] >> 16) & 0xfff);
 650                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
 651                 }
 652                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
 653                 printf(", %d bytes/line", regs[2] & 0xff);
 654                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
 655                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
 656         }
 657
 658         /*
 659          * Opteron Rev E shows a bug as in very rare occasions a read memory
 660          * barrier is not performed as expected if it is followed by a
 661          * non-atomic read-modify-write instruction.
 662          * As long as that bug pops up very rarely (intensive machine usage
 663          * on other operating systems generally generates one unexplainable
 664          * crash any 2 months) and as long as a model specific fix would be
 665          * impratical at this stage, print out a warning string if the broken
 666          * model and family are identified.
 667          */
 668         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
 669             CPUID_TO_MODEL(cpu_id) <= 0x3f)
 670                 printf("WARNING: This architecture revision has known SMP "
 671                     "hardware bugs which may cause random instability\n");
 672 }
 673
 674 static void
 675 print_via_padlock_info(void)
 676 {
 677         u_int regs[4];
 678
 679         do_cpuid(0xc0000001, regs);
 680         printf("\n  VIA Padlock Features=0x%b", regs[3],
 681         "\020"
 682         "\003RNG"               /* RNG */
 683         "\007AES"               /* ACE */
 684         "\011AES-CTR"           /* ACE2 */
 685         "\013SHA1,SHA256"       /* PHE */
 686         "\015RSA"               /* PMM */
 687         );
 688 }