2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
83 * Manages physical address maps.
85 * In addition to hardware address maps, this
86 * module is called upon to provide software-use-only
87 * maps which may or may not be stored in the same
88 * form as hardware maps. These pseudo-maps are
89 * used to store intermediate results from copy
90 * operations to and from address spaces.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
108 #include "opt_pmap.h"
111 #include <sys/param.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/mutex.h>
120 #include <sys/proc.h>
121 #include <sys/rwlock.h>
123 #include <sys/vmmeter.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
129 #include <sys/cpuset.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_reserv.h>
144 #include <machine/intr_machdep.h>
145 #include <machine/apicvar.h>
146 #include <machine/cpu.h>
147 #include <machine/cputypes.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
150 #include <machine/specialreg.h>
152 #include <machine/smp.h>
155 #if !defined(DIAGNOSTIC)
156 #ifdef __GNUC_GNU_INLINE__
157 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
159 #define PMAP_INLINE extern inline
166 #define PV_STAT(x) do { x ; } while (0)
168 #define PV_STAT(x) do { } while (0)
171 #define pa_index(pa) ((pa) >> PDRSHIFT)
172 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
174 #define NPV_LIST_LOCKS MAXCPU
176 #define PHYS_TO_PV_LIST_LOCK(pa) \
177 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
179 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
180 struct rwlock **_lockp = (lockp); \
181 struct rwlock *_new_lock; \
183 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
184 if (_new_lock != *_lockp) { \
185 if (*_lockp != NULL) \
186 rw_wunlock(*_lockp); \
187 *_lockp = _new_lock; \
192 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
193 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
195 #define RELEASE_PV_LIST_LOCK(lockp) do { \
196 struct rwlock **_lockp = (lockp); \
198 if (*_lockp != NULL) { \
199 rw_wunlock(*_lockp); \
204 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
205 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
207 struct pmap kernel_pmap_store;
209 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
210 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
213 static vm_paddr_t dmaplimit;
214 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
217 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
219 static int pat_works = 1;
220 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
221 "Is page attribute table fully functional?");
223 static int pg_ps_enabled = 1;
224 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
225 "Are large page mappings enabled?");
227 #define PAT_INDEX_SIZE 8
228 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
230 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
231 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
232 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
233 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
235 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
236 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
239 * Isolate the global pv list lock from data and other locks to prevent false
240 * sharing within the cache.
244 char padding[CACHE_LINE_SIZE - sizeof(struct rwlock)];
245 } pvh_global __aligned(CACHE_LINE_SIZE);
247 #define pvh_global_lock pvh_global.lock
250 * Data for the pv entry allocation mechanism
252 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
253 static struct mtx pv_chunks_mutex;
254 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
255 static struct md_page *pv_table;
258 * All those kernel PT submaps that BSD is so fond of
260 pt_entry_t *CMAP1 = 0;
266 static caddr_t crashdumpmap;
268 static void free_pv_chunk(struct pv_chunk *pc);
269 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
270 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
271 static int popcnt_pc_map_elem(uint64_t elem);
272 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
273 static void reserve_pv_entries(pmap_t pmap, int needed,
274 struct rwlock **lockp);
275 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
276 struct rwlock **lockp);
277 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
278 struct rwlock **lockp);
279 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
280 struct rwlock **lockp);
281 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
282 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
284 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
286 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
287 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
288 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
289 vm_offset_t va, struct rwlock **lockp);
290 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
292 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
293 vm_prot_t prot, struct rwlock **lockp);
294 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
295 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
296 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
297 static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
298 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
299 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
300 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
301 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
302 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
303 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
304 struct rwlock **lockp);
305 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
307 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
308 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
309 vm_page_t *free, struct rwlock **lockp);
310 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq,
311 vm_offset_t sva, pd_entry_t ptepde, vm_page_t *free,
312 struct rwlock **lockp);
313 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
314 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
316 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
317 vm_page_t m, struct rwlock **lockp);
318 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
320 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
322 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
323 struct rwlock **lockp);
324 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
325 struct rwlock **lockp);
326 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
327 struct rwlock **lockp);
329 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
331 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, vm_page_t *);
332 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
334 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
335 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
338 * Move the kernel virtual free pointer to the next
339 * 2MB. This is used to help improve performance
340 * by using a large (2MB) page for much of the kernel
341 * (.text, .data, .bss)
344 pmap_kmem_choose(vm_offset_t addr)
346 vm_offset_t newaddr = addr;
348 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
352 /********************/
353 /* Inline functions */
354 /********************/
356 /* Return a non-clipped PD index for a given VA */
357 static __inline vm_pindex_t
358 pmap_pde_pindex(vm_offset_t va)
360 return (va >> PDRSHIFT);
364 /* Return various clipped indexes for a given VA */
365 static __inline vm_pindex_t
366 pmap_pte_index(vm_offset_t va)
369 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
372 static __inline vm_pindex_t
373 pmap_pde_index(vm_offset_t va)
376 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
379 static __inline vm_pindex_t
380 pmap_pdpe_index(vm_offset_t va)
383 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
386 static __inline vm_pindex_t
387 pmap_pml4e_index(vm_offset_t va)
390 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
393 /* Return a pointer to the PML4 slot that corresponds to a VA */
394 static __inline pml4_entry_t *
395 pmap_pml4e(pmap_t pmap, vm_offset_t va)
398 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
401 /* Return a pointer to the PDP slot that corresponds to a VA */
402 static __inline pdp_entry_t *
403 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
407 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
408 return (&pdpe[pmap_pdpe_index(va)]);
411 /* Return a pointer to the PDP slot that corresponds to a VA */
412 static __inline pdp_entry_t *
413 pmap_pdpe(pmap_t pmap, vm_offset_t va)
417 pml4e = pmap_pml4e(pmap, va);
418 if ((*pml4e & PG_V) == 0)
420 return (pmap_pml4e_to_pdpe(pml4e, va));
423 /* Return a pointer to the PD slot that corresponds to a VA */
424 static __inline pd_entry_t *
425 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
429 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
430 return (&pde[pmap_pde_index(va)]);
433 /* Return a pointer to the PD slot that corresponds to a VA */
434 static __inline pd_entry_t *
435 pmap_pde(pmap_t pmap, vm_offset_t va)
439 pdpe = pmap_pdpe(pmap, va);
440 if (pdpe == NULL || (*pdpe & PG_V) == 0)
442 return (pmap_pdpe_to_pde(pdpe, va));
445 /* Return a pointer to the PT slot that corresponds to a VA */
446 static __inline pt_entry_t *
447 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
451 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
452 return (&pte[pmap_pte_index(va)]);
455 /* Return a pointer to the PT slot that corresponds to a VA */
456 static __inline pt_entry_t *
457 pmap_pte(pmap_t pmap, vm_offset_t va)
461 pde = pmap_pde(pmap, va);
462 if (pde == NULL || (*pde & PG_V) == 0)
464 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
465 return ((pt_entry_t *)pde);
466 return (pmap_pde_to_pte(pde, va));
470 pmap_resident_count_inc(pmap_t pmap, int count)
473 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
474 pmap->pm_stats.resident_count += count;
478 pmap_resident_count_dec(pmap_t pmap, int count)
481 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
482 pmap->pm_stats.resident_count -= count;
485 PMAP_INLINE pt_entry_t *
486 vtopte(vm_offset_t va)
488 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
490 return (PTmap + ((va >> PAGE_SHIFT) & mask));
493 static __inline pd_entry_t *
494 vtopde(vm_offset_t va)
496 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
498 return (PDmap + ((va >> PDRSHIFT) & mask));
502 allocpages(vm_paddr_t *firstaddr, int n)
507 bzero((void *)ret, n * PAGE_SIZE);
508 *firstaddr += n * PAGE_SIZE;
512 CTASSERT(powerof2(NDMPML4E));
515 create_pagetables(vm_paddr_t *firstaddr)
520 KPTphys = allocpages(firstaddr, NKPT);
521 KPML4phys = allocpages(firstaddr, 1);
522 KPDPphys = allocpages(firstaddr, NKPML4E);
523 KPDphys = allocpages(firstaddr, NKPDPE);
525 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
526 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
528 DMPDPphys = allocpages(firstaddr, NDMPML4E);
530 if ((amd_feature & AMDID_PAGE1GB) != 0)
531 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
533 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
534 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
536 /* Fill in the underlying page table pages */
537 /* Read-only from zero to physfree */
538 /* XXX not fully used, underneath 2M pages */
539 for (i = 0; (i << PAGE_SHIFT) < *firstaddr; i++) {
540 ((pt_entry_t *)KPTphys)[i] = i << PAGE_SHIFT;
541 ((pt_entry_t *)KPTphys)[i] |= PG_RW | PG_V | PG_G;
544 /* Now map the page tables at their location within PTmap */
545 for (i = 0; i < NKPT; i++) {
546 ((pd_entry_t *)KPDphys)[i] = KPTphys + (i << PAGE_SHIFT);
547 ((pd_entry_t *)KPDphys)[i] |= PG_RW | PG_V;
550 /* Map from zero to end of allocations under 2M pages */
551 /* This replaces some of the KPTphys entries above */
552 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++) {
553 ((pd_entry_t *)KPDphys)[i] = i << PDRSHIFT;
554 ((pd_entry_t *)KPDphys)[i] |= PG_RW | PG_V | PG_PS | PG_G;
557 /* And connect up the PD to the PDP */
558 for (i = 0; i < NKPDPE; i++) {
559 ((pdp_entry_t *)KPDPphys)[i + KPDPI] = KPDphys +
561 ((pdp_entry_t *)KPDPphys)[i + KPDPI] |= PG_RW | PG_V | PG_U;
565 * Now, set up the direct map region using 2MB and/or 1GB pages. If
566 * the end of physical memory is not aligned to a 1GB page boundary,
567 * then the residual physical memory is mapped with 2MB pages. Later,
568 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
569 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
570 * that are partially used.
572 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
573 ((pd_entry_t *)DMPDphys)[j] = (vm_paddr_t)i << PDRSHIFT;
574 /* Preset PG_M and PG_A because demotion expects it. */
575 ((pd_entry_t *)DMPDphys)[j] |= PG_RW | PG_V | PG_PS | PG_G |
578 for (i = 0; i < ndm1g; i++) {
579 ((pdp_entry_t *)DMPDPphys)[i] = (vm_paddr_t)i << PDPSHIFT;
580 /* Preset PG_M and PG_A because demotion expects it. */
581 ((pdp_entry_t *)DMPDPphys)[i] |= PG_RW | PG_V | PG_PS | PG_G |
584 for (j = 0; i < ndmpdp; i++, j++) {
585 ((pdp_entry_t *)DMPDPphys)[i] = DMPDphys + (j << PAGE_SHIFT);
586 ((pdp_entry_t *)DMPDPphys)[i] |= PG_RW | PG_V | PG_U;
589 /* And recursively map PML4 to itself in order to get PTmap */
590 ((pdp_entry_t *)KPML4phys)[PML4PML4I] = KPML4phys;
591 ((pdp_entry_t *)KPML4phys)[PML4PML4I] |= PG_RW | PG_V | PG_U;
593 /* Connect the Direct Map slot(s) up to the PML4. */
594 for (i = 0; i < NDMPML4E; i++) {
595 ((pdp_entry_t *)KPML4phys)[DMPML4I + i] = DMPDPphys +
597 ((pdp_entry_t *)KPML4phys)[DMPML4I + i] |= PG_RW | PG_V | PG_U;
600 /* Connect the KVA slot up to the PML4 */
601 ((pdp_entry_t *)KPML4phys)[KPML4I] = KPDPphys;
602 ((pdp_entry_t *)KPML4phys)[KPML4I] |= PG_RW | PG_V | PG_U;
606 * Bootstrap the system enough to run with virtual memory.
608 * On amd64 this is called after mapping has already been enabled
609 * and just syncs the pmap module with what has already been done.
610 * [We can't call it easily with mapping off since the kernel is not
611 * mapped with PA == VA, hence we would have to relocate every address
612 * from the linked base (virtual) address "KERNBASE" to the actual
613 * (physical) address starting relative to 0]
616 pmap_bootstrap(vm_paddr_t *firstaddr)
619 pt_entry_t *pte, *unused;
622 * Create an initial set of page tables to run the kernel in.
624 create_pagetables(firstaddr);
626 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
627 virtual_avail = pmap_kmem_choose(virtual_avail);
629 virtual_end = VM_MAX_KERNEL_ADDRESS;
632 /* XXX do %cr0 as well */
633 load_cr4(rcr4() | CR4_PGE | CR4_PSE);
635 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
636 load_cr4(rcr4() | CR4_SMEP);
639 * Initialize the kernel pmap (which is statically allocated).
641 PMAP_LOCK_INIT(kernel_pmap);
642 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
643 kernel_pmap->pm_root = NULL;
644 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
645 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
648 * Initialize the global pv list lock.
650 rw_init(&pvh_global_lock, "pmap pv global");
653 * Reserve some special page table entries/VA space for temporary
656 #define SYSMAP(c, p, v, n) \
657 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
663 * CMAP1 is only used for the memory test.
665 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
670 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
674 /* Initialize the PAT MSR. */
684 int pat_table[PAT_INDEX_SIZE];
689 /* Bail if this CPU doesn't implement PAT. */
690 if ((cpu_feature & CPUID_PAT) == 0)
693 /* Set default PAT index table. */
694 for (i = 0; i < PAT_INDEX_SIZE; i++)
696 pat_table[PAT_WRITE_BACK] = 0;
697 pat_table[PAT_WRITE_THROUGH] = 1;
698 pat_table[PAT_UNCACHEABLE] = 3;
699 pat_table[PAT_WRITE_COMBINING] = 3;
700 pat_table[PAT_WRITE_PROTECTED] = 3;
701 pat_table[PAT_UNCACHED] = 3;
703 /* Initialize default PAT entries. */
704 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
705 PAT_VALUE(1, PAT_WRITE_THROUGH) |
706 PAT_VALUE(2, PAT_UNCACHED) |
707 PAT_VALUE(3, PAT_UNCACHEABLE) |
708 PAT_VALUE(4, PAT_WRITE_BACK) |
709 PAT_VALUE(5, PAT_WRITE_THROUGH) |
710 PAT_VALUE(6, PAT_UNCACHED) |
711 PAT_VALUE(7, PAT_UNCACHEABLE);
715 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
716 * Program 5 and 6 as WP and WC.
717 * Leave 4 and 7 as WB and UC.
719 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
720 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
721 PAT_VALUE(6, PAT_WRITE_COMBINING);
722 pat_table[PAT_UNCACHED] = 2;
723 pat_table[PAT_WRITE_PROTECTED] = 5;
724 pat_table[PAT_WRITE_COMBINING] = 6;
727 * Just replace PAT Index 2 with WC instead of UC-.
729 pat_msr &= ~PAT_MASK(2);
730 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
731 pat_table[PAT_WRITE_COMBINING] = 2;
736 load_cr4(cr4 & ~CR4_PGE);
738 /* Disable caches (CD = 1, NW = 0). */
740 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
742 /* Flushes caches and TLBs. */
746 /* Update PAT and index table. */
747 wrmsr(MSR_PAT, pat_msr);
748 for (i = 0; i < PAT_INDEX_SIZE; i++)
749 pat_index[i] = pat_table[i];
751 /* Flush caches and TLBs again. */
755 /* Restore caches and PGE. */
761 * Initialize a vm_page's machine-dependent fields.
764 pmap_page_init(vm_page_t m)
767 TAILQ_INIT(&m->md.pv_list);
768 m->md.pat_mode = PAT_WRITE_BACK;
772 * Initialize the pmap module.
773 * Called by vm_init, to initialize any structures that the pmap
774 * system needs to map virtual memory.
784 * Initialize the vm page array entries for the kernel pmap's
787 for (i = 0; i < NKPT; i++) {
788 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
789 KASSERT(mpte >= vm_page_array &&
790 mpte < &vm_page_array[vm_page_array_size],
791 ("pmap_init: page table page is out of range"));
792 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
793 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
797 * If the kernel is running in a virtual machine on an AMD Family 10h
798 * processor, then it must assume that MCA is enabled by the virtual
801 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
802 CPUID_TO_FAMILY(cpu_id) == 0x10)
803 workaround_erratum383 = 1;
806 * Are large page mappings enabled?
808 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
810 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
811 ("pmap_init: can't assign to pagesizes[1]"));
812 pagesizes[1] = NBPDR;
816 * Initialize the pv chunk list mutex.
818 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
821 * Initialize the pool of pv list locks.
823 for (i = 0; i < NPV_LIST_LOCKS; i++)
824 rw_init(&pv_list_locks[i], "pmap pv list");
827 * Calculate the size of the pv head table for superpages.
829 for (i = 0; phys_avail[i + 1]; i += 2);
830 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR;
833 * Allocate memory for the pv head table for superpages.
835 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
837 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
838 for (i = 0; i < pv_npg; i++)
839 TAILQ_INIT(&pv_table[i].pv_list);
842 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
843 "2MB page mapping counters");
845 static u_long pmap_pde_demotions;
846 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
847 &pmap_pde_demotions, 0, "2MB page demotions");
849 static u_long pmap_pde_mappings;
850 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
851 &pmap_pde_mappings, 0, "2MB page mappings");
853 static u_long pmap_pde_p_failures;
854 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
855 &pmap_pde_p_failures, 0, "2MB page promotion failures");
857 static u_long pmap_pde_promotions;
858 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
859 &pmap_pde_promotions, 0, "2MB page promotions");
861 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
862 "1GB page mapping counters");
864 static u_long pmap_pdpe_demotions;
865 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
866 &pmap_pdpe_demotions, 0, "1GB page demotions");
868 /***************************************************
869 * Low level helper routines.....
870 ***************************************************/
873 * Determine the appropriate bits to set in a PTE or PDE for a specified
877 pmap_cache_bits(int mode, boolean_t is_pde)
879 int cache_bits, pat_flag, pat_idx;
881 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
882 panic("Unknown caching mode %d\n", mode);
884 /* The PAT bit is different for PTE's and PDE's. */
885 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
887 /* Map the caching mode to a PAT index. */
888 pat_idx = pat_index[mode];
890 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
893 cache_bits |= pat_flag;
895 cache_bits |= PG_NC_PCD;
897 cache_bits |= PG_NC_PWT;
902 * After changing the page size for the specified virtual address in the page
903 * table, flush the corresponding entries from the processor's TLB. Only the
904 * calling processor's TLB is affected.
906 * The calling thread must be pinned to a processor.
909 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
913 if ((newpde & PG_PS) == 0)
914 /* Demotion: flush a specific 2MB page mapping. */
916 else if ((newpde & PG_G) == 0)
918 * Promotion: flush every 4KB page mapping from the TLB
919 * because there are too many to flush individually.
924 * Promotion: flush every 4KB page mapping from the TLB,
925 * including any global (PG_G) mappings.
928 load_cr4(cr4 & ~CR4_PGE);
930 * Although preemption at this point could be detrimental to
931 * performance, it would not lead to an error. PG_G is simply
932 * ignored if CR4.PGE is clear. Moreover, in case this block
933 * is re-entered, the load_cr4() either above or below will
934 * modify CR4.PGE flushing the TLB.
936 load_cr4(cr4 | CR4_PGE);
941 * For SMP, these functions have to use the IPI mechanism for coherence.
943 * N.B.: Before calling any of the following TLB invalidation functions,
944 * the calling processor must ensure that all stores updating a non-
945 * kernel page table are globally performed. Otherwise, another
946 * processor could cache an old, pre-update entry without being
947 * invalidated. This can happen one of two ways: (1) The pmap becomes
948 * active on another processor after its pm_active field is checked by
949 * one of the following functions but before a store updating the page
950 * table is globally performed. (2) The pmap becomes active on another
951 * processor before its pm_active field is checked but due to
952 * speculative loads one of the following functions stills reads the
953 * pmap as inactive on the other processor.
955 * The kernel page table is exempt because its pm_active field is
956 * immutable. The kernel page table is always active on every
960 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
966 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
970 cpuid = PCPU_GET(cpuid);
971 other_cpus = all_cpus;
972 CPU_CLR(cpuid, &other_cpus);
973 if (CPU_ISSET(cpuid, &pmap->pm_active))
975 CPU_AND(&other_cpus, &pmap->pm_active);
976 if (!CPU_EMPTY(&other_cpus))
977 smp_masked_invlpg(other_cpus, va);
983 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
990 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
991 for (addr = sva; addr < eva; addr += PAGE_SIZE)
993 smp_invlpg_range(sva, eva);
995 cpuid = PCPU_GET(cpuid);
996 other_cpus = all_cpus;
997 CPU_CLR(cpuid, &other_cpus);
998 if (CPU_ISSET(cpuid, &pmap->pm_active))
999 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1001 CPU_AND(&other_cpus, &pmap->pm_active);
1002 if (!CPU_EMPTY(&other_cpus))
1003 smp_masked_invlpg_range(other_cpus, sva, eva);
1009 pmap_invalidate_all(pmap_t pmap)
1011 cpuset_t other_cpus;
1015 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1019 cpuid = PCPU_GET(cpuid);
1020 other_cpus = all_cpus;
1021 CPU_CLR(cpuid, &other_cpus);
1022 if (CPU_ISSET(cpuid, &pmap->pm_active))
1024 CPU_AND(&other_cpus, &pmap->pm_active);
1025 if (!CPU_EMPTY(&other_cpus))
1026 smp_masked_invltlb(other_cpus);
1032 pmap_invalidate_cache(void)
1042 cpuset_t invalidate; /* processors that invalidate their TLB */
1046 u_int store; /* processor that updates the PDE */
1050 pmap_update_pde_action(void *arg)
1052 struct pde_action *act = arg;
1054 if (act->store == PCPU_GET(cpuid))
1055 pde_store(act->pde, act->newpde);
1059 pmap_update_pde_teardown(void *arg)
1061 struct pde_action *act = arg;
1063 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1064 pmap_update_pde_invalidate(act->va, act->newpde);
1068 * Change the page size for the specified virtual address in a way that
1069 * prevents any possibility of the TLB ever having two entries that map the
1070 * same virtual address using different page sizes. This is the recommended
1071 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1072 * machine check exception for a TLB state that is improperly diagnosed as a
1076 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1078 struct pde_action act;
1079 cpuset_t active, other_cpus;
1083 cpuid = PCPU_GET(cpuid);
1084 other_cpus = all_cpus;
1085 CPU_CLR(cpuid, &other_cpus);
1086 if (pmap == kernel_pmap)
1089 active = pmap->pm_active;
1090 if (CPU_OVERLAP(&active, &other_cpus)) {
1092 act.invalidate = active;
1095 act.newpde = newpde;
1096 CPU_SET(cpuid, &active);
1097 smp_rendezvous_cpus(active,
1098 smp_no_rendevous_barrier, pmap_update_pde_action,
1099 pmap_update_pde_teardown, &act);
1101 pde_store(pde, newpde);
1102 if (CPU_ISSET(cpuid, &active))
1103 pmap_update_pde_invalidate(va, newpde);
1109 * Normal, non-SMP, invalidation functions.
1110 * We inline these within pmap.c for speed.
1113 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1116 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1121 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1125 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1126 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1131 pmap_invalidate_all(pmap_t pmap)
1134 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1139 pmap_invalidate_cache(void)
1146 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1149 pde_store(pde, newpde);
1150 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1151 pmap_update_pde_invalidate(va, newpde);
1155 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1158 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1161 KASSERT((sva & PAGE_MASK) == 0,
1162 ("pmap_invalidate_cache_range: sva not page-aligned"));
1163 KASSERT((eva & PAGE_MASK) == 0,
1164 ("pmap_invalidate_cache_range: eva not page-aligned"));
1166 if (cpu_feature & CPUID_SS)
1167 ; /* If "Self Snoop" is supported, do nothing. */
1168 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1169 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1172 * XXX: Some CPUs fault, hang, or trash the local APIC
1173 * registers if we use CLFLUSH on the local APIC
1174 * range. The local APIC is always uncached, so we
1175 * don't need to flush for that range anyway.
1177 if (pmap_kextract(sva) == lapic_paddr)
1181 * Otherwise, do per-cache line flush. Use the mfence
1182 * instruction to insure that previous stores are
1183 * included in the write-back. The processor
1184 * propagates flush to other processors in the cache
1188 for (; sva < eva; sva += cpu_clflush_line_size)
1194 * No targeted cache flush methods are supported by CPU,
1195 * or the supplied range is bigger than 2MB.
1196 * Globally invalidate cache.
1198 pmap_invalidate_cache();
1203 * Remove the specified set of pages from the data and instruction caches.
1205 * In contrast to pmap_invalidate_cache_range(), this function does not
1206 * rely on the CPU's self-snoop feature, because it is intended for use
1207 * when moving pages into a different cache domain.
1210 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1212 vm_offset_t daddr, eva;
1215 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1216 (cpu_feature & CPUID_CLFSH) == 0)
1217 pmap_invalidate_cache();
1220 for (i = 0; i < count; i++) {
1221 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1222 eva = daddr + PAGE_SIZE;
1223 for (; daddr < eva; daddr += cpu_clflush_line_size)
1231 * Are we current address space or kernel?
1234 pmap_is_current(pmap_t pmap)
1236 return (pmap == kernel_pmap ||
1237 (pmap->pm_pml4[PML4PML4I] & PG_FRAME) == (PML4pml4e[0] & PG_FRAME));
1241 * Routine: pmap_extract
1243 * Extract the physical page address associated
1244 * with the given map/virtual_address pair.
1247 pmap_extract(pmap_t pmap, vm_offset_t va)
1256 pdpe = pmap_pdpe(pmap, va);
1257 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1258 if ((*pdpe & PG_PS) != 0)
1259 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1261 pde = pmap_pdpe_to_pde(pdpe, va);
1262 if ((*pde & PG_V) != 0) {
1263 if ((*pde & PG_PS) != 0) {
1264 pa = (*pde & PG_PS_FRAME) |
1267 pte = pmap_pde_to_pte(pde, va);
1268 pa = (*pte & PG_FRAME) |
1279 * Routine: pmap_extract_and_hold
1281 * Atomically extract and hold the physical page
1282 * with the given pmap and virtual address pair
1283 * if that mapping permits the given protection.
1286 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1288 pd_entry_t pde, *pdep;
1297 pdep = pmap_pde(pmap, va);
1298 if (pdep != NULL && (pde = *pdep)) {
1300 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1301 if (vm_page_pa_tryrelock(pmap, (pde &
1302 PG_PS_FRAME) | (va & PDRMASK), &pa))
1304 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1309 pte = *pmap_pde_to_pte(pdep, va);
1311 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1312 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1315 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1326 pmap_kextract(vm_offset_t va)
1331 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1332 pa = DMAP_TO_PHYS(va);
1336 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1339 * Beware of a concurrent promotion that changes the
1340 * PDE at this point! For example, vtopte() must not
1341 * be used to access the PTE because it would use the
1342 * new PDE. It is, however, safe to use the old PDE
1343 * because the page table page is preserved by the
1346 pa = *pmap_pde_to_pte(&pde, va);
1347 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1353 /***************************************************
1354 * Low level mapping routines.....
1355 ***************************************************/
1358 * Add a wired page to the kva.
1359 * Note: not SMP coherent.
1362 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1367 pte_store(pte, pa | PG_RW | PG_V | PG_G);
1370 static __inline void
1371 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1376 pte_store(pte, pa | PG_RW | PG_V | PG_G | pmap_cache_bits(mode, 0));
1380 * Remove a page from the kernel pagetables.
1381 * Note: not SMP coherent.
1384 pmap_kremove(vm_offset_t va)
1393 * Used to map a range of physical addresses into kernel
1394 * virtual address space.
1396 * The value passed in '*virt' is a suggested virtual address for
1397 * the mapping. Architectures which can support a direct-mapped
1398 * physical to virtual region can return the appropriate address
1399 * within that region, leaving '*virt' unchanged. Other
1400 * architectures should map the pages starting at '*virt' and
1401 * update '*virt' with the first usable address after the mapped
1405 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1407 return PHYS_TO_DMAP(start);
1412 * Add a list of wired pages to the kva
1413 * this routine is only used for temporary
1414 * kernel mappings that do not need to have
1415 * page modification or references recorded.
1416 * Note that old mappings are simply written
1417 * over. The page *must* be wired.
1418 * Note: SMP coherent. Uses a ranged shootdown IPI.
1421 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1423 pt_entry_t *endpte, oldpte, pa, *pte;
1428 endpte = pte + count;
1429 while (pte < endpte) {
1431 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1432 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1434 pte_store(pte, pa | PG_G | PG_RW | PG_V);
1438 if (__predict_false((oldpte & PG_V) != 0))
1439 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1444 * This routine tears out page mappings from the
1445 * kernel -- it is meant only for temporary mappings.
1446 * Note: SMP coherent. Uses a ranged shootdown IPI.
1449 pmap_qremove(vm_offset_t sva, int count)
1454 while (count-- > 0) {
1455 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
1459 pmap_invalidate_range(kernel_pmap, sva, va);
1462 /***************************************************
1463 * Page table page management routines.....
1464 ***************************************************/
1465 static __inline void
1466 pmap_free_zero_pages(vm_page_t free)
1470 while (free != NULL) {
1473 /* Preserve the page's PG_ZERO setting. */
1474 vm_page_free_toq(m);
1479 * Schedule the specified unused page table page to be freed. Specifically,
1480 * add the page to the specified list of pages that will be released to the
1481 * physical memory manager after the TLB has been updated.
1483 static __inline void
1484 pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO)
1488 m->flags |= PG_ZERO;
1490 m->flags &= ~PG_ZERO;
1496 * Inserts the specified page table page into the specified pmap's collection
1497 * of idle page table pages. Each of a pmap's page table pages is responsible
1498 * for mapping a distinct range of virtual addresses. The pmap's collection is
1499 * ordered by this virtual address range.
1502 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1506 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1507 root = pmap->pm_root;
1512 root = vm_page_splay(mpte->pindex, root);
1513 if (mpte->pindex < root->pindex) {
1514 mpte->left = root->left;
1517 } else if (mpte->pindex == root->pindex)
1518 panic("pmap_insert_pt_page: pindex already inserted");
1520 mpte->right = root->right;
1525 pmap->pm_root = mpte;
1529 * Looks for a page table page mapping the specified virtual address in the
1530 * specified pmap's collection of idle page table pages. Returns NULL if there
1531 * is no page table page corresponding to the specified virtual address.
1534 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1537 vm_pindex_t pindex = pmap_pde_pindex(va);
1539 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1540 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) {
1541 mpte = vm_page_splay(pindex, mpte);
1542 if ((pmap->pm_root = mpte)->pindex != pindex)
1549 * Removes the specified page table page from the specified pmap's collection
1550 * of idle page table pages. The specified page table page must be a member of
1551 * the pmap's collection.
1554 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1558 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1559 if (mpte != pmap->pm_root) {
1560 root = vm_page_splay(mpte->pindex, pmap->pm_root);
1561 KASSERT(mpte == root,
1562 ("pmap_remove_pt_page: mpte %p is missing from pmap %p",
1565 if (mpte->left == NULL)
1568 root = vm_page_splay(mpte->pindex, mpte->left);
1569 root->right = mpte->right;
1571 pmap->pm_root = root;
1575 * Decrements a page table page's wire count, which is used to record the
1576 * number of valid page table entries within the page. If the wire count
1577 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1578 * page table page was unmapped and FALSE otherwise.
1580 static inline boolean_t
1581 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_page_t *free)
1585 if (m->wire_count == 0) {
1586 _pmap_unwire_ptp(pmap, va, m, free);
1593 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_page_t *free)
1596 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1598 * unmap the page table page
1600 if (m->pindex >= (NUPDE + NUPDPE)) {
1603 pml4 = pmap_pml4e(pmap, va);
1605 } else if (m->pindex >= NUPDE) {
1608 pdp = pmap_pdpe(pmap, va);
1613 pd = pmap_pde(pmap, va);
1616 pmap_resident_count_dec(pmap, 1);
1617 if (m->pindex < NUPDE) {
1618 /* We just released a PT, unhold the matching PD */
1621 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
1622 pmap_unwire_ptp(pmap, va, pdpg, free);
1624 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
1625 /* We just released a PD, unhold the matching PDP */
1628 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
1629 pmap_unwire_ptp(pmap, va, pdppg, free);
1633 * This is a release store so that the ordinary store unmapping
1634 * the page table page is globally performed before TLB shoot-
1637 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1640 * Put page on a list so that it is released after
1641 * *ALL* TLB shootdown is done
1643 pmap_add_delayed_free_list(m, free, TRUE);
1647 * After removing a page table entry, this routine is used to
1648 * conditionally free the page, and manage the hold/wire counts.
1651 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, vm_page_t *free)
1655 if (va >= VM_MAXUSER_ADDRESS)
1657 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1658 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1659 return (pmap_unwire_ptp(pmap, va, mpte, free));
1663 pmap_pinit0(pmap_t pmap)
1666 PMAP_LOCK_INIT(pmap);
1667 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1668 pmap->pm_root = NULL;
1669 CPU_ZERO(&pmap->pm_active);
1670 PCPU_SET(curpmap, pmap);
1671 TAILQ_INIT(&pmap->pm_pvchunk);
1672 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1676 * Initialize a preallocated and zeroed pmap structure,
1677 * such as one in a vmspace structure.
1680 pmap_pinit(pmap_t pmap)
1685 PMAP_LOCK_INIT(pmap);
1688 * allocate the page directory page
1690 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1691 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1694 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
1696 if ((pml4pg->flags & PG_ZERO) == 0)
1697 pagezero(pmap->pm_pml4);
1699 /* Wire in kernel global address entries. */
1700 pmap->pm_pml4[KPML4I] = KPDPphys | PG_RW | PG_V | PG_U;
1701 for (i = 0; i < NDMPML4E; i++) {
1702 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + (i << PAGE_SHIFT)) |
1703 PG_RW | PG_V | PG_U;
1706 /* install self-referential address mapping entry(s) */
1707 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | PG_V | PG_RW | PG_A | PG_M;
1709 pmap->pm_root = NULL;
1710 CPU_ZERO(&pmap->pm_active);
1711 TAILQ_INIT(&pmap->pm_pvchunk);
1712 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1718 * This routine is called if the desired page table page does not exist.
1720 * If page table page allocation fails, this routine may sleep before
1721 * returning NULL. It sleeps only if a lock pointer was given.
1723 * Note: If a page allocation fails at page table level two or three,
1724 * one or two pages may be held during the wait, only to be released
1725 * afterwards. This conservative approach is easily argued to avoid
1729 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1731 vm_page_t m, pdppg, pdpg;
1733 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1736 * Allocate a page table page.
1738 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1739 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1740 if (lockp != NULL) {
1741 RELEASE_PV_LIST_LOCK(lockp);
1743 rw_runlock(&pvh_global_lock);
1745 rw_rlock(&pvh_global_lock);
1750 * Indicate the need to retry. While waiting, the page table
1751 * page may have been allocated.
1755 if ((m->flags & PG_ZERO) == 0)
1759 * Map the pagetable page into the process address space, if
1760 * it isn't already there.
1763 if (ptepindex >= (NUPDE + NUPDPE)) {
1765 vm_pindex_t pml4index;
1767 /* Wire up a new PDPE page */
1768 pml4index = ptepindex - (NUPDE + NUPDPE);
1769 pml4 = &pmap->pm_pml4[pml4index];
1770 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1772 } else if (ptepindex >= NUPDE) {
1773 vm_pindex_t pml4index;
1774 vm_pindex_t pdpindex;
1778 /* Wire up a new PDE page */
1779 pdpindex = ptepindex - NUPDE;
1780 pml4index = pdpindex >> NPML4EPGSHIFT;
1782 pml4 = &pmap->pm_pml4[pml4index];
1783 if ((*pml4 & PG_V) == 0) {
1784 /* Have to allocate a new pdp, recurse */
1785 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
1788 atomic_subtract_int(&cnt.v_wire_count, 1);
1789 vm_page_free_zero(m);
1793 /* Add reference to pdp page */
1794 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
1795 pdppg->wire_count++;
1797 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1799 /* Now find the pdp page */
1800 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1801 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1804 vm_pindex_t pml4index;
1805 vm_pindex_t pdpindex;
1810 /* Wire up a new PTE page */
1811 pdpindex = ptepindex >> NPDPEPGSHIFT;
1812 pml4index = pdpindex >> NPML4EPGSHIFT;
1814 /* First, find the pdp and check that its valid. */
1815 pml4 = &pmap->pm_pml4[pml4index];
1816 if ((*pml4 & PG_V) == 0) {
1817 /* Have to allocate a new pd, recurse */
1818 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
1821 atomic_subtract_int(&cnt.v_wire_count, 1);
1822 vm_page_free_zero(m);
1825 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1826 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1828 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1829 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1830 if ((*pdp & PG_V) == 0) {
1831 /* Have to allocate a new pd, recurse */
1832 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
1835 atomic_subtract_int(&cnt.v_wire_count,
1837 vm_page_free_zero(m);
1841 /* Add reference to the pd page */
1842 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
1846 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
1848 /* Now we know where the page directory page is */
1849 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
1850 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1853 pmap_resident_count_inc(pmap, 1);
1859 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1861 vm_pindex_t pdpindex, ptepindex;
1866 pdpe = pmap_pdpe(pmap, va);
1867 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1868 /* Add a reference to the pd page. */
1869 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
1872 /* Allocate a pd page. */
1873 ptepindex = pmap_pde_pindex(va);
1874 pdpindex = ptepindex >> NPDPEPGSHIFT;
1875 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
1876 if (pdpg == NULL && lockp != NULL)
1883 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1885 vm_pindex_t ptepindex;
1890 * Calculate pagetable page index
1892 ptepindex = pmap_pde_pindex(va);
1895 * Get the page directory entry
1897 pd = pmap_pde(pmap, va);
1900 * This supports switching from a 2MB page to a
1903 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
1904 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
1906 * Invalidation of the 2MB page mapping may have caused
1907 * the deallocation of the underlying PD page.
1914 * If the page table page is mapped, we just increment the
1915 * hold count, and activate it.
1917 if (pd != NULL && (*pd & PG_V) != 0) {
1918 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
1922 * Here if the pte page isn't mapped, or if it has been
1925 m = _pmap_allocpte(pmap, ptepindex, lockp);
1926 if (m == NULL && lockp != NULL)
1933 /***************************************************
1934 * Pmap allocation/deallocation routines.
1935 ***************************************************/
1938 * Release any resources held by the given physical map.
1939 * Called when a pmap initialized by pmap_pinit is being released.
1940 * Should only be called if the map contains no valid mappings.
1943 pmap_release(pmap_t pmap)
1948 KASSERT(pmap->pm_stats.resident_count == 0,
1949 ("pmap_release: pmap resident count %ld != 0",
1950 pmap->pm_stats.resident_count));
1951 KASSERT(pmap->pm_root == NULL,
1952 ("pmap_release: pmap has reserved page table page(s)"));
1954 m = PHYS_TO_VM_PAGE(pmap->pm_pml4[PML4PML4I] & PG_FRAME);
1956 pmap->pm_pml4[KPML4I] = 0; /* KVA */
1957 for (i = 0; i < NDMPML4E; i++) /* Direct Map */
1958 pmap->pm_pml4[DMPML4I + i] = 0;
1959 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
1962 atomic_subtract_int(&cnt.v_wire_count, 1);
1963 vm_page_free_zero(m);
1964 PMAP_LOCK_DESTROY(pmap);
1968 kvm_size(SYSCTL_HANDLER_ARGS)
1970 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1972 return sysctl_handle_long(oidp, &ksize, 0, req);
1974 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1975 0, 0, kvm_size, "LU", "Size of KVM");
1978 kvm_free(SYSCTL_HANDLER_ARGS)
1980 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1982 return sysctl_handle_long(oidp, &kfree, 0, req);
1984 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1985 0, 0, kvm_free, "LU", "Amount of KVM free");
1988 * grow the number of kernel page table entries, if needed
1991 pmap_growkernel(vm_offset_t addr)
1995 pd_entry_t *pde, newpdir;
1998 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2001 * Return if "addr" is within the range of kernel page table pages
2002 * that were preallocated during pmap bootstrap. Moreover, leave
2003 * "kernel_vm_end" and the kernel page table as they were.
2005 * The correctness of this action is based on the following
2006 * argument: vm_map_findspace() allocates contiguous ranges of the
2007 * kernel virtual address space. It calls this function if a range
2008 * ends after "kernel_vm_end". If the kernel is mapped between
2009 * "kernel_vm_end" and "addr", then the range cannot begin at
2010 * "kernel_vm_end". In fact, its beginning address cannot be less
2011 * than the kernel. Thus, there is no immediate need to allocate
2012 * any new kernel page table pages between "kernel_vm_end" and
2015 if (KERNBASE < addr && addr <= KERNBASE + NKPT * NBPDR)
2018 addr = roundup2(addr, NBPDR);
2019 if (addr - 1 >= kernel_map->max_offset)
2020 addr = kernel_map->max_offset;
2021 while (kernel_vm_end < addr) {
2022 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2023 if ((*pdpe & PG_V) == 0) {
2024 /* We need a new PDP entry */
2025 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2026 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2027 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2029 panic("pmap_growkernel: no memory to grow kernel");
2030 if ((nkpg->flags & PG_ZERO) == 0)
2031 pmap_zero_page(nkpg);
2032 paddr = VM_PAGE_TO_PHYS(nkpg);
2033 *pdpe = (pdp_entry_t)
2034 (paddr | PG_V | PG_RW | PG_A | PG_M);
2035 continue; /* try again */
2037 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2038 if ((*pde & PG_V) != 0) {
2039 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2040 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2041 kernel_vm_end = kernel_map->max_offset;
2047 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2048 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2051 panic("pmap_growkernel: no memory to grow kernel");
2052 if ((nkpg->flags & PG_ZERO) == 0)
2053 pmap_zero_page(nkpg);
2054 paddr = VM_PAGE_TO_PHYS(nkpg);
2055 newpdir = (pd_entry_t) (paddr | PG_V | PG_RW | PG_A | PG_M);
2056 pde_store(pde, newpdir);
2058 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2059 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2060 kernel_vm_end = kernel_map->max_offset;
2067 /***************************************************
2068 * page management routines.
2069 ***************************************************/
2071 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2072 CTASSERT(_NPCM == 3);
2073 CTASSERT(_NPCPV == 168);
2075 static __inline struct pv_chunk *
2076 pv_to_chunk(pv_entry_t pv)
2079 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2082 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2084 #define PC_FREE0 0xfffffffffffffffful
2085 #define PC_FREE1 0xfffffffffffffffful
2086 #define PC_FREE2 0x000000fffffffffful
2088 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2091 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2093 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2094 "Current number of pv entry chunks");
2095 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2096 "Current number of pv entry chunks allocated");
2097 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2098 "Current number of pv entry chunks frees");
2099 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2100 "Number of times tried to get a chunk page but failed.");
2102 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2103 static int pv_entry_spare;
2105 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2106 "Current number of pv entry frees");
2107 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2108 "Current number of pv entry allocs");
2109 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2110 "Current number of pv entries");
2111 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2112 "Current number of spare pv entries");
2116 * We are in a serious low memory condition. Resort to
2117 * drastic measures to free some pages so we can allocate
2118 * another pv entry chunk.
2120 * Returns NULL if PV entries were reclaimed from the specified pmap.
2122 * We do not, however, unmap 2mpages because subsequent accesses will
2123 * allocate per-page pv entries until repromotion occurs, thereby
2124 * exacerbating the shortage of free pv entries.
2127 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2129 struct pch new_tail;
2130 struct pv_chunk *pc;
2131 struct md_page *pvh;
2134 pt_entry_t *pte, tpte;
2137 vm_page_t free, m, m_pc;
2139 int bit, field, freed;
2141 rw_assert(&pvh_global_lock, RA_LOCKED);
2142 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2143 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2146 TAILQ_INIT(&new_tail);
2147 mtx_lock(&pv_chunks_mutex);
2148 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && free == NULL) {
2149 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2150 mtx_unlock(&pv_chunks_mutex);
2151 if (pmap != pc->pc_pmap) {
2153 pmap_invalidate_all(pmap);
2154 if (pmap != locked_pmap)
2158 /* Avoid deadlock and lock recursion. */
2159 if (pmap > locked_pmap) {
2160 RELEASE_PV_LIST_LOCK(lockp);
2162 } else if (pmap != locked_pmap &&
2163 !PMAP_TRYLOCK(pmap)) {
2165 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2166 mtx_lock(&pv_chunks_mutex);
2172 * Destroy every non-wired, 4 KB page mapping in the chunk.
2175 for (field = 0; field < _NPCM; field++) {
2176 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2177 inuse != 0; inuse &= ~(1UL << bit)) {
2179 pv = &pc->pc_pventry[field * 64 + bit];
2181 pde = pmap_pde(pmap, va);
2182 if ((*pde & PG_PS) != 0)
2184 pte = pmap_pde_to_pte(pde, va);
2185 if ((*pte & PG_W) != 0)
2187 tpte = pte_load_clear(pte);
2188 if ((tpte & PG_G) != 0)
2189 pmap_invalidate_page(pmap, va);
2190 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2191 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2193 if ((tpte & PG_A) != 0)
2194 vm_page_aflag_set(m, PGA_REFERENCED);
2195 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2196 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2197 if (TAILQ_EMPTY(&m->md.pv_list) &&
2198 (m->flags & PG_FICTITIOUS) == 0) {
2199 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2200 if (TAILQ_EMPTY(&pvh->pv_list)) {
2201 vm_page_aflag_clear(m,
2205 pc->pc_map[field] |= 1UL << bit;
2206 pmap_unuse_pt(pmap, va, *pde, &free);
2211 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2212 mtx_lock(&pv_chunks_mutex);
2215 /* Every freed mapping is for a 4 KB page. */
2216 pmap_resident_count_dec(pmap, freed);
2217 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2218 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2219 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2220 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2221 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2222 pc->pc_map[2] == PC_FREE2) {
2223 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2224 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2225 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2226 /* Entire chunk is free; return it. */
2227 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2228 dump_drop_page(m_pc->phys_addr);
2229 mtx_lock(&pv_chunks_mutex);
2232 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2233 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2234 mtx_lock(&pv_chunks_mutex);
2235 /* One freed pv entry in locked_pmap is sufficient. */
2236 if (pmap == locked_pmap)
2239 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2240 mtx_unlock(&pv_chunks_mutex);
2242 pmap_invalidate_all(pmap);
2243 if (pmap != locked_pmap)
2246 if (m_pc == NULL && free != NULL) {
2249 /* Recycle a freed page table page. */
2250 m_pc->wire_count = 1;
2251 atomic_add_int(&cnt.v_wire_count, 1);
2253 pmap_free_zero_pages(free);
2258 * free the pv_entry back to the free list
2261 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2263 struct pv_chunk *pc;
2264 int idx, field, bit;
2266 rw_assert(&pvh_global_lock, RA_LOCKED);
2267 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2268 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2269 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2270 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2271 pc = pv_to_chunk(pv);
2272 idx = pv - &pc->pc_pventry[0];
2275 pc->pc_map[field] |= 1ul << bit;
2276 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2277 pc->pc_map[2] != PC_FREE2) {
2278 /* 98% of the time, pc is already at the head of the list. */
2279 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2280 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2281 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2285 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2290 free_pv_chunk(struct pv_chunk *pc)
2294 mtx_lock(&pv_chunks_mutex);
2295 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2296 mtx_unlock(&pv_chunks_mutex);
2297 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2298 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2299 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2300 /* entire chunk is free, return it */
2301 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2302 dump_drop_page(m->phys_addr);
2303 vm_page_unwire(m, 0);
2308 * Returns a new PV entry, allocating a new PV chunk from the system when
2309 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2310 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2313 * The given PV list lock may be released.
2316 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2320 struct pv_chunk *pc;
2323 rw_assert(&pvh_global_lock, RA_LOCKED);
2324 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2325 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2327 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2329 for (field = 0; field < _NPCM; field++) {
2330 if (pc->pc_map[field]) {
2331 bit = bsfq(pc->pc_map[field]);
2335 if (field < _NPCM) {
2336 pv = &pc->pc_pventry[field * 64 + bit];
2337 pc->pc_map[field] &= ~(1ul << bit);
2338 /* If this was the last item, move it to tail */
2339 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2340 pc->pc_map[2] == 0) {
2341 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2342 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2345 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2346 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2350 /* No free items, allocate another chunk */
2351 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2354 if (lockp == NULL) {
2355 PV_STAT(pc_chunk_tryfail++);
2358 m = reclaim_pv_chunk(pmap, lockp);
2362 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2363 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2364 dump_add_page(m->phys_addr);
2365 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2367 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2368 pc->pc_map[1] = PC_FREE1;
2369 pc->pc_map[2] = PC_FREE2;
2370 mtx_lock(&pv_chunks_mutex);
2371 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2372 mtx_unlock(&pv_chunks_mutex);
2373 pv = &pc->pc_pventry[0];
2374 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2375 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2376 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2381 * Returns the number of one bits within the given PV chunk map element.
2384 popcnt_pc_map_elem(uint64_t elem)
2389 * This simple method of counting the one bits performs well because
2390 * the given element typically contains more zero bits than one bits.
2393 for (; elem != 0; elem &= elem - 1)
2399 * Ensure that the number of spare PV entries in the specified pmap meets or
2400 * exceeds the given count, "needed".
2402 * The given PV list lock may be released.
2405 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2407 struct pch new_tail;
2408 struct pv_chunk *pc;
2412 rw_assert(&pvh_global_lock, RA_LOCKED);
2413 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2414 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2417 * Newly allocated PV chunks must be stored in a private list until
2418 * the required number of PV chunks have been allocated. Otherwise,
2419 * reclaim_pv_chunk() could recycle one of these chunks. In
2420 * contrast, these chunks must be added to the pmap upon allocation.
2422 TAILQ_INIT(&new_tail);
2425 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2426 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
2427 free = popcnt_pc_map_elem(pc->pc_map[0]);
2428 free += popcnt_pc_map_elem(pc->pc_map[1]);
2429 free += popcnt_pc_map_elem(pc->pc_map[2]);
2431 free = popcntq(pc->pc_map[0]);
2432 free += popcntq(pc->pc_map[1]);
2433 free += popcntq(pc->pc_map[2]);
2438 if (avail >= needed)
2441 for (; avail < needed; avail += _NPCPV) {
2442 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2445 m = reclaim_pv_chunk(pmap, lockp);
2449 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2450 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2451 dump_add_page(m->phys_addr);
2452 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2454 pc->pc_map[0] = PC_FREE0;
2455 pc->pc_map[1] = PC_FREE1;
2456 pc->pc_map[2] = PC_FREE2;
2457 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2458 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2459 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2461 if (!TAILQ_EMPTY(&new_tail)) {
2462 mtx_lock(&pv_chunks_mutex);
2463 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2464 mtx_unlock(&pv_chunks_mutex);
2469 * First find and then remove the pv entry for the specified pmap and virtual
2470 * address from the specified pv list. Returns the pv entry if found and NULL
2471 * otherwise. This operation can be performed on pv lists for either 4KB or
2472 * 2MB page mappings.
2474 static __inline pv_entry_t
2475 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2479 rw_assert(&pvh_global_lock, RA_LOCKED);
2480 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2481 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2482 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2490 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2491 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2492 * entries for each of the 4KB page mappings.
2495 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2496 struct rwlock **lockp)
2498 struct md_page *pvh;
2499 struct pv_chunk *pc;
2501 vm_offset_t va_last;
2505 rw_assert(&pvh_global_lock, RA_LOCKED);
2506 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2507 KASSERT((pa & PDRMASK) == 0,
2508 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
2509 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2512 * Transfer the 2mpage's pv entry for this mapping to the first
2513 * page's pv list. Once this transfer begins, the pv list lock
2514 * must not be released until the last pv entry is reinstantiated.
2516 pvh = pa_to_pvh(pa);
2517 va = trunc_2mpage(va);
2518 pv = pmap_pvh_remove(pvh, pmap, va);
2519 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2520 m = PHYS_TO_VM_PAGE(pa);
2521 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2522 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2523 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
2524 va_last = va + NBPDR - PAGE_SIZE;
2526 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2527 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2528 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
2529 for (field = 0; field < _NPCM; field++) {
2530 while (pc->pc_map[field]) {
2531 bit = bsfq(pc->pc_map[field]);
2532 pc->pc_map[field] &= ~(1ul << bit);
2533 pv = &pc->pc_pventry[field * 64 + bit];
2537 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2538 ("pmap_pv_demote_pde: page %p is not managed", m));
2539 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2544 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2545 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2548 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2549 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2550 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2552 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
2553 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
2557 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2558 * replace the many pv entries for the 4KB page mappings by a single pv entry
2559 * for the 2MB page mapping.
2562 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2563 struct rwlock **lockp)
2565 struct md_page *pvh;
2567 vm_offset_t va_last;
2570 rw_assert(&pvh_global_lock, RA_LOCKED);
2571 KASSERT((pa & PDRMASK) == 0,
2572 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
2573 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2576 * Transfer the first page's pv entry for this mapping to the 2mpage's
2577 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2578 * a transfer avoids the possibility that get_pv_entry() calls
2579 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2580 * mappings that is being promoted.
2582 m = PHYS_TO_VM_PAGE(pa);
2583 va = trunc_2mpage(va);
2584 pv = pmap_pvh_remove(&m->md, pmap, va);
2585 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2586 pvh = pa_to_pvh(pa);
2587 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2588 /* Free the remaining NPTEPG - 1 pv entries. */
2589 va_last = va + NBPDR - PAGE_SIZE;
2593 pmap_pvh_free(&m->md, pmap, va);
2594 } while (va < va_last);
2598 * First find and then destroy the pv entry for the specified pmap and virtual
2599 * address. This operation can be performed on pv lists for either 4KB or 2MB
2603 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2607 pv = pmap_pvh_remove(pvh, pmap, va);
2608 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2609 free_pv_entry(pmap, pv);
2613 * Conditionally create the PV entry for a 4KB page mapping if the required
2614 * memory can be allocated without resorting to reclamation.
2617 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2618 struct rwlock **lockp)
2622 rw_assert(&pvh_global_lock, RA_LOCKED);
2623 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2624 /* Pass NULL instead of the lock pointer to disable reclamation. */
2625 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2627 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2628 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2635 * Conditionally create the PV entry for a 2MB page mapping if the required
2636 * memory can be allocated without resorting to reclamation.
2639 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2640 struct rwlock **lockp)
2642 struct md_page *pvh;
2645 rw_assert(&pvh_global_lock, RA_LOCKED);
2646 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2647 /* Pass NULL instead of the lock pointer to disable reclamation. */
2648 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2650 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2651 pvh = pa_to_pvh(pa);
2652 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2659 * Fills a page table page with mappings to consecutive physical pages.
2662 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2666 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2668 newpte += PAGE_SIZE;
2673 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
2674 * mapping is invalidated.
2677 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2679 struct rwlock *lock;
2683 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
2690 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
2691 struct rwlock **lockp)
2693 pd_entry_t newpde, oldpde;
2694 pt_entry_t *firstpte, newpte;
2696 vm_page_t free, mpte;
2698 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2700 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2701 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2702 mpte = pmap_lookup_pt_page(pmap, va);
2704 pmap_remove_pt_page(pmap, mpte);
2706 KASSERT((oldpde & PG_W) == 0,
2707 ("pmap_demote_pde: page table page for a wired mapping"
2711 * Invalidate the 2MB page mapping and return "failure" if the
2712 * mapping was never accessed or the allocation of the new
2713 * page table page fails. If the 2MB page mapping belongs to
2714 * the direct map region of the kernel's address space, then
2715 * the page allocation request specifies the highest possible
2716 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
2717 * normal. Page table pages are preallocated for every other
2718 * part of the kernel address space, so the direct map region
2719 * is the only part of the kernel address space that must be
2722 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2723 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
2724 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
2725 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2727 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
2729 pmap_invalidate_page(pmap, trunc_2mpage(va));
2730 pmap_free_zero_pages(free);
2731 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
2732 " in pmap %p", va, pmap);
2735 if (va < VM_MAXUSER_ADDRESS)
2736 pmap_resident_count_inc(pmap, 1);
2738 mptepa = VM_PAGE_TO_PHYS(mpte);
2739 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
2740 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2741 KASSERT((oldpde & PG_A) != 0,
2742 ("pmap_demote_pde: oldpde is missing PG_A"));
2743 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2744 ("pmap_demote_pde: oldpde is missing PG_M"));
2745 newpte = oldpde & ~PG_PS;
2746 if ((newpte & PG_PDE_PAT) != 0)
2747 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2750 * If the page table page is new, initialize it.
2752 if (mpte->wire_count == 1) {
2753 mpte->wire_count = NPTEPG;
2754 pmap_fill_ptp(firstpte, newpte);
2756 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2757 ("pmap_demote_pde: firstpte and newpte map different physical"
2761 * If the mapping has changed attributes, update the page table
2764 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2765 pmap_fill_ptp(firstpte, newpte);
2768 * The spare PV entries must be reserved prior to demoting the
2769 * mapping, that is, prior to changing the PDE. Otherwise, the state
2770 * of the PDE and the PV lists will be inconsistent, which can result
2771 * in reclaim_pv_chunk() attempting to remove a PV entry from the
2772 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
2773 * PV entry for the 2MB page mapping that is being demoted.
2775 if ((oldpde & PG_MANAGED) != 0)
2776 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
2779 * Demote the mapping. This pmap is locked. The old PDE has
2780 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2781 * set. Thus, there is no danger of a race with another
2782 * processor changing the setting of PG_A and/or PG_M between
2783 * the read above and the store below.
2785 if (workaround_erratum383)
2786 pmap_update_pde(pmap, va, pde, newpde);
2788 pde_store(pde, newpde);
2791 * Invalidate a stale recursive mapping of the page table page.
2793 if (va >= VM_MAXUSER_ADDRESS)
2794 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2797 * Demote the PV entry.
2799 if ((oldpde & PG_MANAGED) != 0)
2800 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
2802 atomic_add_long(&pmap_pde_demotions, 1);
2803 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
2804 " in pmap %p", va, pmap);
2809 * pmap_remove_pde: do the things to unmap a superpage in a process
2812 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2813 vm_page_t *free, struct rwlock **lockp)
2815 struct md_page *pvh;
2817 vm_offset_t eva, va;
2820 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2821 KASSERT((sva & PDRMASK) == 0,
2822 ("pmap_remove_pde: sva is not 2mpage aligned"));
2823 oldpde = pte_load_clear(pdq);
2825 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2828 * Machines that don't support invlpg, also don't support
2832 pmap_invalidate_page(kernel_pmap, sva);
2833 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
2834 if (oldpde & PG_MANAGED) {
2835 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
2836 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2837 pmap_pvh_free(pvh, pmap, sva);
2839 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2840 va < eva; va += PAGE_SIZE, m++) {
2841 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2844 vm_page_aflag_set(m, PGA_REFERENCED);
2845 if (TAILQ_EMPTY(&m->md.pv_list) &&
2846 TAILQ_EMPTY(&pvh->pv_list))
2847 vm_page_aflag_clear(m, PGA_WRITEABLE);
2850 if (pmap == kernel_pmap) {
2851 if (!pmap_demote_pde_locked(pmap, pdq, sva, lockp))
2852 panic("pmap_remove_pde: failed demotion");
2854 mpte = pmap_lookup_pt_page(pmap, sva);
2856 pmap_remove_pt_page(pmap, mpte);
2857 pmap_resident_count_dec(pmap, 1);
2858 KASSERT(mpte->wire_count == NPTEPG,
2859 ("pmap_remove_pde: pte page wire count error"));
2860 mpte->wire_count = 0;
2861 pmap_add_delayed_free_list(mpte, free, FALSE);
2862 atomic_subtract_int(&cnt.v_wire_count, 1);
2865 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
2869 * pmap_remove_pte: do the things to unmap a page in a process
2872 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2873 pd_entry_t ptepde, vm_page_t *free, struct rwlock **lockp)
2875 struct md_page *pvh;
2879 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2880 oldpte = pte_load_clear(ptq);
2882 pmap->pm_stats.wired_count -= 1;
2883 pmap_resident_count_dec(pmap, 1);
2884 if (oldpte & PG_MANAGED) {
2885 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2886 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2889 vm_page_aflag_set(m, PGA_REFERENCED);
2890 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2891 pmap_pvh_free(&m->md, pmap, va);
2892 if (TAILQ_EMPTY(&m->md.pv_list) &&
2893 (m->flags & PG_FICTITIOUS) == 0) {
2894 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2895 if (TAILQ_EMPTY(&pvh->pv_list))
2896 vm_page_aflag_clear(m, PGA_WRITEABLE);
2899 return (pmap_unuse_pt(pmap, va, ptepde, free));
2903 * Remove a single page from a process address space
2906 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, vm_page_t *free)
2908 struct rwlock *lock;
2911 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2912 if ((*pde & PG_V) == 0)
2914 pte = pmap_pde_to_pte(pde, va);
2915 if ((*pte & PG_V) == 0)
2918 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
2921 pmap_invalidate_page(pmap, va);
2925 * Remove the given range of addresses from the specified map.
2927 * It is assumed that the start and end are properly
2928 * rounded to the page size.
2931 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2933 struct rwlock *lock;
2934 vm_offset_t va, va_next;
2935 pml4_entry_t *pml4e;
2937 pd_entry_t ptpaddr, *pde;
2939 vm_page_t free = NULL;
2943 * Perform an unsynchronized read. This is, however, safe.
2945 if (pmap->pm_stats.resident_count == 0)
2950 rw_rlock(&pvh_global_lock);
2954 * special handling of removing one page. a very
2955 * common operation and easy to short circuit some
2958 if (sva + PAGE_SIZE == eva) {
2959 pde = pmap_pde(pmap, sva);
2960 if (pde && (*pde & PG_PS) == 0) {
2961 pmap_remove_page(pmap, sva, pde, &free);
2967 for (; sva < eva; sva = va_next) {
2969 if (pmap->pm_stats.resident_count == 0)
2972 pml4e = pmap_pml4e(pmap, sva);
2973 if ((*pml4e & PG_V) == 0) {
2974 va_next = (sva + NBPML4) & ~PML4MASK;
2980 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
2981 if ((*pdpe & PG_V) == 0) {
2982 va_next = (sva + NBPDP) & ~PDPMASK;
2989 * Calculate index for next page table.
2991 va_next = (sva + NBPDR) & ~PDRMASK;
2995 pde = pmap_pdpe_to_pde(pdpe, sva);
2999 * Weed out invalid mappings.
3005 * Check for large page.
3007 if ((ptpaddr & PG_PS) != 0) {
3009 * Are we removing the entire large page? If not,
3010 * demote the mapping and fall through.
3012 if (sva + NBPDR == va_next && eva >= va_next) {
3014 * The TLB entry for a PG_G mapping is
3015 * invalidated by pmap_remove_pde().
3017 if ((ptpaddr & PG_G) == 0)
3019 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3021 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3023 /* The large page mapping was destroyed. */
3030 * Limit our scan to either the end of the va represented
3031 * by the current page table page, or to the end of the
3032 * range being removed.
3038 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3041 if (va != va_next) {
3042 pmap_invalidate_range(pmap, va, sva);
3047 if ((*pte & PG_G) == 0)
3049 else if (va == va_next)
3051 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3058 pmap_invalidate_range(pmap, va, sva);
3064 pmap_invalidate_all(pmap);
3065 rw_runlock(&pvh_global_lock);
3067 pmap_free_zero_pages(free);
3071 * Routine: pmap_remove_all
3073 * Removes this physical page from
3074 * all physical maps in which it resides.
3075 * Reflects back modify bits to the pager.
3078 * Original versions of this routine were very
3079 * inefficient because they iteratively called
3080 * pmap_remove (slow...)
3084 pmap_remove_all(vm_page_t m)
3086 struct md_page *pvh;
3089 pt_entry_t *pte, tpte;
3094 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3095 ("pmap_remove_all: page %p is not managed", m));
3097 rw_wlock(&pvh_global_lock);
3098 if ((m->flags & PG_FICTITIOUS) != 0)
3099 goto small_mappings;
3100 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3101 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3105 pde = pmap_pde(pmap, va);
3106 (void)pmap_demote_pde(pmap, pde, va);
3110 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3113 pmap_resident_count_dec(pmap, 1);
3114 pde = pmap_pde(pmap, pv->pv_va);
3115 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3116 " a 2mpage in page %p's pv list", m));
3117 pte = pmap_pde_to_pte(pde, pv->pv_va);
3118 tpte = pte_load_clear(pte);
3120 pmap->pm_stats.wired_count--;
3122 vm_page_aflag_set(m, PGA_REFERENCED);
3125 * Update the vm_page_t clean and reference bits.
3127 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3129 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3130 pmap_invalidate_page(pmap, pv->pv_va);
3131 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3132 free_pv_entry(pmap, pv);
3135 vm_page_aflag_clear(m, PGA_WRITEABLE);
3136 rw_wunlock(&pvh_global_lock);
3137 pmap_free_zero_pages(free);
3141 * pmap_protect_pde: do the things to protect a 2mpage in a process
3144 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3146 pd_entry_t newpde, oldpde;
3147 vm_offset_t eva, va;
3149 boolean_t anychanged;
3151 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3152 KASSERT((sva & PDRMASK) == 0,
3153 ("pmap_protect_pde: sva is not 2mpage aligned"));
3156 oldpde = newpde = *pde;
3157 if (oldpde & PG_MANAGED) {
3159 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3160 va < eva; va += PAGE_SIZE, m++)
3161 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3164 if ((prot & VM_PROT_WRITE) == 0)
3165 newpde &= ~(PG_RW | PG_M);
3166 if ((prot & VM_PROT_EXECUTE) == 0)
3168 if (newpde != oldpde) {
3169 if (!atomic_cmpset_long(pde, oldpde, newpde))
3172 pmap_invalidate_page(pmap, sva);
3176 return (anychanged);
3180 * Set the physical protection on the
3181 * specified range of this map as requested.
3184 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3186 vm_offset_t va_next;
3187 pml4_entry_t *pml4e;
3189 pd_entry_t ptpaddr, *pde;
3191 boolean_t anychanged, pv_lists_locked;
3193 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3194 pmap_remove(pmap, sva, eva);
3198 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3199 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3202 pv_lists_locked = FALSE;
3207 for (; sva < eva; sva = va_next) {
3209 pml4e = pmap_pml4e(pmap, sva);
3210 if ((*pml4e & PG_V) == 0) {
3211 va_next = (sva + NBPML4) & ~PML4MASK;
3217 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3218 if ((*pdpe & PG_V) == 0) {
3219 va_next = (sva + NBPDP) & ~PDPMASK;
3225 va_next = (sva + NBPDR) & ~PDRMASK;
3229 pde = pmap_pdpe_to_pde(pdpe, sva);
3233 * Weed out invalid mappings.
3239 * Check for large page.
3241 if ((ptpaddr & PG_PS) != 0) {
3243 * Are we protecting the entire large page? If not,
3244 * demote the mapping and fall through.
3246 if (sva + NBPDR == va_next && eva >= va_next) {
3248 * The TLB entry for a PG_G mapping is
3249 * invalidated by pmap_protect_pde().
3251 if (pmap_protect_pde(pmap, pde, sva, prot))
3255 if (!pv_lists_locked) {
3256 pv_lists_locked = TRUE;
3257 if (!rw_try_rlock(&pvh_global_lock)) {
3259 pmap_invalidate_all(
3262 rw_rlock(&pvh_global_lock);
3266 if (!pmap_demote_pde(pmap, pde, sva)) {
3268 * The large page mapping was
3279 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3281 pt_entry_t obits, pbits;
3285 obits = pbits = *pte;
3286 if ((pbits & PG_V) == 0)
3289 if ((prot & VM_PROT_WRITE) == 0) {
3290 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3291 (PG_MANAGED | PG_M | PG_RW)) {
3292 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3295 pbits &= ~(PG_RW | PG_M);
3297 if ((prot & VM_PROT_EXECUTE) == 0)
3300 if (pbits != obits) {
3301 if (!atomic_cmpset_long(pte, obits, pbits))
3304 pmap_invalidate_page(pmap, sva);
3311 pmap_invalidate_all(pmap);
3312 if (pv_lists_locked)
3313 rw_runlock(&pvh_global_lock);
3318 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3319 * single page table page (PTP) to a single 2MB page mapping. For promotion
3320 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3321 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3322 * identical characteristics.
3325 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3326 struct rwlock **lockp)
3329 pt_entry_t *firstpte, oldpte, pa, *pte;
3330 vm_offset_t oldpteva;
3333 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3336 * Examine the first PTE in the specified PTP. Abort if this PTE is
3337 * either invalid, unused, or does not map the first 4KB physical page
3338 * within a 2MB page.
3340 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
3343 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3344 atomic_add_long(&pmap_pde_p_failures, 1);
3345 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3346 " in pmap %p", va, pmap);
3349 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3351 * When PG_M is already clear, PG_RW can be cleared without
3352 * a TLB invalidation.
3354 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
3360 * Examine each of the other PTEs in the specified PTP. Abort if this
3361 * PTE maps an unexpected 4KB physical page or does not have identical
3362 * characteristics to the first PTE.
3364 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3365 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3368 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3369 atomic_add_long(&pmap_pde_p_failures, 1);
3370 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3371 " in pmap %p", va, pmap);
3374 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3376 * When PG_M is already clear, PG_RW can be cleared
3377 * without a TLB invalidation.
3379 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
3382 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3384 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
3385 " in pmap %p", oldpteva, pmap);
3387 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3388 atomic_add_long(&pmap_pde_p_failures, 1);
3389 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3390 " in pmap %p", va, pmap);
3397 * Save the page table page in its current state until the PDE
3398 * mapping the superpage is demoted by pmap_demote_pde() or
3399 * destroyed by pmap_remove_pde().
3401 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3402 KASSERT(mpte >= vm_page_array &&
3403 mpte < &vm_page_array[vm_page_array_size],
3404 ("pmap_promote_pde: page table page is out of range"));
3405 KASSERT(mpte->pindex == pmap_pde_pindex(va),
3406 ("pmap_promote_pde: page table page's pindex is wrong"));
3407 pmap_insert_pt_page(pmap, mpte);
3410 * Promote the pv entries.
3412 if ((newpde & PG_MANAGED) != 0)
3413 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
3416 * Propagate the PAT index to its proper position.
3418 if ((newpde & PG_PTE_PAT) != 0)
3419 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3422 * Map the superpage.
3424 if (workaround_erratum383)
3425 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3427 pde_store(pde, PG_PS | newpde);
3429 atomic_add_long(&pmap_pde_promotions, 1);
3430 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
3431 " in pmap %p", va, pmap);
3435 * Insert the given physical page (p) at
3436 * the specified virtual address (v) in the
3437 * target physical map with the protection requested.
3439 * If specified, the page will be wired down, meaning
3440 * that the related pte can not be reclaimed.
3442 * NB: This is the only routine which MAY NOT lazy-evaluate
3443 * or lose information. That is, this routine must actually
3444 * insert this page into the given map NOW.
3447 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3448 vm_prot_t prot, boolean_t wired)
3450 struct rwlock *lock;
3453 pt_entry_t newpte, origpte;
3458 va = trunc_page(va);
3459 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3460 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3461 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
3463 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
3464 va >= kmi.clean_eva,
3465 ("pmap_enter: managed mapping within the clean submap"));
3466 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
3467 VM_OBJECT_LOCKED(m->object),
3468 ("pmap_enter: page %p is not busy", m));
3469 pa = VM_PAGE_TO_PHYS(m);
3470 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3471 if ((access & VM_PROT_WRITE) != 0)
3473 if ((prot & VM_PROT_WRITE) != 0)
3475 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3476 ("pmap_enter: access includes VM_PROT_WRITE but prot doesn't"));
3477 if ((prot & VM_PROT_EXECUTE) == 0)
3481 if (va < VM_MAXUSER_ADDRESS)
3483 if (pmap == kernel_pmap)
3485 newpte |= pmap_cache_bits(m->md.pat_mode, 0);
3490 rw_rlock(&pvh_global_lock);
3494 * In the case that a page table page is not
3495 * resident, we are creating it here.
3498 pde = pmap_pde(pmap, va);
3499 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
3500 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
3501 pte = pmap_pde_to_pte(pde, va);
3502 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3503 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3506 } else if (va < VM_MAXUSER_ADDRESS) {
3508 * Here if the pte page isn't mapped, or if it has been
3511 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va), &lock);
3514 panic("pmap_enter: invalid page directory va=%#lx", va);
3519 * Is the specified virtual address already mapped?
3521 if ((origpte & PG_V) != 0) {
3523 * Wiring change, just update stats. We don't worry about
3524 * wiring PT pages as they remain resident as long as there
3525 * are valid mappings in them. Hence, if a user page is wired,
3526 * the PT page will be also.
3528 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3529 pmap->pm_stats.wired_count++;
3530 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3531 pmap->pm_stats.wired_count--;
3534 * Remove the extra PT page reference.
3538 KASSERT(mpte->wire_count > 0,
3539 ("pmap_enter: missing reference to page table page,"
3544 * Has the physical page changed?
3546 opa = origpte & PG_FRAME;
3549 * No, might be a protection or wiring change.
3551 if ((origpte & PG_MANAGED) != 0) {
3552 newpte |= PG_MANAGED;
3553 if ((newpte & PG_RW) != 0)
3554 vm_page_aflag_set(m, PGA_WRITEABLE);
3556 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3562 * Increment the counters.
3564 if ((newpte & PG_W) != 0)
3565 pmap->pm_stats.wired_count++;
3566 pmap_resident_count_inc(pmap, 1);
3570 * Enter on the PV list if part of our managed memory.
3572 if ((m->oflags & VPO_UNMANAGED) == 0) {
3573 newpte |= PG_MANAGED;
3574 pv = get_pv_entry(pmap, &lock);
3576 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3577 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3578 if ((newpte & PG_RW) != 0)
3579 vm_page_aflag_set(m, PGA_WRITEABLE);
3585 if ((origpte & PG_V) != 0) {
3587 origpte = pte_load_store(pte, newpte);
3588 opa = origpte & PG_FRAME;
3590 if ((origpte & PG_MANAGED) != 0) {
3591 om = PHYS_TO_VM_PAGE(opa);
3592 if ((origpte & (PG_M | PG_RW)) == (PG_M |
3595 if ((origpte & PG_A) != 0)
3596 vm_page_aflag_set(om, PGA_REFERENCED);
3597 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3598 pmap_pvh_free(&om->md, pmap, va);
3599 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3600 TAILQ_EMPTY(&om->md.pv_list) &&
3601 ((om->flags & PG_FICTITIOUS) != 0 ||
3602 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3603 vm_page_aflag_clear(om, PGA_WRITEABLE);
3605 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
3606 PG_RW)) == (PG_M | PG_RW)) {
3607 if ((origpte & PG_MANAGED) != 0)
3611 * Although the PTE may still have PG_RW set, TLB
3612 * invalidation may nonetheless be required because
3613 * the PTE no longer has PG_M set.
3615 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3617 * This PTE change does not require TLB invalidation.
3621 if ((origpte & PG_A) != 0)
3622 pmap_invalidate_page(pmap, va);
3624 pte_store(pte, newpte);
3629 * If both the page table page and the reservation are fully
3630 * populated, then attempt promotion.
3632 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3633 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3634 vm_reserv_level_iffullpop(m) == 0)
3635 pmap_promote_pde(pmap, pde, va, &lock);
3639 rw_runlock(&pvh_global_lock);
3644 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
3645 * otherwise. Fails if (1) a page table page cannot be allocated without
3646 * blocking, (2) a mapping already exists at the specified virtual address, or
3647 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3650 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3651 struct rwlock **lockp)
3653 pd_entry_t *pde, newpde;
3654 vm_page_t free, mpde;
3656 rw_assert(&pvh_global_lock, RA_LOCKED);
3657 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3658 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
3659 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3660 " in pmap %p", va, pmap);
3663 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
3664 pde = &pde[pmap_pde_index(va)];
3665 if ((*pde & PG_V) != 0) {
3666 KASSERT(mpde->wire_count > 1,
3667 ("pmap_enter_pde: mpde's wire count is too low"));
3669 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3670 " in pmap %p", va, pmap);
3673 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3675 if ((m->oflags & VPO_UNMANAGED) == 0) {
3676 newpde |= PG_MANAGED;
3679 * Abort this mapping if its PV entry could not be created.
3681 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
3684 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
3685 pmap_invalidate_page(pmap, va);
3686 pmap_free_zero_pages(free);
3688 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3689 " in pmap %p", va, pmap);
3693 if ((prot & VM_PROT_EXECUTE) == 0)
3695 if (va < VM_MAXUSER_ADDRESS)
3699 * Increment counters.
3701 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
3704 * Map the superpage.
3706 pde_store(pde, newpde);
3708 atomic_add_long(&pmap_pde_mappings, 1);
3709 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3710 " in pmap %p", va, pmap);
3715 * Maps a sequence of resident pages belonging to the same object.
3716 * The sequence begins with the given page m_start. This page is
3717 * mapped at the given virtual address start. Each subsequent page is
3718 * mapped at a virtual address that is offset from start by the same
3719 * amount as the page is offset from m_start within the object. The
3720 * last page in the sequence is the page with the largest offset from
3721 * m_start that can be mapped at a virtual address less than the given
3722 * virtual address end. Not every virtual page between start and end
3723 * is mapped; only those for which a resident page exists with the
3724 * corresponding offset from m_start are mapped.
3727 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3728 vm_page_t m_start, vm_prot_t prot)
3730 struct rwlock *lock;
3733 vm_pindex_t diff, psize;
3735 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
3736 psize = atop(end - start);
3740 rw_rlock(&pvh_global_lock);
3742 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3743 va = start + ptoa(diff);
3744 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3745 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3746 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3747 pmap_enter_pde(pmap, va, m, prot, &lock))
3748 m = &m[NBPDR / PAGE_SIZE - 1];
3750 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3752 m = TAILQ_NEXT(m, listq);
3756 rw_runlock(&pvh_global_lock);
3761 * this code makes some *MAJOR* assumptions:
3762 * 1. Current pmap & pmap exists.
3765 * 4. No page table pages.
3766 * but is *MUCH* faster than pmap_enter...
3770 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3772 struct rwlock *lock;
3775 rw_rlock(&pvh_global_lock);
3777 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3780 rw_runlock(&pvh_global_lock);
3785 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3786 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3792 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3793 (m->oflags & VPO_UNMANAGED) != 0,
3794 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3795 rw_assert(&pvh_global_lock, RA_LOCKED);
3796 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3799 * In the case that a page table page is not
3800 * resident, we are creating it here.
3802 if (va < VM_MAXUSER_ADDRESS) {
3803 vm_pindex_t ptepindex;
3807 * Calculate pagetable page index
3809 ptepindex = pmap_pde_pindex(va);
3810 if (mpte && (mpte->pindex == ptepindex)) {
3814 * Get the page directory entry
3816 ptepa = pmap_pde(pmap, va);
3819 * If the page table page is mapped, we just increment
3820 * the hold count, and activate it. Otherwise, we
3821 * attempt to allocate a page table page. If this
3822 * attempt fails, we don't retry. Instead, we give up.
3824 if (ptepa && (*ptepa & PG_V) != 0) {
3827 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
3831 * Pass NULL instead of the PV list lock
3832 * pointer, because we don't intend to sleep.
3834 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
3839 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3840 pte = &pte[pmap_pte_index(va)];
3854 * Enter on the PV list if part of our managed memory.
3856 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3857 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3860 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3861 pmap_invalidate_page(pmap, va);
3862 pmap_free_zero_pages(free);
3870 * Increment counters
3872 pmap_resident_count_inc(pmap, 1);
3874 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3875 if ((prot & VM_PROT_EXECUTE) == 0)
3879 * Now validate mapping with RO protection
3881 if ((m->oflags & VPO_UNMANAGED) != 0)
3882 pte_store(pte, pa | PG_V | PG_U);
3884 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3889 * Make a temporary mapping for a physical address. This is only intended
3890 * to be used for panic dumps.
3893 pmap_kenter_temporary(vm_paddr_t pa, int i)
3897 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3898 pmap_kenter(va, pa);
3900 return ((void *)crashdumpmap);
3904 * This code maps large physical mmap regions into the
3905 * processor address space. Note that some shortcuts
3906 * are taken, but the code works.
3909 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3910 vm_pindex_t pindex, vm_size_t size)
3913 vm_paddr_t pa, ptepa;
3917 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3918 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3919 ("pmap_object_init_pt: non-device object"));
3920 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3921 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3923 p = vm_page_lookup(object, pindex);
3924 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3925 ("pmap_object_init_pt: invalid page %p", p));
3926 pat_mode = p->md.pat_mode;
3929 * Abort the mapping if the first page is not physically
3930 * aligned to a 2MB page boundary.
3932 ptepa = VM_PAGE_TO_PHYS(p);
3933 if (ptepa & (NBPDR - 1))
3937 * Skip the first page. Abort the mapping if the rest of
3938 * the pages are not physically contiguous or have differing
3939 * memory attributes.
3941 p = TAILQ_NEXT(p, listq);
3942 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3944 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3945 ("pmap_object_init_pt: invalid page %p", p));
3946 if (pa != VM_PAGE_TO_PHYS(p) ||
3947 pat_mode != p->md.pat_mode)
3949 p = TAILQ_NEXT(p, listq);
3953 * Map using 2MB pages. Since "ptepa" is 2M aligned and
3954 * "size" is a multiple of 2M, adding the PAT setting to "pa"
3955 * will not affect the termination of this loop.
3958 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3959 size; pa += NBPDR) {
3960 pdpg = pmap_allocpde(pmap, addr, NULL);
3963 * The creation of mappings below is only an
3964 * optimization. If a page directory page
3965 * cannot be allocated without blocking,
3966 * continue on to the next mapping rather than
3972 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
3973 pde = &pde[pmap_pde_index(addr)];
3974 if ((*pde & PG_V) == 0) {
3975 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3976 PG_U | PG_RW | PG_V);
3977 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
3978 atomic_add_long(&pmap_pde_mappings, 1);
3980 /* Continue on if the PDE is already valid. */
3982 KASSERT(pdpg->wire_count > 0,
3983 ("pmap_object_init_pt: missing reference "
3984 "to page directory page, va: 0x%lx", addr));
3993 * Routine: pmap_change_wiring
3994 * Function: Change the wiring attribute for a map/virtual-address
3996 * In/out conditions:
3997 * The mapping must already exist in the pmap.
4000 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
4004 boolean_t pv_lists_locked;
4006 pv_lists_locked = FALSE;
4009 * Wiring is not a hardware characteristic so there is no need to
4014 pde = pmap_pde(pmap, va);
4015 if ((*pde & PG_PS) != 0) {
4016 if (!wired != ((*pde & PG_W) == 0)) {
4017 if (!pv_lists_locked) {
4018 pv_lists_locked = TRUE;
4019 if (!rw_try_rlock(&pvh_global_lock)) {
4021 rw_rlock(&pvh_global_lock);
4025 if (!pmap_demote_pde(pmap, pde, va))
4026 panic("pmap_change_wiring: demotion failed");
4030 pte = pmap_pde_to_pte(pde, va);
4031 if (wired && (*pte & PG_W) == 0) {
4032 pmap->pm_stats.wired_count++;
4033 atomic_set_long(pte, PG_W);
4034 } else if (!wired && (*pte & PG_W) != 0) {
4035 pmap->pm_stats.wired_count--;
4036 atomic_clear_long(pte, PG_W);
4039 if (pv_lists_locked)
4040 rw_runlock(&pvh_global_lock);
4045 * Copy the range specified by src_addr/len
4046 * from the source map to the range dst_addr/len
4047 * in the destination map.
4049 * This routine is only advisory and need not do anything.
4053 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4054 vm_offset_t src_addr)
4056 struct rwlock *lock;
4059 vm_offset_t end_addr = src_addr + len;
4060 vm_offset_t va_next;
4062 if (dst_addr != src_addr)
4066 rw_rlock(&pvh_global_lock);
4067 if (dst_pmap < src_pmap) {
4068 PMAP_LOCK(dst_pmap);
4069 PMAP_LOCK(src_pmap);
4071 PMAP_LOCK(src_pmap);
4072 PMAP_LOCK(dst_pmap);
4074 for (addr = src_addr; addr < end_addr; addr = va_next) {
4075 pt_entry_t *src_pte, *dst_pte;
4076 vm_page_t dstmpde, dstmpte, srcmpte;
4077 pml4_entry_t *pml4e;
4079 pd_entry_t srcptepaddr, *pde;
4081 KASSERT(addr < UPT_MIN_ADDRESS,
4082 ("pmap_copy: invalid to pmap_copy page tables"));
4084 pml4e = pmap_pml4e(src_pmap, addr);
4085 if ((*pml4e & PG_V) == 0) {
4086 va_next = (addr + NBPML4) & ~PML4MASK;
4092 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4093 if ((*pdpe & PG_V) == 0) {
4094 va_next = (addr + NBPDP) & ~PDPMASK;
4100 va_next = (addr + NBPDR) & ~PDRMASK;
4104 pde = pmap_pdpe_to_pde(pdpe, addr);
4106 if (srcptepaddr == 0)
4109 if (srcptepaddr & PG_PS) {
4110 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4111 if (dstmpde == NULL)
4113 pde = (pd_entry_t *)
4114 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4115 pde = &pde[pmap_pde_index(addr)];
4116 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4117 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4118 PG_PS_FRAME, &lock))) {
4119 *pde = srcptepaddr & ~PG_W;
4120 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4122 dstmpde->wire_count--;
4126 srcptepaddr &= PG_FRAME;
4127 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4128 KASSERT(srcmpte->wire_count > 0,
4129 ("pmap_copy: source page table page is unused"));
4131 if (va_next > end_addr)
4134 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4135 src_pte = &src_pte[pmap_pte_index(addr)];
4137 while (addr < va_next) {
4141 * we only virtual copy managed pages
4143 if ((ptetemp & PG_MANAGED) != 0) {
4144 if (dstmpte != NULL &&
4145 dstmpte->pindex == pmap_pde_pindex(addr))
4146 dstmpte->wire_count++;
4147 else if ((dstmpte = pmap_allocpte(dst_pmap,
4148 addr, NULL)) == NULL)
4150 dst_pte = (pt_entry_t *)
4151 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4152 dst_pte = &dst_pte[pmap_pte_index(addr)];
4153 if (*dst_pte == 0 &&
4154 pmap_try_insert_pv_entry(dst_pmap, addr,
4155 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4158 * Clear the wired, modified, and
4159 * accessed (referenced) bits
4162 *dst_pte = ptetemp & ~(PG_W | PG_M |
4164 pmap_resident_count_inc(dst_pmap, 1);
4167 if (pmap_unwire_ptp(dst_pmap, addr,
4169 pmap_invalidate_page(dst_pmap,
4171 pmap_free_zero_pages(free);
4175 if (dstmpte->wire_count >= srcmpte->wire_count)
4185 rw_runlock(&pvh_global_lock);
4186 PMAP_UNLOCK(src_pmap);
4187 PMAP_UNLOCK(dst_pmap);
4191 * pmap_zero_page zeros the specified hardware page by mapping
4192 * the page into KVM and using bzero to clear its contents.
4195 pmap_zero_page(vm_page_t m)
4197 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4199 pagezero((void *)va);
4203 * pmap_zero_page_area zeros the specified hardware page by mapping
4204 * the page into KVM and using bzero to clear its contents.
4206 * off and size may not cover an area beyond a single hardware page.
4209 pmap_zero_page_area(vm_page_t m, int off, int size)
4211 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4213 if (off == 0 && size == PAGE_SIZE)
4214 pagezero((void *)va);
4216 bzero((char *)va + off, size);
4220 * pmap_zero_page_idle zeros the specified hardware page by mapping
4221 * the page into KVM and using bzero to clear its contents. This
4222 * is intended to be called from the vm_pagezero process only and
4226 pmap_zero_page_idle(vm_page_t m)
4228 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4230 pagezero((void *)va);
4234 * pmap_copy_page copies the specified (machine independent)
4235 * page by mapping the page into virtual memory and using
4236 * bcopy to copy the page, one machine dependent page at a
4240 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4242 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4243 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4245 pagecopy((void *)src, (void *)dst);
4248 int unmapped_buf_allowed = 1;
4251 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4252 vm_offset_t b_offset, int xfersize)
4255 vm_offset_t a_pg_offset, b_pg_offset;
4258 while (xfersize > 0) {
4259 a_pg_offset = a_offset & PAGE_MASK;
4260 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4261 a_cp = (char *)PHYS_TO_DMAP(ma[a_offset >> PAGE_SHIFT]->
4262 phys_addr) + a_pg_offset;
4263 b_pg_offset = b_offset & PAGE_MASK;
4264 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4265 b_cp = (char *)PHYS_TO_DMAP(mb[b_offset >> PAGE_SHIFT]->
4266 phys_addr) + b_pg_offset;
4267 bcopy(a_cp, b_cp, cnt);
4275 * Returns true if the pmap's pv is one of the first
4276 * 16 pvs linked to from this page. This count may
4277 * be changed upwards or downwards in the future; it
4278 * is only necessary that true be returned for a small
4279 * subset of pmaps for proper page aging.
4282 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4284 struct md_page *pvh;
4285 struct rwlock *lock;
4290 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4291 ("pmap_page_exists_quick: page %p is not managed", m));
4293 rw_rlock(&pvh_global_lock);
4294 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4296 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4297 if (PV_PMAP(pv) == pmap) {
4305 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4306 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4307 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4308 if (PV_PMAP(pv) == pmap) {
4318 rw_runlock(&pvh_global_lock);
4323 * pmap_page_wired_mappings:
4325 * Return the number of managed mappings to the given physical page
4329 pmap_page_wired_mappings(vm_page_t m)
4334 if ((m->oflags & VPO_UNMANAGED) != 0)
4336 rw_wlock(&pvh_global_lock);
4337 count = pmap_pvh_wired_mappings(&m->md, count);
4338 if ((m->flags & PG_FICTITIOUS) == 0) {
4339 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4342 rw_wunlock(&pvh_global_lock);
4347 * pmap_pvh_wired_mappings:
4349 * Return the updated number "count" of managed mappings that are wired.
4352 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4358 rw_assert(&pvh_global_lock, RA_WLOCKED);
4359 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4362 pte = pmap_pte(pmap, pv->pv_va);
4363 if ((*pte & PG_W) != 0)
4371 * Returns TRUE if the given page is mapped individually or as part of
4372 * a 2mpage. Otherwise, returns FALSE.
4375 pmap_page_is_mapped(vm_page_t m)
4377 struct rwlock *lock;
4380 if ((m->oflags & VPO_UNMANAGED) != 0)
4382 rw_rlock(&pvh_global_lock);
4383 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4385 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4386 ((m->flags & PG_FICTITIOUS) == 0 &&
4387 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4389 rw_runlock(&pvh_global_lock);
4394 * Remove all pages from specified address space
4395 * this aids process exit speeds. Also, this code
4396 * is special cased for current process only, but
4397 * can have the more generic (and slightly slower)
4398 * mode enabled. This is much faster than pmap_remove
4399 * in the case of running down an entire address space.
4402 pmap_remove_pages(pmap_t pmap)
4405 pt_entry_t *pte, tpte;
4406 vm_page_t free = NULL;
4407 vm_page_t m, mpte, mt;
4409 struct md_page *pvh;
4410 struct pv_chunk *pc, *npc;
4411 struct rwlock *lock;
4413 uint64_t inuse, bitmask;
4414 int allfree, field, freed, idx;
4416 if (pmap != PCPU_GET(curpmap)) {
4417 printf("warning: pmap_remove_pages called with non-current pmap\n");
4421 rw_rlock(&pvh_global_lock);
4423 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4426 for (field = 0; field < _NPCM; field++) {
4427 inuse = ~pc->pc_map[field] & pc_freemask[field];
4428 while (inuse != 0) {
4430 bitmask = 1UL << bit;
4431 idx = field * 64 + bit;
4432 pv = &pc->pc_pventry[idx];
4435 pte = pmap_pdpe(pmap, pv->pv_va);
4437 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
4439 if ((tpte & (PG_PS | PG_V)) == PG_V) {
4441 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
4443 pte = &pte[pmap_pte_index(pv->pv_va)];
4444 tpte = *pte & ~PG_PTE_PAT;
4446 if ((tpte & PG_V) == 0) {
4447 panic("bad pte va %lx pte %lx",
4452 * We cannot remove wired pages from a process' mapping at this time
4459 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4460 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4461 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4462 m, (uintmax_t)m->phys_addr,
4465 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4466 m < &vm_page_array[vm_page_array_size],
4467 ("pmap_remove_pages: bad tpte %#jx",
4473 * Update the vm_page_t clean/reference bits.
4475 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4476 if ((tpte & PG_PS) != 0) {
4477 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4483 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4486 pc->pc_map[field] |= bitmask;
4487 if ((tpte & PG_PS) != 0) {
4488 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4489 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4490 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
4491 if (TAILQ_EMPTY(&pvh->pv_list)) {
4492 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4493 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4494 TAILQ_EMPTY(&mt->md.pv_list))
4495 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4497 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4499 pmap_remove_pt_page(pmap, mpte);
4500 pmap_resident_count_dec(pmap, 1);
4501 KASSERT(mpte->wire_count == NPTEPG,
4502 ("pmap_remove_pages: pte page wire count error"));
4503 mpte->wire_count = 0;
4504 pmap_add_delayed_free_list(mpte, &free, FALSE);
4505 atomic_subtract_int(&cnt.v_wire_count, 1);
4508 pmap_resident_count_dec(pmap, 1);
4509 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4510 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4511 TAILQ_EMPTY(&m->md.pv_list) &&
4512 (m->flags & PG_FICTITIOUS) == 0) {
4513 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4514 if (TAILQ_EMPTY(&pvh->pv_list))
4515 vm_page_aflag_clear(m, PGA_WRITEABLE);
4518 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
4522 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4523 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4524 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4526 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4532 pmap_invalidate_all(pmap);
4533 rw_runlock(&pvh_global_lock);
4535 pmap_free_zero_pages(free);
4541 * Return whether or not the specified physical page was modified
4542 * in any physical maps.
4545 pmap_is_modified(vm_page_t m)
4549 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4550 ("pmap_is_modified: page %p is not managed", m));
4553 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
4554 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4555 * is clear, no PTEs can have PG_M set.
4557 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4558 if ((m->oflags & VPO_BUSY) == 0 &&
4559 (m->aflags & PGA_WRITEABLE) == 0)
4561 rw_wlock(&pvh_global_lock);
4562 rv = pmap_is_modified_pvh(&m->md) ||
4563 ((m->flags & PG_FICTITIOUS) == 0 &&
4564 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4565 rw_wunlock(&pvh_global_lock);
4570 * Returns TRUE if any of the given mappings were used to modify
4571 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4572 * mappings are supported.
4575 pmap_is_modified_pvh(struct md_page *pvh)
4582 rw_assert(&pvh_global_lock, RA_WLOCKED);
4584 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4587 pte = pmap_pte(pmap, pv->pv_va);
4588 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4597 * pmap_is_prefaultable:
4599 * Return whether or not the specified virtual address is elgible
4603 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4611 pde = pmap_pde(pmap, addr);
4612 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
4613 pte = pmap_pde_to_pte(pde, addr);
4614 rv = (*pte & PG_V) == 0;
4621 * pmap_is_referenced:
4623 * Return whether or not the specified physical page was referenced
4624 * in any physical maps.
4627 pmap_is_referenced(vm_page_t m)
4631 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4632 ("pmap_is_referenced: page %p is not managed", m));
4633 rw_wlock(&pvh_global_lock);
4634 rv = pmap_is_referenced_pvh(&m->md) ||
4635 ((m->flags & PG_FICTITIOUS) == 0 &&
4636 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4637 rw_wunlock(&pvh_global_lock);
4642 * Returns TRUE if any of the given mappings were referenced and FALSE
4643 * otherwise. Both page and 2mpage mappings are supported.
4646 pmap_is_referenced_pvh(struct md_page *pvh)
4653 rw_assert(&pvh_global_lock, RA_WLOCKED);
4655 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4658 pte = pmap_pte(pmap, pv->pv_va);
4659 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4668 * Clear the write and modified bits in each of the given page's mappings.
4671 pmap_remove_write(vm_page_t m)
4673 struct md_page *pvh;
4675 pv_entry_t next_pv, pv;
4677 pt_entry_t oldpte, *pte;
4680 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4681 ("pmap_remove_write: page %p is not managed", m));
4684 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4685 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4686 * is clear, no page table entries need updating.
4688 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4689 if ((m->oflags & VPO_BUSY) == 0 &&
4690 (m->aflags & PGA_WRITEABLE) == 0)
4692 rw_wlock(&pvh_global_lock);
4693 if ((m->flags & PG_FICTITIOUS) != 0)
4694 goto small_mappings;
4695 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4696 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4700 pde = pmap_pde(pmap, va);
4701 if ((*pde & PG_RW) != 0)
4702 (void)pmap_demote_pde(pmap, pde, va);
4706 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4709 pde = pmap_pde(pmap, pv->pv_va);
4710 KASSERT((*pde & PG_PS) == 0,
4711 ("pmap_remove_write: found a 2mpage in page %p's pv list",
4713 pte = pmap_pde_to_pte(pde, pv->pv_va);
4716 if (oldpte & PG_RW) {
4717 if (!atomic_cmpset_long(pte, oldpte, oldpte &
4720 if ((oldpte & PG_M) != 0)
4722 pmap_invalidate_page(pmap, pv->pv_va);
4726 vm_page_aflag_clear(m, PGA_WRITEABLE);
4727 rw_wunlock(&pvh_global_lock);
4731 * pmap_ts_referenced:
4733 * Return a count of reference bits for a page, clearing those bits.
4734 * It is not necessary for every reference bit to be cleared, but it
4735 * is necessary that 0 only be returned when there are truly no
4736 * reference bits set.
4738 * XXX: The exact number of bits to check and clear is a matter that
4739 * should be tested and standardized at some point in the future for
4740 * optimal aging of shared pages.
4743 pmap_ts_referenced(vm_page_t m)
4745 struct md_page *pvh;
4746 pv_entry_t pv, pvf, pvn;
4748 pd_entry_t oldpde, *pde;
4753 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4754 ("pmap_ts_referenced: page %p is not managed", m));
4755 rw_wlock(&pvh_global_lock);
4756 if ((m->flags & PG_FICTITIOUS) != 0)
4757 goto small_mappings;
4758 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4759 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) {
4763 pde = pmap_pde(pmap, va);
4765 if ((oldpde & PG_A) != 0) {
4766 if (pmap_demote_pde(pmap, pde, va)) {
4767 if ((oldpde & PG_W) == 0) {
4769 * Remove the mapping to a single page
4770 * so that a subsequent access may
4771 * repromote. Since the underlying
4772 * page table page is fully populated,
4773 * this removal never frees a page
4776 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4778 pmap_remove_page(pmap, va, pde, NULL);
4790 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4793 pvn = TAILQ_NEXT(pv, pv_list);
4794 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4795 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
4798 pde = pmap_pde(pmap, pv->pv_va);
4799 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:"
4800 " found a 2mpage in page %p's pv list", m));
4801 pte = pmap_pde_to_pte(pde, pv->pv_va);
4802 if ((*pte & PG_A) != 0) {
4803 atomic_clear_long(pte, PG_A);
4804 pmap_invalidate_page(pmap, pv->pv_va);
4810 } while ((pv = pvn) != NULL && pv != pvf);
4813 rw_wunlock(&pvh_global_lock);
4818 * Clear the modify bits on the specified physical page.
4821 pmap_clear_modify(vm_page_t m)
4823 struct md_page *pvh;
4825 pv_entry_t next_pv, pv;
4826 pd_entry_t oldpde, *pde;
4827 pt_entry_t oldpte, *pte;
4830 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4831 ("pmap_clear_modify: page %p is not managed", m));
4832 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4833 KASSERT((m->oflags & VPO_BUSY) == 0,
4834 ("pmap_clear_modify: page %p is busy", m));
4837 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4838 * If the object containing the page is locked and the page is not
4839 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4841 if ((m->aflags & PGA_WRITEABLE) == 0)
4843 rw_wlock(&pvh_global_lock);
4844 if ((m->flags & PG_FICTITIOUS) != 0)
4845 goto small_mappings;
4846 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4847 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4851 pde = pmap_pde(pmap, va);
4853 if ((oldpde & PG_RW) != 0) {
4854 if (pmap_demote_pde(pmap, pde, va)) {
4855 if ((oldpde & PG_W) == 0) {
4857 * Write protect the mapping to a
4858 * single page so that a subsequent
4859 * write access may repromote.
4861 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4863 pte = pmap_pde_to_pte(pde, va);
4865 if ((oldpte & PG_V) != 0) {
4866 while (!atomic_cmpset_long(pte,
4868 oldpte & ~(PG_M | PG_RW)))
4871 pmap_invalidate_page(pmap, va);
4879 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4882 pde = pmap_pde(pmap, pv->pv_va);
4883 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4884 " a 2mpage in page %p's pv list", m));
4885 pte = pmap_pde_to_pte(pde, pv->pv_va);
4886 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4887 atomic_clear_long(pte, PG_M);
4888 pmap_invalidate_page(pmap, pv->pv_va);
4892 rw_wunlock(&pvh_global_lock);
4896 * pmap_clear_reference:
4898 * Clear the reference bit on the specified physical page.
4901 pmap_clear_reference(vm_page_t m)
4903 struct md_page *pvh;
4905 pv_entry_t next_pv, pv;
4906 pd_entry_t oldpde, *pde;
4910 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4911 ("pmap_clear_reference: page %p is not managed", m));
4912 rw_wlock(&pvh_global_lock);
4913 if ((m->flags & PG_FICTITIOUS) != 0)
4914 goto small_mappings;
4915 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4916 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4920 pde = pmap_pde(pmap, va);
4922 if ((oldpde & PG_A) != 0) {
4923 if (pmap_demote_pde(pmap, pde, va)) {
4925 * Remove the mapping to a single page so
4926 * that a subsequent access may repromote.
4927 * Since the underlying page table page is
4928 * fully populated, this removal never frees
4929 * a page table page.
4931 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4933 pmap_remove_page(pmap, va, pde, NULL);
4939 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4942 pde = pmap_pde(pmap, pv->pv_va);
4943 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found"
4944 " a 2mpage in page %p's pv list", m));
4945 pte = pmap_pde_to_pte(pde, pv->pv_va);
4947 atomic_clear_long(pte, PG_A);
4948 pmap_invalidate_page(pmap, pv->pv_va);
4952 rw_wunlock(&pvh_global_lock);
4956 * Miscellaneous support routines follow
4959 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
4960 static __inline void
4961 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
4966 * The cache mode bits are all in the low 32-bits of the
4967 * PTE, so we can just spin on updating the low 32-bits.
4970 opte = *(u_int *)pte;
4971 npte = opte & ~PG_PTE_CACHE;
4973 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
4976 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
4977 static __inline void
4978 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
4983 * The cache mode bits are all in the low 32-bits of the
4984 * PDE, so we can just spin on updating the low 32-bits.
4987 opde = *(u_int *)pde;
4988 npde = opde & ~PG_PDE_CACHE;
4990 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
4994 * Map a set of physical memory pages into the kernel virtual
4995 * address space. Return a pointer to where it is mapped. This
4996 * routine is intended to be used for mapping device memory,
5000 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5002 vm_offset_t va, offset;
5006 * If the specified range of physical addresses fits within the direct
5007 * map window, use the direct map.
5009 if (pa < dmaplimit && pa + size < dmaplimit) {
5010 va = PHYS_TO_DMAP(pa);
5011 if (!pmap_change_attr(va, size, mode))
5012 return ((void *)va);
5014 offset = pa & PAGE_MASK;
5015 size = roundup(offset + size, PAGE_SIZE);
5016 va = kmem_alloc_nofault(kernel_map, size);
5018 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
5019 pa = trunc_page(pa);
5020 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5021 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5022 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5023 pmap_invalidate_cache_range(va, va + tmpsize);
5024 return ((void *)(va + offset));
5028 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5031 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5035 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5038 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5042 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5044 vm_offset_t base, offset;
5046 /* If we gave a direct map region in pmap_mapdev, do nothing */
5047 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
5049 base = trunc_page(va);
5050 offset = va & PAGE_MASK;
5051 size = roundup(offset + size, PAGE_SIZE);
5052 kmem_free(kernel_map, base, size);
5056 * Tries to demote a 1GB page mapping.
5059 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
5061 pdp_entry_t newpdpe, oldpdpe;
5062 pd_entry_t *firstpde, newpde, *pde;
5066 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5068 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
5069 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
5070 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
5071 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5072 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
5073 " in pmap %p", va, pmap);
5076 mpdepa = VM_PAGE_TO_PHYS(mpde);
5077 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
5078 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
5079 KASSERT((oldpdpe & PG_A) != 0,
5080 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
5081 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
5082 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
5086 * Initialize the page directory page.
5088 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
5094 * Demote the mapping.
5099 * Invalidate a stale recursive mapping of the page directory page.
5101 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
5103 pmap_pdpe_demotions++;
5104 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
5105 " in pmap %p", va, pmap);
5110 * Sets the memory attribute for the specified page.
5113 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5116 m->md.pat_mode = ma;
5119 * If "m" is a normal page, update its direct mapping. This update
5120 * can be relied upon to perform any cache operations that are
5121 * required for data coherence.
5123 if ((m->flags & PG_FICTITIOUS) == 0 &&
5124 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5126 panic("memory attribute change on the direct map failed");
5130 * Changes the specified virtual address range's memory type to that given by
5131 * the parameter "mode". The specified virtual address range must be
5132 * completely contained within either the direct map or the kernel map. If
5133 * the virtual address range is contained within the kernel map, then the
5134 * memory type for each of the corresponding ranges of the direct map is also
5135 * changed. (The corresponding ranges of the direct map are those ranges that
5136 * map the same physical pages as the specified virtual address range.) These
5137 * changes to the direct map are necessary because Intel describes the
5138 * behavior of their processors as "undefined" if two or more mappings to the
5139 * same physical page have different memory types.
5141 * Returns zero if the change completed successfully, and either EINVAL or
5142 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5143 * of the virtual address range was not mapped, and ENOMEM is returned if
5144 * there was insufficient memory available to complete the change. In the
5145 * latter case, the memory type may have been changed on some part of the
5146 * virtual address range or the direct map.
5149 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5153 PMAP_LOCK(kernel_pmap);
5154 error = pmap_change_attr_locked(va, size, mode);
5155 PMAP_UNLOCK(kernel_pmap);
5160 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5162 vm_offset_t base, offset, tmpva;
5163 vm_paddr_t pa_start, pa_end;
5167 int cache_bits_pte, cache_bits_pde, error;
5170 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5171 base = trunc_page(va);
5172 offset = va & PAGE_MASK;
5173 size = roundup(offset + size, PAGE_SIZE);
5176 * Only supported on kernel virtual addresses, including the direct
5177 * map but excluding the recursive map.
5179 if (base < DMAP_MIN_ADDRESS)
5182 cache_bits_pde = pmap_cache_bits(mode, 1);
5183 cache_bits_pte = pmap_cache_bits(mode, 0);
5187 * Pages that aren't mapped aren't supported. Also break down 2MB pages
5188 * into 4KB pages if required.
5190 for (tmpva = base; tmpva < base + size; ) {
5191 pdpe = pmap_pdpe(kernel_pmap, tmpva);
5194 if (*pdpe & PG_PS) {
5196 * If the current 1GB page already has the required
5197 * memory type, then we need not demote this page. Just
5198 * increment tmpva to the next 1GB page frame.
5200 if ((*pdpe & PG_PDE_CACHE) == cache_bits_pde) {
5201 tmpva = trunc_1gpage(tmpva) + NBPDP;
5206 * If the current offset aligns with a 1GB page frame
5207 * and there is at least 1GB left within the range, then
5208 * we need not break down this page into 2MB pages.
5210 if ((tmpva & PDPMASK) == 0 &&
5211 tmpva + PDPMASK < base + size) {
5215 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
5218 pde = pmap_pdpe_to_pde(pdpe, tmpva);
5223 * If the current 2MB page already has the required
5224 * memory type, then we need not demote this page. Just
5225 * increment tmpva to the next 2MB page frame.
5227 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5228 tmpva = trunc_2mpage(tmpva) + NBPDR;
5233 * If the current offset aligns with a 2MB page frame
5234 * and there is at least 2MB left within the range, then
5235 * we need not break down this page into 4KB pages.
5237 if ((tmpva & PDRMASK) == 0 &&
5238 tmpva + PDRMASK < base + size) {
5242 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
5245 pte = pmap_pde_to_pte(pde, tmpva);
5253 * Ok, all the pages exist, so run through them updating their
5254 * cache mode if required.
5256 pa_start = pa_end = 0;
5257 for (tmpva = base; tmpva < base + size; ) {
5258 pdpe = pmap_pdpe(kernel_pmap, tmpva);
5259 if (*pdpe & PG_PS) {
5260 if ((*pdpe & PG_PDE_CACHE) != cache_bits_pde) {
5261 pmap_pde_attr(pdpe, cache_bits_pde);
5264 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5265 if (pa_start == pa_end) {
5266 /* Start physical address run. */
5267 pa_start = *pdpe & PG_PS_FRAME;
5268 pa_end = pa_start + NBPDP;
5269 } else if (pa_end == (*pdpe & PG_PS_FRAME))
5272 /* Run ended, update direct map. */
5273 error = pmap_change_attr_locked(
5274 PHYS_TO_DMAP(pa_start),
5275 pa_end - pa_start, mode);
5278 /* Start physical address run. */
5279 pa_start = *pdpe & PG_PS_FRAME;
5280 pa_end = pa_start + NBPDP;
5283 tmpva = trunc_1gpage(tmpva) + NBPDP;
5286 pde = pmap_pdpe_to_pde(pdpe, tmpva);
5288 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5289 pmap_pde_attr(pde, cache_bits_pde);
5292 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5293 if (pa_start == pa_end) {
5294 /* Start physical address run. */
5295 pa_start = *pde & PG_PS_FRAME;
5296 pa_end = pa_start + NBPDR;
5297 } else if (pa_end == (*pde & PG_PS_FRAME))
5300 /* Run ended, update direct map. */
5301 error = pmap_change_attr_locked(
5302 PHYS_TO_DMAP(pa_start),
5303 pa_end - pa_start, mode);
5306 /* Start physical address run. */
5307 pa_start = *pde & PG_PS_FRAME;
5308 pa_end = pa_start + NBPDR;
5311 tmpva = trunc_2mpage(tmpva) + NBPDR;
5313 pte = pmap_pde_to_pte(pde, tmpva);
5314 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5315 pmap_pte_attr(pte, cache_bits_pte);
5318 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5319 if (pa_start == pa_end) {
5320 /* Start physical address run. */
5321 pa_start = *pte & PG_FRAME;
5322 pa_end = pa_start + PAGE_SIZE;
5323 } else if (pa_end == (*pte & PG_FRAME))
5324 pa_end += PAGE_SIZE;
5326 /* Run ended, update direct map. */
5327 error = pmap_change_attr_locked(
5328 PHYS_TO_DMAP(pa_start),
5329 pa_end - pa_start, mode);
5332 /* Start physical address run. */
5333 pa_start = *pte & PG_FRAME;
5334 pa_end = pa_start + PAGE_SIZE;
5340 if (error == 0 && pa_start != pa_end)
5341 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
5342 pa_end - pa_start, mode);
5345 * Flush CPU caches if required to make sure any data isn't cached that
5346 * shouldn't be, etc.
5349 pmap_invalidate_range(kernel_pmap, base, tmpva);
5350 pmap_invalidate_cache_range(base, tmpva);
5356 * Demotes any mapping within the direct map region that covers more than the
5357 * specified range of physical addresses. This range's size must be a power
5358 * of two and its starting address must be a multiple of its size. Since the
5359 * demotion does not change any attributes of the mapping, a TLB invalidation
5360 * is not mandatory. The caller may, however, request a TLB invalidation.
5363 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
5372 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
5373 KASSERT((base & (len - 1)) == 0,
5374 ("pmap_demote_DMAP: base is not a multiple of len"));
5375 if (len < NBPDP && base < dmaplimit) {
5376 va = PHYS_TO_DMAP(base);
5378 PMAP_LOCK(kernel_pmap);
5379 pdpe = pmap_pdpe(kernel_pmap, va);
5380 if ((*pdpe & PG_V) == 0)
5381 panic("pmap_demote_DMAP: invalid PDPE");
5382 if ((*pdpe & PG_PS) != 0) {
5383 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
5384 panic("pmap_demote_DMAP: PDPE failed");
5388 pde = pmap_pdpe_to_pde(pdpe, va);
5389 if ((*pde & PG_V) == 0)
5390 panic("pmap_demote_DMAP: invalid PDE");
5391 if ((*pde & PG_PS) != 0) {
5392 if (!pmap_demote_pde(kernel_pmap, pde, va))
5393 panic("pmap_demote_DMAP: PDE failed");
5397 if (changed && invalidate)
5398 pmap_invalidate_page(kernel_pmap, va);
5399 PMAP_UNLOCK(kernel_pmap);
5404 * perform the pmap work for mincore
5407 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5416 pdep = pmap_pde(pmap, addr);
5417 if (pdep != NULL && (*pdep & PG_V)) {
5418 if (*pdep & PG_PS) {
5420 /* Compute the physical address of the 4KB page. */
5421 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5423 val = MINCORE_SUPER;
5425 pte = *pmap_pde_to_pte(pdep, addr);
5426 pa = pte & PG_FRAME;
5434 if ((pte & PG_V) != 0) {
5435 val |= MINCORE_INCORE;
5436 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5437 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5438 if ((pte & PG_A) != 0)
5439 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5441 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5442 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5443 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5444 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5445 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5448 PA_UNLOCK_COND(*locked_pa);
5454 pmap_activate(struct thread *td)
5456 pmap_t pmap, oldpmap;
5461 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5462 oldpmap = PCPU_GET(curpmap);
5463 cpuid = PCPU_GET(cpuid);
5465 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5466 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5468 CPU_CLR(cpuid, &oldpmap->pm_active);
5469 CPU_SET(cpuid, &pmap->pm_active);
5471 cr3 = DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4);
5472 td->td_pcb->pcb_cr3 = cr3;
5474 PCPU_SET(curpmap, pmap);
5479 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5484 * Increase the starting virtual address of the given mapping if a
5485 * different alignment might result in more superpage mappings.
5488 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5489 vm_offset_t *addr, vm_size_t size)
5491 vm_offset_t superpage_offset;
5495 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5496 offset += ptoa(object->pg_color);
5497 superpage_offset = offset & PDRMASK;
5498 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5499 (*addr & PDRMASK) == superpage_offset)
5501 if ((*addr & PDRMASK) < superpage_offset)
5502 *addr = (*addr & ~PDRMASK) + superpage_offset;
5504 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5507 #include "opt_ddb.h"
5509 #include <ddb/ddb.h>
5511 DB_SHOW_COMMAND(pte, pmap_print_pte)
5521 va = (vm_offset_t)addr;
5522 pmap = PCPU_GET(curpmap); /* XXX */
5524 db_printf("show pte addr\n");
5527 pml4 = pmap_pml4e(pmap, va);
5528 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
5529 if ((*pml4 & PG_V) == 0) {
5533 pdp = pmap_pml4e_to_pdpe(pml4, va);
5534 db_printf(" pdpe %#016lx", *pdp);
5535 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
5539 pde = pmap_pdpe_to_pde(pdp, va);
5540 db_printf(" pde %#016lx", *pde);
5541 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
5545 pte = pmap_pde_to_pte(pde, va);
5546 db_printf(" pte %#016lx\n", *pte);
5549 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
5554 a = (vm_paddr_t)addr;
5555 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
5557 db_printf("show phys2dmap addr\n");