2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
38 #include <machine/bus.h>
40 #include <dev/uart/uart.h>
41 #include <dev/uart/uart_cpu.h>
42 #include <dev/uart/uart_bus.h>
43 #include <arm/at91/at91_usartreg.h>
44 #include <arm/at91/at91_pdcreg.h>
45 #include <arm/at91/at91var.h>
49 #define DEFAULT_RCLK at91_master_clock
50 #define USART_BUFFER_SIZE 128
53 * High-level UART interface.
55 struct at91_usart_rx {
61 struct at91_usart_softc {
62 struct uart_softc base;
68 struct at91_usart_rx ping_pong[2];
69 struct at91_usart_rx *ping;
70 struct at91_usart_rx *pong;
73 #define RD4(bas, reg) \
74 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
75 #define WR4(bas, reg, value) \
76 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
78 #define SIGCHG(c, i, s, d) \
81 i |= (i & s) ? s : s | d; \
83 i = (i & s) ? (i & ~s) | d : i; \
87 #define BAUD2DIVISOR(b) \
88 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
91 * Low-level UART interface.
93 static int at91_usart_probe(struct uart_bas *bas);
94 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
95 static void at91_usart_term(struct uart_bas *bas);
96 static void at91_usart_putc(struct uart_bas *bas, int);
97 static int at91_usart_rxready(struct uart_bas *bas);
98 static int at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx);
100 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
103 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
104 int stopbits, int parity)
109 * Assume 3-wire RS-232 configuration.
110 * XXX Not sure how uart will present the other modes to us, so
111 * XXX they are unimplemented. maybe ioctl?
113 mr = USART_MR_MODE_NORMAL;
114 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
117 * Or in the databits requested
120 mr &= ~USART_MR_MODE9;
123 mr |= USART_MR_CHRL_5BITS;
126 mr |= USART_MR_CHRL_6BITS;
129 mr |= USART_MR_CHRL_7BITS;
132 mr |= USART_MR_CHRL_8BITS;
135 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
145 case UART_PARITY_NONE:
146 mr |= USART_MR_PAR_NONE;
148 case UART_PARITY_ODD:
149 mr |= USART_MR_PAR_ODD;
151 case UART_PARITY_EVEN:
152 mr |= USART_MR_PAR_EVEN;
154 case UART_PARITY_MARK:
155 mr |= USART_MR_PAR_MARK;
157 case UART_PARITY_SPACE:
158 mr |= USART_MR_PAR_SPACE;
165 * Or in the stop bits. Note: The hardware supports 1.5 stop
166 * bits in async mode, but there's no way to specify that
167 * AFAICT. Instead, rely on the convention documented at
168 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
169 * states that 1.5 stop bits are used for 5 bit bytes and
170 * 2 stop bits only for longer bytes.
173 mr |= USART_MR_NBSTOP_1;
174 else if (databits > 5)
175 mr |= USART_MR_NBSTOP_2;
177 mr |= USART_MR_NBSTOP_1_5;
180 * We want normal plumbing mode too, none of this fancy
181 * loopback or echo mode.
183 mr |= USART_MR_CHMODE_NORMAL;
185 mr &= ~USART_MR_MSBF; /* lsb first */
186 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
188 WR4(bas, USART_MR, mr);
191 * Set the baud rate (only if we know our master clock rate)
193 if (DEFAULT_RCLK != 0)
194 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
196 /* XXX Need to take possible synchronous mode into account */
200 static struct uart_ops at91_usart_ops = {
201 .probe = at91_usart_probe,
202 .init = at91_usart_init,
203 .term = at91_usart_term,
204 .putc = at91_usart_putc,
205 .rxready = at91_usart_rxready,
206 .getc = at91_usart_getc,
210 at91_usart_probe(struct uart_bas *bas)
213 /* We know that this is always here */
218 * Initialize this device for use as a console.
221 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
225 at91_usart_param(bas, baudrate, databits, stopbits, parity);
227 /* Reset the rx and tx buffers and turn on rx and tx */
228 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
229 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
230 WR4(bas, USART_IDR, 0xffffffff);
234 * Free resources now that we're no longer the console. This appears to
235 * be never called, and I'm unsure quite what to do if I am called.
238 at91_usart_term(struct uart_bas *bas)
245 * Put a character of console output (so we do it here polling rather than
249 at91_usart_putc(struct uart_bas *bas, int c)
252 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
254 WR4(bas, USART_THR, c);
258 * Check for a character available.
261 at91_usart_rxready(struct uart_bas *bas)
264 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
268 * Block waiting for a character.
271 at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx)
276 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) {
281 c = RD4(bas, USART_RHR) & 0xff;
286 static int at91_usart_bus_probe(struct uart_softc *sc);
287 static int at91_usart_bus_attach(struct uart_softc *sc);
288 static int at91_usart_bus_flush(struct uart_softc *, int);
289 static int at91_usart_bus_getsig(struct uart_softc *);
290 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
291 static int at91_usart_bus_ipend(struct uart_softc *);
292 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
293 static int at91_usart_bus_receive(struct uart_softc *);
294 static int at91_usart_bus_setsig(struct uart_softc *, int);
295 static int at91_usart_bus_transmit(struct uart_softc *);
297 static kobj_method_t at91_usart_methods[] = {
298 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
299 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
300 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
301 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
302 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
303 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
304 KOBJMETHOD(uart_param, at91_usart_bus_param),
305 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
306 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
307 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
313 at91_usart_bus_probe(struct uart_softc *sc)
316 sc->sc_txfifosz = USART_BUFFER_SIZE;
317 sc->sc_rxfifosz = USART_BUFFER_SIZE;
323 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
328 *(bus_addr_t *)arg = segs[0].ds_addr;
332 at91_usart_bus_attach(struct uart_softc *sc)
337 struct at91_usart_softc *atsc;
339 atsc = (struct at91_usart_softc *)sc;
342 * See if we have a TIMEOUT bit. We disable all interrupts as
343 * a side effect. Boot loaders may have enabled them. Since
344 * a TIMEOUT interrupt can't happen without other setup, the
345 * apparent race here can't actually happen.
347 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
348 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
349 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
350 atsc->flags |= HAS_TIMEOUT;
351 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
354 * Allocate transmit DMA tag and map. We allow a transmit buffer
355 * to be any size, but it must map to a single contiguous physical
358 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
359 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
360 BUS_SPACE_MAXSIZE_32BIT, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
361 NULL, &atsc->tx_tag);
364 err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map);
368 if (atsc->flags & HAS_TIMEOUT) {
370 * Allocate receive DMA tags, maps, and buffers.
371 * The receive buffers should be aligned to arm_dcache_align,
372 * otherwise partial cache line flushes on every receive
373 * interrupt are pretty much guaranteed.
375 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),
376 arm_dcache_align, 0, BUS_SPACE_MAXADDR_32BIT,
377 BUS_SPACE_MAXADDR, NULL, NULL, sc->sc_rxfifosz, 1,
378 sc->sc_rxfifosz, BUS_DMA_ALLOCNOW, NULL, NULL,
382 for (i = 0; i < 2; i++) {
383 err = bus_dmamem_alloc(atsc->rx_tag,
384 (void **)&atsc->ping_pong[i].buffer,
385 BUS_DMA_NOWAIT, &atsc->ping_pong[i].map);
388 err = bus_dmamap_load(atsc->rx_tag,
389 atsc->ping_pong[i].map,
390 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
391 at91_getaddr, &atsc->ping_pong[i].pa, 0);
394 bus_dmamap_sync(atsc->rx_tag, atsc->ping_pong[i].map,
395 BUS_DMASYNC_PREREAD);
397 atsc->ping = &atsc->ping_pong[0];
398 atsc->pong = &atsc->ping_pong[1];
401 /* Turn on rx and tx */
402 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
403 WR4(&sc->sc_bas, USART_CR, cr);
404 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
407 * Setup the PDC to receive data. We use the ping-pong buffers
408 * so that we can more easily bounce between the two and so that
409 * we get an interrupt 1/2 way through the software 'fifo' we have
412 if (atsc->flags & HAS_TIMEOUT) {
413 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
414 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
415 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
416 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
417 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
420 * Set the receive timeout to be 1.5 character times
423 WR4(&sc->sc_bas, USART_RTOR, 15);
424 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
425 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
426 USART_CSR_RXBUFF | USART_CSR_ENDRX);
428 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
430 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
436 at91_usart_bus_transmit(struct uart_softc *sc)
439 struct at91_usart_softc *atsc;
443 atsc = (struct at91_usart_softc *)sc;
444 uart_lock(sc->sc_hwmtx);
445 if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf,
446 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) {
450 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
453 * Setup the PDC to transfer the data and interrupt us when it
454 * is done. We've already requested the interrupt.
456 WR4(&sc->sc_bas, PDC_TPR, addr);
457 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
458 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
459 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
461 uart_unlock(sc->sc_hwmtx);
466 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
468 uint32_t new, old, cr;
469 struct uart_bas *bas;
475 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
477 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
478 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
480 uart_lock(sc->sc_hwmtx);
483 cr |= USART_CR_DTREN;
485 cr |= USART_CR_DTRDIS;
487 cr |= USART_CR_RTSEN;
489 cr |= USART_CR_RTSDIS;
490 WR4(bas, USART_CR, cr);
491 uart_unlock(sc->sc_hwmtx);
496 at91_usart_bus_receive(struct uart_softc *sc)
503 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
504 int stopbits, int parity)
507 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
512 at91_rx_put(struct uart_softc *sc, int key)
516 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
517 kdb_alt_break(key, &sc->sc_altbrk);
519 uart_rx_put(sc, key);
523 at91_usart_bus_ipend(struct uart_softc *sc)
525 struct at91_usart_softc *atsc;
526 struct at91_usart_rx *p;
531 atsc = (struct at91_usart_softc *)sc;
532 uart_lock(sc->sc_hwmtx);
533 csr = RD4(&sc->sc_bas, USART_CSR);
534 if (csr & USART_CSR_ENDTX) {
535 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map,
536 BUS_DMASYNC_POSTWRITE);
537 bus_dmamap_unload(atsc->tx_tag, atsc->tx_map);
539 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) {
541 ipend |= SER_INT_TXIDLE;
542 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY |
547 * Due to the contraints of the DMA engine present in the
548 * atmel chip, I can't just say I have a rx interrupt pending
549 * and do all the work elsewhere. I need to look at the CSR
550 * bits right now and do things based on them to avoid races.
552 if (atsc->flags & HAS_TIMEOUT) {
553 if (csr & USART_CSR_RXBUFF) {
555 * We have a buffer overflow. Copy all data from both
556 * ping and pong. Insert overflow character. Reset
557 * ping and pong and re-enable the PDC to receive
560 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
561 BUS_DMASYNC_POSTREAD);
562 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
563 BUS_DMASYNC_POSTREAD);
564 for (i = 0; i < sc->sc_rxfifosz; i++)
565 at91_rx_put(sc, atsc->ping->buffer[i]);
566 for (i = 0; i < sc->sc_rxfifosz; i++)
567 at91_rx_put(sc, atsc->pong->buffer[i]);
568 uart_rx_put(sc, UART_STAT_OVERRUN);
569 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
570 BUS_DMASYNC_PREREAD);
571 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
572 BUS_DMASYNC_PREREAD);
573 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
574 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
575 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
576 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
577 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
578 ipend |= SER_INT_RXREADY;
579 } else if (csr & USART_CSR_ENDRX) {
581 * Shuffle data from ping of ping pong buffer, but
582 * leave current pong in place, as it has become the
583 * new ping. We need to copy data and setup the old
584 * ping as the new pong when we're done.
586 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
587 BUS_DMASYNC_POSTREAD);
588 for (i = 0; i < sc->sc_rxfifosz; i++)
589 at91_rx_put(sc, atsc->ping->buffer[i]);
591 atsc->ping = atsc->pong;
593 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
594 BUS_DMASYNC_PREREAD);
595 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
596 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
597 ipend |= SER_INT_RXREADY;
598 } else if (csr & USART_CSR_TIMEOUT) {
600 * We have one partial buffer. We need to stop the
601 * PDC, get the number of characters left and from
602 * that compute number of valid characters. We then
603 * need to reset ping and pong and reenable the PDC.
604 * Not sure if there's a race here at fast baud rates
605 * we need to worry about.
607 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
608 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
609 BUS_DMASYNC_POSTREAD);
610 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
611 for (i = 0; i < len; i++)
612 at91_rx_put(sc, atsc->ping->buffer[i]);
613 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
614 BUS_DMASYNC_PREREAD);
615 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
616 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
617 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
618 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
619 ipend |= SER_INT_RXREADY;
621 } else if (csr & USART_CSR_RXRDY) {
623 * We have another charater in a device that doesn't support
624 * timeouts, so we do it one character at a time.
626 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
627 ipend |= SER_INT_RXREADY;
630 if (csr & USART_CSR_RXBRK) {
631 ipend |= SER_INT_BREAK;
632 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
634 uart_unlock(sc->sc_hwmtx);
639 at91_usart_bus_flush(struct uart_softc *sc, int what)
646 at91_usart_bus_getsig(struct uart_softc *sc)
648 uint32_t csr, new, sig;
650 uart_lock(sc->sc_hwmtx);
651 csr = RD4(&sc->sc_bas, USART_CSR);
653 if (csr & USART_CSR_CTS)
655 if (csr & USART_CSR_DCD)
657 if (csr & USART_CSR_DSR)
659 if (csr & USART_CSR_RI)
661 new = sig & ~SER_MASK_DELTA;
663 uart_unlock(sc->sc_hwmtx);
668 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
672 case UART_IOCTL_BREAK:
673 case UART_IOCTL_IFLOW:
674 case UART_IOCTL_OFLOW:
676 case UART_IOCTL_BAUD:
677 /* only if we know our master clock rate */
678 if (DEFAULT_RCLK != 0)
679 WR4(&sc->sc_bas, USART_BRGR,
680 BAUD2DIVISOR(*(int *)data));
686 struct uart_class at91_usart_class = {
689 sizeof(struct at91_usart_softc),
690 .uc_ops = &at91_usart_ops,